projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5894ca00 MY |
1 | /* |
| 2 | * UniPhier SC (System Control) block registers | |
| 3 | * | |
| 29d63a59 MY |
4 | * Copyright (C) 2011-2015 Panasonic Corporation |
| 5 | * Copyright (C) 2015-2016 Socionext Inc. | |
| 6 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 5894ca00 MY |
7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef ARCH_SC_REGS_H | |
| 12 | #define ARCH_SC_REGS_H | |
| 13 | ||
| 14 | #define SC_BASE_ADDR 0x61840000 | |
| 15 | ||
| 28f40d4a MY |
16 | #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) |
| 17 | #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) | |
| 18 | #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) | |
| 19 | ||
| 5894ca00 MY |
20 | #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) |
| 21 | #define SC_DPLLCTRL_SSC_EN (0x1 << 31) | |
| 22 | #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) | |
| 23 | #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) | |
| 24 | ||
| 25 | #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) | |
| 26 | #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) | |
| 27 | ||
| 28 | #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) | |
| 29 | #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) | |
| 30 | #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) | |
| 31 | ||
| 32 | #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) | |
| 33 | ||
| 34 | #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) | |
| 35 | #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) | |
| 36 | #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) | |
| 37 | ||
| 38 | #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) | |
| 39 | #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) | |
| 40 | #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) | |
| 41 | ||
| 42 | #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) | |
| 1535163a MY |
43 | #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ |
| 44 | #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ | |
| 5894ca00 | 45 | #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) |
| 42ca6982 | 46 | #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) |
| 1535163a | 47 | #define SC_RSTCTRL_NRST_GIO (0x1 << 6) |
| 28f40d4a | 48 | /* Pro4 or older */ |
| 5894ca00 MY |
49 | #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) |
| 50 | #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) | |
| 51 | #define SC_RSTCTRL_NRST_NAND (0x1 << 2) | |
| 52 | ||
| 53 | #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) | |
| 1535163a MY |
54 | #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ |
| 55 | #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ | |
| 56 | ||
| 5894ca00 MY |
57 | #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) |
| 58 | ||
| 28f40d4a MY |
59 | /* Pro5 or newer */ |
| 60 | #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) | |
| 61 | #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ | |
| 62 | #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ | |
| 63 | #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ | |
| 64 | #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */ | |
| 019df879 | 65 | #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */ |
| 28f40d4a MY |
66 | #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ |
| 67 | #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ | |
| 68 | ||
| 29d63a59 MY |
69 | #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) |
| 70 | ||
| 71 | #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) | |
| 72 | ||
| 5894ca00 | 73 | #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) |
| 1535163a MY |
74 | #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ |
| 75 | #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ | |
| f267b81e MY |
76 | #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) |
| 77 | #define SC_CLKCTRL_CEN_MIO (0x1 << 11) | |
| 42ca6982 | 78 | #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) |
| 1535163a | 79 | #define SC_CLKCTRL_CEN_GIO (0x1 << 6) |
| 28f40d4a | 80 | /* Pro4 or older */ |
| f267b81e MY |
81 | #define SC_CLKCTRL_CEN_UMC (0x1 << 4) |
| 82 | #define SC_CLKCTRL_CEN_NAND (0x1 << 2) | |
| 83 | #define SC_CLKCTRL_CEN_SBC (0x1 << 1) | |
| 84 | #define SC_CLKCTRL_CEN_PERI (0x1 << 0) | |
| 5894ca00 | 85 | |
| 28f40d4a MY |
86 | /* Pro5 or newer */ |
| 87 | #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) | |
| 88 | #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ | |
| 019df879 | 89 | #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ |
| 28f40d4a MY |
90 | #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ |
| 91 | #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ | |
| 92 | ||
| 5894ca00 MY |
93 | /* System reset control register */ |
| 94 | #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) | |
| 95 | #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) | |
| 96 | #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) | |
| 97 | ||
| 98 | #endif /* ARCH_SC_REGS_H */ |