[thirdparty/kernel/linux.git] / arch / arm64 / boot / dts / mediatek / mt2712e.dtsi

/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: YT Shen <yt.shen@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt2712";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x000>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x001>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <80>;
				min-residency-us = <2000>;
				arm,psci-suspend-param = <0x0010000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <350>;
				exit-latency-us = <80>;
				min-residency-us = <3000>;
				arm,psci-suspend-param = <0x1010000>;
			};
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	baud_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	sys_clk: dummyclk {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	clkfpc: oscillator@2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "clkfpc";
	};

	clkaud_ext_i_0: oscillator@3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <6500000>;
		clock-output-names = "clkaud_ext_i_0";
	};

	clkaud_ext_i_1: oscillator@4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <196608000>;
		clock-output-names = "clkaud_ext_i_1";
	};

	clkaud_ext_i_2: oscillator@5 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <180633600>;
		clock-output-names = "clkaud_ext_i_2";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2712-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2712-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2712-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	uart5: serial@1000f000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x1000f000 0 0x400>;
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2712-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	mcucfg: syscon@10220000 {
		compatible = "mediatek,mt2712-mcucfg", "syscon";
		reg = <0 0x10220000 0 0x1000>;
		#clock-cells = <1>;
	};

	sysirq: interrupt-controller@10220a80 {
		compatible = "mediatek,mt2712-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10220a80 0 0x40>;
	};

	gic: interrupt-controller@10510000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x10510000 0 0x10000>,
		      <0 0x10520000 0 0x20000>,
		      <0 0x10540000 0 0x20000>,
		      <0 0x10560000 0 0x20000>;
		interrupts = <GIC_PPI 9
			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart4: serial@11019000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11019000 0 0x400>;
		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	mfgcfg: syscon@13000000 {
		compatible = "mediatek,mt2712-mfgcfg", "syscon";
		reg = <0 0x13000000 0 0x1000>;
		#clock-cells = <1>;
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2712-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2712-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bdpsys: syscon@15010000 {
		compatible = "mediatek,mt2712-bdpsys", "syscon";
		reg = <0 0x15010000 0 0x1000>;
		#clock-cells = <1>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2712-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	vencsys: syscon@18000000 {
		compatible = "mediatek,mt2712-vencsys", "syscon";
		reg = <0 0x18000000 0 0x1000>;
		#clock-cells = <1>;
	};

	jpgdecsys: syscon@19000000 {
		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
		reg = <0 0x19000000 0 0x1000>;
		#clock-cells = <1>;
	};
};
Commit	Line	Data
bdf2cbb2	1	/*
	2	* Copyright (c) 2017 MediaTek Inc.
	3	* Author: YT Shen <yt.shen@mediatek.com>
	4	*
	5	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	6	*/
	7
5d483970	8	#include <dt-bindings/clock/mt2712-clk.h>
bdf2cbb2	9	#include <dt-bindings/interrupt-controller/irq.h>
	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	/ {
	13	compatible = "mediatek,mt2712";
	14	interrupt-parent = <&sysirq>;
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
	21
	22	cpu-map {
	23	cluster0 {
	24	core0 {
	25	cpu = <&cpu0>;
	26	};
	27	core1 {
	28	cpu = <&cpu1>;
	29	};
	30	};
	31
	32	cluster1 {
	33	core0 {
	34	cpu = <&cpu2>;
	35	};
	36	};
	37	};
	38
	39	cpu0: cpu@0 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a35";
	42	reg = <0x000>;
f5a3d783	43	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2	44	};
	45
	46	cpu1: cpu@1 {
	47	device_type = "cpu";
	48	compatible = "arm,cortex-a35";
	49	reg = <0x001>;
	50	enable-method = "psci";
f5a3d783	51	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2	52	};
	53
	54	cpu2: cpu@200 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a72";
	57	reg = <0x200>;
	58	enable-method = "psci";
f5a3d783 JL	59	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
	60	};
	61
	62	idle-states {
	63	entry-method = "arm,psci";
	64
	65	CPU_SLEEP_0: cpu-sleep-0 {
	66	compatible = "arm,idle-state";
	67	local-timer-stop;
	68	entry-latency-us = <100>;
	69	exit-latency-us = <80>;
	70	min-residency-us = <2000>;
	71	arm,psci-suspend-param = <0x0010000>;
	72	};
	73
	74	CLUSTER_SLEEP_0: cluster-sleep-0 {
	75	compatible = "arm,idle-state";
	76	local-timer-stop;
	77	entry-latency-us = <350>;
	78	exit-latency-us = <80>;
	79	min-residency-us = <3000>;
	80	arm,psci-suspend-param = <0x1010000>;
	81	};
bdf2cbb2	82	};
	83	};
	84
	85	psci {
	86	compatible = "arm,psci-0.2";
	87	method = "smc";
	88	};
	89
	90	baud_clk: dummy26m {
	91	compatible = "fixed-clock";
	92	clock-frequency = <26000000>;
	93	#clock-cells = <0>;
	94	};
	95
	96	sys_clk: dummyclk {
	97	compatible = "fixed-clock";
	98	clock-frequency = <26000000>;
	99	#clock-cells = <0>;
	100	};
	101
5d483970	102	clk26m: oscillator@0 {
	103	compatible = "fixed-clock";
	104	#clock-cells = <0>;
	105	clock-frequency = <26000000>;
	106	clock-output-names = "clk26m";
	107	};
	108
	109	clk32k: oscillator@1 {
	110	compatible = "fixed-clock";
	111	#clock-cells = <0>;
	112	clock-frequency = <32768>;
	113	clock-output-names = "clk32k";
	114	};
	115
	116	clkfpc: oscillator@2 {
	117	compatible = "fixed-clock";
	118	#clock-cells = <0>;
	119	clock-frequency = <50000000>;
	120	clock-output-names = "clkfpc";
	121	};
	122
	123	clkaud_ext_i_0: oscillator@3 {
	124	compatible = "fixed-clock";
	125	#clock-cells = <0>;
	126	clock-frequency = <6500000>;
	127	clock-output-names = "clkaud_ext_i_0";
	128	};
	129
	130	clkaud_ext_i_1: oscillator@4 {
	131	compatible = "fixed-clock";
	132	#clock-cells = <0>;
	133	clock-frequency = <196608000>;
	134	clock-output-names = "clkaud_ext_i_1";
	135	};
	136
	137	clkaud_ext_i_2: oscillator@5 {
	138	compatible = "fixed-clock";
	139	#clock-cells = <0>;
	140	clock-frequency = <180633600>;
	141	clock-output-names = "clkaud_ext_i_2";
	142	};
	143
bdf2cbb2	144	timer {
	145	compatible = "arm,armv8-timer";
	146	interrupt-parent = <&gic>;
	147	interrupts = <GIC_PPI 13
	148	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	149	<GIC_PPI 14
	150	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	151	<GIC_PPI 11
	152	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	153	<GIC_PPI 10
	154	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>;
	155	};
	156
5d483970	157	topckgen: syscon@10000000 {
	158	compatible = "mediatek,mt2712-topckgen", "syscon";
	159	reg = <0 0x10000000 0 0x1000>;
	160	#clock-cells = <1>;
	161	};
	162
	163	infracfg: syscon@10001000 {
	164	compatible = "mediatek,mt2712-infracfg", "syscon";
	165	reg = <0 0x10001000 0 0x1000>;
	166	#clock-cells = <1>;
	167	};
	168
	169	pericfg: syscon@10003000 {
	170	compatible = "mediatek,mt2712-pericfg", "syscon";
	171	reg = <0 0x10003000 0 0x1000>;
	172	#clock-cells = <1>;
	173	};
	174
bdf2cbb2	175	uart5: serial@1000f000 {
	176	compatible = "mediatek,mt2712-uart",
	177	"mediatek,mt6577-uart";
	178	reg = <0 0x1000f000 0 0x400>;
	179	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
	180	clocks = <&baud_clk>, <&sys_clk>;
	181	clock-names = "baud", "bus";
	182	status = "disabled";
	183	};
	184
5d483970	185	apmixedsys: syscon@10209000 {
	186	compatible = "mediatek,mt2712-apmixedsys", "syscon";
	187	reg = <0 0x10209000 0 0x1000>;
	188	#clock-cells = <1>;
	189	};
	190
	191	mcucfg: syscon@10220000 {
	192	compatible = "mediatek,mt2712-mcucfg", "syscon";
	193	reg = <0 0x10220000 0 0x1000>;
	194	#clock-cells = <1>;
	195	};
	196
bdf2cbb2	197	sysirq: interrupt-controller@10220a80 {
	198	compatible = "mediatek,mt2712-sysirq",
	199	"mediatek,mt6577-sysirq";
	200	interrupt-controller;
	201	#interrupt-cells = <3>;
	202	interrupt-parent = <&gic>;
	203	reg = <0 0x10220a80 0 0x40>;
	204	};
	205
	206	gic: interrupt-controller@10510000 {
	207	compatible = "arm,gic-400";
	208	#interrupt-cells = <3>;
	209	interrupt-parent = <&gic>;
	210	interrupt-controller;
	211	reg = <0 0x10510000 0 0x10000>,
	212	<0 0x10520000 0 0x20000>,
	213	<0 0x10540000 0 0x20000>,
	214	<0 0x10560000 0 0x20000>;
	215	interrupts = <GIC_PPI 9
	216	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_HIGH)>;
	217	};
	218
	219	uart0: serial@11002000 {
	220	compatible = "mediatek,mt2712-uart",
	221	"mediatek,mt6577-uart";
	222	reg = <0 0x11002000 0 0x400>;
	223	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	224	clocks = <&baud_clk>, <&sys_clk>;
	225	clock-names = "baud", "bus";
	226	status = "disabled";
	227	};
	228
	229	uart1: serial@11003000 {
	230	compatible = "mediatek,mt2712-uart",
	231	"mediatek,mt6577-uart";
	232	reg = <0 0x11003000 0 0x400>;
	233	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	234	clocks = <&baud_clk>, <&sys_clk>;
	235	clock-names = "baud", "bus";
	236	status = "disabled";
	237	};
	238
	239	uart2: serial@11004000 {
	240	compatible = "mediatek,mt2712-uart",
	241	"mediatek,mt6577-uart";
	242	reg = <0 0x11004000 0 0x400>;
	243	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	244	clocks = <&baud_clk>, <&sys_clk>;
	245	clock-names = "baud", "bus";
	246	status = "disabled";
	247	};
	248
	249	uart3: serial@11005000 {
	250	compatible = "mediatek,mt2712-uart",
	251	"mediatek,mt6577-uart";
	252	reg = <0 0x11005000 0 0x400>;
	253	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	254	clocks = <&baud_clk>, <&sys_clk>;
	255	clock-names = "baud", "bus";
	256	status = "disabled";
	257	};
	258
	259	uart4: serial@11019000 {
	260	compatible = "mediatek,mt2712-uart",
261	"mediatek,mt6577-uart";
262	reg = <0 0x11019000 0 0x400>;
263	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
264	clocks = <&baud_clk>, <&sys_clk>;
265	clock-names = "baud", "bus";
266	status = "disabled";
267	};
5d483970	268
	269	mfgcfg: syscon@13000000 {
	270	compatible = "mediatek,mt2712-mfgcfg", "syscon";
	271	reg = <0 0x13000000 0 0x1000>;
	272	#clock-cells = <1>;
	273	};
	274
	275	mmsys: syscon@14000000 {
	276	compatible = "mediatek,mt2712-mmsys", "syscon";
	277	reg = <0 0x14000000 0 0x1000>;
	278	#clock-cells = <1>;
	279	};
	280
	281	imgsys: syscon@15000000 {
	282	compatible = "mediatek,mt2712-imgsys", "syscon";
	283	reg = <0 0x15000000 0 0x1000>;
	284	#clock-cells = <1>;
	285	};
	286
	287	bdpsys: syscon@15010000 {
	288	compatible = "mediatek,mt2712-bdpsys", "syscon";
	289	reg = <0 0x15010000 0 0x1000>;
	290	#clock-cells = <1>;
	291	};
	292
	293	vdecsys: syscon@16000000 {
	294	compatible = "mediatek,mt2712-vdecsys", "syscon";
	295	reg = <0 0x16000000 0 0x1000>;
	296	#clock-cells = <1>;
	297	};
	298
	299	vencsys: syscon@18000000 {
	300	compatible = "mediatek,mt2712-vencsys", "syscon";
	301	reg = <0 0x18000000 0 0x1000>;
	302	#clock-cells = <1>;
	303	};
	304
	305	jpgdecsys: syscon@19000000 {
	306	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
	307	reg = <0 0x19000000 0 0x1000>;
	308	#clock-cells = <1>;
	309	};
bdf2cbb2	310	};
bdf2cbb2	311