[thirdparty/kernel/linux.git] / arch / arm64 / boot / dts / mediatek / mt2712e.dtsi

/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: YT Shen <yt.shen@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt2712";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp00 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1000000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <1000000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <1000000>;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;
		opp00 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1000000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <1000000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <1000000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <897000000>;
			opp-microvolt = <1000000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1001000000>;
			opp-microvolt = <1000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x000>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				<&topckgen CLK_TOP_F_MP0_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc0>;
			operating-points-v2 = <&cluster0_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x001>;
			enable-method = "psci";
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				<&topckgen CLK_TOP_F_MP0_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc0>;
			operating-points-v2 = <&cluster0_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				<&topckgen CLK_TOP_F_BIG_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc1>;
			operating-points-v2 = <&cluster1_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <80>;
				min-residency-us = <2000>;
				arm,psci-suspend-param = <0x0010000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <350>;
				exit-latency-us = <80>;
				min-residency-us = <3000>;
				arm,psci-suspend-param = <0x1010000>;
			};
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	baud_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	sys_clk: dummyclk {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	clkfpc: oscillator@2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "clkfpc";
	};

	clkaud_ext_i_0: oscillator@3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <6500000>;
		clock-output-names = "clkaud_ext_i_0";
	};

	clkaud_ext_i_1: oscillator@4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <196608000>;
		clock-output-names = "clkaud_ext_i_1";
	};

	clkaud_ext_i_2: oscillator@5 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <180633600>;
		clock-output-names = "clkaud_ext_i_2";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2712-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2712-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2712-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	uart5: serial@1000f000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x1000f000 0 0x400>;
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2712-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	mcucfg: syscon@10220000 {
		compatible = "mediatek,mt2712-mcucfg", "syscon";
		reg = <0 0x10220000 0 0x1000>;
		#clock-cells = <1>;
	};

	sysirq: interrupt-controller@10220a80 {
		compatible = "mediatek,mt2712-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10220a80 0 0x40>;
	};

	gic: interrupt-controller@10510000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x10510000 0 0x10000>,
		      <0 0x10520000 0 0x20000>,
		      <0 0x10540000 0 0x20000>,
		      <0 0x10560000 0 0x20000>;
		interrupts = <GIC_PPI 9
			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart4: serial@11019000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11019000 0 0x400>;
		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	mfgcfg: syscon@13000000 {
		compatible = "mediatek,mt2712-mfgcfg", "syscon";
		reg = <0 0x13000000 0 0x1000>;
		#clock-cells = <1>;
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2712-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2712-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bdpsys: syscon@15010000 {
		compatible = "mediatek,mt2712-bdpsys", "syscon";
		reg = <0 0x15010000 0 0x1000>;
		#clock-cells = <1>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2712-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	vencsys: syscon@18000000 {
		compatible = "mediatek,mt2712-vencsys", "syscon";
		reg = <0 0x18000000 0 0x1000>;
		#clock-cells = <1>;
	};

	jpgdecsys: syscon@19000000 {
		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
		reg = <0 0x19000000 0 0x1000>;
		#clock-cells = <1>;
	};
};
Commit	Line	Data
bdf2cbb2	1	/*
	2	* Copyright (c) 2017 MediaTek Inc.
	3	* Author: YT Shen <yt.shen@mediatek.com>
	4	*
	5	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	6	*/
	7
5d483970	8	#include <dt-bindings/clock/mt2712-clk.h>
bdf2cbb2	9	#include <dt-bindings/interrupt-controller/irq.h>
	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	/ {
	13	compatible = "mediatek,mt2712";
	14	interrupt-parent = <&sysirq>;
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17
f75dd8bd AC	18	cluster0_opp: opp_table0 {
	19	compatible = "operating-points-v2";
	20	opp-shared;
	21	opp00 {
	22	opp-hz = /bits/ 64 <598000000>;
	23	opp-microvolt = <1000000>;
	24	};
	25	opp01 {
	26	opp-hz = /bits/ 64 <702000000>;
	27	opp-microvolt = <1000000>;
	28	};
	29	opp02 {
	30	opp-hz = /bits/ 64 <793000000>;
	31	opp-microvolt = <1000000>;
	32	};
	33	};
	34
	35	cluster1_opp: opp_table1 {
	36	compatible = "operating-points-v2";
	37	opp-shared;
	38	opp00 {
	39	opp-hz = /bits/ 64 <598000000>;
	40	opp-microvolt = <1000000>;
	41	};
	42	opp01 {
	43	opp-hz = /bits/ 64 <702000000>;
	44	opp-microvolt = <1000000>;
	45	};
	46	opp02 {
	47	opp-hz = /bits/ 64 <793000000>;
	48	opp-microvolt = <1000000>;
	49	};
	50	opp03 {
	51	opp-hz = /bits/ 64 <897000000>;
	52	opp-microvolt = <1000000>;
	53	};
	54	opp04 {
	55	opp-hz = /bits/ 64 <1001000000>;
	56	opp-microvolt = <1000000>;
	57	};
	58	};
	59
bdf2cbb2	60	cpus {
	61	#address-cells = <1>;
	62	#size-cells = <0>;
	63
	64	cpu-map {
	65	cluster0 {
	66	core0 {
	67	cpu = <&cpu0>;
	68	};
	69	core1 {
	70	cpu = <&cpu1>;
	71	};
	72	};
	73
	74	cluster1 {
	75	core0 {
	76	cpu = <&cpu2>;
	77	};
	78	};
	79	};
	80
	81	cpu0: cpu@0 {
	82	device_type = "cpu";
	83	compatible = "arm,cortex-a35";
	84	reg = <0x000>;
f75dd8bd AC	85	clocks = <&mcucfg CLK_MCU_MP0_SEL>,
	86	<&topckgen CLK_TOP_F_MP0_PLL1>;
	87	clock-names = "cpu", "intermediate";
	88	proc-supply = <&cpus_fixed_vproc0>;
	89	operating-points-v2 = <&cluster0_opp>;
f5a3d783	90	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2	91	};
	92
	93	cpu1: cpu@1 {
	94	device_type = "cpu";
	95	compatible = "arm,cortex-a35";
	96	reg = <0x001>;
	97	enable-method = "psci";
f75dd8bd AC	98	clocks = <&mcucfg CLK_MCU_MP0_SEL>,
	99	<&topckgen CLK_TOP_F_MP0_PLL1>;
	100	clock-names = "cpu", "intermediate";
	101	proc-supply = <&cpus_fixed_vproc0>;
	102	operating-points-v2 = <&cluster0_opp>;
f5a3d783	103	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2	104	};
	105
	106	cpu2: cpu@200 {
	107	device_type = "cpu";
	108	compatible = "arm,cortex-a72";
	109	reg = <0x200>;
	110	enable-method = "psci";
f75dd8bd AC	111	clocks = <&mcucfg CLK_MCU_MP2_SEL>,
	112	<&topckgen CLK_TOP_F_BIG_PLL1>;
	113	clock-names = "cpu", "intermediate";
	114	proc-supply = <&cpus_fixed_vproc1>;
	115	operating-points-v2 = <&cluster1_opp>;
f5a3d783 JL	116	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
	117	};
	118
	119	idle-states {
	120	entry-method = "arm,psci";
	121
	122	CPU_SLEEP_0: cpu-sleep-0 {
	123	compatible = "arm,idle-state";
	124	local-timer-stop;
	125	entry-latency-us = <100>;
	126	exit-latency-us = <80>;
	127	min-residency-us = <2000>;
	128	arm,psci-suspend-param = <0x0010000>;
	129	};
	130
	131	CLUSTER_SLEEP_0: cluster-sleep-0 {
	132	compatible = "arm,idle-state";
	133	local-timer-stop;
	134	entry-latency-us = <350>;
	135	exit-latency-us = <80>;
	136	min-residency-us = <3000>;
	137	arm,psci-suspend-param = <0x1010000>;
	138	};
bdf2cbb2	139	};
	140	};
	141
	142	psci {
	143	compatible = "arm,psci-0.2";
	144	method = "smc";
	145	};
	146
	147	baud_clk: dummy26m {
	148	compatible = "fixed-clock";
	149	clock-frequency = <26000000>;
	150	#clock-cells = <0>;
	151	};
	152
	153	sys_clk: dummyclk {
	154	compatible = "fixed-clock";
	155	clock-frequency = <26000000>;
	156	#clock-cells = <0>;
	157	};
	158
5d483970	159	clk26m: oscillator@0 {
	160	compatible = "fixed-clock";
	161	#clock-cells = <0>;
	162	clock-frequency = <26000000>;
	163	clock-output-names = "clk26m";
	164	};
	165
	166	clk32k: oscillator@1 {
	167	compatible = "fixed-clock";
	168	#clock-cells = <0>;
	169	clock-frequency = <32768>;
	170	clock-output-names = "clk32k";
	171	};
	172
	173	clkfpc: oscillator@2 {
	174	compatible = "fixed-clock";
	175	#clock-cells = <0>;
	176	clock-frequency = <50000000>;
	177	clock-output-names = "clkfpc";
	178	};
	179
	180	clkaud_ext_i_0: oscillator@3 {
	181	compatible = "fixed-clock";
	182	#clock-cells = <0>;
	183	clock-frequency = <6500000>;
	184	clock-output-names = "clkaud_ext_i_0";
	185	};
	186
	187	clkaud_ext_i_1: oscillator@4 {
	188	compatible = "fixed-clock";
	189	#clock-cells = <0>;
	190	clock-frequency = <196608000>;
	191	clock-output-names = "clkaud_ext_i_1";
	192	};
	193
	194	clkaud_ext_i_2: oscillator@5 {
	195	compatible = "fixed-clock";
	196	#clock-cells = <0>;
	197	clock-frequency = <180633600>;
	198	clock-output-names = "clkaud_ext_i_2";
	199	};
	200
bdf2cbb2	201	timer {
	202	compatible = "arm,armv8-timer";
	203	interrupt-parent = <&gic>;
	204	interrupts = <GIC_PPI 13
	205	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	206	<GIC_PPI 14
	207	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	208	<GIC_PPI 11
	209	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>,
	210	<GIC_PPI 10
	211	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_LOW)>;
	212	};
	213
5d483970	214	topckgen: syscon@10000000 {
	215	compatible = "mediatek,mt2712-topckgen", "syscon";
	216	reg = <0 0x10000000 0 0x1000>;
	217	#clock-cells = <1>;
	218	};
	219
	220	infracfg: syscon@10001000 {
	221	compatible = "mediatek,mt2712-infracfg", "syscon";
	222	reg = <0 0x10001000 0 0x1000>;
	223	#clock-cells = <1>;
	224	};
	225
	226	pericfg: syscon@10003000 {
	227	compatible = "mediatek,mt2712-pericfg", "syscon";
	228	reg = <0 0x10003000 0 0x1000>;
	229	#clock-cells = <1>;
	230	};
	231
bdf2cbb2	232	uart5: serial@1000f000 {
	233	compatible = "mediatek,mt2712-uart",
	234	"mediatek,mt6577-uart";
	235	reg = <0 0x1000f000 0 0x400>;
	236	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
	237	clocks = <&baud_clk>, <&sys_clk>;
	238	clock-names = "baud", "bus";
	239	status = "disabled";
	240	};
	241
5d483970	242	apmixedsys: syscon@10209000 {
	243	compatible = "mediatek,mt2712-apmixedsys", "syscon";
	244	reg = <0 0x10209000 0 0x1000>;
	245	#clock-cells = <1>;
	246	};
	247
	248	mcucfg: syscon@10220000 {
	249	compatible = "mediatek,mt2712-mcucfg", "syscon";
	250	reg = <0 0x10220000 0 0x1000>;
	251	#clock-cells = <1>;
	252	};
	253
bdf2cbb2	254	sysirq: interrupt-controller@10220a80 {
	255	compatible = "mediatek,mt2712-sysirq",
	256	"mediatek,mt6577-sysirq";
	257	interrupt-controller;
	258	#interrupt-cells = <3>;
	259	interrupt-parent = <&gic>;
	260	reg = <0 0x10220a80 0 0x40>;
	261	};
	262
	263	gic: interrupt-controller@10510000 {
	264	compatible = "arm,gic-400";
	265	#interrupt-cells = <3>;
	266	interrupt-parent = <&gic>;
	267	interrupt-controller;
	268	reg = <0 0x10510000 0 0x10000>,
	269	<0 0x10520000 0 0x20000>,
	270	<0 0x10540000 0 0x20000>,
	271	<0 0x10560000 0 0x20000>;
	272	interrupts = <GIC_PPI 9
	273	(GIC_CPU_MASK_RAW(0x13) \| IRQ_TYPE_LEVEL_HIGH)>;
	274	};
	275
	276	uart0: serial@11002000 {
	277	compatible = "mediatek,mt2712-uart",
	278	"mediatek,mt6577-uart";
	279	reg = <0 0x11002000 0 0x400>;
	280	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
	281	clocks = <&baud_clk>, <&sys_clk>;
	282	clock-names = "baud", "bus";
	283	status = "disabled";
	284	};
	285
	286	uart1: serial@11003000 {
	287	compatible = "mediatek,mt2712-uart",
	288	"mediatek,mt6577-uart";
	289	reg = <0 0x11003000 0 0x400>;
	290	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	291	clocks = <&baud_clk>, <&sys_clk>;
	292	clock-names = "baud", "bus";
	293	status = "disabled";
	294	};
	295
	296	uart2: serial@11004000 {
	297	compatible = "mediatek,mt2712-uart",
	298	"mediatek,mt6577-uart";
	299	reg = <0 0x11004000 0 0x400>;
	300	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
	301	clocks = <&baud_clk>, <&sys_clk>;
	302	clock-names = "baud", "bus";
	303	status = "disabled";
	304	};
	305
	306	uart3: serial@11005000 {
	307	compatible = "mediatek,mt2712-uart",
	308	"mediatek,mt6577-uart";
	309	reg = <0 0x11005000 0 0x400>;
	310	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	311	clocks = <&baud_clk>, <&sys_clk>;
	312	clock-names = "baud", "bus";
	313	status = "disabled";
	314	};
	315
	316	uart4: serial@11019000 {
	317	compatible = "mediatek,mt2712-uart",
318	"mediatek,mt6577-uart";
319	reg = <0 0x11019000 0 0x400>;
320	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
321	clocks = <&baud_clk>, <&sys_clk>;
322	clock-names = "baud", "bus";
323	status = "disabled";
324	};
5d483970	325
	326	mfgcfg: syscon@13000000 {
	327	compatible = "mediatek,mt2712-mfgcfg", "syscon";
	328	reg = <0 0x13000000 0 0x1000>;
	329	#clock-cells = <1>;
	330	};
	331
	332	mmsys: syscon@14000000 {
	333	compatible = "mediatek,mt2712-mmsys", "syscon";
	334	reg = <0 0x14000000 0 0x1000>;
	335	#clock-cells = <1>;
	336	};
	337
	338	imgsys: syscon@15000000 {
	339	compatible = "mediatek,mt2712-imgsys", "syscon";
	340	reg = <0 0x15000000 0 0x1000>;
	341	#clock-cells = <1>;
	342	};
	343
	344	bdpsys: syscon@15010000 {
	345	compatible = "mediatek,mt2712-bdpsys", "syscon";
	346	reg = <0 0x15010000 0 0x1000>;
	347	#clock-cells = <1>;
	348	};
	349
	350	vdecsys: syscon@16000000 {
	351	compatible = "mediatek,mt2712-vdecsys", "syscon";
	352	reg = <0 0x16000000 0 0x1000>;
	353	#clock-cells = <1>;
	354	};
	355
	356	vencsys: syscon@18000000 {
	357	compatible = "mediatek,mt2712-vencsys", "syscon";
	358	reg = <0 0x18000000 0 0x1000>;
	359	#clock-cells = <1>;
	360	};
	361
	362	jpgdecsys: syscon@19000000 {
	363	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
	364	reg = <0 0x19000000 0 0x1000>;
	365	#clock-cells = <1>;
	366	};
bdf2cbb2	367	};
bdf2cbb2	368