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[thirdparty/kernel/linux.git] / arch / arm64 / boot / dts / mediatek / mt2712e.dtsi
CommitLineData
bdf2cbb2 1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: YT Shen <yt.shen@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
5d483970 8#include <dt-bindings/clock/mt2712-clk.h>
bdf2cbb2 9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
e82aa799 11#include <dt-bindings/memory/mt2712-larb-port.h>
1724f4cc 12#include <dt-bindings/phy/phy.h>
ca977a4c 13#include <dt-bindings/power/mt2712-power.h>
f0c64340 14#include "mt2712-pinfunc.h"
bdf2cbb2 15
16/ {
17 compatible = "mediatek,mt2712";
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
6f117db4 22 cluster0_opp: opp-table-0 {
f75dd8bd
AC		 23 compatible = "operating-points-v2";
24 opp-shared;
25 opp00 {
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
28 };
29 opp01 {
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
32 };
33 opp02 {
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
36 };
37 };
38
6f117db4 39 cluster1_opp: opp-table-1 {
f75dd8bd
AC		 40 compatible = "operating-points-v2";
41 opp-shared;
42 opp00 {
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
45 };
46 opp01 {
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
49 };
50 opp02 {
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
53 };
54 opp03 {
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
57 };
58 opp04 {
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
61 };
62 };
63
bdf2cbb2 64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&cpu0>;
72 };
73 core1 {
74 cpu = <&cpu1>;
75 };
76 };
77
78 cluster1 {
79 core0 {
80 cpu = <&cpu2>;
81 };
82 };
83 };
84
85 cpu0: cpu@0 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a35";
88 reg = <0x000>;
f75dd8bd
AC		 89 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
90 <&topckgen CLK_TOP_F_MP0_PLL1>;
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
f5a3d783 94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2 95 };
96
97 cpu1: cpu@1 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a35";
100 reg = <0x001>;
101 enable-method = "psci";
f75dd8bd
AC		 102 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
f5a3d783 107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
bdf2cbb2 108 };
109
110 cpu2: cpu@200 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a72";
113 reg = <0x200>;
114 enable-method = "psci";
f75dd8bd
AC		 115 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
f5a3d783
JL		 120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
121 };
122
123 idle-states {
e9880240 124 entry-method = "psci";
f5a3d783
JL		 125
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
133 };
134
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
142 };
bdf2cbb2 143 };
144 };
145
146 psci {
147 compatible = "arm,psci-0.2";
148 method = "smc";
149 };
150
151 baud_clk: dummy26m {
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
155 };
156
157 sys_clk: dummyclk {
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
161 };
162
e4495a0a 163 clk26m: oscillator-26m {
5d483970 164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
168 };
169
e4495a0a 170 clk32k: oscillator-32k {
5d483970 171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
175 };
176
e4495a0a 177 clkfpc: oscillator-50m {
5d483970 178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
182 };
183
e4495a0a 184 clkaud_ext_i_0: oscillator-aud0 {
5d483970 185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
189 };
190
e4495a0a 191 clkaud_ext_i_1: oscillator-aud1 {
5d483970 192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
196 };
197
e4495a0a 198 clkaud_ext_i_2: oscillator-aud2 {
5d483970 199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
203 };
204
e4495a0a 205 clki2si0_mck_i: oscillator-i2s0 {
f9ce040d 206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
210 };
211
e4495a0a 212 clki2si1_mck_i: oscillator-i2s1 {
f9ce040d 213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
217 };
218
e4495a0a 219 clki2si2_mck_i: oscillator-i2s2 {
f9ce040d 220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
224 };
225
e4495a0a 226 clktdmin_mclk_i: oscillator-mclk {
f9ce040d 227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
231 };
232
bdf2cbb2 233 timer {
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
236 interrupts = <GIC_PPI 13
237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 14
239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
240 <GIC_PPI 11
241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
242 <GIC_PPI 10
243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
244 };
245
5d483970 246 topckgen: syscon@10000000 {
247 compatible = "mediatek,mt2712-topckgen", "syscon";
248 reg = <0 0x10000000 0 0x1000>;
249 #clock-cells = <1>;
250 };
251
252 infracfg: syscon@10001000 {
253 compatible = "mediatek,mt2712-infracfg", "syscon";
254 reg = <0 0x10001000 0 0x1000>;
255 #clock-cells = <1>;
256 };
257
258 pericfg: syscon@10003000 {
259 compatible = "mediatek,mt2712-pericfg", "syscon";
260 reg = <0 0x10003000 0 0x1000>;
261 #clock-cells = <1>;
262 };
263
f0c64340
ZT		 264 syscfg_pctl_a: syscfg_pctl_a@10005000 {
265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
266 reg = <0 0x10005000 0 0x1000>;
267 };
268
1d4516f5 269 pio: pinctrl@1000b000 {
f0c64340
ZT		 270 compatible = "mediatek,mt2712-pinctrl";
271 reg = <0 0x1000b000 0 0x1000>;
272 mediatek,pctl-regmap = <&syscfg_pctl_a>;
f0c64340
ZT		 273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
278 };
279
6fc033b5 280 scpsys: power-controller@10006000 {
ca977a4c 281 compatible = "mediatek,mt2712-scpsys", "syscon";
282 #power-domain-cells = <1>;
283 reg = <0 0x10006000 0 0x1000>;
284 clocks = <&topckgen CLK_TOP_MM_SEL>,
285 <&topckgen CLK_TOP_MFG_SEL>,
286 <&topckgen CLK_TOP_VENC_SEL>,
287 <&topckgen CLK_TOP_JPGDEC_SEL>,
288 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
289 <&topckgen CLK_TOP_VDEC_SEL>;
290 clock-names = "mm", "mfg", "venc",
291 "jpgdec", "audio", "vdec";
292 infracfg = <&infracfg>;
293 };
294
bdf2cbb2 295 uart5: serial@1000f000 {
296 compatible = "mediatek,mt2712-uart",
297 "mediatek,mt6577-uart";
298 reg = <0 0x1000f000 0 0x400>;
299 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
300 clocks = <&baud_clk>, <&sys_clk>;
301 clock-names = "baud", "bus";
21eb9ec7
LC		 302 dmas = <&apdma 10
303 &apdma 11>;
304 dma-names = "tx", "rx";
bdf2cbb2 305 status = "disabled";
306 };
307
836e4a2e
RB		 308 rtc: rtc@10011000 {
309 compatible = "mediatek,mt2712-rtc";
310 reg = <0 0x10011000 0 0x1000>;
311 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
312 };
313
3c2ac5b3
LL		 314 spis1: spi@10013000 {
315 compatible = "mediatek,mt2712-spi-slave";
316 reg = <0 0x10013000 0 0x100>;
317 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
318 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
319 clock-names = "spi";
320 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
321 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
322 status = "disabled";
323 };
324
e82aa799
YS		 325 iommu0: iommu@10205000 {
326 compatible = "mediatek,mt2712-m4u";
327 reg = <0 0x10205000 0 0x1000>;
328 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
329 clocks = <&infracfg CLK_INFRA_M4U>;
330 clock-names = "bclk";
3f180427 331 mediatek,infracfg = <&infracfg>;
33c7874b
NP		 332 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
333 <&larb3>, <&larb6>;
e82aa799
YS		 334 #iommu-cells = <1>;
335 };
336
5d483970 337 apmixedsys: syscon@10209000 {
338 compatible = "mediatek,mt2712-apmixedsys", "syscon";
339 reg = <0 0x10209000 0 0x1000>;
340 #clock-cells = <1>;
341 };
342
e82aa799
YS		 343 iommu1: iommu@1020a000 {
344 compatible = "mediatek,mt2712-m4u";
345 reg = <0 0x1020a000 0 0x1000>;
346 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&infracfg CLK_INFRA_M4U>;
348 clock-names = "bclk";
3f180427 349 mediatek,infracfg = <&infracfg>;
33c7874b 350 mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
e82aa799
YS		 351 #iommu-cells = <1>;
352 };
353
5d483970 354 mcucfg: syscon@10220000 {
355 compatible = "mediatek,mt2712-mcucfg", "syscon";
356 reg = <0 0x10220000 0 0x1000>;
357 #clock-cells = <1>;
358 };
359
bdf2cbb2 360 sysirq: interrupt-controller@10220a80 {
361 compatible = "mediatek,mt2712-sysirq",
362 "mediatek,mt6577-sysirq";
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 interrupt-parent = <&gic>;
366 reg = <0 0x10220a80 0 0x40>;
367 };
368
369 gic: interrupt-controller@10510000 {
370 compatible = "arm,gic-400";
371 #interrupt-cells = <3>;
372 interrupt-parent = <&gic>;
373 interrupt-controller;
374 reg = <0 0x10510000 0 0x10000>,
375 <0 0x10520000 0 0x20000>,
376 <0 0x10540000 0 0x20000>,
377 <0 0x10560000 0 0x20000>;
378 interrupts = <GIC_PPI 9
379 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
380 };
381
21eb9ec7
LC		 382 apdma: dma-controller@11000400 {
383 compatible = "mediatek,mt2712-uart-dma",
384 "mediatek,mt6577-uart-dma";
385 reg = <0 0x11000400 0 0x80>,
386 <0 0x11000480 0 0x80>,
387 <0 0x11000500 0 0x80>,
388 <0 0x11000580 0 0x80>,
389 <0 0x11000600 0 0x80>,
390 <0 0x11000680 0 0x80>,
391 <0 0x11000700 0 0x80>,
392 <0 0x11000780 0 0x80>,
393 <0 0x11000800 0 0x80>,
394 <0 0x11000880 0 0x80>,
395 <0 0x11000900 0 0x80>,
396 <0 0x11000980 0 0x80>;
397 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
398 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
399 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
400 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
401 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
402 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
403 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
404 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
405 <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
406 <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
407 <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
408 <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
409 dma-requests = <12>;
410 clocks = <&pericfg CLK_PERI_AP_DMA>;
411 clock-names = "apdma";
412 #dma-cells = <1>;
413 };
414
5f599552
ZT		 415 auxadc: adc@11001000 {
416 compatible = "mediatek,mt2712-auxadc";
417 reg = <0 0x11001000 0 0x1000>;
418 clocks = <&pericfg CLK_PERI_AUXADC>;
419 clock-names = "main";
420 #io-channel-cells = <1>;
421 status = "disabled";
422 };
423
bdf2cbb2 424 uart0: serial@11002000 {
425 compatible = "mediatek,mt2712-uart",
426 "mediatek,mt6577-uart";
427 reg = <0 0x11002000 0 0x400>;
428 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
429 clocks = <&baud_clk>, <&sys_clk>;
430 clock-names = "baud", "bus";
21eb9ec7
LC		 431 dmas = <&apdma 0
432 &apdma 1>;
433 dma-names = "tx", "rx";
bdf2cbb2 434 status = "disabled";
435 };
436
437 uart1: serial@11003000 {
438 compatible = "mediatek,mt2712-uart",
439 "mediatek,mt6577-uart";
440 reg = <0 0x11003000 0 0x400>;
441 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
442 clocks = <&baud_clk>, <&sys_clk>;
443 clock-names = "baud", "bus";
21eb9ec7
LC		 444 dmas = <&apdma 2
445 &apdma 3>;
446 dma-names = "tx", "rx";
bdf2cbb2 447 status = "disabled";
448 };
449
450 uart2: serial@11004000 {
451 compatible = "mediatek,mt2712-uart",
452 "mediatek,mt6577-uart";
453 reg = <0 0x11004000 0 0x400>;
454 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
455 clocks = <&baud_clk>, <&sys_clk>;
456 clock-names = "baud", "bus";
21eb9ec7
LC		 457 dmas = <&apdma 4
458 &apdma 5>;
459 dma-names = "tx", "rx";
bdf2cbb2 460 status = "disabled";
461 };
462
463 uart3: serial@11005000 {
464 compatible = "mediatek,mt2712-uart",
465 "mediatek,mt6577-uart";
466 reg = <0 0x11005000 0 0x400>;
467 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
468 clocks = <&baud_clk>, <&sys_clk>;
469 clock-names = "baud", "bus";
21eb9ec7
LC		 470 dmas = <&apdma 6
471 &apdma 7>;
472 dma-names = "tx", "rx";
bdf2cbb2 473 status = "disabled";
474 };
475
d85b9774
YS		 476 pwm: pwm@11006000 {
477 compatible = "mediatek,mt2712-pwm";
478 reg = <0 0x11006000 0 0x1000>;
479 #pwm-cells = <2>;
480 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
481 clocks = <&topckgen CLK_TOP_PWM_SEL>,
482 <&pericfg CLK_PERI_PWM>,
483 <&pericfg CLK_PERI_PWM0>,
484 <&pericfg CLK_PERI_PWM1>,
485 <&pericfg CLK_PERI_PWM2>,
486 <&pericfg CLK_PERI_PWM3>,
487 <&pericfg CLK_PERI_PWM4>,
488 <&pericfg CLK_PERI_PWM5>,
489 <&pericfg CLK_PERI_PWM6>,
490 <&pericfg CLK_PERI_PWM7>;
491 clock-names = "top",
492 "main",
493 "pwm1",
494 "pwm2",
495 "pwm3",
496 "pwm4",
497 "pwm5",
498 "pwm6",
499 "pwm7",
500 "pwm8";
501 status = "disabled";
502 };
503
dd00ecfa
YS		 504 i2c0: i2c@11007000 {
505 compatible = "mediatek,mt2712-i2c";
506 reg = <0 0x11007000 0 0x90>,
507 <0 0x11000180 0 0x80>;
508 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
509 clock-div = <4>;
510 clocks = <&pericfg CLK_PERI_I2C0>,
511 <&pericfg CLK_PERI_AP_DMA>;
512 clock-names = "main",
513 "dma";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 status = "disabled";
517 };
518
519 i2c1: i2c@11008000 {
520 compatible = "mediatek,mt2712-i2c";
521 reg = <0 0x11008000 0 0x90>,
522 <0 0x11000200 0 0x80>;
523 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
524 clock-div = <4>;
525 clocks = <&pericfg CLK_PERI_I2C1>,
526 <&pericfg CLK_PERI_AP_DMA>;
527 clock-names = "main",
528 "dma";
529 #address-cells = <1>;
530 #size-cells = <0>;
531 status = "disabled";
532 };
533
534 i2c2: i2c@11009000 {
535 compatible = "mediatek,mt2712-i2c";
536 reg = <0 0x11009000 0 0x90>,
537 <0 0x11000280 0 0x80>;
538 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
539 clock-div = <4>;
540 clocks = <&pericfg CLK_PERI_I2C2>,
541 <&pericfg CLK_PERI_AP_DMA>;
542 clock-names = "main",
543 "dma";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548
9d66740c
YS		 549 spi0: spi@1100a000 {
550 compatible = "mediatek,mt2712-spi";
551 #address-cells = <1>;
552 #size-cells = <0>;
553 reg = <0 0x1100a000 0 0x100>;
554 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
555 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
556 <&topckgen CLK_TOP_SPI_SEL>,
557 <&pericfg CLK_PERI_SPI0>;
558 clock-names = "parent-clk", "sel-clk", "spi-clk";
559 status = "disabled";
560 };
561
a9386c53
YS		 562 nandc: nfi@1100e000 {
563 compatible = "mediatek,mt2712-nfc";
564 reg = <0 0x1100e000 0 0x1000>;
565 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
566 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
567 clock-names = "nfi_clk", "pad_clk";
568 ecc-engine = <&bch>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 status = "disabled";
572 };
573
574 bch: ecc@1100f000 {
575 compatible = "mediatek,mt2712-ecc";
576 reg = <0 0x1100f000 0 0x1000>;
577 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
578 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
579 clock-names = "nfiecc_clk";
580 status = "disabled";
581 };
582
dd00ecfa
YS		 583 i2c3: i2c@11010000 {
584 compatible = "mediatek,mt2712-i2c";
585 reg = <0 0x11010000 0 0x90>,
586 <0 0x11000300 0 0x80>;
587 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
588 clock-div = <4>;
589 clocks = <&pericfg CLK_PERI_I2C3>,
590 <&pericfg CLK_PERI_AP_DMA>;
591 clock-names = "main",
592 "dma";
593 #address-cells = <1>;
594 #size-cells = <0>;
595 status = "disabled";
596 };
597
598 i2c4: i2c@11011000 {
599 compatible = "mediatek,mt2712-i2c";
600 reg = <0 0x11011000 0 0x90>,
601 <0 0x11000380 0 0x80>;
602 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
603 clock-div = <4>;
604 clocks = <&pericfg CLK_PERI_I2C4>,
605 <&pericfg CLK_PERI_AP_DMA>;
606 clock-names = "main",
607 "dma";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 status = "disabled";
611 };
612
613 i2c5: i2c@11013000 {
614 compatible = "mediatek,mt2712-i2c";
615 reg = <0 0x11013000 0 0x90>,
616 <0 0x11000100 0 0x80>;
617 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
618 clock-div = <4>;
619 clocks = <&pericfg CLK_PERI_I2C5>,
620 <&pericfg CLK_PERI_AP_DMA>;
621 clock-names = "main",
622 "dma";
623 #address-cells = <1>;
624 #size-cells = <0>;
625 status = "disabled";
626 };
627
9d66740c
YS		 628 spi2: spi@11015000 {
629 compatible = "mediatek,mt2712-spi";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 reg = <0 0x11015000 0 0x100>;
633 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
634 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
635 <&topckgen CLK_TOP_SPI_SEL>,
636 <&pericfg CLK_PERI_SPI2>;
637 clock-names = "parent-clk", "sel-clk", "spi-clk";
638 status = "disabled";
639 };
640
641 spi3: spi@11016000 {
642 compatible = "mediatek,mt2712-spi";
643 #address-cells = <1>;
644 #size-cells = <0>;
645 reg = <0 0x11016000 0 0x100>;
646 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
647 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
648 <&topckgen CLK_TOP_SPI_SEL>,
649 <&pericfg CLK_PERI_SPI3>;
650 clock-names = "parent-clk", "sel-clk", "spi-clk";
651 status = "disabled";
652 };
653
654 spi4: spi@10012000 {
655 compatible = "mediatek,mt2712-spi";
656 #address-cells = <1>;
657 #size-cells = <0>;
658 reg = <0 0x10012000 0 0x100>;
659 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
660 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
661 <&topckgen CLK_TOP_SPI_SEL>,
662 <&infracfg CLK_INFRA_AO_SPI0>;
663 clock-names = "parent-clk", "sel-clk", "spi-clk";
664 status = "disabled";
665 };
666
667 spi5: spi@11018000 {
668 compatible = "mediatek,mt2712-spi";
669 #address-cells = <1>;
670 #size-cells = <0>;
671 reg = <0 0x11018000 0 0x100>;
672 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
673 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
674 <&topckgen CLK_TOP_SPI_SEL>,
675 <&pericfg CLK_PERI_SPI5>;
676 clock-names = "parent-clk", "sel-clk", "spi-clk";
677 status = "disabled";
678 };
679
bdf2cbb2 680 uart4: serial@11019000 {
681 compatible = "mediatek,mt2712-uart",
682 "mediatek,mt6577-uart";
683 reg = <0 0x11019000 0 0x400>;
684 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
685 clocks = <&baud_clk>, <&sys_clk>;
686 clock-names = "baud", "bus";
21eb9ec7
LC		 687 dmas = <&apdma 8
688 &apdma 9>;
689 dma-names = "tx", "rx";
bdf2cbb2 690 status = "disabled";
691 };
5d483970 692
e9cabfd0
BH		 693 stmmac_axi_setup: stmmac-axi-config {
694 snps,wr_osr_lmt = <0x7>;
695 snps,rd_osr_lmt = <0x7>;
696 snps,blen = <0 0 0 0 16 8 4>;
697 };
698
699 mtl_rx_setup: rx-queues-config {
700 snps,rx-queues-to-use = <1>;
701 snps,rx-sched-sp;
702 queue0 {
703 snps,dcb-algorithm;
704 snps,map-to-dma-channel = <0x0>;
705 snps,priority = <0x0>;
706 };
707 };
708
709 mtl_tx_setup: tx-queues-config {
710 snps,tx-queues-to-use = <3>;
711 snps,tx-sched-wrr;
712 queue0 {
713 snps,weight = <0x10>;
714 snps,dcb-algorithm;
715 snps,priority = <0x0>;
716 };
717 queue1 {
718 snps,weight = <0x11>;
719 snps,dcb-algorithm;
720 snps,priority = <0x1>;
721 };
722 queue2 {
723 snps,weight = <0x12>;
724 snps,dcb-algorithm;
725 snps,priority = <0x2>;
726 };
727 };
728
729 eth: ethernet@1101c000 {
79e11778 730 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
e9cabfd0
BH		 731 reg = <0 0x1101c000 0 0x1300>;
732 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
733 interrupt-names = "macirq";
734 mac-address = [00 55 7b b5 7d f7];
735 clock-names = "axi",
736 "apb",
737 "mac_main",
79e11778
BH		 738 "ptp_ref",
739 "rmii_internal";
e9cabfd0
BH		 740 clocks = <&pericfg CLK_PERI_GMAC>,
741 <&pericfg CLK_PERI_GMAC_PCLK>,
742 <&topckgen CLK_TOP_ETHER_125M_SEL>,
79e11778
BH		 743 <&topckgen CLK_TOP_ETHER_50M_SEL>,
744 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
e9cabfd0 745 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
79e11778
BH		 746 <&topckgen CLK_TOP_ETHER_50M_SEL>,
747 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
e9cabfd0 748 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
79e11778
BH		 749 <&topckgen CLK_TOP_APLL1_D3>,
750 <&topckgen CLK_TOP_ETHERPLL_50M>;
e9cabfd0
BH		 751 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
752 mediatek,pericfg = <&pericfg>;
753 snps,axi-config = <&stmmac_axi_setup>;
754 snps,mtl-rx-config = <&mtl_rx_setup>;
755 snps,mtl-tx-config = <&mtl_tx_setup>;
756 snps,txpbl = <1>;
757 snps,rxpbl = <1>;
7871785c 758 snps,clk-csr = <0>;
e9cabfd0
BH		 759 status = "disabled";
760 };
761
db0b58d8
YS		 762 mmc0: mmc@11230000 {
763 compatible = "mediatek,mt2712-mmc";
764 reg = <0 0x11230000 0 0x1000>;
765 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
766 clocks = <&pericfg CLK_PERI_MSDC30_0>,
767 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
b747fa22
FW		 768 <&pericfg CLK_PERI_MSDC50_0_EN>,
769 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>;
770 clock-names = "source", "hclk", "source_cg", "bus_clk";
db0b58d8
YS		 771 status = "disabled";
772 };
773
774 mmc1: mmc@11240000 {
775 compatible = "mediatek,mt2712-mmc";
776 reg = <0 0x11240000 0 0x1000>;
777 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
778 clocks = <&pericfg CLK_PERI_MSDC30_1>,
779 <&topckgen CLK_TOP_AXI_SEL>,
780 <&pericfg CLK_PERI_MSDC30_1_EN>;
781 clock-names = "source", "hclk", "source_cg";
782 status = "disabled";
783 };
784
785 mmc2: mmc@11250000 {
786 compatible = "mediatek,mt2712-mmc";
787 reg = <0 0x11250000 0 0x1000>;
788 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
789 clocks = <&pericfg CLK_PERI_MSDC30_2>,
790 <&topckgen CLK_TOP_AXI_SEL>,
791 <&pericfg CLK_PERI_MSDC30_2_EN>;
792 clock-names = "source", "hclk", "source_cg";
793 status = "disabled";
794 };
795
1724f4cc
CY		 796 ssusb: usb@11271000 {
797 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
798 reg = <0 0x11271000 0 0x3000>,
799 <0 0x11280700 0 0x0100>;
800 reg-names = "mac", "ippc";
801 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
802 phys = <&u2port0 PHY_TYPE_USB2>,
803 <&u2port1 PHY_TYPE_USB2>;
804 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
805 clocks = <&topckgen CLK_TOP_USB30_SEL>;
806 clock-names = "sys_ck";
807 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
808 #address-cells = <2>;
809 #size-cells = <2>;
810 ranges;
811 status = "disabled";
812
357c5f71 813 usb_host0: usb@11270000 {
1724f4cc
CY		 814 compatible = "mediatek,mt2712-xhci",
815 "mediatek,mtk-xhci";
816 reg = <0 0x11270000 0 0x1000>;
817 reg-names = "mac";
818 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
819 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
820 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
821 clock-names = "sys_ck", "ref_ck";
822 status = "disabled";
823 };
824 };
825
357c5f71 826 u3phy0: t-phy@11290000 {
f0210518
CY		 827 compatible = "mediatek,mt2712-tphy",
828 "mediatek,generic-tphy-v2";
829 #address-cells = <1>;
830 #size-cells = <1>;
831 ranges = <0 0 0x11290000 0x9000>;
1724f4cc
CY		 832 status = "okay";
833
f0210518
CY		 834 u2port0: usb-phy@0 {
835 reg = <0x0 0x700>;
1724f4cc
CY		 836 clocks = <&clk26m>;
837 clock-names = "ref";
838 #phy-cells = <1>;
839 status = "okay";
840 };
841
f0210518
CY		 842 u2port1: usb-phy@8000 {
843 reg = <0x8000 0x700>;
1724f4cc
CY		 844 clocks = <&clk26m>;
845 clock-names = "ref";
846 #phy-cells = <1>;
847 status = "okay";
848 };
849
f0210518
CY		 850 u3port0: usb-phy@8700 {
851 reg = <0x8700 0x900>;
1724f4cc
CY		 852 clocks = <&clk26m>;
853 clock-names = "ref";
854 #phy-cells = <1>;
855 status = "okay";
856 };
857 };
858
859 ssusb1: usb@112c1000 {
860 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
861 reg = <0 0x112c1000 0 0x3000>,
862 <0 0x112d0700 0 0x0100>;
863 reg-names = "mac", "ippc";
864 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
865 phys = <&u2port2 PHY_TYPE_USB2>,
866 <&u2port3 PHY_TYPE_USB2>,
867 <&u3port1 PHY_TYPE_USB3>;
868 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
869 clocks = <&topckgen CLK_TOP_USB30_SEL>;
870 clock-names = "sys_ck";
871 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
872 #address-cells = <2>;
873 #size-cells = <2>;
874 ranges;
875 status = "disabled";
876
357c5f71 877 usb_host1: usb@112c0000 {
1724f4cc
CY		 878 compatible = "mediatek,mt2712-xhci",
879 "mediatek,mtk-xhci";
880 reg = <0 0x112c0000 0 0x1000>;
881 reg-names = "mac";
882 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
883 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
884 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
885 clock-names = "sys_ck", "ref_ck";
886 status = "disabled";
887 };
888 };
889
357c5f71 890 u3phy1: t-phy@112e0000 {
f0210518
CY		 891 compatible = "mediatek,mt2712-tphy",
892 "mediatek,generic-tphy-v2";
893 #address-cells = <1>;
894 #size-cells = <1>;
895 ranges = <0 0 0x112e0000 0x9000>;
1724f4cc
CY		 896 status = "okay";
897
f0210518
CY		 898 u2port2: usb-phy@0 {
899 reg = <0x0 0x700>;
1724f4cc
CY		 900 clocks = <&clk26m>;
901 clock-names = "ref";
902 #phy-cells = <1>;
903 status = "okay";
904 };
905
f0210518
CY		 906 u2port3: usb-phy@8000 {
907 reg = <0x8000 0x700>;
1724f4cc
CY		 908 clocks = <&clk26m>;
909 clock-names = "ref";
910 #phy-cells = <1>;
911 status = "okay";
912 };
913
f0210518
CY		 914 u3port1: usb-phy@8700 {
915 reg = <0x8700 0x900>;
1724f4cc
CY		 916 clocks = <&clk26m>;
917 clock-names = "ref";
918 #phy-cells = <1>;
919 status = "okay";
920 };
921 };
922
c99c4733 923 pcie1: pcie@112ff000 {
a807d5d7
HZ		 924 compatible = "mediatek,mt2712-pcie";
925 device_type = "pci";
c99c4733
CL		 926 reg = <0 0x112ff000 0 0x1000>;
927 reg-names = "port1";
928 linux,pci-domain = <1>;
a807d5d7
HZ		 929 #address-cells = <3>;
930 #size-cells = <2>;
c99c4733
CL		 931 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
932 interrupt-names = "pcie_irq";
933 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
a807d5d7 934 <&pericfg CLK_PERI_PCIE1>;
c99c4733
CL		 935 clock-names = "sys_ck1", "ahb_ck1";
936 phys = <&u3port1 PHY_TYPE_PCIE>;
937 phy-names = "pcie-phy1";
a807d5d7 938 bus-range = <0x00 0xff>;
c99c4733
CL		 939 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
940 status = "disabled";
a807d5d7 941
c99c4733
CL		 942 #interrupt-cells = <1>;
943 interrupt-map-mask = <0 0 0 7>;
944 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
945 <0 0 0 2 &pcie_intc1 1>,
946 <0 0 0 3 &pcie_intc1 2>,
947 <0 0 0 4 &pcie_intc1 3>;
948 pcie_intc1: interrupt-controller {
949 interrupt-controller;
950 #address-cells = <0>;
a807d5d7 951 #interrupt-cells = <1>;
a807d5d7 952 };
c99c4733 953 };
a807d5d7 954
c99c4733
CL		 955 pcie0: pcie@11700000 {
956 compatible = "mediatek,mt2712-pcie";
957 device_type = "pci";
958 reg = <0 0x11700000 0 0x1000>;
959 reg-names = "port0";
960 linux,pci-domain = <0>;
961 #address-cells = <3>;
962 #size-cells = <2>;
963 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
964 interrupt-names = "pcie_irq";
965 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
966 <&pericfg CLK_PERI_PCIE0>;
967 clock-names = "sys_ck0", "ahb_ck0";
968 phys = <&u3port0 PHY_TYPE_PCIE>;
969 phy-names = "pcie-phy0";
970 bus-range = <0x00 0xff>;
971 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
972 status = "disabled";
973
974 #interrupt-cells = <1>;
975 interrupt-map-mask = <0 0 0 7>;
976 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
977 <0 0 0 2 &pcie_intc0 1>,
978 <0 0 0 3 &pcie_intc0 2>,
979 <0 0 0 4 &pcie_intc0 3>;
980 pcie_intc0: interrupt-controller {
981 interrupt-controller;
982 #address-cells = <0>;
a807d5d7 983 #interrupt-cells = <1>;
a807d5d7
HZ		 984 };
985 };
986
5d483970 987 mfgcfg: syscon@13000000 {
988 compatible = "mediatek,mt2712-mfgcfg", "syscon";
989 reg = <0 0x13000000 0 0x1000>;
990 #clock-cells = <1>;
991 };
992
993 mmsys: syscon@14000000 {
994 compatible = "mediatek,mt2712-mmsys", "syscon";
995 reg = <0 0x14000000 0 0x1000>;
996 #clock-cells = <1>;
997 };
998
e82aa799
YS		 999 larb0: larb@14021000 {
1000 compatible = "mediatek,mt2712-smi-larb";
1001 reg = <0 0x14021000 0 0x1000>;
1002 mediatek,smi = <&smi_common0>;
1003 mediatek,larb-id = <0>;
1004 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1005 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1006 <&mmsys CLK_MM_SMI_LARB0>;
1007 clock-names = "apb", "smi";
1008 };
1009
1010 smi_common0: smi@14022000 {
1011 compatible = "mediatek,mt2712-smi-common";
1012 reg = <0 0x14022000 0 0x1000>;
1013 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1014 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1015 <&mmsys CLK_MM_SMI_COMMON>;
1016 clock-names = "apb", "smi";
1017 };
1018
1019 larb4: larb@14027000 {
1020 compatible = "mediatek,mt2712-smi-larb";
1021 reg = <0 0x14027000 0 0x1000>;
1022 mediatek,smi = <&smi_common1>;
1023 mediatek,larb-id = <4>;
1024 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1025 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1026 <&mmsys CLK_MM_SMI_LARB4>;
1027 clock-names = "apb", "smi";
1028 };
1029
1030 larb5: larb@14030000 {
1031 compatible = "mediatek,mt2712-smi-larb";
1032 reg = <0 0x14030000 0 0x1000>;
1033 mediatek,smi = <&smi_common1>;
1034 mediatek,larb-id = <5>;
1035 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1036 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1037 <&mmsys CLK_MM_SMI_LARB5>;
1038 clock-names = "apb", "smi";
1039 };
1040
1041 smi_common1: smi@14031000 {
1042 compatible = "mediatek,mt2712-smi-common";
1043 reg = <0 0x14031000 0 0x1000>;
1044 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1045 clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1046 <&mmsys CLK_MM_SMI_COMMON1>;
1047 clock-names = "apb", "smi";
1048 };
1049
1050 larb7: larb@14032000 {
1051 compatible = "mediatek,mt2712-smi-larb";
1052 reg = <0 0x14032000 0 0x1000>;
1053 mediatek,smi = <&smi_common1>;
1054 mediatek,larb-id = <7>;
1055 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1056 clocks = <&mmsys CLK_MM_SMI_LARB7>,
1057 <&mmsys CLK_MM_SMI_LARB7>;
1058 clock-names = "apb", "smi";
1059 };
1060
5d483970 1061 imgsys: syscon@15000000 {
1062 compatible = "mediatek,mt2712-imgsys", "syscon";
1063 reg = <0 0x15000000 0 0x1000>;
1064 #clock-cells = <1>;
1065 };
1066
e82aa799
YS		 1067 larb2: larb@15001000 {
1068 compatible = "mediatek,mt2712-smi-larb";
1069 reg = <0 0x15001000 0 0x1000>;
1070 mediatek,smi = <&smi_common0>;
1071 mediatek,larb-id = <2>;
1072 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1073 clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1074 <&imgsys CLK_IMG_SMI_LARB2>;
1075 clock-names = "apb", "smi";
1076 };
1077
5d483970 1078 bdpsys: syscon@15010000 {
1079 compatible = "mediatek,mt2712-bdpsys", "syscon";
1080 reg = <0 0x15010000 0 0x1000>;
1081 #clock-cells = <1>;
1082 };
1083
1084 vdecsys: syscon@16000000 {
1085 compatible = "mediatek,mt2712-vdecsys", "syscon";
1086 reg = <0 0x16000000 0 0x1000>;
1087 #clock-cells = <1>;
1088 };
1089
e82aa799
YS		 1090 larb1: larb@16010000 {
1091 compatible = "mediatek,mt2712-smi-larb";
1092 reg = <0 0x16010000 0 0x1000>;
1093 mediatek,smi = <&smi_common0>;
1094 mediatek,larb-id = <1>;
1095 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1096 clocks = <&vdecsys CLK_VDEC_CKEN>,
1097 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1098 clock-names = "apb", "smi";
1099 };
1100
5d483970 1101 vencsys: syscon@18000000 {
1102 compatible = "mediatek,mt2712-vencsys", "syscon";
1103 reg = <0 0x18000000 0 0x1000>;
1104 #clock-cells = <1>;
1105 };
1106
e82aa799
YS		 1107 larb3: larb@18001000 {
1108 compatible = "mediatek,mt2712-smi-larb";
1109 reg = <0 0x18001000 0 0x1000>;
1110 mediatek,smi = <&smi_common0>;
1111 mediatek,larb-id = <3>;
1112 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1113 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1114 <&vencsys CLK_VENC_VENC>;
1115 clock-names = "apb", "smi";
1116 };
1117
1118 larb6: larb@18002000 {
1119 compatible = "mediatek,mt2712-smi-larb";
1120 reg = <0 0x18002000 0 0x1000>;
1121 mediatek,smi = <&smi_common0>;
1122 mediatek,larb-id = <6>;
1123 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1124 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1125 <&vencsys CLK_VENC_VENC>;
1126 clock-names = "apb", "smi";
1127 };
1128
5d483970 1129 jpgdecsys: syscon@19000000 {
1130 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1131 reg = <0 0x19000000 0 0x1000>;
1132 #clock-cells = <1>;
1133 };
bdf2cbb2 1134};
1135
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