projects / people / ms / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b7e8f433 VK |
1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* | |
| 4f23d2a5 | 3 | * Copyright (c) 2020, Linaro Limited |
| b7e8f433 VK |
4 | */ |
| 5 | ||
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 6d91e201 | 7 | #include <dt-bindings/clock/qcom,gcc-sm8350.h> |
| b7e8f433 | 8 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 84c856d0 | 9 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
| b7e8f433 | 10 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
| b7e8f433 VK |
11 | #include <dt-bindings/power/qcom-rpmpd.h> |
| 12 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> | |
| 20f9d94e | 13 | #include <dt-bindings/thermal/thermal.h> |
| f11d3e7d | 14 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
| b7e8f433 VK |
15 | |
| 16 | / { | |
| 17 | interrupt-parent = <&intc>; | |
| 18 | ||
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <2>; | |
| 21 | ||
| 22 | chosen { }; | |
| 23 | ||
| 24 | clocks { | |
| 25 | xo_board: xo-board { | |
| 26 | compatible = "fixed-clock"; | |
| 27 | #clock-cells = <0>; | |
| 28 | clock-frequency = <38400000>; | |
| 29 | clock-output-names = "xo_board"; | |
| 30 | }; | |
| 31 | ||
| 32 | sleep_clk: sleep-clk { | |
| 33 | compatible = "fixed-clock"; | |
| 34 | clock-frequency = <32000>; | |
| 35 | #clock-cells = <0>; | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 39 | cpus { | |
| 40 | #address-cells = <2>; | |
| 41 | #size-cells = <0>; | |
| 42 | ||
| 43 | CPU0: cpu@0 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "qcom,kryo685"; | |
| 46 | reg = <0x0 0x0>; | |
| 47 | enable-method = "psci"; | |
| 48 | next-level-cache = <&L2_0>; | |
| ccbb3abb | 49 | qcom,freq-domain = <&cpufreq_hw 0>; |
| 20f9d94e | 50 | #cooling-cells = <2>; |
| b7e8f433 VK |
51 | L2_0: l2-cache { |
| 52 | compatible = "cache"; | |
| 53 | next-level-cache = <&L3_0>; | |
| 54 | L3_0: l3-cache { | |
| 55 | compatible = "cache"; | |
| 56 | }; | |
| 57 | }; | |
| 58 | }; | |
| 59 | ||
| 60 | CPU1: cpu@100 { | |
| 61 | device_type = "cpu"; | |
| 62 | compatible = "qcom,kryo685"; | |
| 63 | reg = <0x0 0x100>; | |
| 64 | enable-method = "psci"; | |
| 65 | next-level-cache = <&L2_100>; | |
| ccbb3abb | 66 | qcom,freq-domain = <&cpufreq_hw 0>; |
| 20f9d94e | 67 | #cooling-cells = <2>; |
| b7e8f433 VK |
68 | L2_100: l2-cache { |
| 69 | compatible = "cache"; | |
| 70 | next-level-cache = <&L3_0>; | |
| 71 | }; | |
| 72 | }; | |
| 73 | ||
| 74 | CPU2: cpu@200 { | |
| 75 | device_type = "cpu"; | |
| 76 | compatible = "qcom,kryo685"; | |
| 77 | reg = <0x0 0x200>; | |
| 78 | enable-method = "psci"; | |
| 79 | next-level-cache = <&L2_200>; | |
| ccbb3abb | 80 | qcom,freq-domain = <&cpufreq_hw 0>; |
| 20f9d94e | 81 | #cooling-cells = <2>; |
| b7e8f433 VK |
82 | L2_200: l2-cache { |
| 83 | compatible = "cache"; | |
| 84 | next-level-cache = <&L3_0>; | |
| 85 | }; | |
| 86 | }; | |
| 87 | ||
| 88 | CPU3: cpu@300 { | |
| 89 | device_type = "cpu"; | |
| 90 | compatible = "qcom,kryo685"; | |
| 91 | reg = <0x0 0x300>; | |
| 92 | enable-method = "psci"; | |
| 93 | next-level-cache = <&L2_300>; | |
| ccbb3abb | 94 | qcom,freq-domain = <&cpufreq_hw 0>; |
| 20f9d94e | 95 | #cooling-cells = <2>; |
| b7e8f433 VK |
96 | L2_300: l2-cache { |
| 97 | compatible = "cache"; | |
| 98 | next-level-cache = <&L3_0>; | |
| 99 | }; | |
| 100 | }; | |
| 101 | ||
| 102 | CPU4: cpu@400 { | |
| 103 | device_type = "cpu"; | |
| 104 | compatible = "qcom,kryo685"; | |
| 105 | reg = <0x0 0x400>; | |
| 106 | enable-method = "psci"; | |
| 107 | next-level-cache = <&L2_400>; | |
| ccbb3abb | 108 | qcom,freq-domain = <&cpufreq_hw 1>; |
| 20f9d94e | 109 | #cooling-cells = <2>; |
| b7e8f433 VK |
110 | L2_400: l2-cache { |
| 111 | compatible = "cache"; | |
| 112 | next-level-cache = <&L3_0>; | |
| 113 | }; | |
| 114 | }; | |
| 115 | ||
| 116 | CPU5: cpu@500 { | |
| 117 | device_type = "cpu"; | |
| 118 | compatible = "qcom,kryo685"; | |
| 119 | reg = <0x0 0x500>; | |
| 120 | enable-method = "psci"; | |
| 121 | next-level-cache = <&L2_500>; | |
| ccbb3abb | 122 | qcom,freq-domain = <&cpufreq_hw 1>; |
| 20f9d94e | 123 | #cooling-cells = <2>; |
| b7e8f433 VK |
124 | L2_500: l2-cache { |
| 125 | compatible = "cache"; | |
| 126 | next-level-cache = <&L3_0>; | |
| 127 | }; | |
| 128 | ||
| 129 | }; | |
| 130 | ||
| 131 | CPU6: cpu@600 { | |
| 132 | device_type = "cpu"; | |
| 133 | compatible = "qcom,kryo685"; | |
| 134 | reg = <0x0 0x600>; | |
| 135 | enable-method = "psci"; | |
| 136 | next-level-cache = <&L2_600>; | |
| ccbb3abb | 137 | qcom,freq-domain = <&cpufreq_hw 1>; |
| 20f9d94e | 138 | #cooling-cells = <2>; |
| b7e8f433 VK |
139 | L2_600: l2-cache { |
| 140 | compatible = "cache"; | |
| 141 | next-level-cache = <&L3_0>; | |
| 142 | }; | |
| 143 | }; | |
| 144 | ||
| 145 | CPU7: cpu@700 { | |
| 146 | device_type = "cpu"; | |
| 147 | compatible = "qcom,kryo685"; | |
| 148 | reg = <0x0 0x700>; | |
| 149 | enable-method = "psci"; | |
| 150 | next-level-cache = <&L2_700>; | |
| ccbb3abb | 151 | qcom,freq-domain = <&cpufreq_hw 2>; |
| 20f9d94e | 152 | #cooling-cells = <2>; |
| b7e8f433 VK |
153 | L2_700: l2-cache { |
| 154 | compatible = "cache"; | |
| 155 | next-level-cache = <&L3_0>; | |
| 156 | }; | |
| 157 | }; | |
| 158 | }; | |
| 159 | ||
| 160 | firmware { | |
| 161 | scm: scm { | |
| 162 | compatible = "qcom,scm-sm8350", "qcom,scm"; | |
| 163 | #reset-cells = <1>; | |
| 164 | }; | |
| 165 | }; | |
| 166 | ||
| 167 | memory@80000000 { | |
| 168 | device_type = "memory"; | |
| 169 | /* We expect the bootloader to fill in the size */ | |
| 170 | reg = <0x0 0x80000000 0x0 0x0>; | |
| 171 | }; | |
| 172 | ||
| 173 | pmu { | |
| 174 | compatible = "arm,armv8-pmuv3"; | |
| 794d3e30 | 175 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| b7e8f433 VK |
176 | }; |
| 177 | ||
| 178 | psci { | |
| 179 | compatible = "arm,psci-1.0"; | |
| 180 | method = "smc"; | |
| 181 | }; | |
| 182 | ||
| 183 | reserved_memory: reserved-memory { | |
| 184 | #address-cells = <2>; | |
| 185 | #size-cells = <2>; | |
| 186 | ranges; | |
| 187 | ||
| 188 | hyp_mem: memory@80000000 { | |
| 189 | reg = <0x0 0x80000000 0x0 0x600000>; | |
| 190 | no-map; | |
| 191 | }; | |
| 192 | ||
| 193 | xbl_aop_mem: memory@80700000 { | |
| 194 | no-map; | |
| 195 | reg = <0x0 0x80700000 0x0 0x160000>; | |
| 196 | }; | |
| 197 | ||
| 198 | cmd_db: memory@80860000 { | |
| 199 | compatible = "qcom,cmd-db"; | |
| 200 | reg = <0x0 0x80860000 0x0 0x20000>; | |
| 201 | no-map; | |
| 202 | }; | |
| 203 | ||
| 204 | reserved_xbl_uefi_log: memory@80880000 { | |
| 205 | reg = <0x0 0x80880000 0x0 0x14000>; | |
| 206 | no-map; | |
| 207 | }; | |
| 208 | ||
| 209 | smem_mem: memory@80900000 { | |
| 210 | reg = <0x0 0x80900000 0x0 0x200000>; | |
| 211 | no-map; | |
| 212 | }; | |
| 213 | ||
| 214 | cpucp_fw_mem: memory@80b00000 { | |
| 215 | reg = <0x0 0x80b00000 0x0 0x100000>; | |
| 216 | no-map; | |
| 217 | }; | |
| 218 | ||
| 219 | cdsp_secure_heap: memory@80c00000 { | |
| 220 | reg = <0x0 0x80c00000 0x0 0x4600000>; | |
| 221 | no-map; | |
| 222 | }; | |
| 223 | ||
| 224 | pil_camera_mem: mmeory@85200000 { | |
| 225 | reg = <0x0 0x85200000 0x0 0x500000>; | |
| 226 | no-map; | |
| 227 | }; | |
| 228 | ||
| 229 | pil_video_mem: memory@85700000 { | |
| 230 | reg = <0x0 0x85700000 0x0 0x500000>; | |
| 231 | no-map; | |
| 232 | }; | |
| 233 | ||
| 234 | pil_cvp_mem: memory@85c00000 { | |
| 235 | reg = <0x0 0x85c00000 0x0 0x500000>; | |
| 236 | no-map; | |
| 237 | }; | |
| 238 | ||
| 239 | pil_adsp_mem: memory@86100000 { | |
| 240 | reg = <0x0 0x86100000 0x0 0x2100000>; | |
| 241 | no-map; | |
| 242 | }; | |
| 243 | ||
| 244 | pil_slpi_mem: memory@88200000 { | |
| 245 | reg = <0x0 0x88200000 0x0 0x1500000>; | |
| 246 | no-map; | |
| 247 | }; | |
| 248 | ||
| 249 | pil_cdsp_mem: memory@89700000 { | |
| 250 | reg = <0x0 0x89700000 0x0 0x1e00000>; | |
| 251 | no-map; | |
| 252 | }; | |
| 253 | ||
| 254 | pil_ipa_fw_mem: memory@8b500000 { | |
| 255 | reg = <0x0 0x8b500000 0x0 0x10000>; | |
| 256 | no-map; | |
| 257 | }; | |
| 258 | ||
| 259 | pil_ipa_gsi_mem: memory@8b510000 { | |
| 260 | reg = <0x0 0x8b510000 0x0 0xa000>; | |
| 261 | no-map; | |
| 262 | }; | |
| 263 | ||
| 264 | pil_gpu_mem: memory@8b51a000 { | |
| 265 | reg = <0x0 0x8b51a000 0x0 0x2000>; | |
| 266 | no-map; | |
| 267 | }; | |
| 268 | ||
| 269 | pil_spss_mem: memory@8b600000 { | |
| 270 | reg = <0x0 0x8b600000 0x0 0x100000>; | |
| 271 | no-map; | |
| 272 | }; | |
| 273 | ||
| 274 | pil_modem_mem: memory@8b800000 { | |
| 275 | reg = <0x0 0x8b800000 0x0 0x10000000>; | |
| 276 | no-map; | |
| 277 | }; | |
| 278 | ||
| 774890c9 VK |
279 | rmtfs_mem: memory@9b800000 { |
| 280 | compatible = "qcom,rmtfs-mem"; | |
| 281 | reg = <0x0 0x9b800000 0x0 0x280000>; | |
| 282 | no-map; | |
| 283 | ||
| 284 | qcom,client-id = <1>; | |
| 285 | qcom,vmid = <15>; | |
| 286 | }; | |
| 287 | ||
| b7e8f433 VK |
288 | hyp_reserved_mem: memory@d0000000 { |
| 289 | reg = <0x0 0xd0000000 0x0 0x800000>; | |
| 290 | no-map; | |
| 291 | }; | |
| 292 | ||
| 293 | pil_trustedvm_mem: memory@d0800000 { | |
| 294 | reg = <0x0 0xd0800000 0x0 0x76f7000>; | |
| 295 | no-map; | |
| 296 | }; | |
| 297 | ||
| 298 | qrtr_shbuf: memory@d7ef7000 { | |
| 299 | reg = <0x0 0xd7ef7000 0x0 0x9000>; | |
| 300 | no-map; | |
| 301 | }; | |
| 302 | ||
| 303 | chan0_shbuf: memory@d7f00000 { | |
| 304 | reg = <0x0 0xd7f00000 0x0 0x80000>; | |
| 305 | no-map; | |
| 306 | }; | |
| 307 | ||
| 308 | chan1_shbuf: memory@d7f80000 { | |
| 309 | reg = <0x0 0xd7f80000 0x0 0x80000>; | |
| 310 | no-map; | |
| 311 | }; | |
| 312 | ||
| 313 | removed_mem: memory@d8800000 { | |
| 314 | reg = <0x0 0xd8800000 0x0 0x6800000>; | |
| 315 | no-map; | |
| 316 | }; | |
| 317 | }; | |
| 318 | ||
| 319 | smem: qcom,smem { | |
| 320 | compatible = "qcom,smem"; | |
| 321 | memory-region = <&smem_mem>; | |
| 322 | hwlocks = <&tcsr_mutex 3>; | |
| 323 | }; | |
| 324 | ||
| 03a41991 VK |
325 | smp2p-adsp { |
| 326 | compatible = "qcom,smp2p"; | |
| 327 | qcom,smem = <443>, <429>; | |
| 328 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 329 | IPCC_MPROC_SIGNAL_SMP2P | |
| 330 | IRQ_TYPE_EDGE_RISING>; | |
| 331 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 332 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 333 | ||
| 334 | qcom,local-pid = <0>; | |
| 335 | qcom,remote-pid = <2>; | |
| 336 | ||
| 337 | smp2p_adsp_out: master-kernel { | |
| 338 | qcom,entry-name = "master-kernel"; | |
| 339 | #qcom,smem-state-cells = <1>; | |
| 340 | }; | |
| 341 | ||
| 342 | smp2p_adsp_in: slave-kernel { | |
| 343 | qcom,entry-name = "slave-kernel"; | |
| 344 | interrupt-controller; | |
| 345 | #interrupt-cells = <2>; | |
| 346 | }; | |
| 347 | }; | |
| 348 | ||
| 349 | smp2p-cdsp { | |
| 350 | compatible = "qcom,smp2p"; | |
| 351 | qcom,smem = <94>, <432>; | |
| 352 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 353 | IPCC_MPROC_SIGNAL_SMP2P | |
| 354 | IRQ_TYPE_EDGE_RISING>; | |
| 355 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 356 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 357 | ||
| 358 | qcom,local-pid = <0>; | |
| 359 | qcom,remote-pid = <5>; | |
| 360 | ||
| 361 | smp2p_cdsp_out: master-kernel { | |
| 362 | qcom,entry-name = "master-kernel"; | |
| 363 | #qcom,smem-state-cells = <1>; | |
| 364 | }; | |
| 365 | ||
| 366 | smp2p_cdsp_in: slave-kernel { | |
| 367 | qcom,entry-name = "slave-kernel"; | |
| 368 | interrupt-controller; | |
| 369 | #interrupt-cells = <2>; | |
| 370 | }; | |
| 371 | }; | |
| 372 | ||
| 373 | smp2p-modem { | |
| 374 | compatible = "qcom,smp2p"; | |
| 375 | qcom,smem = <435>, <428>; | |
| 376 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
| 377 | IPCC_MPROC_SIGNAL_SMP2P | |
| 378 | IRQ_TYPE_EDGE_RISING>; | |
| 379 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
| 380 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 381 | ||
| 382 | qcom,local-pid = <0>; | |
| 383 | qcom,remote-pid = <1>; | |
| 384 | ||
| 385 | smp2p_modem_out: master-kernel { | |
| 386 | qcom,entry-name = "master-kernel"; | |
| 387 | #qcom,smem-state-cells = <1>; | |
| 388 | }; | |
| 389 | ||
| 390 | smp2p_modem_in: slave-kernel { | |
| 391 | qcom,entry-name = "slave-kernel"; | |
| 392 | interrupt-controller; | |
| 393 | #interrupt-cells = <2>; | |
| 394 | }; | |
| f11d3e7d AE |
395 | |
| 396 | ipa_smp2p_out: ipa-ap-to-modem { | |
| 397 | qcom,entry-name = "ipa"; | |
| 398 | #qcom,smem-state-cells = <1>; | |
| 399 | }; | |
| 400 | ||
| 401 | ipa_smp2p_in: ipa-modem-to-ap { | |
| 402 | qcom,entry-name = "ipa"; | |
| 403 | interrupt-controller; | |
| 404 | #interrupt-cells = <2>; | |
| 405 | }; | |
| 03a41991 VK |
406 | }; |
| 407 | ||
| 408 | smp2p-slpi { | |
| 409 | compatible = "qcom,smp2p"; | |
| 410 | qcom,smem = <481>, <430>; | |
| 411 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 412 | IPCC_MPROC_SIGNAL_SMP2P | |
| 413 | IRQ_TYPE_EDGE_RISING>; | |
| 414 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 415 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 416 | ||
| 417 | qcom,local-pid = <0>; | |
| 418 | qcom,remote-pid = <3>; | |
| 419 | ||
| 420 | smp2p_slpi_out: master-kernel { | |
| 421 | qcom,entry-name = "master-kernel"; | |
| 422 | #qcom,smem-state-cells = <1>; | |
| 423 | }; | |
| 424 | ||
| 425 | smp2p_slpi_in: slave-kernel { | |
| 426 | qcom,entry-name = "slave-kernel"; | |
| 427 | interrupt-controller; | |
| 428 | #interrupt-cells = <2>; | |
| 429 | }; | |
| 430 | }; | |
| 431 | ||
| b7e8f433 VK |
432 | soc: soc@0 { |
| 433 | #address-cells = <2>; | |
| 434 | #size-cells = <2>; | |
| 435 | ranges = <0 0 0 0 0x10 0>; | |
| 436 | dma-ranges = <0 0 0 0 0x10 0>; | |
| 437 | compatible = "simple-bus"; | |
| 438 | ||
| 439 | gcc: clock-controller@100000 { | |
| 440 | compatible = "qcom,gcc-sm8350"; | |
| 441 | reg = <0x0 0x00100000 0x0 0x1f0000>; | |
| 442 | #clock-cells = <1>; | |
| 443 | #reset-cells = <1>; | |
| 444 | #power-domain-cells = <1>; | |
| 445 | clock-names = "bi_tcxo", "sleep_clk"; | |
| 446 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; | |
| 447 | }; | |
| 448 | ||
| 449 | ipcc: mailbox@408000 { | |
| 450 | compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; | |
| 451 | reg = <0 0x00408000 0 0x1000>; | |
| 452 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
| 453 | interrupt-controller; | |
| 454 | #interrupt-cells = <3>; | |
| 455 | #mbox-cells = <2>; | |
| 456 | }; | |
| 457 | ||
| 87f0b434 | 458 | qupv3_id_0: geniqup@9c0000 { |
| b7e8f433 VK |
459 | compatible = "qcom,geni-se-qup"; |
| 460 | reg = <0x0 0x009c0000 0x0 0x6000>; | |
| 461 | clock-names = "m-ahb", "s-ahb"; | |
| 6d91e201 VK |
462 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 463 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
| b7e8f433 VK |
464 | #address-cells = <2>; |
| 465 | #size-cells = <2>; | |
| 466 | ranges; | |
| 467 | status = "disabled"; | |
| 468 | ||
| 469 | uart2: serial@98c000 { | |
| 470 | compatible = "qcom,geni-debug-uart"; | |
| 471 | reg = <0 0x0098c000 0 0x4000>; | |
| 472 | clock-names = "se"; | |
| 6d91e201 | 473 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| b7e8f433 VK |
474 | pinctrl-names = "default"; |
| 475 | pinctrl-0 = <&qup_uart3_default_state>; | |
| 476 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
| 477 | #address-cells = <1>; | |
| 478 | #size-cells = <0>; | |
| 479 | status = "disabled"; | |
| 480 | }; | |
| 481 | }; | |
| 482 | ||
| 06bf656e JM |
483 | qupv3_id_1: geniqup@ac0000 { |
| 484 | compatible = "qcom,geni-se-qup"; | |
| 485 | reg = <0x0 0x00ac0000 0x0 0x6000>; | |
| 486 | clock-names = "m-ahb", "s-ahb"; | |
| 487 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, | |
| 488 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
| 489 | #address-cells = <2>; | |
| 490 | #size-cells = <2>; | |
| 491 | ranges; | |
| 492 | status = "disabled"; | |
| 493 | ||
| 494 | i2c13: i2c@a94000 { | |
| 495 | compatible = "qcom,geni-i2c"; | |
| 496 | reg = <0 0x00a94000 0 0x4000>; | |
| 497 | clock-names = "se"; | |
| 498 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
| 499 | pinctrl-names = "default"; | |
| 500 | pinctrl-0 = <&qup_i2c13_default_state>; | |
| 501 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 502 | #address-cells = <1>; | |
| 503 | #size-cells = <0>; | |
| 504 | status = "disabled"; | |
| 505 | }; | |
| 506 | }; | |
| 507 | ||
| 187f65b7 VK |
508 | apps_smmu: iommu@15000000 { |
| 509 | compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; | |
| 510 | reg = <0 0x15000000 0 0x100000>; | |
| 511 | #iommu-cells = <2>; | |
| 512 | #global-interrupts = <2>; | |
| 513 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
| 514 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
| 515 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
| 516 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
| 517 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
| 518 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
| 519 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
| 520 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
| 521 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
| 522 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| 523 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 524 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 525 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 526 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 527 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 528 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 529 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 530 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 531 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 532 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 533 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 534 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 535 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 536 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 537 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
| 538 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
| 539 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
| 540 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
| 541 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
| 542 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
| 543 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
| 544 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
| 545 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
| 546 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
| 547 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
| 548 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
| 549 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
| 550 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
| 551 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
| 552 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
| 553 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
| 554 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
| 555 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
| 556 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
| 557 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
| 558 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
| 559 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
| 560 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
| 561 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
| 562 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
| 563 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
| 564 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
| 565 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
| 566 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
| 567 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
| 568 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 569 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
| 570 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 571 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
| 572 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
| 573 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
| 574 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
| 575 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
| 576 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
| 577 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
| 578 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
| 579 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
| 580 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
| 581 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
| 582 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
| 583 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
| 584 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
| 585 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
| 586 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
| 587 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
| 588 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
| 589 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
| 590 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, | |
| 591 | <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
| 592 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
| 593 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, | |
| 594 | <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, | |
| 595 | <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, | |
| 596 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
| 597 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
| 598 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
| 599 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
| 600 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
| 601 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
| 602 | <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, | |
| 603 | <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, | |
| 604 | <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, | |
| 605 | <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, | |
| 606 | <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, | |
| 607 | <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, | |
| 608 | <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, | |
| 609 | <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, | |
| 610 | <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; | |
| 611 | }; | |
| 612 | ||
| da6b2482 VK |
613 | config_noc: interconnect@1500000 { |
| 614 | compatible = "qcom,sm8350-config-noc"; | |
| 615 | reg = <0 0x01500000 0 0xa580>; | |
| 616 | #interconnect-cells = <1>; | |
| 617 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 618 | }; | |
| 619 | ||
| 620 | mc_virt: interconnect@1580000 { | |
| 621 | compatible = "qcom,sm8350-mc-virt"; | |
| 622 | reg = <0 0x01580000 0 0x1000>; | |
| 623 | #interconnect-cells = <1>; | |
| 624 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 625 | }; | |
| 626 | ||
| 627 | system_noc: interconnect@1680000 { | |
| 628 | compatible = "qcom,sm8350-system-noc"; | |
| 629 | reg = <0 0x01680000 0 0x1c200>; | |
| 630 | #interconnect-cells = <1>; | |
| 631 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 632 | }; | |
| 633 | ||
| 634 | aggre1_noc: interconnect@16e0000 { | |
| 635 | compatible = "qcom,sm8350-aggre1-noc"; | |
| 636 | reg = <0 0x016e0000 0 0x1f180>; | |
| 637 | #interconnect-cells = <1>; | |
| 638 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 639 | }; | |
| 640 | ||
| 641 | aggre2_noc: interconnect@1700000 { | |
| 642 | compatible = "qcom,sm8350-aggre2-noc"; | |
| 643 | reg = <0 0x01700000 0 0x33000>; | |
| 644 | #interconnect-cells = <1>; | |
| 645 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 646 | }; | |
| 647 | ||
| 648 | mmss_noc: interconnect@1740000 { | |
| 649 | compatible = "qcom,sm8350-mmss-noc"; | |
| 650 | reg = <0 0x01740000 0 0x1f080>; | |
| 651 | #interconnect-cells = <1>; | |
| 652 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 653 | }; | |
| 654 | ||
| 655 | lpass_ag_noc: interconnect@3c40000 { | |
| 656 | compatible = "qcom,sm8350-lpass-ag-noc"; | |
| 657 | reg = <0 0x03c40000 0 0xf080>; | |
| 658 | #interconnect-cells = <1>; | |
| 659 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 660 | }; | |
| 661 | ||
| 662 | compute_noc: interconnect@a0c0000{ | |
| 663 | compatible = "qcom,sm8350-compute-noc"; | |
| 664 | reg = <0 0x0a0c0000 0 0xa180>; | |
| 665 | #interconnect-cells = <1>; | |
| 666 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 667 | }; | |
| 668 | ||
| f11d3e7d AE |
669 | ipa: ipa@1e40000 { |
| 670 | compatible = "qcom,sm8350-ipa"; | |
| 671 | ||
| 672 | iommus = <&apps_smmu 0x5c0 0x0>, | |
| 673 | <&apps_smmu 0x5c2 0x0>; | |
| 674 | reg = <0 0x1e40000 0 0x8000>, | |
| 675 | <0 0x1e50000 0 0x4b20>, | |
| 676 | <0 0x1e04000 0 0x23000>; | |
| 677 | reg-names = "ipa-reg", | |
| 678 | "ipa-shared", | |
| 679 | "gsi"; | |
| 680 | ||
| 681 | interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, | |
| 682 | <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, | |
| 683 | <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 684 | <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; | |
| 685 | interrupt-names = "ipa", | |
| 686 | "gsi", | |
| 687 | "ipa-clock-query", | |
| 688 | "ipa-setup-ready"; | |
| 689 | ||
| 690 | clocks = <&rpmhcc RPMH_IPA_CLK>; | |
| 691 | clock-names = "core"; | |
| 692 | ||
| 84173ca3 | 693 | interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, |
| f11d3e7d | 694 | <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; |
| 84173ca3 AE |
695 | interconnect-names = "memory", |
| 696 | "config"; | |
| f11d3e7d AE |
697 | |
| 698 | qcom,smem-states = <&ipa_smp2p_out 0>, | |
| 699 | <&ipa_smp2p_out 1>; | |
| 700 | qcom,smem-state-names = "ipa-clock-enabled-valid", | |
| 701 | "ipa-clock-enabled"; | |
| 702 | ||
| 703 | status = "disabled"; | |
| 704 | }; | |
| 705 | ||
| b7e8f433 VK |
706 | tcsr_mutex: hwlock@1f40000 { |
| 707 | compatible = "qcom,tcsr-mutex"; | |
| 708 | reg = <0x0 0x01f40000 0x0 0x40000>; | |
| 709 | #hwlock-cells = <1>; | |
| 710 | }; | |
| 711 | ||
| 177fcf0a VK |
712 | mpss: remoteproc@4080000 { |
| 713 | compatible = "qcom,sm8350-mpss-pas"; | |
| 714 | reg = <0x0 0x04080000 0x0 0x4040>; | |
| 715 | ||
| 716 | interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, | |
| 717 | <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 718 | <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 719 | <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 720 | <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, | |
| 721 | <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; | |
| 722 | interrupt-names = "wdog", "fatal", "ready", "handover", | |
| 723 | "stop-ack", "shutdown-ack"; | |
| 724 | ||
| 725 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 726 | clock-names = "xo"; | |
| 727 | ||
| 6b7cb2d2 | 728 | power-domains = <&rpmhpd 0>, |
| 177fcf0a | 729 | <&rpmhpd 12>; |
| 6b7cb2d2 | 730 | power-domain-names = "cx", "mss"; |
| 177fcf0a | 731 | |
| 84c856d0 | 732 | interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; |
| da6b2482 | 733 | |
| 177fcf0a VK |
734 | memory-region = <&pil_modem_mem>; |
| 735 | ||
| 6b7cb2d2 SS |
736 | qcom,qmp = <&aoss_qmp>; |
| 737 | ||
| 177fcf0a VK |
738 | qcom,smem-states = <&smp2p_modem_out 0>; |
| 739 | qcom,smem-state-names = "stop"; | |
| 740 | ||
| 741 | status = "disabled"; | |
| 742 | ||
| 743 | glink-edge { | |
| 744 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
| 745 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 746 | IRQ_TYPE_EDGE_RISING>; | |
| 747 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
| 748 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 749 | interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; | |
| 750 | label = "modem"; | |
| 751 | qcom,remote-pid = <1>; | |
| 752 | }; | |
| 753 | }; | |
| 754 | ||
| b7e8f433 VK |
755 | pdc: interrupt-controller@b220000 { |
| 756 | compatible = "qcom,sm8350-pdc", "qcom,pdc"; | |
| 757 | reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; | |
| 758 | qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, | |
| 759 | <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, | |
| 760 | <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, | |
| 761 | <156 716 12>; | |
| 762 | #interrupt-cells = <2>; | |
| 763 | interrupt-parent = <&intc>; | |
| 764 | interrupt-controller; | |
| 765 | }; | |
| 766 | ||
| 1dee9e3b | 767 | tsens0: thermal-sensor@c263000 { |
| 20f9d94e RF |
768 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
| 769 | reg = <0 0x0c263000 0 0x1ff>, /* TM */ | |
| 770 | <0 0x0c222000 0 0x8>; /* SROT */ | |
| 771 | #qcom,sensors = <15>; | |
| 772 | interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, | |
| 773 | <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 774 | interrupt-names = "uplow", "critical"; | |
| 775 | #thermal-sensor-cells = <1>; | |
| 776 | }; | |
| 777 | ||
| 1dee9e3b | 778 | tsens1: thermal-sensor@c265000 { |
| 20f9d94e RF |
779 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
| 780 | reg = <0 0x0c265000 0 0x1ff>, /* TM */ | |
| 781 | <0 0x0c223000 0 0x8>; /* SROT */ | |
| 782 | #qcom,sensors = <14>; | |
| 783 | interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, | |
| 784 | <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 785 | interrupt-names = "uplow", "critical"; | |
| 786 | #thermal-sensor-cells = <1>; | |
| 787 | }; | |
| 788 | ||
| 97832fa8 | 789 | aoss_qmp: power-controller@c300000 { |
| b7e8f433 | 790 | compatible = "qcom,sm8350-aoss-qmp"; |
| 47cb6a06 | 791 | reg = <0 0x0c300000 0 0x400>; |
| b7e8f433 VK |
792 | interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP |
| 793 | IRQ_TYPE_EDGE_RISING>; | |
| 794 | mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 795 | ||
| 796 | #clock-cells = <0>; | |
| b7e8f433 VK |
797 | }; |
| 798 | ||
| 47cb6a06 MS |
799 | sram@c3f0000 { |
| 800 | compatible = "qcom,rpmh-stats"; | |
| 801 | reg = <0 0x0c3f0000 0 0x400>; | |
| 802 | }; | |
| 803 | ||
| 389cd7ac VK |
804 | spmi_bus: spmi@c440000 { |
| 805 | compatible = "qcom,spmi-pmic-arb"; | |
| 806 | reg = <0x0 0xc440000 0x0 0x1100>, | |
| 807 | <0x0 0xc600000 0x0 0x2000000>, | |
| 808 | <0x0 0xe600000 0x0 0x100000>, | |
| 809 | <0x0 0xe700000 0x0 0xa0000>, | |
| 810 | <0x0 0xc40a000 0x0 0x26000>; | |
| 811 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
| 812 | interrupt-names = "periph_irq"; | |
| 813 | interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 814 | qcom,ee = <0>; | |
| 815 | qcom,channel = <0>; | |
| 816 | #address-cells = <2>; | |
| 817 | #size-cells = <0>; | |
| 818 | interrupt-controller; | |
| 819 | #interrupt-cells = <4>; | |
| 820 | }; | |
| 821 | ||
| b7e8f433 VK |
822 | tlmm: pinctrl@f100000 { |
| 823 | compatible = "qcom,sm8350-tlmm"; | |
| 824 | reg = <0 0x0f100000 0 0x300000>; | |
| 825 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| 826 | gpio-controller; | |
| 827 | #gpio-cells = <2>; | |
| 828 | interrupt-controller; | |
| 829 | #interrupt-cells = <2>; | |
| 79015857 | 830 | gpio-ranges = <&tlmm 0 0 204>; |
| 67146f07 | 831 | wakeup-parent = <&pdc>; |
| b7e8f433 VK |
832 | |
| 833 | qup_uart3_default_state: qup-uart3-default-state { | |
| 834 | rx { | |
| 835 | pins = "gpio18"; | |
| 836 | function = "qup3"; | |
| 837 | }; | |
| 838 | tx { | |
| 839 | pins = "gpio19"; | |
| 840 | function = "qup3"; | |
| 841 | }; | |
| 842 | }; | |
| 06bf656e JM |
843 | |
| 844 | qup_i2c13_default_state: qup-i2c13-default-state { | |
| 845 | mux { | |
| 846 | pins = "gpio0", "gpio1"; | |
| 847 | function = "qup13"; | |
| 848 | }; | |
| 849 | ||
| 850 | config { | |
| 851 | pins = "gpio0", "gpio1"; | |
| 852 | drive-strength = <2>; | |
| 853 | bias-pull-up; | |
| 854 | }; | |
| 855 | }; | |
| b7e8f433 VK |
856 | }; |
| 857 | ||
| 24e3eb2e RF |
858 | rng: rng@10d3000 { |
| 859 | compatible = "qcom,prng-ee"; | |
| 860 | reg = <0 0x010d3000 0 0x1000>; | |
| 861 | clocks = <&rpmhcc RPMH_HWKM_CLK>; | |
| 862 | clock-names = "core"; | |
| 863 | }; | |
| 864 | ||
| b7e8f433 VK |
865 | intc: interrupt-controller@17a00000 { |
| 866 | compatible = "arm,gic-v3"; | |
| 867 | #interrupt-cells = <3>; | |
| 868 | interrupt-controller; | |
| 869 | reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ | |
| 870 | <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ | |
| 871 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 872 | }; | |
| 873 | ||
| 874 | timer@17c20000 { | |
| 875 | compatible = "arm,armv7-timer-mem"; | |
| 876 | #address-cells = <2>; | |
| 877 | #size-cells = <2>; | |
| 878 | ranges; | |
| 879 | reg = <0x0 0x17c20000 0x0 0x1000>; | |
| 880 | clock-frequency = <19200000>; | |
| 881 | ||
| 882 | frame@17c21000 { | |
| 883 | frame-number = <0>; | |
| 884 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| 885 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 886 | reg = <0x0 0x17c21000 0x0 0x1000>, | |
| 887 | <0x0 0x17c22000 0x0 0x1000>; | |
| 888 | }; | |
| 889 | ||
| 890 | frame@17c23000 { | |
| 891 | frame-number = <1>; | |
| 892 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 893 | reg = <0x0 0x17c23000 0x0 0x1000>; | |
| 894 | status = "disabled"; | |
| 895 | }; | |
| 896 | ||
| 897 | frame@17c25000 { | |
| 898 | frame-number = <2>; | |
| 899 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 900 | reg = <0x0 0x17c25000 0x0 0x1000>; | |
| 901 | status = "disabled"; | |
| 902 | }; | |
| 903 | ||
| 904 | frame@17c27000 { | |
| 905 | frame-number = <3>; | |
| 906 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 907 | reg = <0x0 0x17c27000 0x0 0x1000>; | |
| 908 | status = "disabled"; | |
| 909 | }; | |
| 910 | ||
| 911 | frame@17c29000 { | |
| 912 | frame-number = <4>; | |
| 913 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 914 | reg = <0x0 0x17c29000 0x0 0x1000>; | |
| 915 | status = "disabled"; | |
| 916 | }; | |
| 917 | ||
| 918 | frame@17c2b000 { | |
| 919 | frame-number = <5>; | |
| 920 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 921 | reg = <0x0 0x17c2b000 0x0 0x1000>; | |
| 922 | status = "disabled"; | |
| 923 | }; | |
| 924 | ||
| 925 | frame@17c2d000 { | |
| 926 | frame-number = <6>; | |
| 927 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 928 | reg = <0x0 0x17c2d000 0x0 0x1000>; | |
| 929 | status = "disabled"; | |
| 930 | }; | |
| 931 | }; | |
| 932 | ||
| 933 | apps_rsc: rsc@18200000 { | |
| 934 | label = "apps_rsc"; | |
| 935 | compatible = "qcom,rpmh-rsc"; | |
| 936 | reg = <0x0 0x18200000 0x0 0x10000>, | |
| 937 | <0x0 0x18210000 0x0 0x10000>, | |
| 938 | <0x0 0x18220000 0x0 0x10000>; | |
| 939 | reg-names = "drv-0", "drv-1", "drv-2"; | |
| 940 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 941 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 942 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 943 | qcom,tcs-offset = <0xd00>; | |
| 944 | qcom,drv-id = <2>; | |
| 945 | qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, | |
| 946 | <WAKE_TCS 3>, <CONTROL_TCS 1>; | |
| 947 | ||
| 948 | rpmhcc: clock-controller { | |
| 949 | compatible = "qcom,sm8350-rpmh-clk"; | |
| 950 | #clock-cells = <1>; | |
| 951 | clock-names = "xo"; | |
| 952 | clocks = <&xo_board>; | |
| 953 | }; | |
| 954 | ||
| 90f57509 VK |
955 | rpmhpd: power-controller { |
| 956 | compatible = "qcom,sm8350-rpmhpd"; | |
| 957 | #power-domain-cells = <1>; | |
| 958 | operating-points-v2 = <&rpmhpd_opp_table>; | |
| 959 | ||
| 960 | rpmhpd_opp_table: opp-table { | |
| 961 | compatible = "operating-points-v2"; | |
| 962 | ||
| 963 | rpmhpd_opp_ret: opp1 { | |
| 964 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; | |
| 965 | }; | |
| 966 | ||
| 967 | rpmhpd_opp_min_svs: opp2 { | |
| 968 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
| 969 | }; | |
| 970 | ||
| 971 | rpmhpd_opp_low_svs: opp3 { | |
| 972 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
| 973 | }; | |
| 974 | ||
| 975 | rpmhpd_opp_svs: opp4 { | |
| 976 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
| 977 | }; | |
| 978 | ||
| 979 | rpmhpd_opp_svs_l1: opp5 { | |
| 980 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
| 981 | }; | |
| 982 | ||
| 983 | rpmhpd_opp_nom: opp6 { | |
| 984 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
| 985 | }; | |
| 986 | ||
| 987 | rpmhpd_opp_nom_l1: opp7 { | |
| 988 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
| 989 | }; | |
| 990 | ||
| 991 | rpmhpd_opp_nom_l2: opp8 { | |
| 992 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; | |
| 993 | }; | |
| 994 | ||
| 995 | rpmhpd_opp_turbo: opp9 { | |
| 996 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
| 997 | }; | |
| 998 | ||
| 999 | rpmhpd_opp_turbo_l1: opp10 { | |
| 1000 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
| 1001 | }; | |
| 1002 | }; | |
| 1003 | }; | |
| da6b2482 VK |
1004 | |
| 1005 | apps_bcm_voter: bcm_voter { | |
| 1006 | compatible = "qcom,bcm-voter"; | |
| 1007 | }; | |
| b7e8f433 | 1008 | }; |
| e780fb31 | 1009 | |
| ccbb3abb VK |
1010 | cpufreq_hw: cpufreq@18591000 { |
| 1011 | compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; | |
| 1012 | reg = <0 0x18591000 0 0x1000>, | |
| 1013 | <0 0x18592000 0 0x1000>, | |
| 1014 | <0 0x18593000 0 0x1000>; | |
| 1015 | reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; | |
| 1016 | ||
| 1017 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; | |
| 1018 | clock-names = "xo", "alternate"; | |
| 1019 | ||
| 1020 | #freq-domain-cells = <1>; | |
| 1021 | }; | |
| 1022 | ||
| 59c7cf81 VK |
1023 | ufs_mem_hc: ufshc@1d84000 { |
| 1024 | compatible = "qcom,sm8350-ufshc", "qcom,ufshc", | |
| 1025 | "jedec,ufs-2.0"; | |
| 1026 | reg = <0 0x01d84000 0 0x3000>; | |
| 1027 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
| 1028 | phys = <&ufs_mem_phy_lanes>; | |
| 1029 | phy-names = "ufsphy"; | |
| 1030 | lanes-per-direction = <2>; | |
| 1031 | #reset-cells = <1>; | |
| 6d91e201 | 1032 | resets = <&gcc GCC_UFS_PHY_BCR>; |
| 59c7cf81 VK |
1033 | reset-names = "rst"; |
| 1034 | ||
| 6d91e201 | 1035 | power-domains = <&gcc UFS_PHY_GDSC>; |
| 59c7cf81 VK |
1036 | |
| 1037 | iommus = <&apps_smmu 0xe0 0x0>; | |
| 1038 | ||
| 1039 | clock-names = | |
| 1040 | "ref_clk", | |
| 1041 | "core_clk", | |
| 1042 | "bus_aggr_clk", | |
| 1043 | "iface_clk", | |
| 1044 | "core_clk_unipro", | |
| 1045 | "ref_clk", | |
| 1046 | "tx_lane0_sync_clk", | |
| 1047 | "rx_lane0_sync_clk", | |
| 1048 | "rx_lane1_sync_clk"; | |
| 1049 | clocks = | |
| 1050 | <&rpmhcc RPMH_CXO_CLK>, | |
| 6d91e201 VK |
1051 | <&gcc GCC_UFS_PHY_AXI_CLK>, |
| 1052 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
| 1053 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
| 1054 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
| 59c7cf81 | 1055 | <&rpmhcc RPMH_CXO_CLK>, |
| 6d91e201 VK |
1056 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| 1057 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
| 1058 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
| 59c7cf81 VK |
1059 | freq-table-hz = |
| 1060 | <75000000 300000000>, | |
| 1061 | <75000000 300000000>, | |
| 1062 | <0 0>, | |
| 1063 | <0 0>, | |
| 1064 | <75000000 300000000>, | |
| 1065 | <0 0>, | |
| 1066 | <0 0>, | |
| 1067 | <75000000 300000000>, | |
| 1068 | <75000000 300000000>; | |
| 1069 | status = "disabled"; | |
| 1070 | }; | |
| 1071 | ||
| 1072 | ufs_mem_phy: phy@1d87000 { | |
| 1073 | compatible = "qcom,sm8350-qmp-ufs-phy"; | |
| 1074 | reg = <0 0x01d87000 0 0xe10>; | |
| 1075 | #address-cells = <2>; | |
| 1076 | #size-cells = <2>; | |
| 59c7cf81 VK |
1077 | ranges; |
| 1078 | clock-names = "ref", | |
| 1079 | "ref_aux"; | |
| 1080 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
| 6d91e201 | 1081 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| 59c7cf81 VK |
1082 | |
| 1083 | resets = <&ufs_mem_hc 0>; | |
| 1084 | reset-names = "ufsphy"; | |
| 1085 | status = "disabled"; | |
| 1086 | ||
| 1087 | ufs_mem_phy_lanes: lanes@1d87400 { | |
| 1088 | reg = <0 0x01d87400 0 0x108>, | |
| 1089 | <0 0x01d87600 0 0x1e0>, | |
| 1090 | <0 0x01d87c00 0 0x1dc>, | |
| 1091 | <0 0x01d87800 0 0x108>, | |
| 1092 | <0 0x01d87a00 0 0x1e0>; | |
| 1093 | #phy-cells = <0>; | |
| 1094 | #clock-cells = <0>; | |
| 1095 | }; | |
| 1096 | }; | |
| 1097 | ||
| 177fcf0a VK |
1098 | slpi: remoteproc@5c00000 { |
| 1099 | compatible = "qcom,sm8350-slpi-pas"; | |
| 1100 | reg = <0 0x05c00000 0 0x4000>; | |
| 1101 | ||
| 1102 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 1103 | <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 1104 | <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 1105 | <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 1106 | <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 1107 | interrupt-names = "wdog", "fatal", "ready", | |
| 1108 | "handover", "stop-ack"; | |
| 1109 | ||
| 1110 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1111 | clock-names = "xo"; | |
| 1112 | ||
| 6b7cb2d2 | 1113 | power-domains = <&rpmhpd 4>, |
| 177fcf0a | 1114 | <&rpmhpd 5>; |
| 6b7cb2d2 | 1115 | power-domain-names = "lcx", "lmx"; |
| 177fcf0a VK |
1116 | |
| 1117 | memory-region = <&pil_slpi_mem>; | |
| 1118 | ||
| 6b7cb2d2 SS |
1119 | qcom,qmp = <&aoss_qmp>; |
| 1120 | ||
| 177fcf0a VK |
1121 | qcom,smem-states = <&smp2p_slpi_out 0>; |
| 1122 | qcom,smem-state-names = "stop"; | |
| 1123 | ||
| 1124 | status = "disabled"; | |
| 1125 | ||
| 1126 | glink-edge { | |
| 1127 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 1128 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1129 | IRQ_TYPE_EDGE_RISING>; | |
| 1130 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 1131 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1132 | ||
| 1133 | label = "slpi"; | |
| 1134 | qcom,remote-pid = <3>; | |
| 1135 | ||
| 178056a4 OJ |
1136 | fastrpc { |
| 1137 | compatible = "qcom,fastrpc"; | |
| 1138 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 1139 | label = "sdsp"; | |
| 1140 | #address-cells = <1>; | |
| 1141 | #size-cells = <0>; | |
| 1142 | ||
| 1143 | compute-cb@1 { | |
| 1144 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1145 | reg = <1>; | |
| 1146 | iommus = <&apps_smmu 0x0541 0x0>; | |
| 1147 | }; | |
| 1148 | ||
| 1149 | compute-cb@2 { | |
| 1150 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1151 | reg = <2>; | |
| 1152 | iommus = <&apps_smmu 0x0542 0x0>; | |
| 1153 | }; | |
| 1154 | ||
| 1155 | compute-cb@3 { | |
| 1156 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1157 | reg = <3>; | |
| 1158 | iommus = <&apps_smmu 0x0543 0x0>; | |
| 1159 | /* note: shared-cb = <4> in downstream */ | |
| 1160 | }; | |
| 1161 | }; | |
| 177fcf0a VK |
1162 | }; |
| 1163 | }; | |
| 1164 | ||
| 1165 | cdsp: remoteproc@98900000 { | |
| 1166 | compatible = "qcom,sm8350-cdsp-pas"; | |
| 1167 | reg = <0 0x098900000 0 0x1400000>; | |
| 1168 | ||
| 1169 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, | |
| 1170 | <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 1171 | <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 1172 | <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 1173 | <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 1174 | interrupt-names = "wdog", "fatal", "ready", | |
| 1175 | "handover", "stop-ack"; | |
| 1176 | ||
| 1177 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1178 | clock-names = "xo"; | |
| 1179 | ||
| 6b7cb2d2 | 1180 | power-domains = <&rpmhpd 0>, |
| 177fcf0a | 1181 | <&rpmhpd 10>; |
| 6b7cb2d2 | 1182 | power-domain-names = "cx", "mxc"; |
| 177fcf0a | 1183 | |
| 84c856d0 | 1184 | interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; |
| da6b2482 | 1185 | |
| 177fcf0a VK |
1186 | memory-region = <&pil_cdsp_mem>; |
| 1187 | ||
| 6b7cb2d2 SS |
1188 | qcom,qmp = <&aoss_qmp>; |
| 1189 | ||
| 177fcf0a VK |
1190 | qcom,smem-states = <&smp2p_cdsp_out 0>; |
| 1191 | qcom,smem-state-names = "stop"; | |
| 1192 | ||
| 1193 | status = "disabled"; | |
| 1194 | ||
| 1195 | glink-edge { | |
| 1196 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 1197 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1198 | IRQ_TYPE_EDGE_RISING>; | |
| 1199 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 1200 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1201 | ||
| 1202 | label = "cdsp"; | |
| 1203 | qcom,remote-pid = <5>; | |
| 178056a4 OJ |
1204 | |
| 1205 | fastrpc { | |
| 1206 | compatible = "qcom,fastrpc"; | |
| 1207 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 1208 | label = "cdsp"; | |
| 1209 | #address-cells = <1>; | |
| 1210 | #size-cells = <0>; | |
| 1211 | ||
| 1212 | compute-cb@1 { | |
| 1213 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1214 | reg = <1>; | |
| 1215 | iommus = <&apps_smmu 0x2161 0x0400>, | |
| 1216 | <&apps_smmu 0x1181 0x0420>; | |
| 1217 | }; | |
| 1218 | ||
| 1219 | compute-cb@2 { | |
| 1220 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1221 | reg = <2>; | |
| 1222 | iommus = <&apps_smmu 0x2162 0x0400>, | |
| 1223 | <&apps_smmu 0x1182 0x0420>; | |
| 1224 | }; | |
| 1225 | ||
| 1226 | compute-cb@3 { | |
| 1227 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1228 | reg = <3>; | |
| 1229 | iommus = <&apps_smmu 0x2163 0x0400>, | |
| 1230 | <&apps_smmu 0x1183 0x0420>; | |
| 1231 | }; | |
| 1232 | ||
| 1233 | compute-cb@4 { | |
| 1234 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1235 | reg = <4>; | |
| 1236 | iommus = <&apps_smmu 0x2164 0x0400>, | |
| 1237 | <&apps_smmu 0x1184 0x0420>; | |
| 1238 | }; | |
| 1239 | ||
| 1240 | compute-cb@5 { | |
| 1241 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1242 | reg = <5>; | |
| 1243 | iommus = <&apps_smmu 0x2165 0x0400>, | |
| 1244 | <&apps_smmu 0x1185 0x0420>; | |
| 1245 | }; | |
| 1246 | ||
| 1247 | compute-cb@6 { | |
| 1248 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1249 | reg = <6>; | |
| 1250 | iommus = <&apps_smmu 0x2166 0x0400>, | |
| 1251 | <&apps_smmu 0x1186 0x0420>; | |
| 1252 | }; | |
| 1253 | ||
| 1254 | compute-cb@7 { | |
| 1255 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1256 | reg = <7>; | |
| 1257 | iommus = <&apps_smmu 0x2167 0x0400>, | |
| 1258 | <&apps_smmu 0x1187 0x0420>; | |
| 1259 | }; | |
| 1260 | ||
| 1261 | compute-cb@8 { | |
| 1262 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1263 | reg = <8>; | |
| 1264 | iommus = <&apps_smmu 0x2168 0x0400>, | |
| 1265 | <&apps_smmu 0x1188 0x0420>; | |
| 1266 | }; | |
| 1267 | ||
| 1268 | /* note: secure cb9 in downstream */ | |
| 1269 | }; | |
| 177fcf0a VK |
1270 | }; |
| 1271 | }; | |
| 1272 | ||
| e780fb31 JP |
1273 | usb_1_hsphy: phy@88e3000 { |
| 1274 | compatible = "qcom,sm8350-usb-hs-phy", | |
| 1275 | "qcom,usb-snps-hs-7nm-phy"; | |
| 1276 | reg = <0 0x088e3000 0 0x400>; | |
| 1277 | status = "disabled"; | |
| 1278 | #phy-cells = <0>; | |
| 1279 | ||
| 1280 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1281 | clock-names = "ref"; | |
| 1282 | ||
| 6d91e201 | 1283 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| e780fb31 JP |
1284 | }; |
| 1285 | ||
| 1286 | usb_2_hsphy: phy@88e4000 { | |
| 1287 | compatible = "qcom,sm8250-usb-hs-phy", | |
| 1288 | "qcom,usb-snps-hs-7nm-phy"; | |
| 1289 | reg = <0 0x088e4000 0 0x400>; | |
| 1290 | status = "disabled"; | |
| 1291 | #phy-cells = <0>; | |
| 1292 | ||
| 1293 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1294 | clock-names = "ref"; | |
| 1295 | ||
| 6d91e201 | 1296 | resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
| e780fb31 JP |
1297 | }; |
| 1298 | ||
| 1299 | usb_1_qmpphy: phy-wrapper@88e9000 { | |
| 1300 | compatible = "qcom,sm8350-qmp-usb3-phy"; | |
| 1301 | reg = <0 0x088e9000 0 0x200>, | |
| 1302 | <0 0x088e8000 0 0x20>; | |
| 1303 | reg-names = "reg-base", "dp_com"; | |
| 1304 | status = "disabled"; | |
| e780fb31 JP |
1305 | #address-cells = <2>; |
| 1306 | #size-cells = <2>; | |
| 1307 | ranges; | |
| 1308 | ||
| 6d91e201 | 1309 | clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
| e780fb31 | 1310 | <&rpmhcc RPMH_CXO_CLK>, |
| 6d91e201 | 1311 | <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
| e780fb31 JP |
1312 | clock-names = "aux", "ref_clk_src", "com_aux"; |
| 1313 | ||
| 6d91e201 VK |
1314 | resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
| 1315 | <&gcc GCC_USB3_PHY_PRIM_BCR>; | |
| e780fb31 JP |
1316 | reset-names = "phy", "common"; |
| 1317 | ||
| 1318 | usb_1_ssphy: phy@88e9200 { | |
| 1319 | reg = <0 0x088e9200 0 0x200>, | |
| 1320 | <0 0x088e9400 0 0x200>, | |
| 1321 | <0 0x088e9c00 0 0x400>, | |
| 1322 | <0 0x088e9600 0 0x200>, | |
| 1323 | <0 0x088e9800 0 0x200>, | |
| 1324 | <0 0x088e9a00 0 0x100>; | |
| 1325 | #phy-cells = <0>; | |
| 1326 | #clock-cells = <1>; | |
| 6d91e201 | 1327 | clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
| e780fb31 JP |
1328 | clock-names = "pipe0"; |
| 1329 | clock-output-names = "usb3_phy_pipe_clk_src"; | |
| 1330 | }; | |
| 1331 | }; | |
| 1332 | ||
| 1333 | usb_2_qmpphy: phy-wrapper@88eb000 { | |
| 1334 | compatible = "qcom,sm8350-qmp-usb3-uni-phy"; | |
| 1335 | reg = <0 0x088eb000 0 0x200>; | |
| 1336 | status = "disabled"; | |
| e780fb31 JP |
1337 | #address-cells = <2>; |
| 1338 | #size-cells = <2>; | |
| 1339 | ranges; | |
| 1340 | ||
| 6d91e201 | 1341 | clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
| e780fb31 | 1342 | <&rpmhcc RPMH_CXO_CLK>, |
| 6d91e201 VK |
1343 | <&gcc GCC_USB3_SEC_CLKREF_EN>, |
| 1344 | <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; | |
| e780fb31 JP |
1345 | clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
| 1346 | ||
| 6d91e201 VK |
1347 | resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
| 1348 | <&gcc GCC_USB3_PHY_SEC_BCR>; | |
| e780fb31 JP |
1349 | reset-names = "phy", "common"; |
| 1350 | ||
| 1351 | usb_2_ssphy: phy@88ebe00 { | |
| 1352 | reg = <0 0x088ebe00 0 0x200>, | |
| 1353 | <0 0x088ec000 0 0x200>, | |
| 1354 | <0 0x088eb200 0 0x1100>; | |
| 1355 | #phy-cells = <0>; | |
| 1356 | #clock-cells = <1>; | |
| 6d91e201 | 1357 | clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
| e780fb31 JP |
1358 | clock-names = "pipe0"; |
| 1359 | clock-output-names = "usb3_uni_phy_pipe_clk_src"; | |
| 1360 | }; | |
| 1361 | }; | |
| 1362 | ||
| 1dee9e3b | 1363 | dc_noc: interconnect@90c0000 { |
| da6b2482 VK |
1364 | compatible = "qcom,sm8350-dc-noc"; |
| 1365 | reg = <0 0x090c0000 0 0x4200>; | |
| 1366 | #interconnect-cells = <1>; | |
| 1367 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1368 | }; | |
| 1369 | ||
| 1370 | gem_noc: interconnect@9100000 { | |
| 1371 | compatible = "qcom,sm8350-gem-noc"; | |
| 1372 | reg = <0 0x09100000 0 0xb4000>; | |
| 1373 | #interconnect-cells = <1>; | |
| 1374 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1375 | }; | |
| 1376 | ||
| e780fb31 JP |
1377 | usb_1: usb@a6f8800 { |
| 1378 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
| 1379 | reg = <0 0x0a6f8800 0 0x400>; | |
| 1380 | status = "disabled"; | |
| 1381 | #address-cells = <2>; | |
| 1382 | #size-cells = <2>; | |
| 1383 | ranges; | |
| 1384 | ||
| 6d91e201 VK |
1385 | clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| 1386 | <&gcc GCC_USB30_PRIM_MASTER_CLK>, | |
| 1387 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, | |
| 1388 | <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, | |
| 1389 | <&gcc GCC_USB30_PRIM_SLEEP_CLK>; | |
| e780fb31 JP |
1390 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
| 1391 | "sleep"; | |
| 1392 | ||
| 6d91e201 VK |
1393 | assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| 1394 | <&gcc GCC_USB30_PRIM_MASTER_CLK>; | |
| e780fb31 JP |
1395 | assigned-clock-rates = <19200000>, <200000000>; |
| 1396 | ||
| 1397 | interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 1398 | <&pdc 14 IRQ_TYPE_EDGE_BOTH>, | |
| 1399 | <&pdc 15 IRQ_TYPE_EDGE_BOTH>, | |
| 1400 | <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 1401 | interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", | |
| 1402 | "dm_hs_phy_irq", "ss_phy_irq"; | |
| 1403 | ||
| 6d91e201 | 1404 | power-domains = <&gcc USB30_PRIM_GDSC>; |
| e780fb31 | 1405 | |
| 6d91e201 | 1406 | resets = <&gcc GCC_USB30_PRIM_BCR>; |
| e780fb31 | 1407 | |
| 2aa2b50d | 1408 | usb_1_dwc3: usb@a600000 { |
| e780fb31 JP |
1409 | compatible = "snps,dwc3"; |
| 1410 | reg = <0 0x0a600000 0 0xcd00>; | |
| 1411 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
| 1412 | iommus = <&apps_smmu 0x0 0x0>; | |
| 1413 | snps,dis_u2_susphy_quirk; | |
| 1414 | snps,dis_enblslpm_quirk; | |
| 1415 | phys = <&usb_1_hsphy>, <&usb_1_ssphy>; | |
| 1416 | phy-names = "usb2-phy", "usb3-phy"; | |
| 1417 | }; | |
| 1418 | }; | |
| 1419 | ||
| 1420 | usb_2: usb@a8f8800 { | |
| 1421 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
| 1422 | reg = <0 0x0a8f8800 0 0x400>; | |
| 1423 | status = "disabled"; | |
| 1424 | #address-cells = <2>; | |
| 1425 | #size-cells = <2>; | |
| 1426 | ranges; | |
| 1427 | ||
| 6d91e201 VK |
1428 | clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
| 1429 | <&gcc GCC_USB30_SEC_MASTER_CLK>, | |
| 1430 | <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, | |
| 1431 | <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, | |
| 1432 | <&gcc GCC_USB30_SEC_SLEEP_CLK>, | |
| 1433 | <&gcc GCC_USB3_SEC_CLKREF_EN>; | |
| e780fb31 JP |
1434 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
| 1435 | "sleep", "xo"; | |
| 1436 | ||
| 6d91e201 VK |
1437 | assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| 1438 | <&gcc GCC_USB30_SEC_MASTER_CLK>; | |
| e780fb31 JP |
1439 | assigned-clock-rates = <19200000>, <200000000>; |
| 1440 | ||
| 1441 | interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 1442 | <&pdc 12 IRQ_TYPE_EDGE_BOTH>, | |
| 1443 | <&pdc 13 IRQ_TYPE_EDGE_BOTH>, | |
| 1444 | <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 1445 | interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", | |
| 1446 | "dm_hs_phy_irq", "ss_phy_irq"; | |
| 1447 | ||
| 6d91e201 | 1448 | power-domains = <&gcc USB30_SEC_GDSC>; |
| e780fb31 | 1449 | |
| 6d91e201 | 1450 | resets = <&gcc GCC_USB30_SEC_BCR>; |
| e780fb31 | 1451 | |
| 2aa2b50d | 1452 | usb_2_dwc3: usb@a800000 { |
| e780fb31 JP |
1453 | compatible = "snps,dwc3"; |
| 1454 | reg = <0 0x0a800000 0 0xcd00>; | |
| 1455 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
| 1456 | iommus = <&apps_smmu 0x20 0x0>; | |
| 1457 | snps,dis_u2_susphy_quirk; | |
| 1458 | snps,dis_enblslpm_quirk; | |
| 1459 | phys = <&usb_2_hsphy>, <&usb_2_ssphy>; | |
| 1460 | phy-names = "usb2-phy", "usb3-phy"; | |
| 1461 | }; | |
| 1462 | }; | |
| 177fcf0a VK |
1463 | |
| 1464 | adsp: remoteproc@17300000 { | |
| 1465 | compatible = "qcom,sm8350-adsp-pas"; | |
| 1466 | reg = <0 0x17300000 0 0x100>; | |
| 1467 | ||
| 1468 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, | |
| 1469 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 1470 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 1471 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 1472 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 1473 | interrupt-names = "wdog", "fatal", "ready", | |
| 1474 | "handover", "stop-ack"; | |
| 1475 | ||
| 1476 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1477 | clock-names = "xo"; | |
| 1478 | ||
| 6b7cb2d2 | 1479 | power-domains = <&rpmhpd 4>, |
| 177fcf0a | 1480 | <&rpmhpd 5>; |
| 6b7cb2d2 | 1481 | power-domain-names = "lcx", "lmx"; |
| 177fcf0a VK |
1482 | |
| 1483 | memory-region = <&pil_adsp_mem>; | |
| 1484 | ||
| 6b7cb2d2 SS |
1485 | qcom,qmp = <&aoss_qmp>; |
| 1486 | ||
| 177fcf0a VK |
1487 | qcom,smem-states = <&smp2p_adsp_out 0>; |
| 1488 | qcom,smem-state-names = "stop"; | |
| 1489 | ||
| 1490 | status = "disabled"; | |
| 1491 | ||
| 1492 | glink-edge { | |
| 1493 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 1494 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1495 | IRQ_TYPE_EDGE_RISING>; | |
| 1496 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 1497 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1498 | ||
| 1499 | label = "lpass"; | |
| 1500 | qcom,remote-pid = <2>; | |
| 178056a4 OJ |
1501 | |
| 1502 | fastrpc { | |
| 1503 | compatible = "qcom,fastrpc"; | |
| 1504 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 1505 | label = "adsp"; | |
| 1506 | #address-cells = <1>; | |
| 1507 | #size-cells = <0>; | |
| 1508 | ||
| 1509 | compute-cb@3 { | |
| 1510 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1511 | reg = <3>; | |
| 1512 | iommus = <&apps_smmu 0x1803 0x0>; | |
| 1513 | }; | |
| 1514 | ||
| 1515 | compute-cb@4 { | |
| 1516 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1517 | reg = <4>; | |
| 1518 | iommus = <&apps_smmu 0x1804 0x0>; | |
| 1519 | }; | |
| 1520 | ||
| 1521 | compute-cb@5 { | |
| 1522 | compatible = "qcom,fastrpc-compute-cb"; | |
| 1523 | reg = <5>; | |
| 1524 | iommus = <&apps_smmu 0x1805 0x0>; | |
| 1525 | }; | |
| 1526 | }; | |
| 177fcf0a VK |
1527 | }; |
| 1528 | }; | |
| b7e8f433 VK |
1529 | }; |
| 1530 | ||
| 4dcaa68e | 1531 | thermal_zones: thermal-zones { |
| 20f9d94e RF |
1532 | cpu0-thermal { |
| 1533 | polling-delay-passive = <250>; | |
| 1534 | polling-delay = <1000>; | |
| 1535 | ||
| 1536 | thermal-sensors = <&tsens0 1>; | |
| 1537 | ||
| 1538 | trips { | |
| 1539 | cpu0_alert0: trip-point0 { | |
| 1540 | temperature = <90000>; | |
| 1541 | hysteresis = <2000>; | |
| 1542 | type = "passive"; | |
| 1543 | }; | |
| 1544 | ||
| 1545 | cpu0_alert1: trip-point1 { | |
| 1546 | temperature = <95000>; | |
| 1547 | hysteresis = <2000>; | |
| 1548 | type = "passive"; | |
| 1549 | }; | |
| 1550 | ||
| 1551 | cpu0_crit: cpu_crit { | |
| 1552 | temperature = <110000>; | |
| 1553 | hysteresis = <1000>; | |
| 1554 | type = "critical"; | |
| 1555 | }; | |
| 1556 | }; | |
| 1557 | ||
| 1558 | cooling-maps { | |
| 1559 | map0 { | |
| 1560 | trip = <&cpu0_alert0>; | |
| 1561 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1562 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1563 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1564 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1565 | }; | |
| 1566 | map1 { | |
| 1567 | trip = <&cpu0_alert1>; | |
| 1568 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1569 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1570 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1571 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1572 | }; | |
| 1573 | }; | |
| 1574 | }; | |
| 1575 | ||
| 1576 | cpu1-thermal { | |
| 1577 | polling-delay-passive = <250>; | |
| 1578 | polling-delay = <1000>; | |
| 1579 | ||
| 1580 | thermal-sensors = <&tsens0 2>; | |
| 1581 | ||
| 1582 | trips { | |
| 1583 | cpu1_alert0: trip-point0 { | |
| 1584 | temperature = <90000>; | |
| 1585 | hysteresis = <2000>; | |
| 1586 | type = "passive"; | |
| 1587 | }; | |
| 1588 | ||
| 1589 | cpu1_alert1: trip-point1 { | |
| 1590 | temperature = <95000>; | |
| 1591 | hysteresis = <2000>; | |
| 1592 | type = "passive"; | |
| 1593 | }; | |
| 1594 | ||
| 1595 | cpu1_crit: cpu_crit { | |
| 1596 | temperature = <110000>; | |
| 1597 | hysteresis = <1000>; | |
| 1598 | type = "critical"; | |
| 1599 | }; | |
| 1600 | }; | |
| 1601 | ||
| 1602 | cooling-maps { | |
| 1603 | map0 { | |
| 1604 | trip = <&cpu1_alert0>; | |
| 1605 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1606 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1607 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1608 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1609 | }; | |
| 1610 | map1 { | |
| 1611 | trip = <&cpu1_alert1>; | |
| 1612 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1613 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1614 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1615 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1616 | }; | |
| 1617 | }; | |
| 1618 | }; | |
| 1619 | ||
| 1620 | cpu2-thermal { | |
| 1621 | polling-delay-passive = <250>; | |
| 1622 | polling-delay = <1000>; | |
| 1623 | ||
| 1624 | thermal-sensors = <&tsens0 3>; | |
| 1625 | ||
| 1626 | trips { | |
| 1627 | cpu2_alert0: trip-point0 { | |
| 1628 | temperature = <90000>; | |
| 1629 | hysteresis = <2000>; | |
| 1630 | type = "passive"; | |
| 1631 | }; | |
| 1632 | ||
| 1633 | cpu2_alert1: trip-point1 { | |
| 1634 | temperature = <95000>; | |
| 1635 | hysteresis = <2000>; | |
| 1636 | type = "passive"; | |
| 1637 | }; | |
| 1638 | ||
| 1639 | cpu2_crit: cpu_crit { | |
| 1640 | temperature = <110000>; | |
| 1641 | hysteresis = <1000>; | |
| 1642 | type = "critical"; | |
| 1643 | }; | |
| 1644 | }; | |
| 1645 | ||
| 1646 | cooling-maps { | |
| 1647 | map0 { | |
| 1648 | trip = <&cpu2_alert0>; | |
| 1649 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1650 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1651 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1652 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1653 | }; | |
| 1654 | map1 { | |
| 1655 | trip = <&cpu2_alert1>; | |
| 1656 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1657 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1658 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1659 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1660 | }; | |
| 1661 | }; | |
| 1662 | }; | |
| 1663 | ||
| 1664 | cpu3-thermal { | |
| 1665 | polling-delay-passive = <250>; | |
| 1666 | polling-delay = <1000>; | |
| 1667 | ||
| 1668 | thermal-sensors = <&tsens0 4>; | |
| 1669 | ||
| 1670 | trips { | |
| 1671 | cpu3_alert0: trip-point0 { | |
| 1672 | temperature = <90000>; | |
| 1673 | hysteresis = <2000>; | |
| 1674 | type = "passive"; | |
| 1675 | }; | |
| 1676 | ||
| 1677 | cpu3_alert1: trip-point1 { | |
| 1678 | temperature = <95000>; | |
| 1679 | hysteresis = <2000>; | |
| 1680 | type = "passive"; | |
| 1681 | }; | |
| 1682 | ||
| 1683 | cpu3_crit: cpu_crit { | |
| 1684 | temperature = <110000>; | |
| 1685 | hysteresis = <1000>; | |
| 1686 | type = "critical"; | |
| 1687 | }; | |
| 1688 | }; | |
| 1689 | ||
| 1690 | cooling-maps { | |
| 1691 | map0 { | |
| 1692 | trip = <&cpu3_alert0>; | |
| 1693 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1694 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1695 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1696 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1697 | }; | |
| 1698 | map1 { | |
| 1699 | trip = <&cpu3_alert1>; | |
| 1700 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1701 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1702 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1703 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1704 | }; | |
| 1705 | }; | |
| 1706 | }; | |
| 1707 | ||
| 1708 | cpu4-top-thermal { | |
| 1709 | polling-delay-passive = <250>; | |
| 1710 | polling-delay = <1000>; | |
| 1711 | ||
| 1712 | thermal-sensors = <&tsens0 7>; | |
| 1713 | ||
| 1714 | trips { | |
| 1715 | cpu4_top_alert0: trip-point0 { | |
| 1716 | temperature = <90000>; | |
| 1717 | hysteresis = <2000>; | |
| 1718 | type = "passive"; | |
| 1719 | }; | |
| 1720 | ||
| 1721 | cpu4_top_alert1: trip-point1 { | |
| 1722 | temperature = <95000>; | |
| 1723 | hysteresis = <2000>; | |
| 1724 | type = "passive"; | |
| 1725 | }; | |
| 1726 | ||
| 1727 | cpu4_top_crit: cpu_crit { | |
| 1728 | temperature = <110000>; | |
| 1729 | hysteresis = <1000>; | |
| 1730 | type = "critical"; | |
| 1731 | }; | |
| 1732 | }; | |
| 1733 | ||
| 1734 | cooling-maps { | |
| 1735 | map0 { | |
| 1736 | trip = <&cpu4_top_alert0>; | |
| 1737 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1738 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1739 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1740 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1741 | }; | |
| 1742 | map1 { | |
| 1743 | trip = <&cpu4_top_alert1>; | |
| 1744 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1745 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1746 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1747 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1748 | }; | |
| 1749 | }; | |
| 1750 | }; | |
| 1751 | ||
| 1752 | cpu5-top-thermal { | |
| 1753 | polling-delay-passive = <250>; | |
| 1754 | polling-delay = <1000>; | |
| 1755 | ||
| 1756 | thermal-sensors = <&tsens0 8>; | |
| 1757 | ||
| 1758 | trips { | |
| 1759 | cpu5_top_alert0: trip-point0 { | |
| 1760 | temperature = <90000>; | |
| 1761 | hysteresis = <2000>; | |
| 1762 | type = "passive"; | |
| 1763 | }; | |
| 1764 | ||
| 1765 | cpu5_top_alert1: trip-point1 { | |
| 1766 | temperature = <95000>; | |
| 1767 | hysteresis = <2000>; | |
| 1768 | type = "passive"; | |
| 1769 | }; | |
| 1770 | ||
| 1771 | cpu5_top_crit: cpu_crit { | |
| 1772 | temperature = <110000>; | |
| 1773 | hysteresis = <1000>; | |
| 1774 | type = "critical"; | |
| 1775 | }; | |
| 1776 | }; | |
| 1777 | ||
| 1778 | cooling-maps { | |
| 1779 | map0 { | |
| 1780 | trip = <&cpu5_top_alert0>; | |
| 1781 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1782 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1783 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1784 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1785 | }; | |
| 1786 | map1 { | |
| 1787 | trip = <&cpu5_top_alert1>; | |
| 1788 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1789 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1790 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1791 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1792 | }; | |
| 1793 | }; | |
| 1794 | }; | |
| 1795 | ||
| 1796 | cpu6-top-thermal { | |
| 1797 | polling-delay-passive = <250>; | |
| 1798 | polling-delay = <1000>; | |
| 1799 | ||
| 1800 | thermal-sensors = <&tsens0 9>; | |
| 1801 | ||
| 1802 | trips { | |
| 1803 | cpu6_top_alert0: trip-point0 { | |
| 1804 | temperature = <90000>; | |
| 1805 | hysteresis = <2000>; | |
| 1806 | type = "passive"; | |
| 1807 | }; | |
| 1808 | ||
| 1809 | cpu6_top_alert1: trip-point1 { | |
| 1810 | temperature = <95000>; | |
| 1811 | hysteresis = <2000>; | |
| 1812 | type = "passive"; | |
| 1813 | }; | |
| 1814 | ||
| 1815 | cpu6_top_crit: cpu_crit { | |
| 1816 | temperature = <110000>; | |
| 1817 | hysteresis = <1000>; | |
| 1818 | type = "critical"; | |
| 1819 | }; | |
| 1820 | }; | |
| 1821 | ||
| 1822 | cooling-maps { | |
| 1823 | map0 { | |
| 1824 | trip = <&cpu6_top_alert0>; | |
| 1825 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1826 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1827 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1828 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1829 | }; | |
| 1830 | map1 { | |
| 1831 | trip = <&cpu6_top_alert1>; | |
| 1832 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1833 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1834 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1835 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1836 | }; | |
| 1837 | }; | |
| 1838 | }; | |
| 1839 | ||
| 1840 | cpu7-top-thermal { | |
| 1841 | polling-delay-passive = <250>; | |
| 1842 | polling-delay = <1000>; | |
| 1843 | ||
| 1844 | thermal-sensors = <&tsens0 10>; | |
| 1845 | ||
| 1846 | trips { | |
| 1847 | cpu7_top_alert0: trip-point0 { | |
| 1848 | temperature = <90000>; | |
| 1849 | hysteresis = <2000>; | |
| 1850 | type = "passive"; | |
| 1851 | }; | |
| 1852 | ||
| 1853 | cpu7_top_alert1: trip-point1 { | |
| 1854 | temperature = <95000>; | |
| 1855 | hysteresis = <2000>; | |
| 1856 | type = "passive"; | |
| 1857 | }; | |
| 1858 | ||
| 1859 | cpu7_top_crit: cpu_crit { | |
| 1860 | temperature = <110000>; | |
| 1861 | hysteresis = <1000>; | |
| 1862 | type = "critical"; | |
| 1863 | }; | |
| 1864 | }; | |
| 1865 | ||
| 1866 | cooling-maps { | |
| 1867 | map0 { | |
| 1868 | trip = <&cpu7_top_alert0>; | |
| 1869 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1870 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1871 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1872 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1873 | }; | |
| 1874 | map1 { | |
| 1875 | trip = <&cpu7_top_alert1>; | |
| 1876 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1877 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1878 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1879 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1880 | }; | |
| 1881 | }; | |
| 1882 | }; | |
| 1883 | ||
| 1884 | cpu4-bottom-thermal { | |
| 1885 | polling-delay-passive = <250>; | |
| 1886 | polling-delay = <1000>; | |
| 1887 | ||
| 1888 | thermal-sensors = <&tsens0 11>; | |
| 1889 | ||
| 1890 | trips { | |
| 1891 | cpu4_bottom_alert0: trip-point0 { | |
| 1892 | temperature = <90000>; | |
| 1893 | hysteresis = <2000>; | |
| 1894 | type = "passive"; | |
| 1895 | }; | |
| 1896 | ||
| 1897 | cpu4_bottom_alert1: trip-point1 { | |
| 1898 | temperature = <95000>; | |
| 1899 | hysteresis = <2000>; | |
| 1900 | type = "passive"; | |
| 1901 | }; | |
| 1902 | ||
| 1903 | cpu4_bottom_crit: cpu_crit { | |
| 1904 | temperature = <110000>; | |
| 1905 | hysteresis = <1000>; | |
| 1906 | type = "critical"; | |
| 1907 | }; | |
| 1908 | }; | |
| 1909 | ||
| 1910 | cooling-maps { | |
| 1911 | map0 { | |
| 1912 | trip = <&cpu4_bottom_alert0>; | |
| 1913 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1914 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1915 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1916 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1917 | }; | |
| 1918 | map1 { | |
| 1919 | trip = <&cpu4_bottom_alert1>; | |
| 1920 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1921 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1922 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1923 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1924 | }; | |
| 1925 | }; | |
| 1926 | }; | |
| 1927 | ||
| 1928 | cpu5-bottom-thermal { | |
| 1929 | polling-delay-passive = <250>; | |
| 1930 | polling-delay = <1000>; | |
| 1931 | ||
| 1932 | thermal-sensors = <&tsens0 12>; | |
| 1933 | ||
| 1934 | trips { | |
| 1935 | cpu5_bottom_alert0: trip-point0 { | |
| 1936 | temperature = <90000>; | |
| 1937 | hysteresis = <2000>; | |
| 1938 | type = "passive"; | |
| 1939 | }; | |
| 1940 | ||
| 1941 | cpu5_bottom_alert1: trip-point1 { | |
| 1942 | temperature = <95000>; | |
| 1943 | hysteresis = <2000>; | |
| 1944 | type = "passive"; | |
| 1945 | }; | |
| 1946 | ||
| 1947 | cpu5_bottom_crit: cpu_crit { | |
| 1948 | temperature = <110000>; | |
| 1949 | hysteresis = <1000>; | |
| 1950 | type = "critical"; | |
| 1951 | }; | |
| 1952 | }; | |
| 1953 | ||
| 1954 | cooling-maps { | |
| 1955 | map0 { | |
| 1956 | trip = <&cpu5_bottom_alert0>; | |
| 1957 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1958 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1959 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1960 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1961 | }; | |
| 1962 | map1 { | |
| 1963 | trip = <&cpu5_bottom_alert1>; | |
| 1964 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1965 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1966 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 1967 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 1968 | }; | |
| 1969 | }; | |
| 1970 | }; | |
| 1971 | ||
| 1972 | cpu6-bottom-thermal { | |
| 1973 | polling-delay-passive = <250>; | |
| 1974 | polling-delay = <1000>; | |
| 1975 | ||
| 1976 | thermal-sensors = <&tsens0 13>; | |
| 1977 | ||
| 1978 | trips { | |
| 1979 | cpu6_bottom_alert0: trip-point0 { | |
| 1980 | temperature = <90000>; | |
| 1981 | hysteresis = <2000>; | |
| 1982 | type = "passive"; | |
| 1983 | }; | |
| 1984 | ||
| 1985 | cpu6_bottom_alert1: trip-point1 { | |
| 1986 | temperature = <95000>; | |
| 1987 | hysteresis = <2000>; | |
| 1988 | type = "passive"; | |
| 1989 | }; | |
| 1990 | ||
| 1991 | cpu6_bottom_crit: cpu_crit { | |
| 1992 | temperature = <110000>; | |
| 1993 | hysteresis = <1000>; | |
| 1994 | type = "critical"; | |
| 1995 | }; | |
| 1996 | }; | |
| 1997 | ||
| 1998 | cooling-maps { | |
| 1999 | map0 { | |
| 2000 | trip = <&cpu6_bottom_alert0>; | |
| 2001 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2002 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2003 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2004 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2005 | }; | |
| 2006 | map1 { | |
| 2007 | trip = <&cpu6_bottom_alert1>; | |
| 2008 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2009 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2010 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2011 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2012 | }; | |
| 2013 | }; | |
| 2014 | }; | |
| 2015 | ||
| 2016 | cpu7-bottom-thermal { | |
| 2017 | polling-delay-passive = <250>; | |
| 2018 | polling-delay = <1000>; | |
| 2019 | ||
| 2020 | thermal-sensors = <&tsens0 14>; | |
| 2021 | ||
| 2022 | trips { | |
| 2023 | cpu7_bottom_alert0: trip-point0 { | |
| 2024 | temperature = <90000>; | |
| 2025 | hysteresis = <2000>; | |
| 2026 | type = "passive"; | |
| 2027 | }; | |
| 2028 | ||
| 2029 | cpu7_bottom_alert1: trip-point1 { | |
| 2030 | temperature = <95000>; | |
| 2031 | hysteresis = <2000>; | |
| 2032 | type = "passive"; | |
| 2033 | }; | |
| 2034 | ||
| 2035 | cpu7_bottom_crit: cpu_crit { | |
| 2036 | temperature = <110000>; | |
| 2037 | hysteresis = <1000>; | |
| 2038 | type = "critical"; | |
| 2039 | }; | |
| 2040 | }; | |
| 2041 | ||
| 2042 | cooling-maps { | |
| 2043 | map0 { | |
| 2044 | trip = <&cpu7_bottom_alert0>; | |
| 2045 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2046 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2047 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2048 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2049 | }; | |
| 2050 | map1 { | |
| 2051 | trip = <&cpu7_bottom_alert1>; | |
| 2052 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2053 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2054 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2055 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2056 | }; | |
| 2057 | }; | |
| 2058 | }; | |
| 2059 | ||
| 2060 | aoss0-thermal { | |
| 2061 | polling-delay-passive = <250>; | |
| 2062 | polling-delay = <1000>; | |
| 2063 | ||
| 2064 | thermal-sensors = <&tsens0 0>; | |
| 2065 | ||
| 2066 | trips { | |
| 2067 | aoss0_alert0: trip-point0 { | |
| 2068 | temperature = <90000>; | |
| 2069 | hysteresis = <2000>; | |
| 2070 | type = "hot"; | |
| 2071 | }; | |
| 2072 | }; | |
| 2073 | }; | |
| 2074 | ||
| 2075 | cluster0-thermal { | |
| 2076 | polling-delay-passive = <250>; | |
| 2077 | polling-delay = <1000>; | |
| 2078 | ||
| 2079 | thermal-sensors = <&tsens0 5>; | |
| 2080 | ||
| 2081 | trips { | |
| 2082 | cluster0_alert0: trip-point0 { | |
| 2083 | temperature = <90000>; | |
| 2084 | hysteresis = <2000>; | |
| 2085 | type = "hot"; | |
| 2086 | }; | |
| 2087 | cluster0_crit: cluster0_crit { | |
| 2088 | temperature = <110000>; | |
| 2089 | hysteresis = <2000>; | |
| 2090 | type = "critical"; | |
| 2091 | }; | |
| 2092 | }; | |
| 2093 | }; | |
| 2094 | ||
| 2095 | cluster1-thermal { | |
| 2096 | polling-delay-passive = <250>; | |
| 2097 | polling-delay = <1000>; | |
| 2098 | ||
| 2099 | thermal-sensors = <&tsens0 6>; | |
| 2100 | ||
| 2101 | trips { | |
| 2102 | cluster1_alert0: trip-point0 { | |
| 2103 | temperature = <90000>; | |
| 2104 | hysteresis = <2000>; | |
| 2105 | type = "hot"; | |
| 2106 | }; | |
| 2107 | cluster1_crit: cluster1_crit { | |
| 2108 | temperature = <110000>; | |
| 2109 | hysteresis = <2000>; | |
| 2110 | type = "critical"; | |
| 2111 | }; | |
| 2112 | }; | |
| 2113 | }; | |
| 2114 | ||
| 2115 | aoss1-thermal { | |
| 2116 | polling-delay-passive = <250>; | |
| 2117 | polling-delay = <1000>; | |
| 2118 | ||
| 2119 | thermal-sensors = <&tsens1 0>; | |
| 2120 | ||
| 2121 | trips { | |
| 2122 | aoss1_alert0: trip-point0 { | |
| 2123 | temperature = <90000>; | |
| 2124 | hysteresis = <2000>; | |
| 2125 | type = "hot"; | |
| 2126 | }; | |
| 2127 | }; | |
| 2128 | }; | |
| 2129 | ||
| 2130 | gpu-thermal-top { | |
| 2131 | polling-delay-passive = <250>; | |
| 2132 | polling-delay = <1000>; | |
| 2133 | ||
| 2134 | thermal-sensors = <&tsens1 1>; | |
| 2135 | ||
| 2136 | trips { | |
| 2137 | gpu1_alert0: trip-point0 { | |
| 2138 | temperature = <90000>; | |
| 2139 | hysteresis = <1000>; | |
| 2140 | type = "hot"; | |
| 2141 | }; | |
| 2142 | }; | |
| 2143 | }; | |
| 2144 | ||
| 2145 | gpu-thermal-bottom { | |
| 2146 | polling-delay-passive = <250>; | |
| 2147 | polling-delay = <1000>; | |
| 2148 | ||
| 2149 | thermal-sensors = <&tsens1 2>; | |
| 2150 | ||
| 2151 | trips { | |
| 2152 | gpu2_alert0: trip-point0 { | |
| 2153 | temperature = <90000>; | |
| 2154 | hysteresis = <1000>; | |
| 2155 | type = "hot"; | |
| 2156 | }; | |
| 2157 | }; | |
| 2158 | }; | |
| 2159 | ||
| 2160 | nspss1-thermal { | |
| 2161 | polling-delay-passive = <250>; | |
| 2162 | polling-delay = <1000>; | |
| 2163 | ||
| 2164 | thermal-sensors = <&tsens1 3>; | |
| 2165 | ||
| 2166 | trips { | |
| 2167 | nspss1_alert0: trip-point0 { | |
| 2168 | temperature = <90000>; | |
| 2169 | hysteresis = <1000>; | |
| 2170 | type = "hot"; | |
| 2171 | }; | |
| 2172 | }; | |
| 2173 | }; | |
| 2174 | ||
| 2175 | nspss2-thermal { | |
| 2176 | polling-delay-passive = <250>; | |
| 2177 | polling-delay = <1000>; | |
| 2178 | ||
| 2179 | thermal-sensors = <&tsens1 4>; | |
| 2180 | ||
| 2181 | trips { | |
| 2182 | nspss2_alert0: trip-point0 { | |
| 2183 | temperature = <90000>; | |
| 2184 | hysteresis = <1000>; | |
| 2185 | type = "hot"; | |
| 2186 | }; | |
| 2187 | }; | |
| 2188 | }; | |
| 2189 | ||
| 2190 | nspss3-thermal { | |
| 2191 | polling-delay-passive = <250>; | |
| 2192 | polling-delay = <1000>; | |
| 2193 | ||
| 2194 | thermal-sensors = <&tsens1 5>; | |
| 2195 | ||
| 2196 | trips { | |
| 2197 | nspss3_alert0: trip-point0 { | |
| 2198 | temperature = <90000>; | |
| 2199 | hysteresis = <1000>; | |
| 2200 | type = "hot"; | |
| 2201 | }; | |
| 2202 | }; | |
| 2203 | }; | |
| 2204 | ||
| 2205 | video-thermal { | |
| 2206 | polling-delay-passive = <250>; | |
| 2207 | polling-delay = <1000>; | |
| 2208 | ||
| 2209 | thermal-sensors = <&tsens1 6>; | |
| 2210 | ||
| 2211 | trips { | |
| 2212 | video_alert0: trip-point0 { | |
| 2213 | temperature = <90000>; | |
| 2214 | hysteresis = <2000>; | |
| 2215 | type = "hot"; | |
| 2216 | }; | |
| 2217 | }; | |
| 2218 | }; | |
| 2219 | ||
| 2220 | mem-thermal { | |
| 2221 | polling-delay-passive = <250>; | |
| 2222 | polling-delay = <1000>; | |
| 2223 | ||
| 2224 | thermal-sensors = <&tsens1 7>; | |
| 2225 | ||
| 2226 | trips { | |
| 2227 | mem_alert0: trip-point0 { | |
| 2228 | temperature = <90000>; | |
| 2229 | hysteresis = <2000>; | |
| 2230 | type = "hot"; | |
| 2231 | }; | |
| 2232 | }; | |
| 2233 | }; | |
| 2234 | ||
| 2235 | modem1-thermal-top { | |
| 2236 | polling-delay-passive = <250>; | |
| 2237 | polling-delay = <1000>; | |
| 2238 | ||
| 2239 | thermal-sensors = <&tsens1 8>; | |
| 2240 | ||
| 2241 | trips { | |
| 2242 | modem1_alert0: trip-point0 { | |
| 2243 | temperature = <90000>; | |
| 2244 | hysteresis = <2000>; | |
| 2245 | type = "hot"; | |
| 2246 | }; | |
| 2247 | }; | |
| 2248 | }; | |
| 2249 | ||
| 2250 | modem2-thermal-top { | |
| 2251 | polling-delay-passive = <250>; | |
| 2252 | polling-delay = <1000>; | |
| 2253 | ||
| 2254 | thermal-sensors = <&tsens1 9>; | |
| 2255 | ||
| 2256 | trips { | |
| 2257 | modem2_alert0: trip-point0 { | |
| 2258 | temperature = <90000>; | |
| 2259 | hysteresis = <2000>; | |
| 2260 | type = "hot"; | |
| 2261 | }; | |
| 2262 | }; | |
| 2263 | }; | |
| 2264 | ||
| 2265 | modem3-thermal-top { | |
| 2266 | polling-delay-passive = <250>; | |
| 2267 | polling-delay = <1000>; | |
| 2268 | ||
| 2269 | thermal-sensors = <&tsens1 10>; | |
| 2270 | ||
| 2271 | trips { | |
| 2272 | modem3_alert0: trip-point0 { | |
| 2273 | temperature = <90000>; | |
| 2274 | hysteresis = <2000>; | |
| 2275 | type = "hot"; | |
| 2276 | }; | |
| 2277 | }; | |
| 2278 | }; | |
| 2279 | ||
| 2280 | modem4-thermal-top { | |
| 2281 | polling-delay-passive = <250>; | |
| 2282 | polling-delay = <1000>; | |
| 2283 | ||
| 2284 | thermal-sensors = <&tsens1 11>; | |
| 2285 | ||
| 2286 | trips { | |
| 2287 | modem4_alert0: trip-point0 { | |
| 2288 | temperature = <90000>; | |
| 2289 | hysteresis = <2000>; | |
| 2290 | type = "hot"; | |
| 2291 | }; | |
| 2292 | }; | |
| 2293 | }; | |
| 2294 | ||
| 2295 | camera-thermal-top { | |
| 2296 | polling-delay-passive = <250>; | |
| 2297 | polling-delay = <1000>; | |
| 2298 | ||
| 2299 | thermal-sensors = <&tsens1 12>; | |
| 2300 | ||
| 2301 | trips { | |
| 2302 | camera1_alert0: trip-point0 { | |
| 2303 | temperature = <90000>; | |
| 2304 | hysteresis = <2000>; | |
| 2305 | type = "hot"; | |
| 2306 | }; | |
| 2307 | }; | |
| 2308 | }; | |
| 2309 | ||
| 2310 | camera-thermal-bottom { | |
| 2311 | polling-delay-passive = <250>; | |
| 2312 | polling-delay = <1000>; | |
| 2313 | ||
| 2314 | thermal-sensors = <&tsens1 13>; | |
| 2315 | ||
| 2316 | trips { | |
| 2317 | camera2_alert0: trip-point0 { | |
| 2318 | temperature = <90000>; | |
| 2319 | hysteresis = <2000>; | |
| 2320 | type = "hot"; | |
| 2321 | }; | |
| 2322 | }; | |
| 2323 | }; | |
| 2324 | }; | |
| 2325 | ||
| b7e8f433 VK |
2326 | timer { |
| 2327 | compatible = "arm,armv8-timer"; | |
| 2328 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2329 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2330 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2331 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
| 2332 | }; | |
| 2333 | }; |