[people/ms/u-boot.git] / arch / m68k / cpu / mcf523x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>

#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
	scm_t *scm = (scm_t *) MMAP_SCM;

	/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
	out_be16(&wdog->cr, 0);
#endif

	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);

	/* Port configuration */
	out_8(&gpio->par_cs, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif

#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif

#ifdef CONFIG_FSL_I2C
	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
#endif
		break;
	}
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if (setclear) {
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_FECEMDC |
			GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
	} else {
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK |
			GPIO_PAR_FECI2C_EMDIO_MASK);
	}

	return 0;
}
#endif
Commit	Line	Data
4a442d31 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
c6d88630	6	* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
4a442d31 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4a442d31 TL	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
4a442d31 TL	10	*/
	11
	12	#include <common.h>
	13	#include <watchdog.h>
4a442d31	14	#include <asm/immap.h>
c6d88630	15	#include <asm/io.h>
4a442d31	16
f3962d3f TL	17	#if defined(CONFIG_CMD_NET)
	18	#include <config.h>
	19	#include <net.h>
	20	#include <asm/fec.h>
	21	#endif
	22
4a442d31 TL	23	/*
	24	* Breath some life into the CPU...
	25	*
	26	* Set up the memory map,
	27	* initialize a bunch of registers,
	28	* initialize the UPM's
	29	*/
	30	void cpu_init_f(void)
	31	{
c6d88630 AW	32	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	33	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	34	wdog_t wdog = (wdog_t ) MMAP_WDOG;
	35	scm_t scm = (scm_t ) MMAP_SCM;
4a442d31 TL	36
	37	/* watchdog is enabled by default - disable the watchdog */
	38	#ifndef CONFIG_WATCHDOG
c6d88630	39	out_be16(&wdog->cr, 0);
4a442d31 TL	40	#endif
4a442d31 TL	41
c6d88630	42	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR \| SCM_RAMBAR_BDE);
4a442d31 TL	43
4a442d31 TL	44	/* Port configuration */
c6d88630	45	out_8(&gpio->par_cs, 0);
4a442d31	46
6d0f6bcf	47	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
c6d88630 AW	48	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	49	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	50	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
4a442d31 TL	51	#endif
4a442d31 TL	52
6d0f6bcf	53	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
c6d88630 AW	54	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
	55	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	56	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	57	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
4a442d31 TL	58	#endif
4a442d31 TL	59
6d0f6bcf	60	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
c6d88630 AW	61	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
	62	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	63	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	64	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
4a442d31 TL	65	#endif
4a442d31 TL	66
6d0f6bcf	67	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
c6d88630 AW	68	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
	69	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	70	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	71	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
4a442d31 TL	72	#endif
4a442d31 TL	73
6d0f6bcf	74	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
c6d88630 AW	75	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
	76	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	77	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	78	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
4a442d31 TL	79	#endif
4a442d31 TL	80
6d0f6bcf	81	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
c6d88630 AW	82	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
	83	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	84	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	85	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
4a442d31 TL	86	#endif
4a442d31 TL	87
6d0f6bcf	88	#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
c6d88630 AW	89	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
	90	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
	91	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
	92	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
4a442d31 TL	93	#endif
4a442d31 TL	94
6d0f6bcf	95	#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
c6d88630 AW	96	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
	97	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
	98	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
	99	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
4a442d31 TL	100	#endif
	101
	102	#ifdef CONFIG_FSL_I2C
6d0f6bcf JCPV	103	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
6d0f6bcf JCPV	104	CONFIG_SYS_I2C_PINMUX_REG \|= CONFIG_SYS_I2C_PINMUX_SET;
4a442d31 TL	105	#endif
	106
	107	icache_enable();
	108	}
	109
	110	/*
	111	* initialize higher level parts of CPU like timers
	112	*/
	113	int cpu_init_r(void)
	114	{
	115	return (0);
	116	}
	117
52affe04	118	void uart_port_conf(int port)
4a442d31	119	{
c6d88630	120	gpio_t gpio = (gpio_t ) MMAP_GPIO;
8280f6a1 SR	121
8280f6a1 SR	122	/* Setup Ports: */
52affe04	123	switch (port) {
8280f6a1	124	case 0:
c6d88630 AW	125	clrbits_be16(&gpio->par_uart,
	126	GPIO_PAR_UART_U0RXD \| GPIO_PAR_UART_U0TXD);
	127	setbits_be16(&gpio->par_uart,
	128	GPIO_PAR_UART_U0RXD \| GPIO_PAR_UART_U0TXD);
8280f6a1 SR	129	break;
8280f6a1 SR	130	case 1:
c6d88630 AW	131	clrbits_be16(&gpio->par_uart,
	132	GPIO_PAR_UART_U1RXD_MASK \| GPIO_PAR_UART_U1TXD_MASK);
	133	setbits_be16(&gpio->par_uart,
	134	GPIO_PAR_UART_U1RXD_U1RXD \| GPIO_PAR_UART_U1TXD_U1TXD);
8280f6a1 SR	135	break;
8280f6a1 SR	136	case 2:
52affe04	137	#ifdef CONFIG_SYS_UART2_PRI_GPIO
c6d88630 AW	138	clrbits_be16(&gpio->par_uart,
	139	GPIO_PAR_UART_U2RXD \| GPIO_PAR_UART_U2TXD);
	140	setbits_be16(&gpio->par_uart,
	141	GPIO_PAR_UART_U2RXD \| GPIO_PAR_UART_U2TXD);
52affe04	142	#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
c6d88630 AW	143	clrbits_8(&gpio->par_feci2c,
	144	GPIO_PAR_FECI2C_EMDC_MASK \| GPIO_PAR_FECI2C_EMDIO_MASK);
	145	setbits_8(&gpio->par_feci2c,
	146	GPIO_PAR_FECI2C_EMDC_U2TXD \| GPIO_PAR_FECI2C_EMDIO_U2RXD);
52affe04	147	#endif
8280f6a1 SR	148	break;
8280f6a1 SR	149	}
4a442d31	150	}
f3962d3f TL	151
	152	#if defined(CONFIG_CMD_NET)
	153	int fecpin_setclear(struct eth_device *dev, int setclear)
	154	{
c6d88630	155	gpio_t gpio = (gpio_t ) MMAP_GPIO;
f3962d3f TL	156
f3962d3f TL	157	if (setclear) {
c6d88630 AW	158	setbits_8(&gpio->par_feci2c,
	159	GPIO_PAR_FECI2C_EMDC_FECEMDC \|
	160	GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
f3962d3f	161	} else {
c6d88630 AW	162	clrbits_8(&gpio->par_feci2c,
	163	GPIO_PAR_FECI2C_EMDC_MASK \|
	164	GPIO_PAR_FECI2C_EMDIO_MASK);
f3962d3f TL	165	}
	166
	167	return 0;
	168	}
	169	#endif