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Commit | Line | Data |
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8ae158cd TL |
1 | /* |
2 | * | |
3 | * (C) Copyright 2000-2003 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
198cafbf | 6 | * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. |
8ae158cd TL |
7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
8ae158cd TL |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <watchdog.h> | |
8ae158cd | 14 | #include <asm/immap.h> |
68e4e76a | 15 | #include <asm/processor.h> |
8ae158cd | 16 | #include <asm/rtc.h> |
198cafbf | 17 | #include <asm/io.h> |
2b05593d | 18 | #include <linux/compiler.h> |
8ae158cd | 19 | |
f3962d3f TL |
20 | #if defined(CONFIG_CMD_NET) |
21 | #include <config.h> | |
22 | #include <net.h> | |
23 | #include <asm/fec.h> | |
24 | #endif | |
25 | ||
45370e18 | 26 | void init_fbcs(void) |
8ae158cd | 27 | { |
2b05593d | 28 | fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; |
198cafbf | 29 | |
45370e18 | 30 | #if !defined(CONFIG_SERIAL_BOOT) |
6d0f6bcf | 31 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) |
198cafbf AW |
32 | out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); |
33 | out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); | |
34 | out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); | |
8ae158cd | 35 | #endif |
9f751551 | 36 | #endif |
8ae158cd | 37 | |
6d0f6bcf | 38 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) |
8ae158cd | 39 | /* Latch chipselect */ |
198cafbf AW |
40 | out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); |
41 | out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); | |
42 | out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); | |
8ae158cd TL |
43 | #endif |
44 | ||
6d0f6bcf | 45 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) |
198cafbf AW |
46 | out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); |
47 | out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); | |
48 | out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); | |
8ae158cd TL |
49 | #endif |
50 | ||
6d0f6bcf | 51 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) |
198cafbf AW |
52 | out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); |
53 | out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); | |
54 | out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); | |
8ae158cd TL |
55 | #endif |
56 | ||
6d0f6bcf | 57 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) |
198cafbf AW |
58 | out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); |
59 | out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); | |
60 | out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); | |
8ae158cd TL |
61 | #endif |
62 | ||
6d0f6bcf | 63 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) |
198cafbf AW |
64 | out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); |
65 | out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); | |
66 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); | |
8ae158cd | 67 | #endif |
45370e18 AW |
68 | } |
69 | ||
70 | /* | |
71 | * Breath some life into the CPU... | |
72 | * | |
73 | * Set up the memory map, | |
74 | * initialize a bunch of registers, | |
75 | * initialize the UPM's | |
76 | */ | |
77 | void cpu_init_f(void) | |
78 | { | |
79 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
80 | ||
81 | #ifdef CONFIG_MCF5441x | |
82 | scm_t *scm = (scm_t *) MMAP_SCM; | |
83 | pm_t *pm = (pm_t *) MMAP_PM; | |
84 | ||
85 | /* Disable Switch */ | |
86 | *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0; | |
87 | ||
88 | /* Disable core watchdog */ | |
89 | out_be16(&scm->cwcr, 0); | |
90 | out_8(&gpio->par_fbctl, | |
91 | GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE | | |
92 | GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW | | |
93 | GPIO_PAR_FBCTL_TA_TA); | |
94 | out_8(&gpio->par_be, | |
95 | GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | | |
96 | GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); | |
97 | ||
98 | /* eDMA */ | |
99 | out_8(&pm->pmcr0, 17); | |
100 | ||
101 | /* INTR0 - INTR2 */ | |
102 | out_8(&pm->pmcr0, 18); | |
103 | out_8(&pm->pmcr0, 19); | |
104 | out_8(&pm->pmcr0, 20); | |
105 | ||
106 | /* I2C */ | |
107 | out_8(&pm->pmcr0, 22); | |
108 | out_8(&pm->pmcr1, 4); | |
109 | out_8(&pm->pmcr1, 7); | |
110 | ||
111 | /* DTMR0 - DTMR3*/ | |
112 | out_8(&pm->pmcr0, 28); | |
113 | out_8(&pm->pmcr0, 29); | |
114 | out_8(&pm->pmcr0, 30); | |
115 | out_8(&pm->pmcr0, 31); | |
116 | ||
117 | /* PIT0 - PIT3 */ | |
118 | out_8(&pm->pmcr0, 32); | |
119 | out_8(&pm->pmcr0, 33); | |
120 | out_8(&pm->pmcr0, 34); | |
121 | out_8(&pm->pmcr0, 35); | |
122 | ||
123 | /* Edge Port */ | |
124 | out_8(&pm->pmcr0, 36); | |
125 | out_8(&pm->pmcr0, 37); | |
126 | ||
127 | /* USB OTG */ | |
128 | out_8(&pm->pmcr0, 44); | |
129 | /* USB Host */ | |
130 | out_8(&pm->pmcr0, 45); | |
131 | ||
132 | /* ESDHC */ | |
133 | out_8(&pm->pmcr0, 51); | |
134 | ||
135 | /* ENET0 - ENET1 */ | |
136 | out_8(&pm->pmcr0, 53); | |
137 | out_8(&pm->pmcr0, 54); | |
138 | ||
139 | /* NAND */ | |
140 | out_8(&pm->pmcr0, 63); | |
141 | ||
142 | #ifdef CONFIG_SYS_I2C_0 | |
143 | out_8(&gpio->par_cani2c, 0xF0); | |
144 | /* I2C0 pull up */ | |
145 | out_be16(&gpio->pcr_b, 0x003C); | |
146 | /* I2C0 max speed */ | |
147 | out_8(&gpio->srcr_cani2c, 0x03); | |
148 | #endif | |
149 | #ifdef CONFIG_SYS_I2C_2 | |
150 | /* I2C2 */ | |
151 | out_8(&gpio->par_ssi0h, 0xA0); | |
152 | /* I2C2, UART7 */ | |
153 | out_8(&gpio->par_ssi0h, 0xA8); | |
154 | /* UART7 */ | |
155 | out_8(&gpio->par_ssi0l, 0x2); | |
156 | /* UART8, UART9 */ | |
157 | out_8(&gpio->par_cani2c, 0xAA); | |
158 | /* UART4, UART0 */ | |
159 | out_8(&gpio->par_uart0, 0xAF); | |
160 | /* UART5, UART1 */ | |
161 | out_8(&gpio->par_uart1, 0xAF); | |
162 | /* UART6, UART2 */ | |
163 | out_8(&gpio->par_uart2, 0xAF); | |
164 | /* I2C2 pull up */ | |
165 | out_be16(&gpio->pcr_h, 0xF000); | |
166 | #endif | |
167 | #ifdef CONFIG_SYS_I2C_5 | |
168 | /* I2C5 */ | |
169 | out_8(&gpio->par_uart1, 0x0A); | |
170 | /* I2C5 pull up */ | |
171 | out_be16(&gpio->pcr_e, 0x0003); | |
172 | out_be16(&gpio->pcr_f, 0xC000); | |
173 | #endif | |
174 | ||
175 | /* Lowest slew rate for UART0,1,2 */ | |
176 | out_8(&gpio->srcr_uart, 0x00); | |
177 | #endif /* CONFIG_MCF5441x */ | |
178 | ||
179 | #ifdef CONFIG_MCF5445x | |
180 | scm1_t *scm1 = (scm1_t *) MMAP_SCM1; | |
181 | ||
182 | out_be32(&scm1->mpr, 0x77777777); | |
183 | out_be32(&scm1->pacra, 0); | |
184 | out_be32(&scm1->pacrb, 0); | |
185 | out_be32(&scm1->pacrc, 0); | |
186 | out_be32(&scm1->pacrd, 0); | |
187 | out_be32(&scm1->pacre, 0); | |
188 | out_be32(&scm1->pacrf, 0); | |
189 | out_be32(&scm1->pacrg, 0); | |
190 | ||
191 | /* FlexBus */ | |
192 | out_8(&gpio->par_be, | |
193 | GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | | |
194 | GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); | |
195 | out_8(&gpio->par_fbctl, | |
196 | GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | | |
197 | GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); | |
198 | ||
199 | #ifdef CONFIG_FSL_I2C | |
200 | out_be16(&gpio->par_feci2c, | |
201 | GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); | |
202 | #endif | |
203 | #endif /* CONFIG_MCF5445x */ | |
204 | ||
205 | /* FlexBus Chipselect */ | |
206 | init_fbcs(); | |
8ae158cd | 207 | |
68e4e76a TL |
208 | /* |
209 | * now the flash base address is no longer at 0 (Newer ColdFire family | |
210 | * boot at address 0 instead of 0xFFnn_nnnn). The vector table must | |
211 | * also move to the new location. | |
212 | */ | |
213 | if (CONFIG_SYS_CS0_BASE != 0) | |
214 | setvbr(CONFIG_SYS_CS0_BASE); | |
215 | ||
8ae158cd TL |
216 | icache_enable(); |
217 | } | |
218 | ||
219 | /* | |
220 | * initialize higher level parts of CPU like timers | |
221 | */ | |
222 | int cpu_init_r(void) | |
223 | { | |
bc3ccb13 | 224 | #ifdef CONFIG_MCFRTC |
198cafbf AW |
225 | rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); |
226 | rtcex_t *rtcex = (rtcex_t *)&rtc->extended; | |
8ae158cd | 227 | |
198cafbf AW |
228 | out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); |
229 | out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); | |
8ae158cd TL |
230 | #endif |
231 | ||
232 | return (0); | |
233 | } | |
234 | ||
52affe04 | 235 | void uart_port_conf(int port) |
8ae158cd | 236 | { |
198cafbf | 237 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
45370e18 AW |
238 | #ifdef CONFIG_MCF5441x |
239 | pm_t *pm = (pm_t *) MMAP_PM; | |
240 | #endif | |
8ae158cd TL |
241 | |
242 | /* Setup Ports: */ | |
52affe04 | 243 | switch (port) { |
45370e18 AW |
244 | #ifdef CONFIG_MCF5441x |
245 | case 0: | |
246 | /* UART0 */ | |
247 | out_8(&pm->pmcr0, 24); | |
248 | clrbits_8(&gpio->par_uart0, | |
249 | ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK)); | |
250 | setbits_8(&gpio->par_uart0, | |
251 | GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD); | |
252 | break; | |
253 | case 1: | |
254 | /* UART1 */ | |
255 | out_8(&pm->pmcr0, 25); | |
256 | clrbits_8(&gpio->par_uart1, | |
257 | ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK)); | |
258 | setbits_8(&gpio->par_uart1, | |
259 | GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD); | |
260 | break; | |
261 | case 2: | |
262 | /* UART2 */ | |
263 | out_8(&pm->pmcr0, 26); | |
264 | clrbits_8(&gpio->par_uart2, | |
265 | ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK)); | |
266 | setbits_8(&gpio->par_uart2, | |
267 | GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD); | |
268 | break; | |
269 | case 3: | |
270 | /* UART3 */ | |
271 | out_8(&pm->pmcr0, 27); | |
272 | clrbits_8(&gpio->par_dspi0, | |
273 | ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK)); | |
274 | setbits_8(&gpio->par_dspi0, | |
275 | GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD); | |
276 | break; | |
277 | case 4: | |
278 | /* UART4 */ | |
279 | out_8(&pm->pmcr1, 24); | |
280 | clrbits_8(&gpio->par_uart0, | |
281 | ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK)); | |
282 | setbits_8(&gpio->par_uart0, | |
283 | GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD); | |
284 | break; | |
285 | case 5: | |
286 | /* UART5 */ | |
287 | out_8(&pm->pmcr1, 25); | |
288 | clrbits_8(&gpio->par_uart1, | |
289 | ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK)); | |
290 | setbits_8(&gpio->par_uart1, | |
291 | GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD); | |
292 | break; | |
293 | case 6: | |
294 | /* UART6 */ | |
295 | out_8(&pm->pmcr1, 26); | |
296 | clrbits_8(&gpio->par_uart2, | |
297 | ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK)); | |
298 | setbits_8(&gpio->par_uart2, | |
299 | GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD); | |
300 | break; | |
301 | case 7: | |
302 | /* UART7 */ | |
303 | out_8(&pm->pmcr1, 27); | |
304 | clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK); | |
305 | clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK); | |
306 | setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD); | |
307 | setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD); | |
308 | break; | |
309 | case 8: | |
310 | /* UART8 */ | |
311 | out_8(&pm->pmcr0, 28); | |
312 | clrbits_8(&gpio->par_cani2c, | |
313 | ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK)); | |
314 | setbits_8(&gpio->par_cani2c, | |
315 | GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD); | |
316 | break; | |
317 | case 9: | |
318 | /* UART9 */ | |
319 | out_8(&pm->pmcr1, 29); | |
320 | clrbits_8(&gpio->par_cani2c, | |
321 | ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK)); | |
322 | setbits_8(&gpio->par_cani2c, | |
323 | GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD); | |
324 | break; | |
325 | #endif | |
326 | #ifdef CONFIG_MCF5445x | |
8ae158cd | 327 | case 0: |
198cafbf AW |
328 | clrbits_8(&gpio->par_uart, |
329 | GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); | |
330 | setbits_8(&gpio->par_uart, | |
331 | GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); | |
8ae158cd TL |
332 | break; |
333 | case 1: | |
52affe04 | 334 | #ifdef CONFIG_SYS_UART1_PRI_GPIO |
198cafbf AW |
335 | clrbits_8(&gpio->par_uart, |
336 | GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); | |
337 | setbits_8(&gpio->par_uart, | |
338 | GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); | |
52affe04 | 339 | #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) |
198cafbf AW |
340 | clrbits_be16(&gpio->par_ssi, |
341 | ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); | |
342 | setbits_be16(&gpio->par_ssi, | |
343 | GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); | |
52affe04 TL |
344 | #endif |
345 | break; | |
346 | case 2: | |
347 | #if defined(CONFIG_SYS_UART2_ALT1_GPIO) | |
198cafbf AW |
348 | clrbits_8(&gpio->par_timer, |
349 | ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); | |
350 | setbits_8(&gpio->par_timer, | |
351 | GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); | |
52affe04 | 352 | #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) |
198cafbf AW |
353 | clrbits_8(&gpio->par_timer, |
354 | ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); | |
355 | setbits_8(&gpio->par_timer, | |
356 | GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); | |
52affe04 | 357 | #endif |
8ae158cd | 358 | break; |
45370e18 | 359 | #endif /* CONFIG_MCF5445x */ |
8ae158cd TL |
360 | } |
361 | } | |
f3962d3f TL |
362 | |
363 | #if defined(CONFIG_CMD_NET) | |
364 | int fecpin_setclear(struct eth_device *dev, int setclear) | |
365 | { | |
198cafbf | 366 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
f3962d3f TL |
367 | struct fec_info_s *info = (struct fec_info_s *)dev->priv; |
368 | ||
45370e18 | 369 | #ifdef CONFIG_MCF5445x |
f3962d3f | 370 | if (setclear) { |
ae490997 WW |
371 | #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY |
372 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) | |
198cafbf AW |
373 | setbits_be16(&gpio->par_feci2c, |
374 | GPIO_PAR_FECI2C_MDC0_MDC0 | | |
375 | GPIO_PAR_FECI2C_MDIO0_MDIO0); | |
ae490997 | 376 | else |
198cafbf AW |
377 | setbits_be16(&gpio->par_feci2c, |
378 | GPIO_PAR_FECI2C_MDC1_MDC1 | | |
379 | GPIO_PAR_FECI2C_MDIO1_MDIO1); | |
ae490997 | 380 | #else |
198cafbf AW |
381 | setbits_be16(&gpio->par_feci2c, |
382 | GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); | |
ae490997 | 383 | #endif |
f3962d3f TL |
384 | |
385 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) | |
198cafbf | 386 | setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); |
f3962d3f | 387 | else |
198cafbf | 388 | setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); |
f3962d3f | 389 | } else { |
198cafbf AW |
390 | clrbits_be16(&gpio->par_feci2c, |
391 | GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); | |
f3962d3f | 392 | |
adf55679 WW |
393 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { |
394 | #ifdef CONFIG_SYS_FEC_FULL_MII | |
198cafbf | 395 | setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); |
adf55679 | 396 | #else |
198cafbf | 397 | clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); |
adf55679 WW |
398 | #endif |
399 | } else { | |
400 | #ifdef CONFIG_SYS_FEC_FULL_MII | |
198cafbf | 401 | setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); |
adf55679 | 402 | #else |
198cafbf | 403 | clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); |
adf55679 WW |
404 | #endif |
405 | } | |
f3962d3f | 406 | } |
45370e18 AW |
407 | #endif /* CONFIG_MCF5445x */ |
408 | ||
409 | #ifdef CONFIG_MCF5441x | |
410 | if (setclear) { | |
411 | out_8(&gpio->par_fec, 0x03); | |
412 | out_8(&gpio->srcr_fec, 0x0F); | |
413 | clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK, | |
414 | GPIO_PAR_SIMP0H_DAT_GPIO); | |
415 | clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK, | |
416 | GPIO_PDDR_G4_OUTPUT); | |
417 | clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK); | |
418 | ||
419 | } else | |
420 | clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK); | |
421 | #endif | |
f3962d3f TL |
422 | return 0; |
423 | } | |
424 | #endif | |
ee0a8462 TL |
425 | |
426 | #ifdef CONFIG_CF_DSPI | |
427 | void cfspi_port_conf(void) | |
428 | { | |
198cafbf | 429 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
ee0a8462 | 430 | |
45370e18 | 431 | #ifdef CONFIG_MCF5445x |
198cafbf AW |
432 | out_8(&gpio->par_dspi, |
433 | GPIO_PAR_DSPI_SIN_SIN | | |
434 | GPIO_PAR_DSPI_SOUT_SOUT | | |
435 | GPIO_PAR_DSPI_SCK_SCK); | |
45370e18 AW |
436 | #endif |
437 | ||
438 | #ifdef CONFIG_MCF5441x | |
439 | pm_t *pm = (pm_t *) MMAP_PM; | |
440 | ||
441 | out_8(&gpio->par_dspi0, | |
442 | GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | | |
443 | GPIO_PAR_DSPI0_SCK_DSPI0SCK); | |
444 | out_8(&gpio->srcr_dspiow, 3); | |
445 | ||
446 | /* DSPI0 */ | |
447 | out_8(&pm->pmcr0, 23); | |
448 | #endif | |
ee0a8462 TL |
449 | } |
450 | ||
451 | int cfspi_claim_bus(uint bus, uint cs) | |
452 | { | |
198cafbf AW |
453 | dspi_t *dspi = (dspi_t *) MMAP_DSPI; |
454 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
ee0a8462 | 455 | |
198cafbf | 456 | if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) |
ee0a8462 TL |
457 | return -1; |
458 | ||
459 | /* Clear FIFO and resume transfer */ | |
198cafbf | 460 | clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); |
ee0a8462 | 461 | |
45370e18 | 462 | #ifdef CONFIG_MCF5445x |
ee0a8462 TL |
463 | switch (cs) { |
464 | case 0: | |
198cafbf AW |
465 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); |
466 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); | |
ee0a8462 TL |
467 | break; |
468 | case 1: | |
198cafbf AW |
469 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); |
470 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); | |
ee0a8462 TL |
471 | break; |
472 | case 2: | |
198cafbf AW |
473 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); |
474 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); | |
ee0a8462 | 475 | break; |
e9b43cae | 476 | case 3: |
198cafbf AW |
477 | clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); |
478 | setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); | |
e9b43cae | 479 | break; |
ee0a8462 | 480 | case 5: |
198cafbf AW |
481 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); |
482 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); | |
ee0a8462 TL |
483 | break; |
484 | } | |
45370e18 AW |
485 | #endif |
486 | ||
487 | #ifdef CONFIG_MCF5441x | |
488 | switch (cs) { | |
489 | case 0: | |
490 | clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK); | |
491 | setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0); | |
492 | break; | |
493 | case 1: | |
494 | clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); | |
495 | setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); | |
496 | break; | |
497 | } | |
498 | #endif | |
ee0a8462 TL |
499 | |
500 | return 0; | |
501 | } | |
502 | ||
503 | void cfspi_release_bus(uint bus, uint cs) | |
504 | { | |
198cafbf AW |
505 | dspi_t *dspi = (dspi_t *) MMAP_DSPI; |
506 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
ee0a8462 | 507 | |
198cafbf AW |
508 | /* Clear FIFO */ |
509 | clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); | |
ee0a8462 | 510 | |
45370e18 | 511 | #ifdef CONFIG_MCF5445x |
ee0a8462 TL |
512 | switch (cs) { |
513 | case 0: | |
198cafbf | 514 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); |
ee0a8462 TL |
515 | break; |
516 | case 1: | |
198cafbf | 517 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); |
ee0a8462 TL |
518 | break; |
519 | case 2: | |
198cafbf | 520 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); |
ee0a8462 | 521 | break; |
e9b43cae | 522 | case 3: |
198cafbf | 523 | clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); |
e9b43cae | 524 | break; |
ee0a8462 | 525 | case 5: |
198cafbf | 526 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); |
ee0a8462 TL |
527 | break; |
528 | } | |
45370e18 AW |
529 | #endif |
530 | ||
531 | #ifdef CONFIG_MCF5441x | |
532 | if (cs == 1) | |
533 | clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); | |
534 | #endif | |
ee0a8462 TL |
535 | } |
536 | #endif |