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m68k: code reformatting for all start.S files
[people/ms/u-boot.git] / arch / m68k / cpu / mcf5445x / start.S
CommitLineData
8ae158cd
TL		 1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
45370e18
AW		 5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
8ae158cd
TL		 9 */
10
45370e18 11#include <common.h>
25ddd1fb 12#include <asm-offsets.h>
8ae158cd 13#include <config.h>
45370e18 14#include <timestamp.h>
8ae158cd 15#include "version.h"
dd9f054e 16#include <asm/cache.h>
8ae158cd
TL		 17
18#ifndef CONFIG_IDENT_STRING
19#define CONFIG_IDENT_STRING ""
20#endif
21
8ae158cd
TL		 22#define _START _start
23#define _FAULT _fault
24
25#define SAVE_ALL \
26 move.w #0x2700,%sr; /* disable intrs */ \
27 subl #60,%sp; /* space for 15 regs */ \
28 moveml %d0-%d7/%a0-%a6,%sp@;
29
30#define RESTORE_ALL \
31 moveml %sp@,%d0-%d7/%a0-%a6; \
32 addl #60,%sp; /* space for 15 regs */ \
33 rte;
34
45370e18 35#if defined(CONFIG_SERIAL_BOOT)
5c928d02
AD		 36#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
37 CONFIG_SYS_INIT_RAM_ADDR)
61a4392a 38#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
5c928d02
AD		 39#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
40 CONFIG_SYS_INIT_RAM_ADDR)
9f751551
TL		 41#endif
42
8ae158cd 43.text
9f751551 44
8ae158cd 45/*
5c928d02
AD		 46 * Vector table. This is used for initial platform startup.
47 * These vectors are to catch any un-intended traps.
8ae158cd
TL		 48 */
49_vectors:
45370e18 50#if defined(CONFIG_SERIAL_BOOT)
9f751551 51
5c928d02 52INITSP: .long 0 /* Initial SP */
45370e18 53#ifdef CONFIG_CF_SBF
5c928d02 54INITPC: .long ASM_DRAMINIT /* Initial PC */
45370e18
AW		 55#endif
56#ifdef CONFIG_SYS_NAND_BOOT
5c928d02 57INITPC: .long ASM_DRAMINIT_N /* Initial PC */
45370e18 58#endif
9f751551
TL		 59
60#else
61
5c928d02
AD		 62INITSP: .long 0 /* Initial SP */
63INITPC: .long _START /* Initial PC */
9f751551
TL		 64
65#endif
8ae158cd 66
5c928d02
AD		 67vector02_0F:
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
8ae158cd
TL		 70
71/* Reserved */
72vector10_17:
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74
5c928d02
AD		 75vector18_1F:
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
8ae158cd 77
45370e18 78#if !defined(CONFIG_SERIAL_BOOT)
9f751551 79
8ae158cd
TL		 80/* TRAP #0 - #15 */
81vector20_2F:
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85/* Reserved */
86vector30_3F:
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89
90vector64_127:
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99
100vector128_191:
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109
110vector192_255:
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
9f751551 119#endif
8ae158cd 120
45370e18 121#if defined(CONFIG_SERIAL_BOOT)
9f751551
TL		 122 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
123asm_sbf_img_hdr:
5c928d02
AD		 124 .long 0x00000000 /* checksum, not yet implemented */
125 .long 0x00040000 /* image length */
14d0a02a 126 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
9f751551
TL		 127
128asm_dram_init:
5c928d02 129 move.w #0x2700,%sr /* Mask off Interrupt */
709b384b 130
45370e18
AW		 131#ifdef CONFIG_SYS_NAND_BOOT
132 /* for assembly stack */
133 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
134 movec %d0, %RAMBAR1
135
136 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
5c928d02 137 clr.l %sp@-
45370e18
AW		 138#endif
139
140#ifdef CONFIG_CF_SBF
709b384b
TL		 141 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
142 movec %d0, %VBR
143
6d0f6bcf 144 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
709b384b
TL		 145 movec %d0, %RAMBAR1
146
147 /* initialize general use internal ram */
5c928d02
AD		 148 move.l #0, %d0
149 move.l #(ICACHE_STATUS), %a1 /* icache */
150 move.l #(DCACHE_STATUS), %a2 /* dcache */
151 move.l %d0, (%a1)
152 move.l %d0, (%a2)
709b384b
TL		 153
154 /* invalidate and disable cache */
dd9f054e 155 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
709b384b
TL		 156 movec %d0, %CACR /* Invalidate cache */
157 move.l #0, %d0
158 movec %d0, %ACR0
159 movec %d0, %ACR1
160 movec %d0, %ACR2
161 movec %d0, %ACR3
162
6d0f6bcf 163 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
5c928d02 164 clr.l %sp@-
9f751551
TL		 165
166 /* Must disable global address */
167 move.l #0xFC008000, %a1
6d0f6bcf 168 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
9f751551 169 move.l #0xFC008008, %a1
6d0f6bcf 170 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
9f751551 171 move.l #0xFC008004, %a1
6d0f6bcf 172 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
5c928d02 173#endif /* CONFIG_CF_SBF */
45370e18
AW		 174
175#ifdef CONFIG_MCF5441x
176 /* TC: enable all peripherals,
177 in the future only enable certain peripherals */
178 move.l #0xFC04002D, %a1
9f751551 179
45370e18 180#if defined(CONFIG_CF_SBF)
5c928d02 181 move.b #23, (%a1) /* dspi */
45370e18 182#endif
5c928d02 183 move.b #46, (%a1) /* DDR */
45370e18
AW		 184
185 /* slew settings */
186 move.l #0xEC094060, %a1
187 move.b #0, (%a1)
188
189 /* use vco instead of cpu*2 clock for ddr clock */
190 move.l #0xEC09001A, %a1
191 move.w #0xE01D, (%a1)
192
193 /* DDR settings */
194 move.l #0xFC0B8180, %a1
195 move.l #0x00000000, (%a1)
196 move.l #0x40000000, (%a1)
197
198 move.l #0xFC0B81AC, %a1
199 move.l #0x01030203, (%a1)
200
201 move.l #0xFC0B8000, %a1
202 move.l #0x01010101, (%a1)+ /* 0x00 */
203 move.l #0x00000101, (%a1)+ /* 0x04 */
204 move.l #0x01010100, (%a1)+ /* 0x08 */
205 move.l #0x01010000, (%a1)+ /* 0x0C */
206 move.l #0x00010101, (%a1)+ /* 0x10 */
207 move.l #0xFC0B8018, %a1
208 move.l #0x00010100, (%a1)+ /* 0x18 */
209 move.l #0x00000001, (%a1)+ /* 0x1C */
210 move.l #0x01000001, (%a1)+ /* 0x20 */
211 move.l #0x00000100, (%a1)+ /* 0x24 */
212 move.l #0x00010001, (%a1)+ /* 0x28 */
213 move.l #0x00000200, (%a1)+ /* 0x2C */
214 move.l #0x01000002, (%a1)+ /* 0x30 */
215 move.l #0x00000000, (%a1)+ /* 0x34 */
216 move.l #0x00000100, (%a1)+ /* 0x38 */
217 move.l #0x02000100, (%a1)+ /* 0x3C */
218 move.l #0x02000407, (%a1)+ /* 0x40 */
219 move.l #0x02030007, (%a1)+ /* 0x44 */
220 move.l #0x02000100, (%a1)+ /* 0x48 */
221 move.l #0x0A030203, (%a1)+ /* 0x4C */
222 move.l #0x00020708, (%a1)+ /* 0x50 */
223 move.l #0x00050008, (%a1)+ /* 0x54 */
224 move.l #0x04030002, (%a1)+ /* 0x58 */
225 move.l #0x00000004, (%a1)+ /* 0x5C */
226 move.l #0x020A0000, (%a1)+ /* 0x60 */
227 move.l #0x0C00000E, (%a1)+ /* 0x64 */
228 move.l #0x00002004, (%a1)+ /* 0x68 */
229 move.l #0x00000000, (%a1)+ /* 0x6C */
230 move.l #0x00100010, (%a1)+ /* 0x70 */
231 move.l #0x00100010, (%a1)+ /* 0x74 */
232 move.l #0x00000000, (%a1)+ /* 0x78 */
233 move.l #0x07990000, (%a1)+ /* 0x7C */
234 move.l #0xFC0B80A0, %a1
235 move.l #0x00000000, (%a1)+ /* 0xA0 */
236 move.l #0x00C80064, (%a1)+ /* 0xA4 */
237 move.l #0x44520002, (%a1)+ /* 0xA8 */
238 move.l #0x00C80023, (%a1)+ /* 0xAC */
239 move.l #0xFC0B80B4, %a1
240 move.l #0x0000C350, (%a1) /* 0xB4 */
241 move.l #0xFC0B80E0, %a1
242 move.l #0x04000000, (%a1)+ /* 0xE0 */
243 move.l #0x03000304, (%a1)+ /* 0xE4 */
244 move.l #0x40040000, (%a1)+ /* 0xE8 */
245 move.l #0xC0004004, (%a1)+ /* 0xEC */
246 move.l #0x0642C000, (%a1)+ /* 0xF0 */
247 move.l #0x00000642, (%a1)+ /* 0xF4 */
248 move.l #0xFC0B8024, %a1
249 tpf
250 move.l #0x01000100, (%a1) /* 0x24 */
251
252 move.l #0x2000, %d1
253 jsr asm_delay
254#endif /* CONFIG_MCF5441x */
255
256#ifdef CONFIG_MCF5445x
709b384b 257 /* Dram Initialization a1, a2, and d0 */
9f751551
TL		 258 /* mscr sdram */
259 move.l #0xFC0A4074, %a1
6d0f6bcf 260 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
9f751551
TL		 261 nop
262
263 /* SDRAM Chip 0 and 1 */
264 move.l #0xFC0B8110, %a1
265 move.l #0xFC0B8114, %a2
266
267 /* calculate the size */
268 move.l #0x13, %d1
6d0f6bcf
JCPV		 269 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
270#ifdef CONFIG_SYS_SDRAM_BASE1
9f751551
TL		 271 lsr.l #1, %d2
272#endif
273
274dramsz_loop:
275 lsr.l #1, %d2
276 add.l #1, %d1
277 cmp.l #1, %d2
278 bne dramsz_loop
45370e18
AW		 279#ifdef CONFIG_SYS_NAND_BOOT
280 beq asm_nand_chk_status
281#endif
9f751551 282 /* SDRAM Chip 0 and 1 */
6d0f6bcf 283 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
9f751551 284 or.l %d1, (%a1)
6d0f6bcf
JCPV		 285#ifdef CONFIG_SYS_SDRAM_BASE1
286 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
9f751551
TL		 287 or.l %d1, (%a2)
288#endif
289 nop
290
291 /* dram cfg1 and cfg2 */
292 move.l #0xFC0B8008, %a1
6d0f6bcf 293 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
9f751551
TL		 294 nop
295 move.l #0xFC0B800C, %a2
6d0f6bcf 296 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
9f751551
TL		 297 nop
298
299 move.l #0xFC0B8000, %a1 /* Mode */
300 move.l #0xFC0B8004, %a2 /* Ctrl */
301
9f751551 302 /* Issue PALL */
6d0f6bcf 303 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
9f751551
TL		 304 nop
305
709b384b 306#ifdef CONFIG_M54455EVB
9f751551 307 /* Issue LEMR */
6d0f6bcf 308 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
9f751551 309 nop
6d0f6bcf 310 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
9f751551 311 nop
9f751551
TL		 312#endif
313
709b384b
TL		 314 move.l #1000, %d1
315 jsr asm_delay
316
9f751551 317 /* Issue PALL */
6d0f6bcf 318 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
9f751551
TL		 319 nop
320
321 /* Perform two refresh cycles */
6d0f6bcf 322 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
9f751551
TL		 323 nop
324 move.l %d0, (%a2)
325 move.l %d0, (%a2)
326 nop
327
328#ifdef CONFIG_M54455EVB
6d0f6bcf 329 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
9f751551
TL		 330 nop
331#elif defined(CONFIG_M54451EVB)
332 /* Issue LEMR */
c3a9e637 333 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
9f751551 334 nop
c3a9e637 335 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
9f751551
TL		 336#endif
337
709b384b
TL		 338 move.l #500, %d1
339 jsr asm_delay
9f751551 340
709b384b
TL		 341 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
342 and.l #0x7FFFFFFF, %d1
9f751551 343#ifdef CONFIG_M54455EVB
709b384b 344 or.l #0x10000C00, %d1
9f751551 345#elif defined(CONFIG_M54451EVB)
709b384b 346 or.l #0x10000C00, %d1
9f751551 347#endif
709b384b 348 move.l %d1, (%a2)
9f751551
TL		 349 nop
350
709b384b
TL		 351 move.l #2000, %d1
352 jsr asm_delay
5c928d02 353#endif /* CONFIG_MCF5445x */
709b384b 354
45370e18 355#ifdef CONFIG_CF_SBF
9f751551
TL		 356 /*
357 * DSPI Initialization
358 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
359 * a1 - dspi status
360 * a2 - dtfr
361 * a3 - drfr
362 * a4 - Dst addr
363 */
364 /* Enable pins for DSPI mode - chip-selects are enabled later */
709b384b 365asm_dspi_init:
45370e18
AW		 366#ifdef CONFIG_MCF5441x
367 move.l #0xEC09404E, %a1
368 move.l #0xEC09404F, %a2
369 move.b #0xFF, (%a1)
370 move.b #0x80, (%a2)
371#endif
372
373#ifdef CONFIG_MCF5445x
9f751551
TL		 374 move.l #0xFC0A4063, %a0
375 move.b #0x7F, (%a0)
45370e18 376#endif
9f751551
TL		 377 /* Configure DSPI module */
378 move.l #0xFC05C000, %a0
379 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
380
381 move.l #0xFC05C00C, %a0
45370e18
AW		 382#ifdef CONFIG_MCF5441x
383 move.l #0x3E000016, (%a0)
384#endif
385#ifdef CONFIG_MCF5445x
9f751551 386 move.l #0x3E000011, (%a0)
45370e18 387#endif
9f751551
TL		 388
389 move.l #0xFC05C034, %a2 /* dtfr */
390 move.l #0xFC05C03B, %a3 /* drfr */
391
392 move.l #(ASM_SBF_IMG_HDR + 4), %a1
393 move.l (%a1)+, %d5
394 move.l (%a1), %a4
395
6d0f6bcf
JCPV		 396 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
397 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
9f751551
TL		 398
399 move.l #0xFC05C02C, %a1 /* dspi status */
400
401 /* Issue commands and address */
402 move.l #0x8002000B, %d2 /* Fast Read Cmd */
403 jsr asm_dspi_wr_status
404 jsr asm_dspi_rd_status
405
406 move.l #0x80020000, %d2 /* Address byte 2 */
407 jsr asm_dspi_wr_status
408 jsr asm_dspi_rd_status
409
410 move.l #0x80020000, %d2 /* Address byte 1 */
411 jsr asm_dspi_wr_status
412 jsr asm_dspi_rd_status
413
414 move.l #0x80020000, %d2 /* Address byte 0 */
415 jsr asm_dspi_wr_status
416 jsr asm_dspi_rd_status
417
418 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
419 jsr asm_dspi_wr_status
420 jsr asm_dspi_rd_status
421
422 /* Transfer serial boot header to sram */
423asm_dspi_rd_loop1:
424 move.l #0x80020000, %d2
425 jsr asm_dspi_wr_status
426 jsr asm_dspi_rd_status
427
428 move.b %d1, (%a0) /* read, copy to dst */
429
430 add.l #1, %a0 /* inc dst by 1 */
431 sub.l #1, %d4 /* dec cnt by 1 */
432 bne asm_dspi_rd_loop1
433
434 /* Transfer u-boot from serial flash to memory */
435asm_dspi_rd_loop2:
436 move.l #0x80020000, %d2
437 jsr asm_dspi_wr_status
438 jsr asm_dspi_rd_status
439
440 move.b %d1, (%a4) /* read, copy to dst */
441
442 add.l #1, %a4 /* inc dst by 1 */
443 sub.l #1, %d5 /* dec cnt by 1 */
444 bne asm_dspi_rd_loop2
445
446 move.l #0x00020000, %d2 /* Terminate */
447 jsr asm_dspi_wr_status
448 jsr asm_dspi_rd_status
449
450 /* jump to memory and execute */
14d0a02a 451 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
9f751551
TL		 452 jmp (%a0)
453
454asm_dspi_wr_status:
455 move.l (%a1), %d0 /* status */
456 and.l #0x0000F000, %d0
457 cmp.l #0x00003000, %d0
458 bgt asm_dspi_wr_status
459
460 move.l %d2, (%a2)
461 rts
462
463asm_dspi_rd_status:
464 move.l (%a1), %d0 /* status */
465 and.l #0x000000F0, %d0
466 lsr.l #4, %d0
467 cmp.l #0, %d0
468 beq asm_dspi_rd_status
469
470 move.b (%a3), %d1
471 rts
5c928d02 472#endif /* CONFIG_CF_SBF */
45370e18
AW		 473
474#ifdef CONFIG_SYS_NAND_BOOT
475 /* copy 4 boot pages to dram as soon as possible */
476 /* each page is 996 bytes (1056 total with 60 ECC bytes */
477 move.l #0x00000000, %a1 /* src */
61a4392a 478 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
45370e18
AW		 479 move.l #0x3E0, %d0 /* sz in long */
480
481asm_boot_nand_copy:
482 move.l (%a1)+, (%a2)+
483 subq.l #1, %d0
484 bne asm_boot_nand_copy
485
486 /* jump to memory and execute */
487 move.l #(asm_nand_init), %a0
488 jmp (%a0)
489
490asm_nand_init:
491 /* exit nand boot-mode */
492 move.l #0xFC0FFF30, %a1
493 or.l #0x00000040, %d1
494 move.l %d1, (%a1)
495
496 /* initialize general use internal ram */
5c928d02
AD		 497 move.l #0, %d0
498 move.l #(CACR_STATUS), %a1 /* CACR */
499 move.l #(ICACHE_STATUS), %a2 /* icache */
500 move.l #(DCACHE_STATUS), %a3 /* dcache */
501 move.l %d0, (%a1)
502 move.l %d0, (%a2)
503 move.l %d0, (%a3)
45370e18
AW		 504
505 /* invalidate and disable cache */
506 move.l #0x01004100, %d0 /* Invalidate cache cmd */
507 movec %d0, %CACR /* Invalidate cache */
508 move.l #0, %d0
509 movec %d0, %ACR0
510 movec %d0, %ACR1
511 movec %d0, %ACR2
512 movec %d0, %ACR3
513
514 /* Must disable global address */
515 move.l #0xFC008000, %a1
516 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
517 move.l #0xFC008008, %a1
518 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
519 move.l #0xFC008004, %a1
520 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
521
522 /* NAND port configuration */
523 move.l #0xEC094048, %a1
524 move.b #0xFD, (%a1)+
525 move.b #0x5F, (%a1)+
526 move.b #0x04, (%a1)+
527
528 /* reset nand */
529 move.l #0xFC0FFF38, %a1 /* isr */
530 move.l #0x000e0000, (%a1)
531 move.l #0xFC0FFF08, %a2
532 move.l #0x00000000, (%a2)+ /* car */
533 move.l #0x11000000, (%a2)+ /* rar */
534 move.l #0x00000000, (%a2)+ /* rpt */
535 move.l #0x00000000, (%a2)+ /* rai */
536 move.l #0xFC0FFF2c, %a2 /* cfg */
537 move.l #0x00000000, (%a2)+ /* secsz */
538 move.l #0x000e0681, (%a2)+
539 move.l #0xFC0FFF04, %a2 /* cmd2 */
540 move.l #0xFF404001, (%a2)
541 move.l #0x000e0000, (%a1)
542
543 move.l #0x2000, %d1
544 jsr asm_delay
545
546 /* setup nand */
547 move.l #0xFC0FFF00, %a1
548 move.l #0x30700000, (%a1)+ /* cmd1 */
549 move.l #0x007EF000, (%a1)+ /* cmd2 */
550
551 move.l #0xFC0FFF2C, %a1
552 move.l #0x00000841, (%a1)+ /* secsz */
553 move.l #0x000e0681, (%a1)+ /* cfg */
554
555 move.l #100, %d4 /* 100 pages ~200KB */
556 move.l #4, %d2 /* start at 4 */
557 move.l #0xFC0FFF04, %a0 /* cmd2 */
558 move.l #0xFC0FFF0C, %a1 /* rar */
5c928d02 559 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
45370e18
AW		 560
561asm_nand_read:
562 move.l #0x11000000, %d0 /* rar */
563 or.l %d2, %d0
564 move.l %d0, (%a1)
565 add.l #1, %d2
566
567 move.l (%a0), %d0 /* cmd2 */
568 or.l #1, %d0
569 move.l %d0, (%a0)
570
571 move.l #0x200, %d1
572 jsr asm_delay
573
574asm_nand_chk_status:
575 move.l #0xFC0FFF38, %a4 /* isr */
576 move.l (%a4), %d0
577 and.l #0x40000000, %d0
578 tst.l %d0
579 beq asm_nand_chk_status
580
581 move.l #0xFC0FFF38, %a4 /* isr */
582 move.l (%a4), %d0
583 or.l #0x000E0000, %d0
584 move.l %d0, (%a4)
585
586 move.l #0x200, %d3
587 move.l #0xFC0FC000, %a3 /* buf 1 */
588asm_nand_copy:
589 move.l (%a3)+, (%a2)+
590 subq.l #1, %d3
591 bgt asm_nand_copy
592
593 subq.l #1, %d4
594 bgt asm_nand_read
595
596 /* jump to memory and execute */
61a4392a 597 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
45370e18
AW		 598 jmp (%a0)
599
600#endif /* CONFIG_SYS_NAND_BOOT */
709b384b
TL		 601
602asm_delay:
603 nop
604 subq.l #1, %d1
605 bne asm_delay
606 rts
45370e18 607#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
9f751551 608
5c928d02 609.text
9f751551 610 . = 0x400
5c928d02 611.globl _start
8ae158cd 612_start:
45370e18 613#if !defined(CONFIG_SERIAL_BOOT)
8ae158cd
TL		 614 nop
615 nop
5c928d02 616 move.w #0x2700,%sr /* Mask off Interrupt */
8ae158cd
TL		 617
618 /* Set vector base register at the beginning of the Flash */
6d0f6bcf 619 move.l #CONFIG_SYS_FLASH_BASE, %d0
8ae158cd
TL		 620 movec %d0, %VBR
621
6d0f6bcf 622 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
225a24b5 623 movec %d0, %RAMBAR1
8ae158cd
TL		 624
625 /* initialize general use internal ram */
5c928d02
AD		 626 move.l #0, %d0
627 move.l #(ICACHE_STATUS), %a1 /* icache */
628 move.l #(DCACHE_STATUS), %a2 /* dcache */
629 move.l %d0, (%a1)
630 move.l %d0, (%a2)
8ae158cd
TL		 631
632 /* invalidate and disable cache */
dd9f054e 633 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
8ae158cd
TL		 634 movec %d0, %CACR /* Invalidate cache */
635 move.l #0, %d0
636 movec %d0, %ACR0
637 movec %d0, %ACR1
638 movec %d0, %ACR2
639 movec %d0, %ACR3
45370e18
AW		 640#else
641 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
642 movec %d0, %RAMBAR1
643#endif
8ae158cd 644
5044c9cc 645 /* put relocation table address to a5 */
5c928d02 646 move.l #__got_start, %a5
5044c9cc 647
648 /* setup stack initially on top of internal static ram */
5c928d02 649 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
5044c9cc 650
651 /*
652 * if configured, malloc_f arena will be reserved first,
653 * then (and always) gd struct space will be reserved
654 */
655 move.l %sp, -(%sp)
656 move.l #board_init_f_alloc_reserve, %a1
657 jsr (%a1)
658
659 /* update stack and frame-pointers */
5c928d02
AD		 660 move.l %d0, %sp
661 move.l %sp, %fp
8ae158cd 662
5044c9cc 663 /* initialize reserved area */
5c928d02 664 move.l %d0, -(%sp)
5044c9cc 665 move.l #board_init_f_init_reserve, %a1
666 jsr (%a1)
8ae158cd 667
55ac54c4 668 /* run low-level CPU init code (from flash) */
5c928d02
AD		 669 move.l #cpu_init_f, %a1
670 jsr (%a1)
671
55ac54c4 672 /* run low-level board init code (from flash) */
5044c9cc 673 clr.l %sp@-
5c928d02
AD		 674 move.l #board_init_f, %a1
675 jsr (%a1)
8ae158cd
TL		 676
677 /* board_init_f() does not return */
678
5c928d02 679/******************************************************************************/
8ae158cd
TL		 680
681/*
682 * void relocate_code (addr_sp, gd, addr_moni)
683 *
684 * This "function" does not return, instead it continues in RAM
685 * after relocating the monitor code.
686 *
687 * r3 = dest
688 * r4 = src
689 * r5 = length in bytes
690 * r6 = cachelinesize
691 */
5c928d02 692.globl relocate_code
8ae158cd 693relocate_code:
5c928d02
AD		 694 link.w %a6,#0
695 move.l 8(%a6), %sp /* set new stack pointer */
8ae158cd 696
5c928d02
AD		 697 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
698 move.l 16(%a6), %a0 /* Save copy of Destination Address */
8ae158cd 699
5c928d02
AD		 700 move.l #CONFIG_SYS_MONITOR_BASE, %a1
701 move.l #__init_end, %a2
702 move.l %a0, %a3
8ae158cd
TL		 703
704 /* copy the code to RAM */
7051:
5c928d02
AD		 706 move.l (%a1)+, (%a3)+
707 cmp.l %a1,%a2
708 bgt.s 1b
8ae158cd
TL		 709
710/*
711 * We are done. Do not return, instead branch to second part of board
712 * initialization, now running from RAM.
713 */
714 move.l %a0, %a1
6d0f6bcf 715 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
8ae158cd
TL		 716 jmp (%a1)
717
718in_ram:
719
720clear_bss:
721 /*
722 * Now clear BSS segment
723 */
724 move.l %a0, %a1
6d0f6bcf 725 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
8ae158cd 726 move.l %a0, %d1
6d0f6bcf 727 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
8ae158cd
TL		 7286:
729 clr.l (%a1)+
730 cmp.l %a1,%d1
731 bgt.s 6b
732
733 /*
734 * fix got table in RAM
735 */
736 move.l %a0, %a1
6d0f6bcf 737 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
5c928d02 738 move.l %a1,%a5 /* fix got pointer register a5 */
8ae158cd
TL		 739
740 move.l %a0, %a2
6d0f6bcf 741 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
8ae158cd
TL		 742
7437:
744 move.l (%a1),%d1
745 sub.l #_start,%d1
746 add.l %a0,%d1
747 move.l %d1,(%a1)+
748 cmp.l %a2, %a1
749 bne 7b
750
751 /* calculate relative jump to board_init_r in ram */
5c928d02
AD		 752 move.l %a0, %a1
753 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
8ae158cd
TL		 754
755 /* set parameters for board_init_r */
5c928d02
AD		 756 move.l %a0,-(%sp) /* dest_addr */
757 move.l %d0,-(%sp) /* gd */
8ae158cd
TL		 758 jsr (%a1)
759
5c928d02
AD		 760/******************************************************************************/
761
8ae158cd 762/* exception code */
5c928d02 763.globl _fault
8ae158cd 764_fault:
5c928d02 765 bra _fault
8ae158cd 766
5c928d02 767.globl _exc_handler
8ae158cd
TL		 768_exc_handler:
769 SAVE_ALL
770 movel %sp,%sp@-
5c928d02 771 bsr exc_handler
8ae158cd
TL		 772 addql #4,%sp
773 RESTORE_ALL
774
5c928d02 775.globl _int_handler
8ae158cd
TL		 776_int_handler:
777 SAVE_ALL
778 movel %sp,%sp@-
5c928d02 779 bsr int_handler
8ae158cd
TL		 780 addql #4,%sp
781 RESTORE_ALL
782
5c928d02 783/******************************************************************************/
8ae158cd 784
5c928d02 785.globl version_string
8ae158cd 786version_string:
5c928d02
AD		 787.ascii U_BOOT_VERSION_STRING, "\0"
788.align 4
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