[people/ms/u-boot.git] / arch / m68k / cpu / mcf547x_8x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <MCD_dma.h>
#include <asm/immap.h>
#include <asm/io.h>

#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fsl_mcdmafec.h>
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
	xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;

	out_be32(&xlbarb->adrto, 0x2000);
	out_be32(&xlbarb->datto, 0x2500);
	out_be32(&xlbarb->busto, 0x3000);

	out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);

	/* Master Priority Enable */
	out_be32(&xlbarb->prien, 0xff);
	out_be32(&xlbarb->pri, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#ifdef CONFIG_SYS_I2C_FSL
	out_be16(&gpio->par_feci2cirq,
		GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
	MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
		    MCD_RELOC_TASKS);
#endif
	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);

	/* Setup Ports: */
	switch (port) {
	case 0:
		out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
		break;
	case 1:
		out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
		break;
	case 2:
		out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
		break;
	case 3:
		out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
		break;
	}

	clrbits_8(pscsicr, 0x07);
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;

	if (setclear) {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
			setbits_be16(&gpio->par_feci2cirq, 0xf000);
		else
			setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
	} else {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
			clrbits_be16(&gpio->par_feci2cirq, 0xf000);
		else
			clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
	}
	return 0;
}
#endif
Commit	Line	Data
570c0186 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
a4110eec	6	* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
570c0186 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <MCD_dma.h>
	30	#include <asm/immap.h>
a4110eec	31	#include <asm/io.h>
570c0186	32
f3962d3f TL	33	#if defined(CONFIG_CMD_NET)
	34	#include <config.h>
	35	#include <net.h>
	36	#include <asm/fsl_mcdmafec.h>
	37	#endif
	38
570c0186 TL	39	/*
	40	* Breath some life into the CPU...
	41	*
	42	* Set up the memory map,
	43	* initialize a bunch of registers,
	44	* initialize the UPM's
	45	*/
	46	void cpu_init_f(void)
	47	{
a4110eec AW	48	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	49	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	50	xlbarb_t xlbarb = (xlbarb_t ) MMAP_XARB;
570c0186	51
a4110eec AW	52	out_be32(&xlbarb->adrto, 0x2000);
	53	out_be32(&xlbarb->datto, 0x2500);
	54	out_be32(&xlbarb->busto, 0x3000);
570c0186	55
a4110eec	56	out_be32(&xlbarb->cfg, XARB_CFG_AT \| XARB_CFG_DT);
570c0186 TL	57
570c0186 TL	58	/* Master Priority Enable */
a4110eec AW	59	out_be32(&xlbarb->prien, 0xff);
a4110eec AW	60	out_be32(&xlbarb->pri, 0);
570c0186	61
6d0f6bcf	62	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
a4110eec AW	63	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	64	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	65	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
570c0186 TL	66	#endif
570c0186 TL	67
6d0f6bcf	68	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
a4110eec AW	69	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	70	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	71	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
570c0186 TL	72	#endif
570c0186 TL	73
6d0f6bcf	74	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
a4110eec AW	75	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	76	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	77	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
570c0186 TL	78	#endif
570c0186 TL	79
6d0f6bcf	80	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
a4110eec AW	81	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	82	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	83	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
570c0186 TL	84	#endif
570c0186 TL	85
6d0f6bcf	86	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
a4110eec AW	87	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	88	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	89	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
570c0186 TL	90	#endif
570c0186 TL	91
6d0f6bcf	92	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
a4110eec AW	93	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	94	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	95	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
570c0186 TL	96	#endif
570c0186 TL	97
00f792e0	98	#ifdef CONFIG_SYS_I2C_FSL
a4110eec AW	99	out_be16(&gpio->par_feci2cirq,
a4110eec AW	100	GPIO_PAR_FECI2CIRQ_SCL \| GPIO_PAR_FECI2CIRQ_SDA);
570c0186 TL	101	#endif
	102
	103	icache_enable();
	104	}
	105
	106	/*
	107	* initialize higher level parts of CPU like timers
	108	*/
	109	int cpu_init_r(void)
	110	{
	111	#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
	112	MCD_initDma((dmaRegs ) (MMAP_MCDMA), (void )(MMAP_SRAM + 512),
	113	MCD_RELOC_TASKS);
	114	#endif
	115	return (0);
	116	}
	117
52affe04	118	void uart_port_conf(int port)
570c0186	119	{
a4110eec AW	120	gpio_t gpio = (gpio_t ) MMAP_GPIO;
a4110eec AW	121	u8 pscsicr = (u8 ) (CONFIG_SYS_UART_BASE + 0x40);
570c0186 TL	122
570c0186 TL	123	/* Setup Ports: */
52affe04	124	switch (port) {
570c0186	125	case 0:
a4110eec	126	out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 \| GPIO_PAR_PSC0_RXD0);
570c0186 TL	127	break;
570c0186 TL	128	case 1:
a4110eec	129	out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 \| GPIO_PAR_PSC1_RXD1);
570c0186 TL	130	break;
570c0186 TL	131	case 2:
a4110eec	132	out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 \| GPIO_PAR_PSC2_RXD2);
570c0186 TL	133	break;
570c0186 TL	134	case 3:
a4110eec	135	out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 \| GPIO_PAR_PSC3_RXD3);
570c0186 TL	136	break;
	137	}
	138
a4110eec	139	clrbits_8(pscsicr, 0x07);
570c0186	140	}
f3962d3f TL	141
	142	#if defined(CONFIG_CMD_NET)
	143	int fecpin_setclear(struct eth_device *dev, int setclear)
	144	{
a4110eec	145	gpio_t gpio = (gpio_t ) MMAP_GPIO;
f3962d3f TL	146	struct fec_info_dma info = (struct fec_info_dma )dev->priv;
	147
	148	if (setclear) {
	149	if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
a4110eec	150	setbits_be16(&gpio->par_feci2cirq, 0xf000);
f3962d3f	151	else
a4110eec	152	setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
f3962d3f TL	153	} else {
f3962d3f TL	154	if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
a4110eec	155	clrbits_be16(&gpio->par_feci2cirq, 0xf000);
f3962d3f	156	else
a4110eec	157	clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
f3962d3f TL	158	}
	159	return 0;
	160	}
	161	#endif