projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ae158cd TL |
1 | /* |
| 2 | * MCF5445x Internal Memory Map | |
| 3 | * | |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8ae158cd TL |
8 | */ |
| 9 | ||
| 10 | #ifndef __MCF5445X__ | |
| 11 | #define __MCF5445X__ | |
| 12 | ||
| 8ae158cd TL |
13 | /********************************************************************* |
| 14 | * Interrupt Controller (INTC) | |
| 15 | *********************************************************************/ | |
| 16 | #define INT0_LO_RSVD0 (0) | |
| 17 | #define INT0_LO_EPORT1 (1) | |
| 18 | #define INT0_LO_EPORT2 (2) | |
| 19 | #define INT0_LO_EPORT3 (3) | |
| 20 | #define INT0_LO_EPORT4 (4) | |
| 21 | #define INT0_LO_EPORT5 (5) | |
| 22 | #define INT0_LO_EPORT6 (6) | |
| 23 | #define INT0_LO_EPORT7 (7) | |
| 24 | #define INT0_LO_EDMA_00 (8) | |
| 25 | #define INT0_LO_EDMA_01 (9) | |
| 26 | #define INT0_LO_EDMA_02 (10) | |
| 27 | #define INT0_LO_EDMA_03 (11) | |
| 28 | #define INT0_LO_EDMA_04 (12) | |
| 29 | #define INT0_LO_EDMA_05 (13) | |
| 30 | #define INT0_LO_EDMA_06 (14) | |
| 31 | #define INT0_LO_EDMA_07 (15) | |
| 32 | #define INT0_LO_EDMA_08 (16) | |
| 33 | #define INT0_LO_EDMA_09 (17) | |
| 34 | #define INT0_LO_EDMA_10 (18) | |
| 35 | #define INT0_LO_EDMA_11 (19) | |
| 36 | #define INT0_LO_EDMA_12 (20) | |
| 37 | #define INT0_LO_EDMA_13 (21) | |
| 38 | #define INT0_LO_EDMA_14 (22) | |
| 39 | #define INT0_LO_EDMA_15 (23) | |
| 40 | #define INT0_LO_EDMA_ERR (24) | |
| 41 | #define INT0_LO_SCM (25) | |
| 42 | #define INT0_LO_UART0 (26) | |
| 43 | #define INT0_LO_UART1 (27) | |
| 44 | #define INT0_LO_UART2 (28) | |
| 45 | #define INT0_LO_RSVD1 (29) | |
| 46 | #define INT0_LO_I2C (30) | |
| 47 | #define INT0_LO_QSPI (31) | |
| 48 | #define INT0_HI_DTMR0 (32) | |
| 49 | #define INT0_HI_DTMR1 (33) | |
| 50 | #define INT0_HI_DTMR2 (34) | |
| 51 | #define INT0_HI_DTMR3 (35) | |
| 52 | #define INT0_HI_FEC0_TXF (36) | |
| 53 | #define INT0_HI_FEC0_TXB (37) | |
| 54 | #define INT0_HI_FEC0_UN (38) | |
| 55 | #define INT0_HI_FEC0_RL (39) | |
| 56 | #define INT0_HI_FEC0_RXF (40) | |
| 57 | #define INT0_HI_FEC0_RXB (41) | |
| 58 | #define INT0_HI_FEC0_MII (42) | |
| 59 | #define INT0_HI_FEC0_LC (43) | |
| 60 | #define INT0_HI_FEC0_HBERR (44) | |
| 61 | #define INT0_HI_FEC0_GRA (45) | |
| 62 | #define INT0_HI_FEC0_EBERR (46) | |
| 63 | #define INT0_HI_FEC0_BABT (47) | |
| 64 | #define INT0_HI_FEC0_BABR (48) | |
| 65 | #define INT0_HI_FEC1_TXF (49) | |
| 66 | #define INT0_HI_FEC1_TXB (50) | |
| 67 | #define INT0_HI_FEC1_UN (51) | |
| 68 | #define INT0_HI_FEC1_RL (52) | |
| 69 | #define INT0_HI_FEC1_RXF (53) | |
| 70 | #define INT0_HI_FEC1_RXB (54) | |
| 71 | #define INT0_HI_FEC1_MII (55) | |
| 72 | #define INT0_HI_FEC1_LC (56) | |
| 73 | #define INT0_HI_FEC1_HBERR (57) | |
| 74 | #define INT0_HI_FEC1_GRA (58) | |
| 75 | #define INT0_HI_FEC1_EBERR (59) | |
| 76 | #define INT0_HI_FEC1_BABT (60) | |
| 77 | #define INT0_HI_FEC1_BABR (61) | |
| 78 | #define INT0_HI_SCMIR (62) | |
| 79 | #define INT0_HI_RTC_ISR (63) | |
| 80 | ||
| 81 | #define INT1_HI_DSPI_EOQF (33) | |
| 82 | #define INT1_HI_DSPI_TFFF (34) | |
| 83 | #define INT1_HI_DSPI_TCF (35) | |
| 84 | #define INT1_HI_DSPI_TFUF (36) | |
| 85 | #define INT1_HI_DSPI_RFDF (37) | |
| 86 | #define INT1_HI_DSPI_RFOF (38) | |
| 87 | #define INT1_HI_DSPI_RFOF_TFUF (39) | |
| 88 | #define INT1_HI_RNG_EI (40) | |
| 89 | #define INT1_HI_PIT0_PIF (43) | |
| 90 | #define INT1_HI_PIT1_PIF (44) | |
| 91 | #define INT1_HI_PIT2_PIF (45) | |
| 92 | #define INT1_HI_PIT3_PIF (46) | |
| 93 | #define INT1_HI_USBOTG_USBSTS (47) | |
| 94 | #define INT1_HI_SSI_ISR (49) | |
| 95 | #define INT1_HI_CCM_UOCSR (53) | |
| 96 | #define INT1_HI_ATA_ISR (54) | |
| 97 | #define INT1_HI_PCI_SCR (55) | |
| 98 | #define INT1_HI_PCI_ASR (56) | |
| 99 | #define INT1_HI_PLL_LOCKS (57) | |
| 100 | ||
| 8ae158cd TL |
101 | /********************************************************************* |
| 102 | * Watchdog Timer Modules (WTM) | |
| 103 | *********************************************************************/ | |
| 104 | ||
| 105 | /* Bit definitions and macros for WCR */ | |
| 106 | #define WTM_WCR_EN (0x0001) | |
| 107 | #define WTM_WCR_HALTED (0x0002) | |
| 108 | #define WTM_WCR_DOZE (0x0004) | |
| 109 | #define WTM_WCR_WAIT (0x0008) | |
| 110 | ||
| 111 | /********************************************************************* | |
| 112 | * Serial Boot Facility (SBF) | |
| 113 | *********************************************************************/ | |
| 114 | ||
| 115 | /* Bit definitions and macros for SBFCR */ | |
| 116 | #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ | |
| 117 | #define SBF_SBFCR_FR (0x0010) /* Fast read */ | |
| 118 | ||
| 119 | /********************************************************************* | |
| 120 | * Reset Controller Module (RCM) | |
| 121 | *********************************************************************/ | |
| 122 | ||
| 123 | /* Bit definitions and macros for RCR */ | |
| 124 | #define RCM_RCR_FRCRSTOUT (0x40) | |
| 125 | #define RCM_RCR_SOFTRST (0x80) | |
| 126 | ||
| 127 | /* Bit definitions and macros for RSR */ | |
| 128 | #define RCM_RSR_LOL (0x01) | |
| 129 | #define RCM_RSR_WDR_CORE (0x02) | |
| 130 | #define RCM_RSR_EXT (0x04) | |
| 131 | #define RCM_RSR_POR (0x08) | |
| 132 | #define RCM_RSR_SOFT (0x20) | |
| 133 | ||
| 134 | /********************************************************************* | |
| 135 | * Chip Configuration Module (CCM) | |
| 136 | *********************************************************************/ | |
| 137 | ||
| 138 | /* Bit definitions and macros for CCR_360 */ | |
| 139 | #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ | |
| 140 | #define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ | |
| 141 | #define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ | |
| 142 | #define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ | |
| 143 | #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ | |
| 144 | #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ | |
| 145 | #define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ | |
| 146 | #define CCM_CCR_360_FBCONFIG_MASK (0x00E0) | |
| 147 | #define CCM_CCR_360_PLLMULT2_MASK (0x0003) | |
| 148 | #define CCM_CCR_360_PLLMULT3_MASK (0x0007) | |
| 149 | #define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) | |
| 150 | #define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) | |
| 151 | #define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) | |
| 152 | #define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) | |
| 153 | #define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) | |
| 154 | #define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) | |
| 155 | #define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) | |
| 156 | #define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) | |
| 157 | #define CCM_CCR_360_PLLMULT2_12X (0x0000) | |
| 158 | #define CCM_CCR_360_PLLMULT2_6X (0x0001) | |
| 159 | #define CCM_CCR_360_PLLMULT2_16X (0x0002) | |
| 160 | #define CCM_CCR_360_PLLMULT2_8X (0x0003) | |
| 161 | #define CCM_CCR_360_PLLMULT3_20X (0x0000) | |
| 162 | #define CCM_CCR_360_PLLMULT3_10X (0x0001) | |
| 163 | #define CCM_CCR_360_PLLMULT3_24X (0x0002) | |
| 164 | #define CCM_CCR_360_PLLMULT3_18X (0x0003) | |
| 165 | #define CCM_CCR_360_PLLMULT3_12X (0x0004) | |
| 166 | #define CCM_CCR_360_PLLMULT3_6X (0x0005) | |
| 167 | #define CCM_CCR_360_PLLMULT3_16X (0x0006) | |
| 168 | #define CCM_CCR_360_PLLMULT3_8X (0x0007) | |
| 169 | ||
| 170 | /* Bit definitions and macros for CCR_256 */ | |
| 171 | #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ | |
| 172 | #define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ | |
| 173 | #define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ | |
| 174 | #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ | |
| 175 | #define CCM_CCR_256_FBCONFIG_MASK (0x00E0) | |
| 176 | #define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) | |
| 177 | #define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) | |
| 178 | #define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) | |
| 179 | #define CCM_CCR_256_FBCONFIG_M_32 (0x0080) | |
| 180 | #define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) | |
| 181 | #define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) | |
| 182 | #define CCM_CCR_256_PLLMULT3_MASK (0x0007) | |
| 183 | #define CCM_CCR_256_PLLMULT3_20X (0x0000) | |
| 184 | #define CCM_CCR_256_PLLMULT3_10X (0x0001) | |
| 185 | #define CCM_CCR_256_PLLMULT3_24X (0x0002) | |
| 186 | #define CCM_CCR_256_PLLMULT3_18X (0x0003) | |
| 187 | #define CCM_CCR_256_PLLMULT3_12X (0x0004) | |
| 188 | #define CCM_CCR_256_PLLMULT3_6X (0x0005) | |
| 189 | #define CCM_CCR_256_PLLMULT3_16X (0x0006) | |
| 190 | #define CCM_CCR_256_PLLMULT3_8X (0x0007) | |
| 191 | ||
| 192 | /* Bit definitions and macros for RCON_360 */ | |
| 193 | #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ | |
| 194 | #define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ | |
| 195 | #define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ | |
| 196 | #define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ | |
| 197 | #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ | |
| 198 | ||
| 199 | /* Bit definitions and macros for RCON_256 */ | |
| 200 | #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ | |
| 201 | #define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ | |
| 202 | #define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ | |
| 203 | #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ | |
| 204 | ||
| 205 | /* Bit definitions and macros for CIR */ | |
| 206 | #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ | |
| 207 | #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ | |
| 208 | #define CCM_CIR_PIN_MASK (0xFFC0) | |
| 209 | #define CCM_CIR_PRN_MASK (0x003F) | |
| 210 | #define CCM_CIR_PIN_MCF54450 (0x4F<<6) | |
| 211 | #define CCM_CIR_PIN_MCF54451 (0x4D<<6) | |
| 212 | #define CCM_CIR_PIN_MCF54452 (0x4B<<6) | |
| 213 | #define CCM_CIR_PIN_MCF54453 (0x49<<6) | |
| 214 | #define CCM_CIR_PIN_MCF54454 (0x4A<<6) | |
| 215 | #define CCM_CIR_PIN_MCF54455 (0x48<<6) | |
| 216 | ||
| 217 | /* Bit definitions and macros for MISCCR */ | |
| 218 | #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ | |
| 219 | #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ | |
| 220 | #define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ | |
| 221 | #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ | |
| 222 | #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ | |
| 223 | #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ | |
| 224 | #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ | |
| 225 | #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ | |
| 226 | #define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ | |
| 227 | #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ | |
| 228 | #define CCM_MISCCR_BMT_65536 (0) | |
| 229 | #define CCM_MISCCR_BMT_32768 (1) | |
| 230 | #define CCM_MISCCR_BMT_16384 (2) | |
| 231 | #define CCM_MISCCR_BMT_8192 (3) | |
| 232 | #define CCM_MISCCR_BMT_4096 (4) | |
| 233 | #define CCM_MISCCR_BMT_2048 (5) | |
| 234 | #define CCM_MISCCR_BMT_1024 (6) | |
| 235 | #define CCM_MISCCR_BMT_512 (7) | |
| 236 | #define CCM_MISCCR_SSIPUS_UP (1) | |
| 237 | #define CCM_MISCCR_SSIPUS_DOWN (0) | |
| 238 | #define CCM_MISCCR_TIMDMA_TIM (1) | |
| 239 | #define CCM_MISCCR_TIMDMA_SSI (0) | |
| 240 | #define CCM_MISCCR_SSISRC_CLKIN (0) | |
| 241 | #define CCM_MISCCR_SSISRC_PLL (1) | |
| 242 | #define CCM_MISCCR_USBOC_ACTHI (0) | |
| 243 | #define CCM_MISCCR_USBOV_ACTLO (1) | |
| 244 | #define CCM_MISCCR_USBSRC_CLKIN (0) | |
| 245 | #define CCM_MISCCR_USBSRC_PLL (1) | |
| 246 | ||
| 247 | /* Bit definitions and macros for CDR */ | |
| 248 | #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ | |
| 249 | #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ | |
| 250 | ||
| 251 | /* Bit definitions and macros for UOCSR */ | |
| 252 | #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ | |
| 253 | #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ | |
| 254 | #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ | |
| 255 | #define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ | |
| 256 | #define CCM_UOCSR_SEND (0x0010) /* Session end */ | |
| 257 | #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ | |
| 258 | #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ | |
| 259 | #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ | |
| 260 | #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ | |
| 261 | #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ | |
| 262 | #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ | |
| 263 | #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ | |
| 264 | #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ | |
| 265 | ||
| 266 | /********************************************************************* | |
| 267 | * General Purpose I/O Module (GPIO) | |
| 268 | *********************************************************************/ | |
| 269 | ||
| 270 | /* Bit definitions and macros for PAR_FEC */ | |
| 271 | #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) | |
| 272 | #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) | |
| d04c1efa | 273 | #define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) |
| 8ae158cd TL |
274 | #define GPIO_PAR_FEC_FEC1_MII (0x70) |
| 275 | #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) | |
| 276 | #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) | |
| 277 | #define GPIO_PAR_FEC_FEC1_ATA (0x10) | |
| 278 | #define GPIO_PAR_FEC_FEC1_GPIO (0x00) | |
| d04c1efa | 279 | #define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) |
| 8ae158cd TL |
280 | #define GPIO_PAR_FEC_FEC0_MII (0x07) |
| 281 | #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) | |
| 225a24b5 TL |
282 | #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) |
| 283 | #define GPIO_PAR_FEC_FEC0_ULPI (0x01) | |
| 8ae158cd TL |
284 | #define GPIO_PAR_FEC_FEC0_GPIO (0x00) |
| 285 | ||
| 286 | /* Bit definitions and macros for PAR_DMA */ | |
| 287 | #define GPIO_PAR_DMA_DREQ0 (0x01) | |
| 288 | #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) | |
| 289 | #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) | |
| 290 | #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) | |
| d04c1efa | 291 | #define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) |
| 8ae158cd TL |
292 | #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) |
| 293 | #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) | |
| 294 | #define GPIO_PAR_DMA_DACK1_GPIO (0x00) | |
| d04c1efa | 295 | #define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) |
| 8ae158cd TL |
296 | #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) |
| 297 | #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) | |
| 298 | #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) | |
| d04c1efa | 299 | #define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) |
| 8ae158cd | 300 | #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) |
| e9b43cae | 301 | #define GPIO_PAR_DMA_DACK0_PCS3 (0x08) |
| 8ae158cd TL |
302 | #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) |
| 303 | #define GPIO_PAR_DMA_DACK0_GPIO (0x00) | |
| 304 | #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) | |
| 305 | #define GPIO_PAR_DMA_DREQ0_GPIO (0x00) | |
| 306 | ||
| 307 | /* Bit definitions and macros for PAR_FBCTL */ | |
| 308 | #define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) | |
| 309 | #define GPIO_PAR_FBCTL_RW (0x20) | |
| 310 | #define GPIO_PAR_FBCTL_TA (0x40) | |
| 311 | #define GPIO_PAR_FBCTL_OE (0x80) | |
| 312 | #define GPIO_PAR_FBCTL_OE_OE (0x80) | |
| 313 | #define GPIO_PAR_FBCTL_OE_GPIO (0x00) | |
| 314 | #define GPIO_PAR_FBCTL_TA_TA (0x40) | |
| 315 | #define GPIO_PAR_FBCTL_TA_GPIO (0x00) | |
| 316 | #define GPIO_PAR_FBCTL_RW_RW (0x20) | |
| 317 | #define GPIO_PAR_FBCTL_RW_GPIO (0x00) | |
| d04c1efa | 318 | #define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) |
| 8ae158cd TL |
319 | #define GPIO_PAR_FBCTL_TS_TS (0x18) |
| 320 | #define GPIO_PAR_FBCTL_TS_ALE (0x10) | |
| 321 | #define GPIO_PAR_FBCTL_TS_TBST (0x08) | |
| 322 | #define GPIO_PAR_FBCTL_TS_GPIO (0x80) | |
| 323 | ||
| 324 | /* Bit definitions and macros for PAR_DSPI */ | |
| 325 | #define GPIO_PAR_DSPI_SCK (0x01) | |
| 326 | #define GPIO_PAR_DSPI_SOUT (0x02) | |
| 327 | #define GPIO_PAR_DSPI_SIN (0x04) | |
| 328 | #define GPIO_PAR_DSPI_PCS0 (0x08) | |
| 329 | #define GPIO_PAR_DSPI_PCS1 (0x10) | |
| 330 | #define GPIO_PAR_DSPI_PCS2 (0x20) | |
| 331 | #define GPIO_PAR_DSPI_PCS5 (0x40) | |
| 332 | #define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) | |
| 333 | #define GPIO_PAR_DSPI_PCS5_GPIO (0x00) | |
| 334 | #define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) | |
| 335 | #define GPIO_PAR_DSPI_PCS2_GPIO (0x00) | |
| 336 | #define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) | |
| 337 | #define GPIO_PAR_DSPI_PCS1_GPIO (0x00) | |
| 338 | #define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) | |
| 339 | #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) | |
| 340 | #define GPIO_PAR_DSPI_SIN_SIN (0x04) | |
| 341 | #define GPIO_PAR_DSPI_SIN_GPIO (0x00) | |
| 342 | #define GPIO_PAR_DSPI_SOUT_SOUT (0x02) | |
| 343 | #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) | |
| 344 | #define GPIO_PAR_DSPI_SCK_SCK (0x01) | |
| 345 | #define GPIO_PAR_DSPI_SCK_GPIO (0x00) | |
| 346 | ||
| 347 | /* Bit definitions and macros for PAR_BE */ | |
| 348 | #define GPIO_PAR_BE_BS0 (0x01) | |
| 349 | #define GPIO_PAR_BE_BS1 (0x04) | |
| 350 | #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) | |
| 351 | #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) | |
| d04c1efa | 352 | #define GPIO_PAR_BE_BE3_UNMASK (0x3F) |
| 8ae158cd TL |
353 | #define GPIO_PAR_BE_BE3_BE3 (0xC0) |
| 354 | #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) | |
| 355 | #define GPIO_PAR_BE_BE3_GPIO (0x00) | |
| d04c1efa | 356 | #define GPIO_PAR_BE_BE2_UNMASK (0xCF) |
| 8ae158cd TL |
357 | #define GPIO_PAR_BE_BE2_BE2 (0x30) |
| 358 | #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) | |
| 359 | #define GPIO_PAR_BE_BE2_GPIO (0x00) | |
| 360 | #define GPIO_PAR_BE_BE1_BE1 (0x04) | |
| 361 | #define GPIO_PAR_BE_BE1_GPIO (0x00) | |
| 362 | #define GPIO_PAR_BE_BE0_BE0 (0x01) | |
| 363 | #define GPIO_PAR_BE_BE0_GPIO (0x00) | |
| 364 | ||
| 365 | /* Bit definitions and macros for PAR_CS */ | |
| 366 | #define GPIO_PAR_CS_CS1 (0x02) | |
| 367 | #define GPIO_PAR_CS_CS2 (0x04) | |
| 368 | #define GPIO_PAR_CS_CS3 (0x08) | |
| 369 | #define GPIO_PAR_CS_CS3_CS3 (0x08) | |
| 370 | #define GPIO_PAR_CS_CS3_GPIO (0x00) | |
| 371 | #define GPIO_PAR_CS_CS2_CS2 (0x04) | |
| 372 | #define GPIO_PAR_CS_CS2_GPIO (0x00) | |
| 373 | #define GPIO_PAR_CS_CS1_CS1 (0x02) | |
| 374 | #define GPIO_PAR_CS_CS1_GPIO (0x00) | |
| 375 | ||
| 376 | /* Bit definitions and macros for PAR_TIMER */ | |
| 377 | #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) | |
| 378 | #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) | |
| 379 | #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) | |
| 380 | #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) | |
| d04c1efa | 381 | #define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) |
| 8ae158cd TL |
382 | #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) |
| 383 | #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) | |
| 384 | #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) | |
| 385 | #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) | |
| d04c1efa | 386 | #define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) |
| 8ae158cd TL |
387 | #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) |
| 388 | #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) | |
| 389 | #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) | |
| 390 | #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) | |
| d04c1efa | 391 | #define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) |
| 8ae158cd TL |
392 | #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) |
| 393 | #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) | |
| 394 | #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) | |
| 395 | #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) | |
| d04c1efa | 396 | #define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) |
| 8ae158cd TL |
397 | #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) |
| 398 | #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) | |
| 399 | #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) | |
| 400 | #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) | |
| 401 | ||
| 402 | /* Bit definitions and macros for PAR_USB */ | |
| 403 | #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) | |
| 404 | #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) | |
| d04c1efa | 405 | #define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) |
| 8ae158cd TL |
406 | #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) |
| 407 | #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) | |
| 408 | #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) | |
| 409 | #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) | |
| d04c1efa | 410 | #define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) |
| 8ae158cd TL |
411 | #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) |
| 412 | #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) | |
| 413 | #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) | |
| 414 | ||
| 415 | /* Bit definitions and macros for PAR_UART */ | |
| 416 | #define GPIO_PAR_UART_U0TXD (0x01) | |
| 417 | #define GPIO_PAR_UART_U0RXD (0x02) | |
| 418 | #define GPIO_PAR_UART_U0RTS (0x04) | |
| 419 | #define GPIO_PAR_UART_U0CTS (0x08) | |
| 420 | #define GPIO_PAR_UART_U1TXD (0x10) | |
| 421 | #define GPIO_PAR_UART_U1RXD (0x20) | |
| 422 | #define GPIO_PAR_UART_U1RTS (0x40) | |
| 423 | #define GPIO_PAR_UART_U1CTS (0x80) | |
| 424 | #define GPIO_PAR_UART_U1CTS_U1CTS (0x80) | |
| 425 | #define GPIO_PAR_UART_U1CTS_GPIO (0x00) | |
| 426 | #define GPIO_PAR_UART_U1RTS_U1RTS (0x40) | |
| 427 | #define GPIO_PAR_UART_U1RTS_GPIO (0x00) | |
| 428 | #define GPIO_PAR_UART_U1RXD_U1RXD (0x20) | |
| 429 | #define GPIO_PAR_UART_U1RXD_GPIO (0x00) | |
| 430 | #define GPIO_PAR_UART_U1TXD_U1TXD (0x10) | |
| 431 | #define GPIO_PAR_UART_U1TXD_GPIO (0x00) | |
| 432 | #define GPIO_PAR_UART_U0CTS_U0CTS (0x08) | |
| 433 | #define GPIO_PAR_UART_U0CTS_GPIO (0x00) | |
| 434 | #define GPIO_PAR_UART_U0RTS_U0RTS (0x04) | |
| 435 | #define GPIO_PAR_UART_U0RTS_GPIO (0x00) | |
| 436 | #define GPIO_PAR_UART_U0RXD_U0RXD (0x02) | |
| 437 | #define GPIO_PAR_UART_U0RXD_GPIO (0x00) | |
| 438 | #define GPIO_PAR_UART_U0TXD_U0TXD (0x01) | |
| 439 | #define GPIO_PAR_UART_U0TXD_GPIO (0x00) | |
| 440 | ||
| 441 | /* Bit definitions and macros for PAR_FECI2C */ | |
| 442 | #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) | |
| 443 | #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) | |
| 444 | #define GPIO_PAR_FECI2C_MDIO0 (0x0010) | |
| 445 | #define GPIO_PAR_FECI2C_MDC0 (0x0040) | |
| 446 | #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) | |
| 447 | #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) | |
| d04c1efa | 448 | #define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) |
| 8ae158cd TL |
449 | #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) |
| 450 | #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) | |
| 451 | #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) | |
| d04c1efa | 452 | #define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) |
| 8ae158cd TL |
453 | #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) |
| 454 | #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) | |
| 455 | #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) | |
| 456 | #define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) | |
| 457 | #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) | |
| 458 | #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) | |
| 459 | #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) | |
| d04c1efa | 460 | #define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) |
| 8ae158cd TL |
461 | #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) |
| 462 | #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) | |
| 463 | #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) | |
| d04c1efa | 464 | #define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) |
| 8ae158cd TL |
465 | #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) |
| 466 | #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) | |
| 467 | #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) | |
| 468 | ||
| 469 | /* Bit definitions and macros for PAR_SSI */ | |
| 470 | #define GPIO_PAR_SSI_MCLK (0x0001) | |
| 471 | #define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) | |
| 472 | #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) | |
| 473 | #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) | |
| 474 | #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) | |
| d04c1efa | 475 | #define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) |
| 8ae158cd TL |
476 | #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) |
| 477 | #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) | |
| 478 | #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) | |
| d04c1efa | 479 | #define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) |
| 8ae158cd TL |
480 | #define GPIO_PAR_SSI_FS_FS (0x00C0) |
| 481 | #define GPIO_PAR_SSI_FS_U1RTS (0x0080) | |
| 482 | #define GPIO_PAR_SSI_FS_GPIO (0x0000) | |
| d04c1efa | 483 | #define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) |
| 8ae158cd TL |
484 | #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) |
| 485 | #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) | |
| 486 | #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) | |
| d04c1efa | 487 | #define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) |
| 8ae158cd TL |
488 | #define GPIO_PAR_SSI_STXD_STXD (0x000C) |
| 489 | #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) | |
| 490 | #define GPIO_PAR_SSI_STXD_GPIO (0x0000) | |
| 491 | #define GPIO_PAR_SSI_MCLK_MCLK (0x0001) | |
| 492 | #define GPIO_PAR_SSI_MCLK_GPIO (0x0000) | |
| 493 | ||
| 494 | /* Bit definitions and macros for PAR_ATA */ | |
| 495 | #define GPIO_PAR_ATA_IORDY (0x0001) | |
| 496 | #define GPIO_PAR_ATA_DMARQ (0x0002) | |
| 497 | #define GPIO_PAR_ATA_RESET (0x0004) | |
| 498 | #define GPIO_PAR_ATA_DA0 (0x0020) | |
| 499 | #define GPIO_PAR_ATA_DA1 (0x0040) | |
| 500 | #define GPIO_PAR_ATA_DA2 (0x0080) | |
| 501 | #define GPIO_PAR_ATA_CS0 (0x0100) | |
| 502 | #define GPIO_PAR_ATA_CS1 (0x0200) | |
| 503 | #define GPIO_PAR_ATA_BUFEN (0x0400) | |
| 504 | #define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) | |
| 505 | #define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) | |
| 506 | #define GPIO_PAR_ATA_CS1_CS1 (0x0200) | |
| 507 | #define GPIO_PAR_ATA_CS1_GPIO (0x0000) | |
| 508 | #define GPIO_PAR_ATA_CS0_CS0 (0x0100) | |
| 509 | #define GPIO_PAR_ATA_CS0_GPIO (0x0000) | |
| 510 | #define GPIO_PAR_ATA_DA2_DA2 (0x0080) | |
| 511 | #define GPIO_PAR_ATA_DA2_GPIO (0x0000) | |
| 512 | #define GPIO_PAR_ATA_DA1_DA1 (0x0040) | |
| 513 | #define GPIO_PAR_ATA_DA1_GPIO (0x0000) | |
| 514 | #define GPIO_PAR_ATA_DA0_DA0 (0x0020) | |
| 515 | #define GPIO_PAR_ATA_DA0_GPIO (0x0000) | |
| 516 | #define GPIO_PAR_ATA_RESET_RESET (0x0004) | |
| 517 | #define GPIO_PAR_ATA_RESET_GPIO (0x0000) | |
| 518 | #define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) | |
| 519 | #define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) | |
| 520 | #define GPIO_PAR_ATA_IORDY_IORDY (0x0001) | |
| 521 | #define GPIO_PAR_ATA_IORDY_GPIO (0x0000) | |
| 522 | ||
| 523 | /* Bit definitions and macros for PAR_IRQ */ | |
| 524 | #define GPIO_PAR_IRQ_IRQ1 (0x02) | |
| 525 | #define GPIO_PAR_IRQ_IRQ4 (0x10) | |
| 526 | #define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) | |
| 527 | #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) | |
| 528 | #define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) | |
| 529 | #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) | |
| 530 | ||
| 531 | /* Bit definitions and macros for PAR_PCI */ | |
| 532 | #define GPIO_PAR_PCI_REQ0 (0x0001) | |
| 533 | #define GPIO_PAR_PCI_REQ1 (0x0004) | |
| 534 | #define GPIO_PAR_PCI_REQ2 (0x0010) | |
| 535 | #define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) | |
| 536 | #define GPIO_PAR_PCI_GNT0 (0x0100) | |
| 537 | #define GPIO_PAR_PCI_GNT1 (0x0400) | |
| 538 | #define GPIO_PAR_PCI_GNT2 (0x1000) | |
| 539 | #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) | |
| d04c1efa | 540 | #define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) |
| 8ae158cd TL |
541 | #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) |
| 542 | #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) | |
| 543 | #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) | |
| 544 | #define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) | |
| 545 | #define GPIO_PAR_PCI_GNT2_GPIO (0x0000) | |
| 546 | #define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) | |
| 547 | #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) | |
| 548 | #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) | |
| 549 | #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) | |
| d04c1efa | 550 | #define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) |
| 8ae158cd TL |
551 | #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) |
| 552 | #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) | |
| 553 | #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) | |
| 554 | #define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) | |
| 555 | #define GPIO_PAR_PCI_REQ2_GPIO (0x0000) | |
| 556 | #define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) | |
| 557 | #define GPIO_PAR_PCI_REQ1_GPIO (0x0000) | |
| 558 | #define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) | |
| 559 | #define GPIO_PAR_PCI_REQ0_GPIO (0x0000) | |
| 560 | ||
| 561 | /* Bit definitions and macros for MSCR_SDRAM */ | |
| 562 | #define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) | |
| 563 | #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) | |
| 564 | #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) | |
| 565 | #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) | |
| d04c1efa | 566 | #define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) |
| 8ae158cd TL |
567 | #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) |
| 568 | #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) | |
| 569 | #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) | |
| 570 | #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) | |
| d04c1efa | 571 | #define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) |
| 8ae158cd TL |
572 | #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) |
| 573 | #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) | |
| 574 | #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) | |
| 575 | #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) | |
| d04c1efa | 576 | #define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) |
| 8ae158cd TL |
577 | #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) |
| 578 | #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) | |
| 579 | #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) | |
| 580 | #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) | |
| d04c1efa | 581 | #define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) |
| 8ae158cd TL |
582 | #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) |
| 583 | #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) | |
| 584 | #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) | |
| 585 | #define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) | |
| 586 | ||
| 587 | /* Bit definitions and macros for MSCR_PCI */ | |
| 588 | #define GPIO_MSCR_PCI_PCI (0x01) | |
| 589 | #define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) | |
| 590 | #define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) | |
| 591 | ||
| 592 | /* Bit definitions and macros for DSCR_I2C */ | |
| 593 | #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) | |
| 594 | #define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) | |
| 595 | #define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) | |
| 596 | #define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) | |
| 597 | #define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) | |
| 598 | ||
| 599 | /* Bit definitions and macros for DSCR_FLEXBUS */ | |
| 600 | #define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) | |
| 601 | #define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) | |
| 602 | #define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) | |
| 603 | #define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) | |
| 604 | #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) | |
| 605 | #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) | |
| 606 | #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) | |
| 607 | #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) | |
| 608 | #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) | |
| 609 | #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) | |
| 610 | #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) | |
| 611 | #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) | |
| 612 | #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) | |
| 613 | #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) | |
| 614 | #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) | |
| 615 | #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) | |
| 616 | #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) | |
| 617 | #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) | |
| 618 | #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) | |
| 619 | #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) | |
| 620 | ||
| 621 | /* Bit definitions and macros for DSCR_FEC */ | |
| 622 | #define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) | |
| 623 | #define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) | |
| 624 | #define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) | |
| 625 | #define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) | |
| 626 | #define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) | |
| 627 | #define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) | |
| 628 | #define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) | |
| 629 | #define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) | |
| 630 | #define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) | |
| 631 | #define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) | |
| 632 | ||
| 633 | /* Bit definitions and macros for DSCR_UART */ | |
| 634 | #define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) | |
| 635 | #define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) | |
| 636 | #define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) | |
| 637 | #define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) | |
| 638 | #define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) | |
| 639 | #define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) | |
| 640 | #define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) | |
| 641 | #define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) | |
| 642 | #define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) | |
| 643 | #define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) | |
| 644 | ||
| 645 | /* Bit definitions and macros for DSCR_DSPI */ | |
| 646 | #define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) | |
| 647 | #define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) | |
| 648 | #define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) | |
| 649 | #define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) | |
| 650 | #define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) | |
| 651 | ||
| 652 | /* Bit definitions and macros for DSCR_TIMER */ | |
| 653 | #define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) | |
| 654 | #define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) | |
| 655 | #define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) | |
| 656 | #define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) | |
| 657 | #define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) | |
| 658 | ||
| 659 | /* Bit definitions and macros for DSCR_SSI */ | |
| 660 | #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) | |
| 661 | #define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) | |
| 662 | #define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) | |
| 663 | #define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) | |
| 664 | #define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) | |
| 665 | ||
| 666 | /* Bit definitions and macros for DSCR_DMA */ | |
| 667 | #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) | |
| 668 | #define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) | |
| 669 | #define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) | |
| 670 | #define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) | |
| 671 | #define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) | |
| 672 | ||
| 673 | /* Bit definitions and macros for DSCR_DEBUG */ | |
| 674 | #define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) | |
| 675 | #define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) | |
| 676 | #define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) | |
| 677 | #define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) | |
| 678 | #define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) | |
| 679 | ||
| 680 | /* Bit definitions and macros for DSCR_RESET */ | |
| 681 | #define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) | |
| 682 | #define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) | |
| 683 | #define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) | |
| 684 | #define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) | |
| 685 | #define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) | |
| 686 | ||
| 687 | /* Bit definitions and macros for DSCR_IRQ */ | |
| 688 | #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) | |
| 689 | #define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) | |
| 690 | #define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) | |
| 691 | #define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) | |
| 692 | #define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) | |
| 693 | ||
| 694 | /* Bit definitions and macros for DSCR_USB */ | |
| 695 | #define GPIO_DSCR_USB_USB(x) (((x)&0x03)) | |
| 696 | #define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) | |
| 697 | #define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) | |
| 698 | #define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) | |
| 699 | #define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) | |
| 700 | ||
| 701 | /* Bit definitions and macros for DSCR_ATA */ | |
| 702 | #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) | |
| 703 | #define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) | |
| 704 | #define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) | |
| 705 | #define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) | |
| 706 | #define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) | |
| 707 | ||
| 8ae158cd TL |
708 | /********************************************************************* |
| 709 | * SDRAM Controller (SDRAMC) | |
| 710 | *********************************************************************/ | |
| 711 | ||
| 712 | /* Bit definitions and macros for SDMR */ | |
| 713 | #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ | |
| 714 | #define SDRAMC_SDMR_CMD (0x00010000) /* Command */ | |
| 715 | #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ | |
| 716 | #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ | |
| 717 | #define SDRAMC_SDMR_BK_LMR (0x00000000) | |
| 718 | #define SDRAMC_SDMR_BK_LEMR (0x40000000) | |
| 719 | ||
| 720 | /* Bit definitions and macros for SDCR */ | |
| 721 | #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ | |
| 722 | #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ | |
| 723 | #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ | |
| 724 | #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ | |
| 725 | #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ | |
| 726 | #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ | |
| 727 | #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ | |
| 728 | #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ | |
| 729 | #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ | |
| 730 | #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ | |
| 731 | #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ | |
| 732 | #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ | |
| 733 | #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ | |
| 734 | #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) | |
| 735 | ||
| 736 | /* Bit definitions and macros for SDCFG1 */ | |
| 737 | #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ | |
| 738 | #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ | |
| 739 | #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ | |
| 740 | #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ | |
| 741 | #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ | |
| 742 | #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ | |
| 743 | #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ | |
| 744 | ||
| 745 | /* Bit definitions and macros for SDCFG2 */ | |
| 746 | #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ | |
| 747 | #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ | |
| 748 | #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ | |
| 749 | #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ | |
| 750 | ||
| 751 | /* Bit definitions and macros for SDCS group */ | |
| 752 | #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ | |
| 753 | #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ | |
| 754 | #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) | |
| 755 | #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) | |
| 756 | #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) | |
| 757 | #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) | |
| 758 | #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) | |
| 759 | #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) | |
| 760 | #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) | |
| 761 | #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) | |
| 762 | #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) | |
| 763 | #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) | |
| 764 | #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) | |
| 765 | #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) | |
| 766 | #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) | |
| 767 | #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) | |
| 768 | #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) | |
| 769 | ||
| 8ae158cd TL |
770 | /********************************************************************* |
| 771 | * Phase Locked Loop (PLL) | |
| 772 | *********************************************************************/ | |
| 773 | ||
| 774 | /* Bit definitions and macros for PCR */ | |
| 775 | #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ | |
| 776 | #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ | |
| 777 | #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ | |
| 778 | #define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ | |
| 779 | #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ | |
| 780 | #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ | |
| 781 | #define PLL_PCR_PFDR_MASK (0x000F0000) | |
| 782 | #define PLL_PCR_OUTDIV5_MASK (0x000F0000) | |
| 783 | #define PLL_PCR_OUTDIV4_MASK (0x0000F000) | |
| 784 | #define PLL_PCR_OUTDIV3_MASK (0x00000F00) | |
| 785 | #define PLL_PCR_OUTDIV2_MASK (0x000000F0) | |
| 786 | #define PLL_PCR_OUTDIV1_MASK (0x0000000F) | |
| 787 | ||
| 788 | /* Bit definitions and macros for PSR */ | |
| 789 | #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ | |
| 790 | #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ | |
| 791 | #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ | |
| 792 | #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ | |
| 793 | ||
| 794 | /********************************************************************* | |
| 795 | * PCI | |
| 796 | *********************************************************************/ | |
| 797 | ||
| 798 | /* Bit definitions and macros for SCR */ | |
| 799 | #define PCI_SCR_PE (0x80000000) /* Parity Error detected */ | |
| 800 | #define PCI_SCR_SE (0x40000000) /* System error signalled */ | |
| 801 | #define PCI_SCR_MA (0x20000000) /* Master aboart received */ | |
| 802 | #define PCI_SCR_TR (0x10000000) /* Target abort received */ | |
| 803 | #define PCI_SCR_TS (0x08000000) /* Target abort signalled */ | |
| 804 | #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ | |
| 805 | #define PCI_SCR_DP (0x01000000) /* Master data parity err */ | |
| 806 | #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ | |
| 807 | #define PCI_SCR_R (0x00400000) /* Reserved */ | |
| 808 | #define PCI_SCR_66M (0x00200000) /* 66Mhz */ | |
| 809 | #define PCI_SCR_C (0x00100000) /* Capabilities list */ | |
| 810 | #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ | |
| 811 | #define PCI_SCR_S (0x00000100) /* SERR enable */ | |
| 812 | #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ | |
| 813 | #define PCI_SCR_PER (0x00000040) /* Parity error response */ | |
| 814 | #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ | |
| 815 | #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ | |
| 816 | #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ | |
| 817 | #define PCI_SCR_B (0x00000004) /* Bus master enable */ | |
| 818 | #define PCI_SCR_M (0x00000002) /* Memory access control */ | |
| 819 | #define PCI_SCR_IO (0x00000001) /* I/O access control */ | |
| 820 | ||
| 821 | #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ | |
| 822 | #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ | |
| 823 | #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ | |
| 824 | #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ | |
| 825 | ||
| 826 | #define PCI_BAR_BAR0(x) (x & 0xFFFC0000) | |
| 827 | #define PCI_BAR_BAR1(x) (x & 0xFFF00000) | |
| 828 | #define PCI_BAR_BAR2(x) (x & 0xFFC00000) | |
| 829 | #define PCI_BAR_BAR3(x) (x & 0xFF000000) | |
| 830 | #define PCI_BAR_BAR4(x) (x & 0xF8000000) | |
| 831 | #define PCI_BAR_BAR5(x) (x & 0xE0000000) | |
| 832 | #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ | |
| 833 | #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ | |
| 834 | #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ | |
| 835 | ||
| 836 | #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ | |
| 837 | #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ | |
| 838 | #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ | |
| 839 | #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ | |
| 840 | ||
| 841 | #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ | |
| 842 | #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ | |
| 843 | #define PCI_GSCR_SE (0x10000000) /* SERR detected */ | |
| 844 | #define PCI_GSCR_ER (0x08000000) /* Error response detected */ | |
| 845 | #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ | |
| 846 | #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ | |
| 847 | #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ | |
| 848 | #define PCI_GSCR_PR (0x00000001) /* PCI reset */ | |
| 849 | ||
| 850 | #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ | |
| 851 | #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ | |
| 852 | #define PCI_TCR1_P (0x00010000) /* Prefetch reads */ | |
| 853 | #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ | |
| 854 | ||
| 2e72ad06 TL |
855 | #define PCI_TCR2_B5E (0x00002000) /* */ |
| 856 | #define PCI_TCR2_B4E (0x00001000) /* */ | |
| 857 | #define PCI_TCR2_B3E (0x00000800) /* */ | |
| 858 | #define PCI_TCR2_B2E (0x00000400) /* */ | |
| 859 | #define PCI_TCR2_B1E (0x00000200) /* */ | |
| 860 | #define PCI_TCR2_B0E (0x00000100) /* */ | |
| 861 | #define PCI_TCR2_CR (0x00000001) /* */ | |
| 8ae158cd TL |
862 | |
| 863 | #define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) | |
| 864 | #define PCI_TBATR_EN (0x00000001) /* Enable */ | |
| 865 | ||
| 866 | #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ | |
| 867 | #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ | |
| 868 | #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ | |
| 869 | #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ | |
| 870 | #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ | |
| 871 | #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ | |
| 872 | #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ | |
| 873 | #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ | |
| 874 | #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ | |
| 875 | #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ | |
| 876 | #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ | |
| 877 | #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ | |
| 878 | #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ | |
| 879 | #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ | |
| 880 | #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ | |
| 881 | ||
| 882 | #define PCI_ICR_REE (0x04000000) /* Retry error enable */ | |
| 883 | #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ | |
| 884 | #define PCI_ICR_TAE (0x01000000) /* Target abort enable */ | |
| d2b16493 | 885 | #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) |
| 8ae158cd TL |
886 | |
| 887 | /********************************************************************/ | |
| 888 | ||
| 889 | #endif /* __MCF5445X__ */ |