projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ca9d3ab5 SK |
1 | /* |
| 2 | * SPR Definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2000 Damjan Lampret | |
| 5 | * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> | |
| 6 | * Copyright (C) 2008, 2010 Embecosm Limited | |
| 7 | * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> | |
| 8 | * et al. | |
| 9 | * | |
| 1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
| ca9d3ab5 SK |
11 | * |
| 12 | * This file is part of OpenRISC 1000 Architectural Simulator. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef SPR_DEFS__H | |
| 16 | #define SPR_DEFS__H | |
| 17 | ||
| 18 | /* Definition of special-purpose registers (SPRs) */ | |
| 19 | ||
| 20 | #define MAX_GRPS (32) | |
| 21 | #define MAX_SPRS_PER_GRP_BITS (11) | |
| 22 | #define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) | |
| 23 | #define MAX_SPRS (0x10000) | |
| 24 | ||
| 25 | /* Base addresses for the groups */ | |
| 26 | #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS) | |
| 27 | #define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS) | |
| 28 | #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS) | |
| 29 | #define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS) | |
| 30 | #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS) | |
| 31 | #define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS) | |
| 32 | #define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS) | |
| 33 | #define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS) | |
| 34 | #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS) | |
| 35 | #define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS) | |
| 36 | #define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS) | |
| 37 | #define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS) | |
| 38 | ||
| 39 | /* System control and status group */ | |
| 40 | #define SPR_VR (SPRGROUP_SYS + 0) | |
| 41 | #define SPR_UPR (SPRGROUP_SYS + 1) | |
| 42 | #define SPR_CPUCFGR (SPRGROUP_SYS + 2) | |
| 43 | #define SPR_DMMUCFGR (SPRGROUP_SYS + 3) | |
| 44 | #define SPR_IMMUCFGR (SPRGROUP_SYS + 4) | |
| 45 | #define SPR_DCCFGR (SPRGROUP_SYS + 5) | |
| 46 | #define SPR_ICCFGR (SPRGROUP_SYS + 6) | |
| 47 | #define SPR_DCFGR (SPRGROUP_SYS + 7) | |
| 48 | #define SPR_PCCFGR (SPRGROUP_SYS + 8) | |
| 49 | #define SPR_NPC (SPRGROUP_SYS + 16) | |
| 50 | #define SPR_SR (SPRGROUP_SYS + 17) | |
| 51 | #define SPR_PPC (SPRGROUP_SYS + 18) | |
| 52 | #define SPR_FPCSR (SPRGROUP_SYS + 20) | |
| 53 | #define SPR_EPCR_BASE (SPRGROUP_SYS + 32) | |
| 54 | #define SPR_EPCR_LAST (SPRGROUP_SYS + 47) | |
| 55 | #define SPR_EEAR_BASE (SPRGROUP_SYS + 48) | |
| 56 | #define SPR_EEAR_LAST (SPRGROUP_SYS + 63) | |
| 57 | #define SPR_ESR_BASE (SPRGROUP_SYS + 64) | |
| 58 | #define SPR_ESR_LAST (SPRGROUP_SYS + 79) | |
| 59 | #define SPR_GPR_BASE (SPRGROUP_SYS + 1024) | |
| 60 | ||
| 61 | /* Data MMU group */ | |
| 62 | #define SPR_DMMUCR (SPRGROUP_DMMU + 0) | |
| 63 | #define SPR_DTLBEIR (SPRGROUP_DMMU + 2) | |
| 64 | #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) | |
| 65 | #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) | |
| 66 | #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) | |
| 67 | #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) | |
| 68 | ||
| 69 | /* Instruction MMU group */ | |
| 70 | #define SPR_IMMUCR (SPRGROUP_IMMU + 0) | |
| 71 | #define SPR_ITLBEIR (SPRGROUP_IMMU + 2) | |
| 72 | #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) | |
| 73 | #define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) | |
| 74 | #define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) | |
| 75 | #define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) | |
| 76 | ||
| 77 | /* Data cache group */ | |
| 78 | #define SPR_DCCR (SPRGROUP_DC + 0) | |
| 79 | #define SPR_DCBPR (SPRGROUP_DC + 1) | |
| 80 | #define SPR_DCBFR (SPRGROUP_DC + 2) | |
| 81 | #define SPR_DCBIR (SPRGROUP_DC + 3) | |
| 82 | #define SPR_DCBWR (SPRGROUP_DC + 4) | |
| 83 | #define SPR_DCBLR (SPRGROUP_DC + 5) | |
| 84 | #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) | |
| 85 | #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) | |
| 86 | ||
| 87 | /* Instruction cache group */ | |
| 88 | #define SPR_ICCR (SPRGROUP_IC + 0) | |
| 89 | #define SPR_ICBPR (SPRGROUP_IC + 1) | |
| 90 | #define SPR_ICBIR (SPRGROUP_IC + 2) | |
| 91 | #define SPR_ICBLR (SPRGROUP_IC + 3) | |
| 92 | #define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) | |
| 93 | #define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) | |
| 94 | ||
| 95 | /* MAC group */ | |
| 96 | #define SPR_MACLO (SPRGROUP_MAC + 1) | |
| 97 | #define SPR_MACHI (SPRGROUP_MAC + 2) | |
| 98 | ||
| 99 | /* Debug group */ | |
| 100 | #define SPR_DVR(N) (SPRGROUP_D + (N)) | |
| 101 | #define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) | |
| 102 | #define SPR_DMR1 (SPRGROUP_D + 16) | |
| 103 | #define SPR_DMR2 (SPRGROUP_D + 17) | |
| 104 | #define SPR_DWCR0 (SPRGROUP_D + 18) | |
| 105 | #define SPR_DWCR1 (SPRGROUP_D + 19) | |
| 106 | #define SPR_DSR (SPRGROUP_D + 20) | |
| 107 | #define SPR_DRR (SPRGROUP_D + 21) | |
| 108 | ||
| 109 | /* Performance counters group */ | |
| 110 | #define SPR_PCCR(N) (SPRGROUP_PC + (N)) | |
| 111 | #define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) | |
| 112 | ||
| 113 | /* Power management group */ | |
| 114 | #define SPR_PMR (SPRGROUP_PM + 0) | |
| 115 | ||
| 116 | /* PIC group */ | |
| 117 | #define SPR_PICMR (SPRGROUP_PIC + 0) | |
| 118 | #define SPR_PICPR (SPRGROUP_PIC + 1) | |
| 119 | #define SPR_PICSR (SPRGROUP_PIC + 2) | |
| 120 | ||
| 121 | /* Tick Timer group */ | |
| 122 | #define SPR_TTMR (SPRGROUP_TT + 0) | |
| 123 | #define SPR_TTCR (SPRGROUP_TT + 1) | |
| 124 | ||
| 125 | /* | |
| 126 | * Bit definitions for the Version Register | |
| 127 | */ | |
| 128 | #define SPR_VR_VER 0xff000000 /* Processor version */ | |
| 129 | #define SPR_VR_CFG 0x00ff0000 /* Processor configuration */ | |
| 130 | #define SPR_VR_RES 0x0000ffc0 /* Reserved */ | |
| 131 | #define SPR_VR_REV 0x0000003f /* Processor revision */ | |
| 132 | ||
| 133 | #define SPR_VR_VER_OFF 24 | |
| 134 | #define SPR_VR_CFG_OFF 16 | |
| 135 | #define SPR_VR_REV_OFF 0 | |
| 136 | ||
| 137 | /* | |
| 138 | * Bit definitions for the Unit Present Register | |
| 139 | */ | |
| 140 | #define SPR_UPR_UP 0x00000001 /* UPR present */ | |
| 141 | #define SPR_UPR_DCP 0x00000002 /* Data cache present */ | |
| 142 | #define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ | |
| 143 | #define SPR_UPR_DMP 0x00000008 /* Data MMU present */ | |
| 144 | #define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ | |
| 145 | #define SPR_UPR_MP 0x00000020 /* MAC present */ | |
| 146 | #define SPR_UPR_DUP 0x00000040 /* Debug unit present */ | |
| 147 | #define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ | |
| 148 | #define SPR_UPR_PMP 0x00000100 /* Power management present */ | |
| 149 | #define SPR_UPR_PICP 0x00000200 /* PIC present */ | |
| 150 | #define SPR_UPR_TTP 0x00000400 /* Tick timer present */ | |
| 151 | #define SPR_UPR_RES 0x00fe0000 /* Reserved */ | |
| 152 | #define SPR_UPR_CUP 0xff000000 /* Context units present */ | |
| 153 | ||
| 154 | /* | |
| 155 | * Bit definitions for the CPU configuration register | |
| 156 | */ | |
| 157 | #define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ | |
| 158 | #define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ | |
| 159 | #define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ | |
| 160 | #define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ | |
| 161 | #define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ | |
| 162 | #define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ | |
| 163 | #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ | |
| 164 | #define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ | |
| 165 | ||
| 166 | /* | |
| 167 | * Bit definitions for the Debug configuration register and other | |
| 168 | * constants. | |
| 169 | */ | |
| 170 | ||
| 171 | #define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ | |
| 172 | #define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ | |
| 173 | #define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ | |
| 174 | #define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ | |
| 175 | #define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ | |
| 176 | #define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ | |
| 177 | #define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ | |
| 178 | #define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ | |
| 179 | #define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ | |
| 180 | #define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */ | |
| 181 | ||
| 182 | #define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ | |
| 183 | 2 == n ? SPR_DCFGR_NDP2 : \ | |
| 184 | 3 == n ? SPR_DCFGR_NDP3 : \ | |
| 185 | 4 == n ? SPR_DCFGR_NDP4 : \ | |
| 186 | 5 == n ? SPR_DCFGR_NDP5 : \ | |
| 187 | 6 == n ? SPR_DCFGR_NDP6 : \ | |
| 188 | 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) | |
| 189 | #define MAX_MATCHPOINTS 8 | |
| 190 | #define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) | |
| 191 | ||
| 192 | /* | |
| 193 | * Bit definitions for the Supervision Register | |
| 194 | */ | |
| 195 | #define SPR_SR_SM 0x00000001 /* Supervisor Mode */ | |
| 196 | #define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ | |
| 197 | #define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ | |
| 198 | #define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ | |
| 199 | #define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ | |
| 200 | #define SPR_SR_DME 0x00000020 /* Data MMU Enable */ | |
| 201 | #define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ | |
| 202 | #define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ | |
| 203 | #define SPR_SR_CE 0x00000100 /* CID Enable */ | |
| 204 | #define SPR_SR_F 0x00000200 /* Condition Flag */ | |
| 205 | #define SPR_SR_CY 0x00000400 /* Carry flag */ | |
| 206 | #define SPR_SR_OV 0x00000800 /* Overflow flag */ | |
| 207 | #define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ | |
| 208 | #define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ | |
| 209 | #define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ | |
| 210 | #define SPR_SR_FO 0x00008000 /* Fixed one */ | |
| 211 | #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ | |
| 212 | #define SPR_SR_RES 0x0ffe0000 /* Reserved */ | |
| 213 | #define SPR_SR_CID 0xf0000000 /* Context ID */ | |
| 214 | ||
| 215 | /* | |
| 216 | * Bit definitions for the Data MMU Control Register | |
| 217 | */ | |
| 218 | #define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ | |
| 219 | #define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ | |
| 220 | #define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ | |
| 221 | #define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ | |
| 222 | ||
| 223 | /* | |
| 224 | * Bit definitions for the Instruction MMU Control Register | |
| 225 | */ | |
| 226 | #define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ | |
| 227 | #define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ | |
| 228 | #define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ | |
| 229 | #define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ | |
| 230 | ||
| 231 | /* | |
| 232 | * Bit definitions for the Data TLB Match Register | |
| 233 | */ | |
| 234 | #define SPR_DTLBMR_V 0x00000001 /* Valid */ | |
| 235 | #define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ | |
| 236 | #define SPR_DTLBMR_CID 0x0000003c /* Context ID */ | |
| 237 | #define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ | |
| 238 | #define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ | |
| 239 | ||
| 240 | /* | |
| 241 | * Bit definitions for the Data TLB Translate Register | |
| 242 | */ | |
| 243 | #define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ | |
| 244 | #define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ | |
| 245 | #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ | |
| 246 | #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ | |
| 247 | #define SPR_DTLBTR_A 0x00000010 /* Accessed */ | |
| 248 | #define SPR_DTLBTR_D 0x00000020 /* Dirty */ | |
| 249 | #define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ | |
| 250 | #define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ | |
| 251 | #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ | |
| 252 | #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ | |
| 253 | #define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ | |
| 254 | ||
| 255 | /* | |
| 256 | * Bit definitions for the Instruction TLB Match Register | |
| 257 | */ | |
| 258 | #define SPR_ITLBMR_V 0x00000001 /* Valid */ | |
| 259 | #define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ | |
| 260 | #define SPR_ITLBMR_CID 0x0000003c /* Context ID */ | |
| 261 | #define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ | |
| 262 | #define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ | |
| 263 | ||
| 264 | /* | |
| 265 | * Bit definitions for the Instruction TLB Translate Register | |
| 266 | */ | |
| 267 | #define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ | |
| 268 | #define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ | |
| 269 | #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ | |
| 270 | #define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ | |
| 271 | #define SPR_ITLBTR_A 0x00000010 /* Accessed */ | |
| 272 | #define SPR_ITLBTR_D 0x00000020 /* Dirty */ | |
| 273 | #define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ | |
| 274 | #define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ | |
| 275 | #define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ | |
| 276 | ||
| 277 | /* | |
| 278 | * Bit definitions for Data Cache Control register | |
| 279 | */ | |
| 280 | #define SPR_DCCR_EW 0x000000ff /* Enable ways */ | |
| 281 | ||
| 282 | /* | |
| 283 | * Bit definitions for Insn Cache Control register | |
| 284 | */ | |
| 285 | #define SPR_ICCR_EW 0x000000ff /* Enable ways */ | |
| 286 | ||
| 287 | /* | |
| 288 | * Bit definitions for Data Cache Configuration Register | |
| 289 | */ | |
| 290 | ||
| 291 | #define SPR_DCCFGR_NCW 0x00000007 | |
| 292 | #define SPR_DCCFGR_NCS 0x00000078 | |
| 293 | #define SPR_DCCFGR_CBS 0x00000080 | |
| 294 | #define SPR_DCCFGR_CWS 0x00000100 | |
| 295 | #define SPR_DCCFGR_CCRI 0x00000200 | |
| 296 | #define SPR_DCCFGR_CBIRI 0x00000400 | |
| 297 | #define SPR_DCCFGR_CBPRI 0x00000800 | |
| 298 | #define SPR_DCCFGR_CBLRI 0x00001000 | |
| 299 | #define SPR_DCCFGR_CBFRI 0x00002000 | |
| 300 | #define SPR_DCCFGR_CBWBRI 0x00004000 | |
| 301 | ||
| 302 | #define SPR_DCCFGR_NCW_OFF 0 | |
| 303 | #define SPR_DCCFGR_NCS_OFF 3 | |
| 304 | #define SPR_DCCFGR_CBS_OFF 7 | |
| 305 | ||
| 306 | /* | |
| 307 | * Bit definitions for Instruction Cache Configuration Register | |
| 308 | */ | |
| 309 | #define SPR_ICCFGR_NCW 0x00000007 | |
| 310 | #define SPR_ICCFGR_NCS 0x00000078 | |
| 311 | #define SPR_ICCFGR_CBS 0x00000080 | |
| 312 | #define SPR_ICCFGR_CCRI 0x00000200 | |
| 313 | #define SPR_ICCFGR_CBIRI 0x00000400 | |
| 314 | #define SPR_ICCFGR_CBPRI 0x00000800 | |
| 315 | #define SPR_ICCFGR_CBLRI 0x00001000 | |
| 316 | ||
| 317 | #define SPR_ICCFGR_NCW_OFF 0 | |
| 318 | #define SPR_ICCFGR_NCS_OFF 3 | |
| 319 | #define SPR_ICCFGR_CBS_OFF 7 | |
| 320 | ||
| 321 | /* | |
| 322 | * Bit definitions for Data MMU Configuration Register | |
| 323 | */ | |
| 324 | #define SPR_DMMUCFGR_NTW 0x00000003 | |
| 325 | #define SPR_DMMUCFGR_NTS 0x0000001C | |
| 326 | #define SPR_DMMUCFGR_NAE 0x000000E0 | |
| 327 | #define SPR_DMMUCFGR_CRI 0x00000100 | |
| 328 | #define SPR_DMMUCFGR_PRI 0x00000200 | |
| 329 | #define SPR_DMMUCFGR_TEIRI 0x00000400 | |
| 330 | #define SPR_DMMUCFGR_HTR 0x00000800 | |
| 331 | ||
| 332 | #define SPR_DMMUCFGR_NTW_OFF 0 | |
| 333 | #define SPR_DMMUCFGR_NTS_OFF 2 | |
| 334 | ||
| 335 | /* | |
| 336 | * Bit definitions for Instruction MMU Configuration Register | |
| 337 | */ | |
| 338 | #define SPR_IMMUCFGR_NTW 0x00000003 | |
| 339 | #define SPR_IMMUCFGR_NTS 0x0000001C | |
| 340 | #define SPR_IMMUCFGR_NAE 0x000000E0 | |
| 341 | #define SPR_IMMUCFGR_CRI 0x00000100 | |
| 342 | #define SPR_IMMUCFGR_PRI 0x00000200 | |
| 343 | #define SPR_IMMUCFGR_TEIRI 0x00000400 | |
| 344 | #define SPR_IMMUCFGR_HTR 0x00000800 | |
| 345 | ||
| 346 | #define SPR_IMMUCFGR_NTW_OFF 0 | |
| 347 | #define SPR_IMMUCFGR_NTS_OFF 2 | |
| 348 | ||
| 349 | /* | |
| 350 | * Bit definitions for Debug Control registers | |
| 351 | */ | |
| 352 | #define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ | |
| 353 | #define SPR_DCR_CC 0x0000000e /* Compare condition */ | |
| 354 | #define SPR_DCR_SC 0x00000010 /* Signed compare */ | |
| 355 | #define SPR_DCR_CT 0x000000e0 /* Compare to */ | |
| 356 | ||
| 357 | /* Bit results with SPR_DCR_CC mask */ | |
| 358 | #define SPR_DCR_CC_MASKED 0x00000000 | |
| 359 | #define SPR_DCR_CC_EQUAL 0x00000002 | |
| 360 | #define SPR_DCR_CC_LESS 0x00000004 | |
| 361 | #define SPR_DCR_CC_LESSE 0x00000006 | |
| 362 | #define SPR_DCR_CC_GREAT 0x00000008 | |
| 363 | #define SPR_DCR_CC_GREATE 0x0000000a | |
| 364 | #define SPR_DCR_CC_NEQUAL 0x0000000c | |
| 365 | ||
| 366 | /* Bit results with SPR_DCR_CT mask */ | |
| 367 | #define SPR_DCR_CT_DISABLED 0x00000000 | |
| 368 | #define SPR_DCR_CT_IFEA 0x00000020 | |
| 369 | #define SPR_DCR_CT_LEA 0x00000040 | |
| 370 | #define SPR_DCR_CT_SEA 0x00000060 | |
| 371 | #define SPR_DCR_CT_LD 0x00000080 | |
| 372 | #define SPR_DCR_CT_SD 0x000000a0 | |
| 373 | #define SPR_DCR_CT_LSEA 0x000000c0 | |
| 374 | #define SPR_DCR_CT_LSD 0x000000e0 | |
| 375 | ||
| 376 | /* | |
| 377 | * Bit definitions for Debug Mode 1 register | |
| 378 | */ | |
| 379 | #define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ | |
| 380 | #define SPR_DMR1_CW0_AND 0x00000001 | |
| 381 | #define SPR_DMR1_CW0_OR 0x00000002 | |
| 382 | #define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) | |
| 383 | #define SPR_DMR1_CW1_AND 0x00000004 | |
| 384 | #define SPR_DMR1_CW1_OR 0x00000008 | |
| 385 | #define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) | |
| 386 | #define SPR_DMR1_CW2_AND 0x00000010 | |
| 387 | #define SPR_DMR1_CW2_OR 0x00000020 | |
| 388 | #define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) | |
| 389 | #define SPR_DMR1_CW3_AND 0x00000040 | |
| 390 | #define SPR_DMR1_CW3_OR 0x00000080 | |
| 391 | #define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) | |
| 392 | #define SPR_DMR1_CW4_AND 0x00000100 | |
| 393 | #define SPR_DMR1_CW4_OR 0x00000200 | |
| 394 | #define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) | |
| 395 | #define SPR_DMR1_CW5_AND 0x00000400 | |
| 396 | #define SPR_DMR1_CW5_OR 0x00000800 | |
| 397 | #define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) | |
| 398 | #define SPR_DMR1_CW6_AND 0x00001000 | |
| 399 | #define SPR_DMR1_CW6_OR 0x00002000 | |
| 400 | #define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) | |
| 401 | #define SPR_DMR1_CW7_AND 0x00004000 | |
| 402 | #define SPR_DMR1_CW7_OR 0x00008000 | |
| 403 | #define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) | |
| 404 | #define SPR_DMR1_CW8_AND 0x00010000 | |
| 405 | #define SPR_DMR1_CW8_OR 0x00020000 | |
| 406 | #define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) | |
| 407 | #define SPR_DMR1_CW9_AND 0x00040000 | |
| 408 | #define SPR_DMR1_CW9_OR 0x00080000 | |
| 409 | #define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) | |
| 410 | #define SPR_DMR1_RES1 0x00300000 /* Reserved */ | |
| 411 | #define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ | |
| 412 | #define SPR_DMR1_BT 0x00800000 /* Branch trace */ | |
| 413 | #define SPR_DMR1_RES2 0xff000000 /* Reserved */ | |
| 414 | ||
| 415 | /* | |
| 416 | * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB | |
| 417 | */ | |
| 418 | #define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ | |
| 419 | #define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ | |
| 420 | #define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ | |
| 421 | #define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ | |
| 422 | #define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */ | |
| 423 | #define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ | |
| 424 | #define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */ | |
| 425 | #define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ | |
| 426 | ||
| 427 | /* | |
| 428 | * Bit definitions for Debug watchpoint counter registers | |
| 429 | */ | |
| 430 | #define SPR_DWCR_COUNT 0x0000ffff /* Count */ | |
| 431 | #define SPR_DWCR_MATCH 0xffff0000 /* Match */ | |
| 432 | #define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ | |
| 433 | ||
| 434 | /* | |
| 435 | * Bit definitions for Debug stop register | |
| 436 | * | |
| 437 | */ | |
| 438 | #define SPR_DSR_RSTE 0x00000001 /* Reset exception */ | |
| 439 | #define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ | |
| 440 | #define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ | |
| 441 | #define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ | |
| 442 | #define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ | |
| 443 | #define SPR_DSR_AE 0x00000020 /* Alignment exception */ | |
| 444 | #define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ | |
| 445 | #define SPR_DSR_IE 0x00000080 /* Interrupt exception */ | |
| 446 | #define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ | |
| 447 | #define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ | |
| 448 | #define SPR_DSR_RE 0x00000400 /* Range exception */ | |
| 449 | #define SPR_DSR_SCE 0x00000800 /* System call exception */ | |
| 450 | #define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */ | |
| 451 | #define SPR_DSR_TE 0x00002000 /* Trap exception */ | |
| 452 | ||
| 453 | /* | |
| 454 | * Bit definitions for Debug reason register | |
| 455 | */ | |
| 456 | #define SPR_DRR_RSTE 0x00000001 /* Reset exception */ | |
| 457 | #define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ | |
| 458 | #define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ | |
| 459 | #define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ | |
| 460 | #define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ | |
| 461 | #define SPR_DRR_AE 0x00000020 /* Alignment exception */ | |
| 462 | #define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ | |
| 463 | #define SPR_DRR_IE 0x00000080 /* Interrupt exception */ | |
| 464 | #define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ | |
| 465 | #define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ | |
| 466 | #define SPR_DRR_RE 0x00000400 /* Range exception */ | |
| 467 | #define SPR_DRR_SCE 0x00000800 /* System call exception */ | |
| 468 | #define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */ | |
| 469 | #define SPR_DRR_TE 0x00002000 /* Trap exception */ | |
| 470 | ||
| 471 | /* | |
| 472 | * Bit definitions for Performance counters mode registers | |
| 473 | */ | |
| 474 | #define SPR_PCMR_CP 0x00000001 /* Counter present */ | |
| 475 | #define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ | |
| 476 | #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ | |
| 477 | #define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ | |
| 478 | #define SPR_PCMR_LA 0x00000010 /* Load access event */ | |
| 479 | #define SPR_PCMR_SA 0x00000020 /* Store access event */ | |
| 480 | #define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ | |
| 481 | #define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ | |
| 482 | #define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ | |
| 483 | #define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ | |
| 484 | #define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ | |
| 485 | #define SPR_PCMR_BS 0x00000800 /* Branch stall event */ | |
| 486 | #define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ | |
| 487 | #define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ | |
| 488 | #define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ | |
| 489 | #define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ | |
| 490 | ||
| 491 | /* | |
| 492 | * Bit definitions for the Power management register | |
| 493 | */ | |
| 494 | #define SPR_PMR_SDF 0x0000000f /* Slow down factor */ | |
| 495 | #define SPR_PMR_DME 0x00000010 /* Doze mode enable */ | |
| 496 | #define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ | |
| 497 | #define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ | |
| 498 | #define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ | |
| 499 | ||
| 500 | /* | |
| 501 | * Bit definitions for PICMR | |
| 502 | */ | |
| 503 | #define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ | |
| 504 | ||
| 505 | /* | |
| 506 | * Bit definitions for PICPR | |
| 507 | */ | |
| 508 | #define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ | |
| 509 | ||
| 510 | /* | |
| 511 | * Bit definitions for PICSR | |
| 512 | */ | |
| 513 | #define SPR_PICSR_IS 0xffffffff /* Interrupt status */ | |
| 514 | ||
| 515 | /* | |
| 516 | * Bit definitions for Tick Timer Control Register | |
| 517 | */ | |
| 518 | #define SPR_TTCR_CNT 0xffffffff /* Count, time period */ | |
| 519 | #define SPR_TTMR_TP 0x0fffffff /* Time period */ | |
| 520 | #define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ | |
| 521 | #define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ | |
| 522 | #define SPR_TTMR_DI 0x00000000 /* Disabled */ | |
| 523 | #define SPR_TTMR_RT 0x40000000 /* Restart tick */ | |
| 524 | #define SPR_TTMR_SR 0x80000000 /* Single run */ | |
| 525 | #define SPR_TTMR_CR 0xc0000000 /* Continuous run */ | |
| 526 | #define SPR_TTMR_M 0xc0000000 /* Tick mode */ | |
| 527 | ||
| 528 | /* | |
| 529 | * Bit definitions for the FP Control Status Register | |
| 530 | */ | |
| 531 | #define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */ | |
| 532 | #define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */ | |
| 533 | #define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */ | |
| 534 | #define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */ | |
| 535 | #define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */ | |
| 536 | #define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */ | |
| 537 | #define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */ | |
| 538 | #define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */ | |
| 539 | #define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */ | |
| 540 | #define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */ | |
| 541 | #define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */ | |
| 542 | #define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \ | |
| 543 | SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \ | |
| 544 | SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF) | |
| 545 | ||
| 546 | #define FPCSR_RM_RN (0<<1) | |
| 547 | #define FPCSR_RM_RZ (1<<1) | |
| 548 | #define FPCSR_RM_RIP (2<<1) | |
| 549 | #define FPCSR_RM_RIN (3<<1) | |
| 550 | ||
| 551 | /* | |
| 552 | * l.nop constants | |
| 553 | */ | |
| 554 | #define NOP_NOP 0x0000 /* Normal nop instruction */ | |
| 555 | #define NOP_EXIT 0x0001 /* End of simulation */ | |
| 556 | #define NOP_REPORT 0x0002 /* Simple report */ | |
| 557 | #define NOP_PUTC 0x0004 /* Simputc instruction */ | |
| 558 | #define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ | |
| 559 | #define NOP_GET_TICKS 0x0006 /* Get # ticks running */ | |
| 560 | #define NOP_GET_PS 0x0007 /* Get picosecs/cycle */ | |
| 561 | #define NOP_REPORT_FIRST 0x0400 /* Report with number */ | |
| 562 | #define NOP_REPORT_LAST 0x03ff /* Report with number */ | |
| 563 | ||
| 564 | #endif /* SPR_DEFS__H */ |