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8993e54b RJ |
1 | /* |
2 | * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. | |
843efb11 | 3 | * Copyright (C) 2007-2009 DENX Software Engineering |
8993e54b RJ |
4 | * |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * Derived from the MPC83xx code. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
843efb11 WD |
28 | #include <asm/io.h> |
29 | #include <asm/processor.h> | |
8993e54b RJ |
30 | |
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
33 | /* | |
34 | * Set up the memory map, initialize registers, | |
35 | */ | |
36 | void cpu_init_f (volatile immap_t * im) | |
37 | { | |
38 | u32 ips_div; | |
39 | ||
40 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 41 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
8993e54b RJ |
42 | |
43 | /* Clear initial global data */ | |
44 | memset ((void *) gd, 0, sizeof (gd_t)); | |
45 | ||
46 | /* system performance tweaking */ | |
47 | ||
6d0f6bcf | 48 | #ifdef CONFIG_SYS_ACR_PIPE_DEP |
8993e54b | 49 | /* Arbiter pipeline depth */ |
843efb11 WD |
50 | out_be32(&im->arbiter.acr, |
51 | (im->arbiter.acr & ~ACR_PIPE_DEP) | | |
52 | (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | |
53 | ); | |
8993e54b RJ |
54 | #endif |
55 | ||
6d0f6bcf | 56 | #ifdef CONFIG_SYS_ACR_RPTCNT |
8993e54b | 57 | /* Arbiter repeat count */ |
843efb11 WD |
58 | out_be32(im->arbiter.acr, |
59 | (im->arbiter.acr & ~(ACR_RPTCNT)) | | |
60 | (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | |
61 | ); | |
8993e54b RJ |
62 | #endif |
63 | ||
64 | /* RSR - Reset Status Register - clear all status */ | |
65 | gd->reset_status = im->reset.rsr; | |
843efb11 | 66 | out_be32(&im->reset.rsr, ~RSR_RES); |
8993e54b RJ |
67 | |
68 | /* | |
69 | * RMR - Reset Mode Register - enable checkstop reset | |
70 | */ | |
843efb11 | 71 | out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT)); |
8993e54b RJ |
72 | |
73 | /* Set IPS-CSB divider: IPS = 1/2 CSB */ | |
843efb11 | 74 | ips_div = in_be32(&im->clk.scfr[0]); |
8993e54b RJ |
75 | ips_div &= ~(SCFR1_IPS_DIV_MASK); |
76 | ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; | |
843efb11 | 77 | out_be32(&im->clk.scfr[0], ips_div); |
8993e54b RJ |
78 | |
79 | /* | |
80 | * Enable Time Base/Decrementer | |
81 | * | |
82 | * NOTICE: TB needs to be enabled as early as possible in order to | |
83 | * have udelay() working; if not enabled, usually leads to a hang, like | |
b1b54e35 | 84 | * during FLASH chip identification etc. |
8993e54b | 85 | */ |
843efb11 | 86 | setbits_be32(&im->sysconf.spcr, SPCR_TBEN); |
8993e54b RJ |
87 | } |
88 | ||
89 | int cpu_init_r (void) | |
90 | { | |
91 | return 0; | |
92 | } |