[people/ms/u-boot.git] / arch / powerpc / cpu / mpc512x / start.S

/*
 * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Based on the MPC83xx code.
 */

/*
 *  U-Boot - Startup Code for MPC512x based Embedded Boards
 */

#include <config.h>
#include <timestamp.h>
#include <version.h>

#define CONFIG_521X	1		/* needed for Linux kernel header files*/

#include <asm/immap_512x.h>
#include "asm-offsets.h"

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING "MPC512X"
#endif

/*
 * Floating Point enable, Machine Check and Recoverable Interr.
 */
#undef	MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif

/* Macros for manipulating CSx_START/STOP */
#define START_REG(start)	((start) >> 16)
#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)

/*
 * Set up GOT: Global Offset Table
 *
 * Use r12 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * Magic number and version string
 */
	.long	0x27051956		/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
	.ascii " ", CONFIG_IDENT_STRING, "\0"

/*
 * Vector Table
 */
	.text
	. = EXC_OFF_SYS_RESET

	.globl	_start
	/* Start from here after reset/power on */
_start:
	b	boot_cold

	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
		MSR_KERNEL, COPY_EE)

/* Floating Point Unit unavailable exception */
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

/* Decrementer */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)

/* Critical interrupt */
	STD_EXCEPTION(0xa00, Critical, UnknownException)

/* System Call */
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)

/* Trace interrupt */
	STD_EXCEPTION(0xd00, Trace, UnknownException)

/* Performance Monitor interrupt */
	STD_EXCEPTION(0xf00, PerfMon, UnknownException)

/* Intruction Translation Miss */
	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)

/* Data Load Translation Miss */
	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)

/* Data Store Translation Miss */
	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)

/* Instruction Address Breakpoint */
	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)

/* System Management interrupt */
	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)

	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000
boot_cold:
	/* Save msr contents */
	mfmsr	r5

	/* Set IMMR area to our preferred location */
	lis	r4, CONFIG_DEFAULT_IMMR@h
	lis	r3, CONFIG_SYS_IMMR@h
	ori	r3, r3, CONFIG_SYS_IMMR@l
	stw	r3, IMMRBAR(r4)
	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */

	/* Initialise the machine */
	bl	cpu_early_init

	/*
	 * Set up Local Access Windows:
	 *
	 * 1) Boot/CS0 (boot FLASH)
	 * 2) On-chip SRAM (initial stack purposes)
	 */

	/* Boot CS/CS0 window range */
	lis     r3, CONFIG_SYS_IMMR@h
	ori     r3, r3, CONFIG_SYS_IMMR@l

	lis	r4, START_REG(CONFIG_SYS_FLASH_BASE)
	ori	r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
	stw	r4, LPCS0AW(r3)

	/*
	 * The SRAM window has a fixed size (256K), so only the start address
	 * is necessary
	 */
	lis	r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
	stw	r4, SRAMBAR(r3)

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lwz	r4, SRAMBAR(r3)
	isync

	/*
	 * Set configuration of the Boot/CS0, the SRAM window does not have a
	 * config register so no params can be set for it
	 */
	lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
	ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l

	lis     r4, CONFIG_SYS_CS0_CFG@h
	ori     r4, r4, CONFIG_SYS_CS0_CFG@l
	stw     r4, CS0_CONFIG(r3)

	/* Master enable all CS's */
	lis	r4, CS_CTRL_ME@h
	ori	r4, r4, CS_CTRL_ME@l
	stw	r4, CS_CTRL(r3)

	lis	r4, (CONFIG_SYS_MONITOR_BASE)@h
	ori	r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r5
	blr

in_flash:
	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l

	li	r0, 0		/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest			*/
	/*							*/
	/* Be careful to keep code relocatable & stack humble	*/
	/*------------------------------------------------------*/

	GET_GOT			/* initialize GOT access	*/

	/* r3: IMMR */
	lis	r3, CONFIG_SYS_IMMR@h
	/* run low-level CPU init code (in Flash) */
	bl	cpu_init_f

	/* run 1st part of board init code (in Flash) */
	bl	board_init_f

	/* NOTREACHED - board_init_f() does not return */

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/*
 * This code initialises the machine, it expects original MSR contents to be in r5.
 */
cpu_early_init:
	/* Initialize machine status; enable machine check interrupt */
	/*-----------------------------------------------------------*/

	li	r3, MSR_KERNEL			/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
#ifdef DEBUG
	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
#endif
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */

	lis	r3, CONFIG_SYS_IMMR@h

#if defined(CONFIG_WATCHDOG)
	/* Initialise the watchdog and reset it */
	/*--------------------------------------*/
	lis r4, CONFIG_SYS_WATCHDOG_VALUE
	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
	stw r4, SWCRR(r3)

	/* reset */
	li	r4, 0x556C
	sth	r4, SWSRR@l(r3)
	li	r4, 0x0
	ori	r4, r4, 0xAA39
	sth	r4, SWSRR@l(r3)
#else
	/* Disable the watchdog */
	/*----------------------*/
	lwz r4, SWCRR(r3)
	/*
	 * Check to see if it's enabled for disabling: once disabled by s/w
	 * it's not possible to re-enable it
	 */
	andi. r4, r4, 0x4
	beq 1f
	xor r4, r4, r4
	stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */

	/* Initialize the Hardware Implementation-dependent Registers */
	/* HID0 also contains cache control			*/
	/*------------------------------------------------------*/
	lis	r3, CONFIG_SYS_HID0_INIT@h
	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID0_FINAL@h
	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID2@h
	ori	r3, r3, CONFIG_SYS_HID2@l
	SYNC
	mtspr	HID2, r3
	sync
	blr


/* Cache functions.
 *
 * Note: requires that all cache bits in
 * HID0 are in the low half word.
 */
	.globl	icache_enable
icache_enable:
	mfspr	r3, HID0
	ori	r3, r3, HID0_ICE
	lis	r4, 0
	ori	r4, r4, HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_disable
icache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_ICE|HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	blr

	.globl	dcache_enable
dcache_enable:
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
	blr

	.globl	dcache_disable
dcache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_DCE|HID0_DLOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_DCI
	sync
	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
	sync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr

/*-------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer	*/
	mr	r9,  r4		/* Save copy of Global Data pointer */
	mr	r10, r5		/* Save copy of Destination Address */

	GET_GOT
	mr	r3,  r5				/* Destination Address */
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
	 *		+ Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r12, r12, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */
	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary */
	beq	7f		/* Protect against 0 count	  */
	mtctr	r0
	bge	cr1,2f
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* copy */
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b

	addi	r0,r5,3
	srwi.	r0,r0,2
	mtctr	r0
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* and compare */
20:	lwzu	r20,4(r8)
	lwzu	r21,4(r7)
	xor. r22, r20, r21
	bne  30f
	bdnz	20b
	b 4f

	/* compare failed */
30:	li r3, 0
	blr

2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:
	/*
	 * Relocation Function, r12 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	cmpwi	r0,0
	beq-	2f
	add	r0,r0,r11
	stw	r0,0(r3)
2:	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:
	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	mflr	r4		/* save link register */
	GET_GOT
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100	/* reset vector at 0x100 */

	cmplw	0, r7, r8
	bgelr			/* return if r7>=r8 - just in case */
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	4b

	mfmsr	r3			/* now that the vectors have */
	lis	r7, MSR_IP@h		/* relocated into low memory */
	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
	andc	r3, r3, r7		/* (if it was on) */
	SYNC				/* Some chip revs need this... */
	mtmsr	r3
	SYNC

	mtlr	r4			/* restore link register    */
	blr
Commit	Line	Data
8993e54b RJ	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
3b74e7ec	4	* Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
4c2e3da8	5	* Copyright Freescale Semiconductor, Inc. 2004, 2006.
8993e54b RJ	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*
	25	* Based on the MPC83xx code.
	26	*/
	27
	28	/*
	29	* U-Boot - Startup Code for MPC512x based Embedded Boards
	30	*/
	31
	32	#include <config.h>
561858ee	33	#include <timestamp.h>
8993e54b RJ	34	#include <version.h>
	35
	36	#define CONFIG_521X 1 /* needed for Linux kernel header files*/
	37
3b74e7ec WD	38	#include <asm/immap_512x.h>
	39	#include "asm-offsets.h"
	40
8993e54b RJ	41	#include <ppc_asm.tmpl>
	42	#include <ppc_defs.h>
	43
	44	#include <asm/cache.h>
	45	#include <asm/mmu.h>
d98b0523	46	#include <asm/u-boot.h>
8993e54b RJ	47
	48	#ifndef CONFIG_IDENT_STRING
	49	#define CONFIG_IDENT_STRING "MPC512X"
	50	#endif
	51
	52	/*
	53	* Floating Point enable, Machine Check and Recoverable Interr.
	54	*/
	55	#undef MSR_KERNEL
	56	#ifdef DEBUG
	57	#define MSR_KERNEL (MSR_FP\|MSR_RI)
	58	#else
	59	#define MSR_KERNEL (MSR_FP\|MSR_ME\|MSR_RI)
	60	#endif
	61
	62	/* Macros for manipulating CSx_START/STOP */
	63	#define START_REG(start) ((start) >> 16)
	64	#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
	65
	66	/*
	67	* Set up GOT: Global Offset Table
	68	*
0f8aa159	69	* Use r12 to access the GOT
8993e54b RJ	70	*/
	71	START_GOT
	72	GOT_ENTRY(_GOT2_TABLE_)
	73	GOT_ENTRY(_FIXUP_TABLE_)
	74
	75	GOT_ENTRY(_start)
	76	GOT_ENTRY(_start_of_vectors)
	77	GOT_ENTRY(_end_of_vectors)
	78	GOT_ENTRY(transfer_to_handler)
	79
	80	GOT_ENTRY(__init_end)
	81	GOT_ENTRY(_end)
	82	GOT_ENTRY(__bss_start)
	83	END_GOT
	84
	85	/*
	86	* Magic number and version string
	87	*/
	88	.long 0x27051956 /* U-Boot Magic Number */
	89	.globl version_string
	90	version_string:
	91	.ascii U_BOOT_VERSION
561858ee	92	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
8993e54b RJ	93	.ascii " ", CONFIG_IDENT_STRING, "\0"
	94
	95	/*
	96	* Vector Table
	97	*/
	98	.text
	99	. = EXC_OFF_SYS_RESET
	100
	101	.globl _start
	102	/* Start from here after reset/power on */
	103	_start:
8993e54b RJ	104	b boot_cold
	105
	106	.globl _start_of_vectors
	107	_start_of_vectors:
	108
	109	/* Machine check */
	110	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	111
	112	/* Data Storage exception. */
	113	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	114
	115	/* Instruction Storage exception. */
	116	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	117
	118	/* External Interrupt exception. */
	119	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
	120
	121	/* Alignment exception. */
	122	. = 0x600
	123	Alignment:
	124	EXCEPTION_PROLOG(SRR0, SRR1)
	125	mfspr r4,DAR
	126	stw r4,_DAR(r21)
	127	mfspr r5,DSISR
	128	stw r5,_DSISR(r21)
	129	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887	130	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
8993e54b RJ	131
	132	/* Program check exception */
	133	. = 0x700
	134	ProgramCheck:
	135	EXCEPTION_PROLOG(SRR0, SRR1)
	136	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887 JT	137	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
fc4e1887 JT	138	MSR_KERNEL, COPY_EE)
8993e54b RJ	139
	140	/* Floating Point Unit unavailable exception */
	141	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	142
	143	/* Decrementer */
	144	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	145
	146	/* Critical interrupt */
	147	STD_EXCEPTION(0xa00, Critical, UnknownException)
	148
	149	/* System Call */
	150	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	151
	152	/* Trace interrupt */
	153	STD_EXCEPTION(0xd00, Trace, UnknownException)
	154
	155	/* Performance Monitor interrupt */
	156	STD_EXCEPTION(0xf00, PerfMon, UnknownException)
	157
	158	/* Intruction Translation Miss */
	159	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
	160
	161	/* Data Load Translation Miss */
	162	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
	163
	164	/* Data Store Translation Miss */
	165	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
	166
	167	/* Instruction Address Breakpoint */
	168	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
	169
	170	/* System Management interrupt */
	171	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
	172
	173	.globl _end_of_vectors
	174	_end_of_vectors:
	175
	176	. = 0x3000
	177	boot_cold:
	178	/* Save msr contents */
	179	mfmsr r5
	180
	181	/* Set IMMR area to our preferred location */
	182	lis r4, CONFIG_DEFAULT_IMMR@h
6d0f6bcf JCPV	183	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	184	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b RJ	185	stw r3, IMMRBAR(r4)
	186	mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
	187
	188	/* Initialise the machine */
	189	bl cpu_early_init
	190
	191	/*
	192	* Set up Local Access Windows:
	193	*
	194	* 1) Boot/CS0 (boot FLASH)
	195	* 2) On-chip SRAM (initial stack purposes)
	196	*/
	197
	198	/* Boot CS/CS0 window range */
6d0f6bcf JCPV	199	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	200	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b	201
6d0f6bcf JCPV	202	lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	203	ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
8993e54b RJ	204	stw r4, LPCS0AW(r3)
	205
	206	/*
	207	* The SRAM window has a fixed size (256K), so only the start address
	208	* is necessary
	209	*/
6d0f6bcf	210	lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
8993e54b RJ	211	stw r4, SRAMBAR(r3)
8993e54b RJ	212
b1b54e35	213	/*
8993e54b	214	* According to MPC5121e RM, configuring local access windows should
b1b54e35	215	* be followed by a dummy read of the config register that was
8993e54b	216	* modified last and an isync
b1b54e35	217	*/
8993e54b RJ	218	lwz r4, SRAMBAR(r3)
	219	isync
	220
	221	/*
	222	* Set configuration of the Boot/CS0, the SRAM window does not have a
	223	* config register so no params can be set for it
	224	*/
6d0f6bcf JCPV	225	lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
6d0f6bcf JCPV	226	ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
8993e54b	227
6d0f6bcf JCPV	228	lis r4, CONFIG_SYS_CS0_CFG@h
6d0f6bcf JCPV	229	ori r4, r4, CONFIG_SYS_CS0_CFG@l
b1b54e35	230	stw r4, CS0_CONFIG(r3)
8993e54b RJ	231
	232	/* Master enable all CS's */
	233	lis r4, CS_CTRL_ME@h
	234	ori r4, r4, CS_CTRL_ME@l
	235	stw r4, CS_CTRL(r3)
	236
6d0f6bcf JCPV	237	lis r4, (CONFIG_SYS_MONITOR_BASE)@h
6d0f6bcf JCPV	238	ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
8993e54b RJ	239	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	240	mtlr r5
	241	blr
	242
	243	in_flash:
6d0f6bcf JCPV	244	lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
6d0f6bcf JCPV	245	ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
8993e54b RJ	246
	247	li r0, 0 /* Make room for stack frame header and */
	248	stwu r0, -4(r1) /* clear final stack frame so that */
	249	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	250
	251	/* let the C-code set up the rest */
	252	/* */
	253	/* Be careful to keep code relocatable & stack humble */
	254	/------------------------------------------------------/
	255
	256	GET_GOT /* initialize GOT access */
	257
	258	/* r3: IMMR */
6d0f6bcf	259	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	260	/* run low-level CPU init code (in Flash) */
	261	bl cpu_init_f
	262
8993e54b RJ	263	/* run 1st part of board init code (in Flash) */
	264	bl board_init_f
	265
	266	/* NOTREACHED - board_init_f() does not return */
	267
	268	/*
	269	* This code finishes saving the registers to the exception frame
	270	* and jumps to the appropriate handler for the exception.
	271	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	272	*/
	273	.globl transfer_to_handler
	274	transfer_to_handler:
	275	stw r22,_NIP(r21)
	276	lis r22,MSR_POW@h
	277	andc r23,r23,r22
	278	stw r23,_MSR(r21)
	279	SAVE_GPR(7, r21)
	280	SAVE_4GPRS(8, r21)
	281	SAVE_8GPRS(12, r21)
	282	SAVE_8GPRS(24, r21)
	283	mflr r23
	284	andi. r24,r23,0x3f00 /* get vector offset */
	285	stw r24,TRAP(r21)
	286	li r22,0
	287	stw r22,RESULT(r21)
	288	lwz r24,0(r23) /* virtual address of handler */
	289	lwz r23,4(r23) /* where to go when done */
	290	mtspr SRR0,r24
	291	mtspr SRR1,r20
	292	mtlr r23
	293	SYNC
	294	rfi /* jump to handler, enable MMU */
	295
	296	int_return:
	297	mfmsr r28 /* Disable interrupts */
	298	li r4,0
	299	ori r4,r4,MSR_EE
	300	andc r28,r28,r4
	301	SYNC /* Some chip revs need this... */
	302	mtmsr r28
	303	SYNC
	304	lwz r2,_CTR(r1)
	305	lwz r0,_LINK(r1)
	306	mtctr r2
	307	mtlr r0
	308	lwz r2,_XER(r1)
	309	lwz r0,_CCR(r1)
	310	mtspr XER,r2
	311	mtcrf 0xFF,r0
	312	REST_10GPRS(3, r1)
	313	REST_10GPRS(13, r1)
	314	REST_8GPRS(23, r1)
	315	REST_GPR(31, r1)
	316	lwz r2,_NIP(r1) /* Restore environment */
	317	lwz r0,_MSR(r1)
	318	mtspr SRR0,r2
	319	mtspr SRR1,r0
	320	lwz r0,GPR0(r1)
	321	lwz r2,GPR2(r1)
	322	lwz r1,GPR1(r1)
	323	SYNC
	324	rfi
	325
	326	/*
327	* This code initialises the machine, it expects original MSR contents to be in r5.
328	*/
329	cpu_early_init:
330	/* Initialize machine status; enable machine check interrupt */
331	/-----------------------------------------------------------/
332
333	li r3, MSR_KERNEL /* Set ME and RI flags */
334	rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
335	#ifdef DEBUG
336	rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
337	#endif
338	mtmsr r3
339	SYNC
340	mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
341
6d0f6bcf	342	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	343
	344	#if defined(CONFIG_WATCHDOG)
	345	/* Initialise the watchdog and reset it */
	346	/--------------------------------------/
6d0f6bcf	347	lis r4, CONFIG_SYS_WATCHDOG_VALUE
8993e54b RJ	348	ori r4, r4, (SWCRR_SWEN \| SWCRR_SWRI \| SWCRR_SWPR)
	349	stw r4, SWCRR(r3)
	350
	351	/* reset */
	352	li r4, 0x556C
	353	sth r4, SWSRR@l(r3)
	354	li r4, 0x0
	355	ori r4, r4, 0xAA39
	356	sth r4, SWSRR@l(r3)
	357	#else
	358	/* Disable the watchdog */
	359	/----------------------/
	360	lwz r4, SWCRR(r3)
	361	/*
	362	* Check to see if it's enabled for disabling: once disabled by s/w
	363	* it's not possible to re-enable it
	364	*/
	365	andi. r4, r4, 0x4
	366	beq 1f
	367	xor r4, r4, r4
	368	stw r4, SWCRR(r3)
	369	1:
	370	#endif /* CONFIG_WATCHDOG */
	371
	372	/* Initialize the Hardware Implementation-dependent Registers */
	373	/* HID0 also contains cache control */
	374	/------------------------------------------------------/
6d0f6bcf JCPV	375	lis r3, CONFIG_SYS_HID0_INIT@h
6d0f6bcf JCPV	376	ori r3, r3, CONFIG_SYS_HID0_INIT@l
8993e54b RJ	377	SYNC
	378	mtspr HID0, r3
	379
6d0f6bcf JCPV	380	lis r3, CONFIG_SYS_HID0_FINAL@h
6d0f6bcf JCPV	381	ori r3, r3, CONFIG_SYS_HID0_FINAL@l
8993e54b RJ	382	SYNC
	383	mtspr HID0, r3
	384
6d0f6bcf JCPV	385	lis r3, CONFIG_SYS_HID2@h
6d0f6bcf JCPV	386	ori r3, r3, CONFIG_SYS_HID2@l
8993e54b RJ	387	SYNC
	388	mtspr HID2, r3
	389	sync
	390	blr
	391
	392
	393	/* Cache functions.
	394	*
	395	* Note: requires that all cache bits in
	396	* HID0 are in the low half word.
	397	*/
	398	.globl icache_enable
	399	icache_enable:
	400	mfspr r3, HID0
	401	ori r3, r3, HID0_ICE
	402	lis r4, 0
	403	ori r4, r4, HID0_ILOCK
	404	andc r3, r3, r4
	405	ori r4, r3, HID0_ICFI
	406	isync
	407	mtspr HID0, r4 /* sets enable and invalidate, clears lock */
	408	isync
	409	mtspr HID0, r3 /* clears invalidate */
	410	blr
	411
	412	.globl icache_disable
	413	icache_disable:
	414	mfspr r3, HID0
	415	lis r4, 0
	416	ori r4, r4, HID0_ICE\|HID0_ILOCK
	417	andc r3, r3, r4
	418	ori r4, r3, HID0_ICFI
	419	isync
	420	mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
	421	isync
	422	mtspr HID0, r3 /* clears invalidate */
	423	blr
	424
	425	.globl icache_status
	426	icache_status:
	427	mfspr r3, HID0
	428	rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	429	blr
	430
	431	.globl dcache_enable
	432	dcache_enable:
	433	mfspr r3, HID0
	434	li r5, HID0_DCFI\|HID0_DLOCK
	435	andc r3, r3, r5
	436	mtspr HID0, r3 /* no invalidate, unlock */
	437	ori r3, r3, HID0_DCE
	438	ori r5, r3, HID0_DCFI
	439	mtspr HID0, r5 /* enable + invalidate */
	440	mtspr HID0, r3 /* enable */
	441	sync
	442	blr
	443
	444	.globl dcache_disable
	445	dcache_disable:
	446	mfspr r3, HID0
	447	lis r4, 0
	448	ori r4, r4, HID0_DCE\|HID0_DLOCK
	449	andc r3, r3, r4
	450	ori r4, r3, HID0_DCI
451	sync
452	mtspr HID0, r4 /* sets invalidate, clears enable and lock */
453	sync
454	mtspr HID0, r3 /* clears invalidate */
455	blr
456
457	.globl dcache_status
458	dcache_status:
459	mfspr r3, HID0
460	rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
461	blr
462
463	.globl get_pvr
464	get_pvr:
465	mfspr r3, PVR
466	blr
467
8993e54b RJ	468	/-------------------------------------------------------------------/
	469
	470	/*
	471	* void relocate_code (addr_sp, gd, addr_moni)
	472	*
	473	* This "function" does not return, instead it continues in RAM
	474	* after relocating the monitor code.
	475	*
	476	* r3 = dest
	477	* r4 = src
	478	* r5 = length in bytes
	479	* r6 = cachelinesize
	480	*/
	481	.globl relocate_code
	482	relocate_code:
	483	mr r1, r3 /* Set new stack pointer */
	484	mr r9, r4 /* Save copy of Global Data pointer */
	485	mr r10, r5 /* Save copy of Destination Address */
	486
0f8aa159	487	GET_GOT
8993e54b	488	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	489	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	490	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
8993e54b RJ	491	lwz r5, GOT(__init_end)
8993e54b RJ	492	sub r5, r5, r4
6d0f6bcf	493	li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
8993e54b RJ	494
	495	/*
	496	* Fix GOT pointer:
	497	*
6d0f6bcf	498	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
8993e54b RJ	499	* + Destination Address
	500	*
	501	* Offset:
	502	*/
	503	sub r15, r10, r4
	504
	505	/* First our own GOT */
0f8aa159	506	add r12, r12, r15
8993e54b RJ	507	/* then the one used by the C code */
	508	add r30, r30, r15
	509
	510	/*
	511	* Now relocate code
	512	*/
	513	cmplw cr1,r3,r4
	514	addi r0,r5,3
	515	srwi. r0,r0,2
	516	beq cr1,4f /* In place copy is not necessary */
	517	beq 7f /* Protect against 0 count */
	518	mtctr r0
	519	bge cr1,2f
	520	la r8,-4(r4)
	521	la r7,-4(r3)
	522
	523	/* copy */
	524	1: lwzu r0,4(r8)
	525	stwu r0,4(r7)
	526	bdnz 1b
	527
	528	addi r0,r5,3
	529	srwi. r0,r0,2
	530	mtctr r0
	531	la r8,-4(r4)
	532	la r7,-4(r3)
	533
	534	/* and compare */
	535	20: lwzu r20,4(r8)
	536	lwzu r21,4(r7)
	537	xor. r22, r20, r21
	538	bne 30f
	539	bdnz 20b
	540	b 4f
	541
	542	/* compare failed */
	543	30: li r3, 0
	544	blr
	545
	546	2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	547	add r8,r4,r0
	548	add r7,r3,r0
	549	3: lwzu r0,-4(r8)
	550	stwu r0,-4(r7)
	551	bdnz 3b
	552
	553	/*
	554	* Now flush the cache: note that we must start from a cache aligned
	555	* address. Otherwise we might miss one cache line.
	556	*/
	557	4: cmpwi r6,0
	558	add r5,r3,r5
	559	beq 7f /* Always flush prefetch queue in any case */
	560	subi r0,r6,1
	561	andc r3,r3,r0
	562	mr r4,r3
	563	5: dcbst 0,r4
	564	add r4,r4,r6
	565	cmplw r4,r5
	566	blt 5b
	567	sync /* Wait for all dcbst to complete on bus */
	568	mr r4,r3
	569	6: icbi 0,r4
	570	add r4,r4,r6
571	cmplw r4,r5
572	blt 6b
573	7: sync /* Wait for all icbi to complete on bus */
574	isync
575
576	/*
577	* We are done. Do not return, instead branch to second part of board
578	* initialization, now running from RAM.
579	*/
580	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
581	mtlr r0
582	blr
583
584	in_ram:
585	/*
0f8aa159	586	* Relocation Function, r12 point to got2+0x8000
8993e54b RJ	587	*
	588	* Adjust got2 pointers, no need to check for 0, this code
	589	* already puts a few entries in the table.
	590	*/
	591	li r0,__got2_entries@sectoff@l
	592	la r3,GOT(_GOT2_TABLE_)
	593	lwz r11,GOT(_GOT2_TABLE_)
	594	mtctr r0
	595	sub r11,r3,r11
	596	addi r3,r3,-4
	597	1: lwzu r0,4(r3)
afc3ba0f JT	598	cmpwi r0,0
afc3ba0f JT	599	beq- 2f
8993e54b RJ	600	add r0,r0,r11
8993e54b RJ	601	stw r0,0(r3)
afc3ba0f	602	2: bdnz 1b
8993e54b RJ	603
	604	/*
	605	* Now adjust the fixups and the pointers to the fixups
	606	* in case we need to move ourselves again.
	607	*/
afc3ba0f	608	li r0,__fixup_entries@sectoff@l
8993e54b RJ	609	lwz r3,GOT(_FIXUP_TABLE_)
	610	cmpwi r0,0
	611	mtctr r0
	612	addi r3,r3,-4
	613	beq 4f
	614	3: lwzu r4,4(r3)
	615	lwzux r0,r4,r11
	616	add r0,r0,r11
	617	stw r10,0(r3)
	618	stw r0,0(r4)
	619	bdnz 3b
	620	4:
	621	clear_bss:
	622	/*
	623	* Now clear BSS segment
	624	*/
	625	lwz r3,GOT(__bss_start)
	626	lwz r4,GOT(_end)
	627
	628	cmplw 0, r3, r4
	629	beq 6f
	630
	631	li r0, 0
	632	5:
	633	stw r0, 0(r3)
	634	addi r3, r3, 4
	635	cmplw 0, r3, r4
	636	bne 5b
	637	6:
	638	mr r3, r9 /* Global Data pointer */
	639	mr r4, r10 /* Destination Address */
	640	bl board_init_r
	641
	642	/*
	643	* Copy exception vector code to low memory
	644	*
	645	* r3: dest_addr
	646	* r7: source address, r8: end address, r9: target address
	647	*/
	648	.globl trap_init
	649	trap_init:
0f8aa159 JT	650	mflr r4 /* save link register */
0f8aa159 JT	651	GET_GOT
8993e54b RJ	652	lwz r7, GOT(_start)
	653	lwz r8, GOT(_end_of_vectors)
	654
	655	li r9, 0x100 /* reset vector at 0x100 */
	656
	657	cmplw 0, r7, r8
	658	bgelr /* return if r7>=r8 - just in case */
8993e54b RJ	659	1:
	660	lwz r0, 0(r7)
	661	stw r0, 0(r9)
	662	addi r7, r7, 4
	663	addi r9, r9, 4
	664	cmplw 0, r7, r8
	665	bne 1b
	666
	667	/*
	668	* relocate `hdlr' and `int_return' entries
	669	*/
	670	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	671	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	672	2:
	673	bl trap_reloc
	674	addi r7, r7, 0x100 /* next exception vector */
	675	cmplw 0, r7, r8
	676	blt 2b
	677
	678	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	679	bl trap_reloc
	680
	681	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	682	bl trap_reloc
	683
	684	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	685	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	686	3:
	687	bl trap_reloc
	688	addi r7, r7, 0x100 /* next exception vector */
	689	cmplw 0, r7, r8
	690	blt 3b
	691
	692	li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	693	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	694	4:
	695	bl trap_reloc
	696	addi r7, r7, 0x100 /* next exception vector */
	697	cmplw 0, r7, r8
	698	blt 4b
	699
	700	mfmsr r3 /* now that the vectors have */
	701	lis r7, MSR_IP@h /* relocated into low memory */
	702	ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
	703	andc r3, r3, r7 /* (if it was on) */
	704	SYNC /* Some chip revs need this... */
	705	mtmsr r3
	706	SYNC
	707
	708	mtlr r4 /* restore link register */
	709	blr