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0db5bca8 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Martin Winistoerfer, martinwinistoerfer@gmx.ch. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0db5bca8 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * File: serial.c | |
8bde7f77 WD |
10 | * |
11 | * Discription: Serial interface driver for SCI1 and SCI2. | |
53677ef1 WD |
12 | * Since this code will be called from ROM use |
13 | * only non-static local variables. | |
0db5bca8 WD |
14 | * |
15 | */ | |
16 | ||
17 | #include <common.h> | |
18 | #include <watchdog.h> | |
19 | #include <command.h> | |
20 | #include <mpc5xx.h> | |
b57c6528 MV |
21 | #include <serial.h> |
22 | #include <linux/compiler.h> | |
0db5bca8 | 23 | |
d87080b7 | 24 | DECLARE_GLOBAL_DATA_PTR; |
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25 | |
26 | /* | |
b57c6528 | 27 | * Local functions |
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28 | */ |
29 | ||
b57c6528 MV |
30 | static int ready_to_send(void) |
31 | { | |
32 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; | |
33 | volatile short status; | |
34 | ||
35 | do { | |
36 | #if defined(CONFIG_5xx_CONS_SCI1) | |
37 | status = immr->im_qsmcm.qsmcm_sc1sr; | |
38 | #else | |
39 | status = immr->im_qsmcm.qsmcm_sc2sr; | |
40 | #endif | |
41 | ||
42 | #if defined(CONFIG_WATCHDOG) | |
43 | reset_5xx_watchdog (immr); | |
44 | #endif | |
45 | } while ((status & SCI_TDRE) == 0); | |
46 | return 1; | |
47 | ||
48 | } | |
0db5bca8 WD |
49 | |
50 | /* | |
51 | * Minimal global serial functions needed to use one of the SCI modules. | |
52 | */ | |
53 | ||
b57c6528 | 54 | static int mpc5xx_serial_init(void) |
0db5bca8 | 55 | { |
6d0f6bcf | 56 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
0db5bca8 WD |
57 | |
58 | serial_setbrg(); | |
59 | ||
60 | #if defined(CONFIG_5xx_CONS_SCI1) | |
61 | /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */ | |
62 | immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10; | |
8bde7f77 | 63 | immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE; |
0db5bca8 | 64 | #else |
8bde7f77 | 65 | immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10; |
0db5bca8 WD |
66 | immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE; |
67 | #endif | |
68 | return 0; | |
69 | } | |
70 | ||
b57c6528 | 71 | static void mpc5xx_serial_putc(const char c) |
8bde7f77 | 72 | { |
6d0f6bcf | 73 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
8bde7f77 | 74 | |
0db5bca8 WD |
75 | /* Test for completition */ |
76 | if(ready_to_send()) { | |
77 | #if defined(CONFIG_5xx_CONS_SCI1) | |
8bde7f77 | 78 | immr->im_qsmcm.qsmcm_sc1dr = (short)c; |
0db5bca8 WD |
79 | #else |
80 | immr->im_qsmcm.qsmcm_sc2dr = (short)c; | |
8bde7f77 | 81 | #endif |
0db5bca8 WD |
82 | if(c == '\n') { |
83 | if(ready_to_send()); | |
84 | #if defined(CONFIG_5xx_CONS_SCI1) | |
85 | immr->im_qsmcm.qsmcm_sc1dr = (short)'\r'; | |
86 | #else | |
87 | immr->im_qsmcm.qsmcm_sc2dr = (short)'\r'; | |
88 | #endif | |
89 | } | |
90 | } | |
91 | } | |
92 | ||
b57c6528 | 93 | static int mpc5xx_serial_getc(void) |
8bde7f77 | 94 | { |
6d0f6bcf | 95 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
0db5bca8 WD |
96 | volatile short status; |
97 | unsigned char tmp; | |
8bde7f77 | 98 | |
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99 | /* New data ? */ |
100 | do { | |
101 | #if defined(CONFIG_5xx_CONS_SCI1) | |
8bde7f77 | 102 | status = immr->im_qsmcm.qsmcm_sc1sr; |
0db5bca8 WD |
103 | #else |
104 | status = immr->im_qsmcm.qsmcm_sc2sr; | |
105 | #endif | |
106 | ||
107 | #if defined(CONFIG_WATCHDOG) | |
8bde7f77 | 108 | reset_5xx_watchdog (immr); |
0db5bca8 | 109 | #endif |
8bde7f77 WD |
110 | } while ((status & SCI_RDRF) == 0); |
111 | ||
0db5bca8 WD |
112 | /* Read data */ |
113 | #if defined(CONFIG_5xx_CONS_SCI1) | |
8bde7f77 | 114 | tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK); |
0db5bca8 WD |
115 | #else |
116 | tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK); | |
117 | #endif | |
118 | return tmp; | |
119 | } | |
120 | ||
b57c6528 | 121 | static int mpc5xx_serial_tstc(void) |
0db5bca8 | 122 | { |
6d0f6bcf | 123 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
8bde7f77 | 124 | short status; |
0db5bca8 WD |
125 | |
126 | /* New data character ? */ | |
127 | #if defined(CONFIG_5xx_CONS_SCI1) | |
8bde7f77 | 128 | status = immr->im_qsmcm.qsmcm_sc1sr; |
0db5bca8 WD |
129 | #else |
130 | status = immr->im_qsmcm.qsmcm_sc2sr; | |
131 | #endif | |
8bde7f77 | 132 | return (status & SCI_RDRF); |
0db5bca8 WD |
133 | } |
134 | ||
b57c6528 | 135 | static void mpc5xx_serial_setbrg(void) |
0db5bca8 | 136 | { |
6d0f6bcf | 137 | volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
0db5bca8 WD |
138 | short scxbr; |
139 | ||
140 | /* Set baudrate */ | |
141 | scxbr = (gd->cpu_clk / (32 * gd->baudrate)); | |
142 | #if defined(CONFIG_5xx_CONS_SCI1) | |
8bde7f77 | 143 | immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK); |
0db5bca8 WD |
144 | #else |
145 | immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK); | |
146 | #endif | |
147 | } | |
148 | ||
b57c6528 MV |
149 | static struct serial_device mpc5xx_serial_drv = { |
150 | .name = "mpc5xx_serial", | |
151 | .start = mpc5xx_serial_init, | |
152 | .stop = NULL, | |
153 | .setbrg = mpc5xx_serial_setbrg, | |
154 | .putc = mpc5xx_serial_putc, | |
ec3fd689 | 155 | .puts = default_serial_puts, |
b57c6528 MV |
156 | .getc = mpc5xx_serial_getc, |
157 | .tstc = mpc5xx_serial_tstc, | |
158 | }; | |
159 | ||
160 | void mpc5xx_serial_initialize(void) | |
0db5bca8 | 161 | { |
b57c6528 MV |
162 | serial_register(&mpc5xx_serial_drv); |
163 | } | |
0db5bca8 | 164 | |
b57c6528 MV |
165 | __weak struct serial_device *default_serial_console(void) |
166 | { | |
167 | return &mpc5xx_serial_drv; | |
168 | } |