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1 | /********************************************************************* |
2 | * mpc8240epic.h - EPIC module of the MPC8240 micro-controller | |
3 | * | |
4 | * Copyrigh 1999 Motorola Inc. | |
5 | * | |
6 | * Modification History: | |
7 | * ===================== | |
8 | * 01a,04Feb99,My Created. | |
9 | * 15Nov200, robt -modified to use in U-Boot | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef __INCEPICh | |
14 | #define __INCEPICh | |
15 | ||
16 | #define ULONG unsigned long | |
17 | #define MAXVEC 20 | |
18 | #define MAXIRQ 5 /* IRQs */ | |
19 | #define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ | |
20 | ||
21 | /* EPIC register addresses */ | |
22 | ||
23 | #define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ | |
24 | #define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ | |
25 | #define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ | |
26 | #define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ | |
27 | #define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ | |
28 | #define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ | |
29 | #define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ | |
30 | #define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ | |
31 | ||
32 | #define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ | |
33 | #define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ | |
34 | #define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ | |
35 | #define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ | |
36 | ||
37 | #define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ | |
38 | #define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ | |
39 | #define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ | |
40 | #define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ | |
41 | ||
42 | #define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ | |
43 | #define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ | |
44 | #define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ | |
45 | #define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ | |
46 | ||
47 | #define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ | |
48 | #define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ | |
49 | #define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ | |
50 | #define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ | |
51 | ||
52 | #define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ | |
53 | #define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ | |
54 | #define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ | |
55 | #define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ | |
56 | #define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ | |
57 | #define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ | |
58 | #define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ | |
59 | #define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ | |
60 | #define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ | |
61 | #define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ | |
62 | ||
63 | #define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ | |
64 | #define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ | |
65 | #define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ | |
66 | #define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ | |
67 | #define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ | |
68 | #define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ | |
69 | #define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ | |
70 | #define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ | |
71 | #define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ | |
72 | #define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ | |
73 | ||
74 | #define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ | |
75 | #define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ | |
76 | #define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ | |
77 | #define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ | |
78 | #define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ | |
79 | #define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ | |
80 | #define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ | |
81 | #define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ | |
82 | #define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ | |
83 | #define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ | |
84 | ||
85 | #define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ | |
86 | #define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ | |
87 | #define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ | |
88 | #define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ | |
89 | #define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ | |
90 | #define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ | |
91 | #define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ | |
92 | #define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ | |
93 | #define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ | |
94 | #define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ | |
95 | #define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ | |
96 | #define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ | |
97 | ||
98 | #define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ | |
99 | #define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ | |
100 | #define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ | |
101 | #define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ | |
102 | #define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ | |
103 | #define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ | |
104 | #define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ | |
105 | #define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ | |
106 | ||
107 | #define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ | |
108 | #define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ | |
109 | #define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ | |
110 | ||
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111 | #define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */ |
112 | #define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */ | |
113 | ||
e2211743 WD |
114 | /* Error code */ |
115 | ||
116 | #define OK 0 | |
117 | #define ERROR -1 | |
118 | ||
119 | /* function prototypes */ | |
120 | ||
121 | void epicVendorId( unsigned int *step, | |
122 | unsigned int *devId, | |
123 | unsigned int *venId | |
124 | ); | |
125 | void epicFeatures( unsigned int *noIRQs, | |
8bde7f77 | 126 | unsigned int *noCPUs, |
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127 | unsigned int *VerId ); |
128 | extern void epicInit( unsigned int IRQType, unsigned int clkRatio); | |
129 | ULONG sysEUMBBARRead ( ULONG regNum ); | |
130 | void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); | |
131 | extern void epicTmFrequencySet( unsigned int frq ); | |
132 | extern unsigned int epicTmFrequencyGet(void); | |
133 | extern unsigned int epicTmBaseSet( ULONG srcAddr, | |
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134 | unsigned int cnt, |
135 | unsigned int inhibit ); | |
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136 | extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); |
137 | extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); | |
138 | extern unsigned int epicTmInhibit( unsigned int timer ); | |
139 | extern unsigned int epicTmEnable( ULONG srcAdr ); | |
140 | extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ | |
141 | extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ | |
142 | extern unsigned char epicIntTaskGet(void); | |
143 | extern void epicIntTaskSet( unsigned char val ); | |
144 | extern unsigned int epicIntAck(void); | |
145 | extern void epicSprSet( unsigned int eumbbar, unsigned char ); | |
146 | extern void epicConfigGet( unsigned int *clkRatio, | |
8bde7f77 | 147 | unsigned int *serEnable ); |
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148 | extern void SrcVecTableInit(void); |
149 | extern unsigned int epicModeGet(void); | |
150 | extern void epicIntEnable(int Vect); | |
151 | extern void epicIntDisable(int Vect); | |
152 | extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); | |
153 | extern unsigned int epicIntAck(void); | |
154 | extern void epicEOI(void); | |
155 | extern int epicCurTaskPrioSet(int Vect); | |
156 | ||
157 | struct SrcVecTable | |
158 | { | |
159 | ULONG srcAddr; | |
160 | char srcName[40]; | |
161 | }; | |
162 | ||
163 | #endif /* EPIC_H */ |