]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
f046ccd1 | 2 | /* |
03051c3d | 3 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
f046ccd1 EL |
4 | */ |
5 | ||
6 | /* | |
7 | * CPU specific code for the MPC83xx family. | |
8 | * | |
9 | * Derived from the MPC8260 and MPC85xx. | |
10 | */ | |
11 | ||
d678a59d | 12 | #include <common.h> |
30c7c434 | 13 | #include <cpu_func.h> |
36bf446b | 14 | #include <irq_func.h> |
90526e9f | 15 | #include <net.h> |
049f8d6f | 16 | #include <time.h> |
2189d5f1 | 17 | #include <vsprintf.h> |
f046ccd1 EL |
18 | #include <watchdog.h> |
19 | #include <command.h> | |
20 | #include <mpc83xx.h> | |
401d1c4f | 21 | #include <asm/global_data.h> |
f046ccd1 | 22 | #include <asm/processor.h> |
c05ed00a | 23 | #include <linux/delay.h> |
b08c8c48 | 24 | #include <linux/libfdt.h> |
75b9d4ae | 25 | #include <tsec.h> |
0e8454e9 | 26 | #include <netdev.h> |
e1ac387f | 27 | #include <fsl_esdhc.h> |
9403fc41 | 28 | #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X) |
38d67a4e | 29 | #include <linux/immap_qe.h> |
f70fd13e HS |
30 | #include <asm/io.h> |
31 | #endif | |
f046ccd1 | 32 | |
d87080b7 WD |
33 | DECLARE_GLOBAL_DATA_PTR; |
34 | ||
19fbdca4 | 35 | #ifndef CONFIG_CPU_MPC83XX |
f046ccd1 EL |
36 | int checkcpu(void) |
37 | { | |
5f820439 | 38 | volatile immap_t *immr; |
f046ccd1 EL |
39 | ulong clock = gd->cpu_clk; |
40 | u32 pvr = get_pvr(); | |
5f820439 | 41 | u32 spridr; |
f046ccd1 | 42 | char buf[32]; |
d891ab95 | 43 | int ret; |
e5c4ade4 KP |
44 | int i; |
45 | ||
e5c4ade4 KP |
46 | const struct cpu_type { |
47 | char name[15]; | |
48 | u32 partid; | |
49 | } cpu_type_list [] = { | |
7c619ddc | 50 | CPU_TYPE_ENTRY(8308), |
a88731a6 | 51 | CPU_TYPE_ENTRY(8309), |
e5c4ade4 KP |
52 | CPU_TYPE_ENTRY(8311), |
53 | CPU_TYPE_ENTRY(8313), | |
54 | CPU_TYPE_ENTRY(8314), | |
55 | CPU_TYPE_ENTRY(8315), | |
56 | CPU_TYPE_ENTRY(8321), | |
57 | CPU_TYPE_ENTRY(8323), | |
58 | CPU_TYPE_ENTRY(8343), | |
59 | CPU_TYPE_ENTRY(8347_TBGA_), | |
60 | CPU_TYPE_ENTRY(8347_PBGA_), | |
61 | CPU_TYPE_ENTRY(8349), | |
62 | CPU_TYPE_ENTRY(8358_TBGA_), | |
63 | CPU_TYPE_ENTRY(8358_PBGA_), | |
64 | CPU_TYPE_ENTRY(8360), | |
65 | CPU_TYPE_ENTRY(8377), | |
66 | CPU_TYPE_ENTRY(8378), | |
67 | CPU_TYPE_ENTRY(8379), | |
68 | }; | |
f046ccd1 | 69 | |
6d0f6bcf | 70 | immr = (immap_t *)CONFIG_SYS_IMMR; |
5f820439 | 71 | |
d891ab95 SG |
72 | ret = prt_83xx_rsr(); |
73 | if (ret) | |
74 | return ret; | |
75 | ||
54b2d434 | 76 | puts("CPU: "); |
95e7ef89 SW |
77 | |
78 | switch (pvr & 0xffff0000) { | |
79 | case PVR_E300C1: | |
80 | printf("e300c1, "); | |
81 | break; | |
82 | ||
83 | case PVR_E300C2: | |
84 | printf("e300c2, "); | |
85 | break; | |
86 | ||
87 | case PVR_E300C3: | |
88 | printf("e300c3, "); | |
89 | break; | |
90 | ||
03051c3d DL |
91 | case PVR_E300C4: |
92 | printf("e300c4, "); | |
93 | break; | |
94 | ||
95e7ef89 SW |
95 | default: |
96 | printf("Unknown core, "); | |
f046ccd1 EL |
97 | } |
98 | ||
5f820439 | 99 | spridr = immr->sysconf.spridr; |
6902df56 | 100 | |
e5c4ade4 KP |
101 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) |
102 | if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { | |
103 | puts("MPC"); | |
104 | puts(cpu_type_list[i].name); | |
105 | if (IS_E_PROCESSOR(spridr)) | |
106 | puts("E"); | |
dfe812c7 KP |
107 | if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || |
108 | SPR_FAMILY(spridr) == SPR_836X_FAMILY) && | |
109 | REVID_MAJOR(spridr) >= 2) | |
e5c4ade4 KP |
110 | puts("A"); |
111 | printf(", Rev: %d.%d", REVID_MAJOR(spridr), | |
112 | REVID_MINOR(spridr)); | |
113 | break; | |
114 | } | |
115 | ||
116 | if (i == ARRAY_SIZE(cpu_type_list)) | |
117 | printf("(SPRIDR %08x unknown), ", spridr); | |
118 | ||
119 | printf(" at %s MHz, ", strmhz(buf, clock)); | |
120 | ||
c6731fe2 | 121 | printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk)); |
54b2d434 | 122 | |
f046ccd1 EL |
123 | return 0; |
124 | } | |
19fbdca4 | 125 | #endif |
f046ccd1 | 126 | |
76fdad1f | 127 | #ifndef CONFIG_SYSRESET |
09140113 | 128 | int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) |
f046ccd1 | 129 | { |
07a2505f | 130 | ulong msr; |
6d0f6bcf | 131 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
f046ccd1 | 132 | |
4c006dd1 MZ |
133 | puts("Resetting the board.\n"); |
134 | ||
f046ccd1 | 135 | /* Interrupts and MMU off */ |
5c229985 MS |
136 | msr = mfmsr(); |
137 | msr &= ~(MSR_EE | MSR_IR | MSR_DR); | |
138 | mtmsr(msr); | |
f046ccd1 EL |
139 | |
140 | /* enable Reset Control Reg */ | |
141 | immap->reset.rpr = 0x52535445; | |
5c229985 MS |
142 | sync(); |
143 | isync(); | |
f046ccd1 EL |
144 | |
145 | /* confirm Reset Control Reg is enabled */ | |
5c229985 MS |
146 | while(!((immap->reset.rcer) & RCER_CRE)) |
147 | ; | |
f046ccd1 | 148 | |
f046ccd1 EL |
149 | udelay(200); |
150 | ||
151 | /* perform reset, only one bit */ | |
07a2505f WD |
152 | immap->reset.rcr = RCR_SWHR; |
153 | ||
f046ccd1 EL |
154 | return 1; |
155 | } | |
76fdad1f | 156 | #endif |
f046ccd1 EL |
157 | |
158 | /* | |
159 | * Get timebase clock frequency (like cpu_clk in Hz) | |
160 | */ | |
2c21749d | 161 | #ifndef CONFIG_TIMER |
f046ccd1 EL |
162 | unsigned long get_tbclk(void) |
163 | { | |
63a7578e | 164 | return (gd->bus_clk + 3L) / 4L; |
f046ccd1 | 165 | } |
2c21749d | 166 | #endif |
f046ccd1 | 167 | |
0fd79138 | 168 | #if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT) |
f046ccd1 EL |
169 | void watchdog_reset (void) |
170 | { | |
2ad6b513 TT |
171 | int re_enable = disable_interrupts(); |
172 | ||
173 | /* Reset the 83xx watchdog */ | |
6d0f6bcf | 174 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
2ad6b513 TT |
175 | immr->wdt.swsrr = 0x556c; |
176 | immr->wdt.swsrr = 0xaa39; | |
177 | ||
178 | if (re_enable) | |
9d3915b2 | 179 | enable_interrupts(); |
f046ccd1 | 180 | } |
2ad6b513 | 181 | #endif |
62ec6418 | 182 | |
e1ac387f AF |
183 | /* |
184 | * Initializes on-chip MMC controllers. | |
185 | * to override, implement board_mmc_init() | |
186 | */ | |
b75d8dc5 | 187 | int cpu_mmc_init(struct bd_info *bis) |
e1ac387f AF |
188 | { |
189 | #ifdef CONFIG_FSL_ESDHC | |
190 | return fsl_esdhc_mmc_init(bis); | |
191 | #else | |
192 | return 0; | |
193 | #endif | |
194 | } | |
1e718f43 MS |
195 | |
196 | void ppcDWstore(unsigned int *addr, unsigned int *value) | |
197 | { | |
198 | asm("lfd 1, 0(%1)\n\t" | |
199 | "stfd 1, 0(%0)" | |
200 | : | |
201 | : "r" (addr), "r" (value) | |
202 | : "memory"); | |
203 | } | |
204 | ||
205 | void ppcDWload(unsigned int *addr, unsigned int *ret) | |
206 | { | |
207 | asm("lfd 1, 0(%0)\n\t" | |
208 | "stfd 1, 0(%1)" | |
209 | : | |
210 | : "r" (addr), "r" (ret) | |
211 | : "memory"); | |
212 | } |