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1 | /* |
2 | * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. | |
3 | * Copyright (C) 2008-2009 MontaVista Software, Inc. | |
4 | * | |
5 | * Authors: Tony Li <tony.li@freescale.com> | |
6 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <pci.h> | |
26 | #include <mpc83xx.h> | |
27 | #include <asm/io.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #define PCIE_MAX_BUSES 2 | |
32 | ||
33 | #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES | |
34 | ||
35 | static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) | |
36 | { | |
37 | int bus = PCI_BUS(dev) - hose->first_busno; | |
38 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; | |
39 | pex83xx_t *pex = &immr->pciexp[bus]; | |
40 | struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; | |
41 | u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); | |
42 | u32 dev_base = bus << 24 | devfn << 16; | |
43 | ||
44 | if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) | |
45 | return -1; | |
46 | /* | |
47 | * Workaround for the HW bug: for Type 0 configure transactions the | |
48 | * PCI-E controller does not check the device number bits and just | |
49 | * assumes that the device number bits are 0. | |
50 | */ | |
51 | if (devfn & 0xf8) | |
52 | return -1; | |
53 | ||
54 | out_le32(&out_win->tarl, dev_base); | |
55 | return 0; | |
56 | } | |
57 | ||
58 | #define cfg_read(val, addr, type, op) \ | |
59 | do { *val = op((type)(addr)); } while (0) | |
60 | #define cfg_write(val, addr, type, op) \ | |
61 | do { op((type *)(addr), (val)); } while (0) | |
62 | ||
b24a99f6 AV |
63 | #define cfg_read_err(val) do { *val = -1; } while (0) |
64 | #define cfg_write_err(val) do { } while (0) | |
65 | ||
fd6646c0 AV |
66 | #define PCIE_OP(rw, size, type, op) \ |
67 | static int pcie_##rw##_config_##size(struct pci_controller *hose, \ | |
68 | pci_dev_t dev, int offset, \ | |
69 | type val) \ | |
70 | { \ | |
71 | int ret; \ | |
72 | \ | |
73 | ret = mpc83xx_pcie_remap_cfg(hose, dev); \ | |
b24a99f6 AV |
74 | if (ret) { \ |
75 | cfg_##rw##_err(val); \ | |
76 | return ret; \ | |
77 | } \ | |
fd6646c0 AV |
78 | cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ |
79 | return 0; \ | |
80 | } | |
81 | ||
82 | PCIE_OP(read, byte, u8 *, in_8) | |
83 | PCIE_OP(read, word, u16 *, in_le16) | |
84 | PCIE_OP(read, dword, u32 *, in_le32) | |
85 | PCIE_OP(write, byte, u8, out_8) | |
86 | PCIE_OP(write, word, u16, out_le16) | |
87 | PCIE_OP(write, dword, u32, out_le32) | |
88 | ||
89 | static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, | |
90 | u8 link) | |
91 | { | |
92 | extern void disable_addr_trans(void); /* start.S */ | |
93 | static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; | |
fd6646c0 AV |
94 | struct pci_controller *hose = &pcie_hose[bus]; |
95 | int i; | |
96 | ||
97 | /* | |
98 | * There are no spare BATs to remap all PCI-E windows for U-Boot, so | |
99 | * disable translations. In general, this is not great solution, and | |
100 | * that's why we don't register PCI-E hoses by default. | |
101 | */ | |
102 | disable_addr_trans(); | |
103 | ||
104 | for (i = 0; i < 2; i++, reg++) { | |
105 | if (reg->size == 0) | |
106 | break; | |
107 | ||
108 | hose->regions[i] = *reg; | |
109 | hose->region_count++; | |
110 | } | |
111 | ||
112 | i = hose->region_count++; | |
113 | hose->regions[i].bus_start = 0; | |
114 | hose->regions[i].phys_start = 0; | |
115 | hose->regions[i].size = gd->ram_size; | |
ff4e66e9 | 116 | hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; |
fd6646c0 AV |
117 | |
118 | i = hose->region_count++; | |
119 | hose->regions[i].bus_start = CONFIG_SYS_IMMR; | |
120 | hose->regions[i].phys_start = CONFIG_SYS_IMMR; | |
121 | hose->regions[i].size = 0x100000; | |
ff4e66e9 | 122 | hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; |
fd6646c0 | 123 | |
e2d72ba5 | 124 | hose->first_busno = pci_last_busno() + 1; |
fd6646c0 AV |
125 | hose->last_busno = 0xff; |
126 | ||
127 | if (bus == 0) | |
128 | hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE; | |
129 | else | |
130 | hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE; | |
131 | ||
132 | pci_set_ops(hose, | |
133 | pcie_read_config_byte, | |
134 | pcie_read_config_word, | |
135 | pcie_read_config_dword, | |
136 | pcie_write_config_byte, | |
137 | pcie_write_config_word, | |
138 | pcie_write_config_dword); | |
139 | ||
140 | if (!link) | |
141 | hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; | |
142 | ||
143 | pci_register_hose(hose); | |
144 | ||
145 | #ifdef CONFIG_PCI_SCAN_SHOW | |
146 | printf("PCI: Bus Dev VenId DevId Class Int\n"); | |
147 | #endif | |
148 | /* | |
149 | * Hose scan. | |
150 | */ | |
151 | hose->last_busno = pci_hose_scan(hose); | |
fd6646c0 AV |
152 | } |
153 | ||
154 | #else | |
155 | ||
156 | static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, | |
157 | u8 link) {} | |
158 | ||
159 | #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ | |
160 | ||
161 | static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) | |
162 | { | |
163 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; | |
164 | pex83xx_t *pex = &immr->pciexp[bus]; | |
165 | struct pex_outbound_window *out_win; | |
166 | struct pex_inbound_window *in_win; | |
167 | void *hose_cfg_base; | |
168 | unsigned int ram_sz; | |
169 | unsigned int barl; | |
170 | unsigned int tar; | |
171 | u16 reg16; | |
172 | int i; | |
173 | ||
174 | /* Enable pex csb bridge inbound & outbound transactions */ | |
175 | out_le32(&pex->bridge.pex_csb_ctrl, | |
176 | in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | | |
177 | PEX_CSB_CTRL_IBPIOE); | |
178 | ||
179 | /* Enable bridge outbound */ | |
180 | out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | | |
181 | PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE | | |
182 | PEX_CSB_OBCTRL_CFGWE); | |
183 | ||
184 | out_win = &pex->bridge.pex_outbound_win[0]; | |
185 | if (bus) { | |
186 | out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | | |
187 | CONFIG_SYS_PCIE2_CFG_SIZE); | |
188 | out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE); | |
189 | } else { | |
190 | out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | | |
191 | CONFIG_SYS_PCIE1_CFG_SIZE); | |
192 | out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE); | |
193 | } | |
194 | out_le32(&out_win->tarl, 0); | |
195 | out_le32(&out_win->tarh, 0); | |
196 | ||
197 | for (i = 0; i < 2; i++, reg++) { | |
198 | u32 ar; | |
199 | ||
200 | if (reg->size == 0) | |
201 | break; | |
202 | ||
203 | out_win = &pex->bridge.pex_outbound_win[i + 1]; | |
204 | out_le32(&out_win->bar, reg->phys_start); | |
205 | out_le32(&out_win->tarl, reg->bus_start); | |
206 | out_le32(&out_win->tarh, 0); | |
207 | ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE); | |
208 | if (reg->flags & PCI_REGION_IO) | |
209 | ar |= PEX_OWAR_TYPE_IO; | |
210 | else | |
211 | ar |= PEX_OWAR_TYPE_MEM; | |
212 | out_le32(&out_win->ar, ar); | |
213 | } | |
214 | ||
215 | out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); | |
216 | ||
217 | ram_sz = gd->ram_size; | |
218 | barl = 0; | |
219 | tar = 0; | |
220 | i = 0; | |
221 | while (ram_sz > 0) { | |
222 | in_win = &pex->bridge.pex_inbound_win[i]; | |
223 | out_le32(&in_win->barl, barl); | |
224 | out_le32(&in_win->barh, 0x0); | |
225 | out_le32(&in_win->tar, tar); | |
226 | if (ram_sz >= 0x10000000) { | |
227 | /* The maxium windows size is 256M */ | |
228 | out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | | |
229 | PEX_IWAR_TYPE_PF | 0x0FFFF000); | |
230 | barl += 0x10000000; | |
231 | tar += 0x10000000; | |
232 | ram_sz -= 0x10000000; | |
233 | } else { | |
234 | /* The UM is not clear here. | |
235 | * So, round up to even Mb boundary */ | |
236 | ||
237 | ram_sz = ram_sz >> (20 + | |
238 | ((ram_sz & 0xFFFFF) ? 1 : 0)); | |
239 | if (!(ram_sz % 2)) | |
240 | ram_sz -= 1; | |
241 | out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | | |
242 | PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000); | |
243 | ram_sz = 0; | |
244 | } | |
245 | i++; | |
246 | } | |
247 | ||
248 | in_win = &pex->bridge.pex_inbound_win[i]; | |
249 | out_le32(&in_win->barl, CONFIG_SYS_IMMR); | |
250 | out_le32(&in_win->barh, 0); | |
251 | out_le32(&in_win->tar, CONFIG_SYS_IMMR); | |
252 | out_le32(&in_win->ar, PEX_IWAR_EN | | |
253 | PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M); | |
254 | ||
255 | /* Enable the host virtual INTX interrupts */ | |
256 | out_le32(&pex->bridge.pex_int_axi_misc_enb, | |
257 | in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); | |
258 | ||
259 | /* Hose configure header is memory-mapped */ | |
260 | hose_cfg_base = (void *)pex; | |
261 | ||
262 | get_clocks(); | |
263 | /* Configure the PCIE controller core clock ratio */ | |
264 | out_le32(hose_cfg_base + PEX_GCLK_RATIO, | |
265 | (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) | |
266 | / 333); | |
267 | udelay(1000000); | |
268 | ||
269 | /* Do Type 1 bridge configuration */ | |
270 | out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0); | |
271 | out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1); | |
272 | out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255); | |
273 | ||
274 | /* | |
275 | * Write to Command register | |
276 | */ | |
277 | reg16 = in_le16(hose_cfg_base + PCI_COMMAND); | |
278 | reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | | |
279 | PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
280 | out_le16(hose_cfg_base + PCI_COMMAND, reg16); | |
281 | ||
282 | /* | |
283 | * Clear non-reserved bits in status register. | |
284 | */ | |
285 | out_le16(hose_cfg_base + PCI_STATUS, 0xffff); | |
286 | out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80); | |
287 | out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08); | |
288 | ||
289 | printf("PCIE%d: ", bus); | |
290 | ||
291 | reg16 = in_le16(hose_cfg_base + PCI_LTSSM); | |
292 | if (reg16 >= PCI_LTSSM_L0) | |
293 | printf("link\n"); | |
294 | else | |
295 | printf("No link\n"); | |
296 | ||
297 | mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); | |
298 | } | |
299 | ||
300 | /* | |
301 | * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs | |
302 | * must have been set to cover all of the requested regions. | |
303 | */ | |
304 | void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot) | |
305 | { | |
306 | int i; | |
307 | ||
308 | /* | |
309 | * Release PCI RST Output signal. | |
310 | * Power on to RST high must be at least 100 ms as per PCI spec. | |
311 | * On warm boots only 1 ms is required. | |
312 | */ | |
313 | udelay(warmboot ? 1000 : 100000); | |
314 | ||
315 | for (i = 0; i < num_buses; i++) | |
316 | mpc83xx_pcie_init_bus(i, reg[i]); | |
317 | } |