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Commit | Line | Data |
---|---|---|
dd84058d MY |
1 | menu "mpc85xx CPU" |
2 | depends on MPC85xx | |
3 | ||
4 | config SYS_CPU | |
dd84058d MY |
5 | default "mpc85xx" |
6 | ||
7 | choice | |
8 | prompt "Target select" | |
a26cd049 | 9 | optional |
dd84058d MY |
10 | |
11 | config TARGET_SBC8548 | |
12 | bool "Support sbc8548" | |
281ed4c7 | 13 | select ARCH_MPC8548 |
dd84058d MY |
14 | |
15 | config TARGET_SOCRATES | |
16 | bool "Support socrates" | |
25cb74b3 | 17 | select ARCH_MPC8544 |
dd84058d | 18 | |
45a8d117 YS |
19 | config TARGET_B4420QDS |
20 | bool "Support B4420QDS" | |
b41f192b | 21 | select ARCH_B4420 |
45a8d117 YS |
22 | select SUPPORT_SPL |
23 | select PHYS_64BIT | |
24 | ||
dd84058d MY |
25 | config TARGET_B4860QDS |
26 | bool "Support B4860QDS" | |
3006ebc3 | 27 | select ARCH_B4860 |
02627356 | 28 | select SUPPORT_SPL |
bb6b142f | 29 | select PHYS_64BIT |
dd84058d MY |
30 | |
31 | config TARGET_BSC9131RDB | |
32 | bool "Support BSC9131RDB" | |
115d60c0 | 33 | select ARCH_BSC9131 |
02627356 | 34 | select SUPPORT_SPL |
dd84058d MY |
35 | |
36 | config TARGET_BSC9132QDS | |
37 | bool "Support BSC9132QDS" | |
115d60c0 | 38 | select ARCH_BSC9132 |
02627356 | 39 | select SUPPORT_SPL |
dd84058d MY |
40 | |
41 | config TARGET_C29XPCIE | |
42 | bool "Support C29XPCIE" | |
4fd64746 | 43 | select ARCH_C29X |
02627356 | 44 | select SUPPORT_SPL |
cf6bbe4c | 45 | select SUPPORT_TPL |
bb6b142f | 46 | select PHYS_64BIT |
dd84058d MY |
47 | |
48 | config TARGET_P3041DS | |
49 | bool "Support P3041DS" | |
bb6b142f | 50 | select PHYS_64BIT |
5e5fdd2d | 51 | select ARCH_P3041 |
dd84058d MY |
52 | |
53 | config TARGET_P4080DS | |
54 | bool "Support P4080DS" | |
bb6b142f | 55 | select PHYS_64BIT |
e71372cb | 56 | select ARCH_P4080 |
dd84058d MY |
57 | |
58 | config TARGET_P5020DS | |
59 | bool "Support P5020DS" | |
bb6b142f | 60 | select PHYS_64BIT |
cefe11cd | 61 | select ARCH_P5020 |
dd84058d MY |
62 | |
63 | config TARGET_P5040DS | |
64 | bool "Support P5040DS" | |
bb6b142f | 65 | select PHYS_64BIT |
95390360 | 66 | select ARCH_P5040 |
dd84058d MY |
67 | |
68 | config TARGET_MPC8536DS | |
69 | bool "Support MPC8536DS" | |
24ad75ae | 70 | select ARCH_MPC8536 |
d26e34c4 YS |
71 | # Use DDR3 controller with DDR2 DIMMs on this board |
72 | select SYS_FSL_DDRC_GEN3 | |
dd84058d MY |
73 | |
74 | config TARGET_MPC8540ADS | |
75 | bool "Support MPC8540ADS" | |
7f825218 | 76 | select ARCH_MPC8540 |
dd84058d MY |
77 | |
78 | config TARGET_MPC8541CDS | |
79 | bool "Support MPC8541CDS" | |
3aff3082 | 80 | select ARCH_MPC8541 |
dd84058d MY |
81 | |
82 | config TARGET_MPC8544DS | |
83 | bool "Support MPC8544DS" | |
25cb74b3 | 84 | select ARCH_MPC8544 |
dd84058d MY |
85 | |
86 | config TARGET_MPC8548CDS | |
87 | bool "Support MPC8548CDS" | |
281ed4c7 | 88 | select ARCH_MPC8548 |
dd84058d MY |
89 | |
90 | config TARGET_MPC8555CDS | |
91 | bool "Support MPC8555CDS" | |
3c3d8ab5 | 92 | select ARCH_MPC8555 |
dd84058d MY |
93 | |
94 | config TARGET_MPC8560ADS | |
95 | bool "Support MPC8560ADS" | |
99d0a312 | 96 | select ARCH_MPC8560 |
dd84058d MY |
97 | |
98 | config TARGET_MPC8568MDS | |
99 | bool "Support MPC8568MDS" | |
d07c3843 | 100 | select ARCH_MPC8568 |
dd84058d MY |
101 | |
102 | config TARGET_MPC8569MDS | |
103 | bool "Support MPC8569MDS" | |
23b36a7d | 104 | select ARCH_MPC8569 |
dd84058d MY |
105 | |
106 | config TARGET_MPC8572DS | |
107 | bool "Support MPC8572DS" | |
c8f48474 | 108 | select ARCH_MPC8572 |
d26e34c4 YS |
109 | # Use DDR3 controller with DDR2 DIMMs on this board |
110 | select SYS_FSL_DDRC_GEN3 | |
dd84058d | 111 | |
7601686c YS |
112 | config TARGET_P1010RDB_PA |
113 | bool "Support P1010RDB_PA" | |
114 | select ARCH_P1010 | |
115 | select SUPPORT_SPL | |
116 | select SUPPORT_TPL | |
117 | ||
118 | config TARGET_P1010RDB_PB | |
119 | bool "Support P1010RDB_PB" | |
7d5f9f84 | 120 | select ARCH_P1010 |
02627356 | 121 | select SUPPORT_SPL |
cf6bbe4c | 122 | select SUPPORT_TPL |
dd84058d MY |
123 | |
124 | config TARGET_P1022DS | |
125 | bool "Support P1022DS" | |
feb9e25b | 126 | select ARCH_P1022 |
02627356 | 127 | select SUPPORT_SPL |
cf6bbe4c | 128 | select SUPPORT_TPL |
dd84058d MY |
129 | |
130 | config TARGET_P1023RDB | |
131 | bool "Support P1023RDB" | |
9bb1d6bc | 132 | select ARCH_P1023 |
dd84058d | 133 | |
fedae6eb YS |
134 | config TARGET_P1020MBG |
135 | bool "Support P1020MBG-PC" | |
136 | select SUPPORT_SPL | |
137 | select SUPPORT_TPL | |
484fff64 YS |
138 | select ARCH_P1020 |
139 | ||
aa14620c YS |
140 | config TARGET_P1020RDB_PC |
141 | bool "Support P1020RDB-PC" | |
142 | select SUPPORT_SPL | |
143 | select SUPPORT_TPL | |
484fff64 | 144 | select ARCH_P1020 |
aa14620c | 145 | |
f404b66c YS |
146 | config TARGET_P1020RDB_PD |
147 | bool "Support P1020RDB-PD" | |
148 | select SUPPORT_SPL | |
149 | select SUPPORT_TPL | |
484fff64 | 150 | select ARCH_P1020 |
f404b66c | 151 | |
e9bc8a8f YS |
152 | config TARGET_P1020UTM |
153 | bool "Support P1020UTM" | |
154 | select SUPPORT_SPL | |
155 | select SUPPORT_TPL | |
484fff64 | 156 | select ARCH_P1020 |
fedae6eb | 157 | |
da439db3 YS |
158 | config TARGET_P1021RDB |
159 | bool "Support P1021RDB" | |
160 | select SUPPORT_SPL | |
161 | select SUPPORT_TPL | |
a990799d | 162 | select ARCH_P1021 |
da439db3 | 163 | |
4eedabfe YS |
164 | config TARGET_P1024RDB |
165 | bool "Support P1024RDB" | |
166 | select SUPPORT_SPL | |
167 | select SUPPORT_TPL | |
52b6f13d | 168 | select ARCH_P1024 |
4eedabfe | 169 | |
b0c98b4b YS |
170 | config TARGET_P1025RDB |
171 | bool "Support P1025RDB" | |
172 | select SUPPORT_SPL | |
173 | select SUPPORT_TPL | |
4167a67d | 174 | select ARCH_P1025 |
b0c98b4b | 175 | |
8435aa77 YS |
176 | config TARGET_P2020RDB |
177 | bool "Support P2020RDB-PC" | |
178 | select SUPPORT_SPL | |
179 | select SUPPORT_TPL | |
4593637b | 180 | select ARCH_P2020 |
8435aa77 | 181 | |
dd84058d MY |
182 | config TARGET_P1_TWR |
183 | bool "Support p1_twr" | |
4167a67d | 184 | select ARCH_P1025 |
dd84058d | 185 | |
dd84058d MY |
186 | config TARGET_P2041RDB |
187 | bool "Support P2041RDB" | |
ce040c83 | 188 | select ARCH_P2041 |
bb6b142f | 189 | select PHYS_64BIT |
dd84058d MY |
190 | |
191 | config TARGET_QEMU_PPCE500 | |
192 | bool "Support qemu-ppce500" | |
10343403 | 193 | select ARCH_QEMU_E500 |
bb6b142f | 194 | select PHYS_64BIT |
dd84058d | 195 | |
6f53bd47 YS |
196 | config TARGET_T1024QDS |
197 | bool "Support T1024QDS" | |
e5d5f5a8 | 198 | select ARCH_T1024 |
aba80048 | 199 | select SUPPORT_SPL |
bb6b142f | 200 | select PHYS_64BIT |
aba80048 | 201 | |
08c75292 YS |
202 | config TARGET_T1023RDB |
203 | bool "Support T1023RDB" | |
5ff3f41d | 204 | select ARCH_T1023 |
08c75292 YS |
205 | select SUPPORT_SPL |
206 | select PHYS_64BIT | |
207 | ||
208 | config TARGET_T1024RDB | |
209 | bool "Support T1024RDB" | |
e5d5f5a8 | 210 | select ARCH_T1024 |
48c6f328 | 211 | select SUPPORT_SPL |
bb6b142f | 212 | select PHYS_64BIT |
48c6f328 | 213 | |
dd84058d MY |
214 | config TARGET_T1040QDS |
215 | bool "Support T1040QDS" | |
5d737010 | 216 | select ARCH_T1040 |
bb6b142f | 217 | select PHYS_64BIT |
dd84058d | 218 | |
95a809b9 YS |
219 | config TARGET_T1040RDB |
220 | bool "Support T1040RDB" | |
5d737010 | 221 | select ARCH_T1040 |
95a809b9 YS |
222 | select SUPPORT_SPL |
223 | select PHYS_64BIT | |
224 | ||
a016735c YS |
225 | config TARGET_T1040D4RDB |
226 | bool "Support T1040D4RDB" | |
227 | select ARCH_T1040 | |
228 | select SUPPORT_SPL | |
229 | select PHYS_64BIT | |
230 | ||
95a809b9 YS |
231 | config TARGET_T1042RDB |
232 | bool "Support T1042RDB" | |
5449c98a | 233 | select ARCH_T1042 |
02627356 | 234 | select SUPPORT_SPL |
bb6b142f | 235 | select PHYS_64BIT |
dd84058d | 236 | |
319ed24a YS |
237 | config TARGET_T1042D4RDB |
238 | bool "Support T1042D4RDB" | |
239 | select ARCH_T1042 | |
240 | select SUPPORT_SPL | |
241 | select PHYS_64BIT | |
242 | ||
55ed8ae3 YS |
243 | config TARGET_T1042RDB_PI |
244 | bool "Support T1042RDB_PI" | |
245 | select ARCH_T1042 | |
246 | select SUPPORT_SPL | |
247 | select PHYS_64BIT | |
248 | ||
638d5be0 YS |
249 | config TARGET_T2080QDS |
250 | bool "Support T2080QDS" | |
0f3d80e9 | 251 | select ARCH_T2080 |
02627356 | 252 | select SUPPORT_SPL |
bb6b142f | 253 | select PHYS_64BIT |
dd84058d | 254 | |
01671e66 YS |
255 | config TARGET_T2080RDB |
256 | bool "Support T2080RDB" | |
0f3d80e9 | 257 | select ARCH_T2080 |
02627356 | 258 | select SUPPORT_SPL |
bb6b142f | 259 | select PHYS_64BIT |
dd84058d | 260 | |
638d5be0 YS |
261 | config TARGET_T2081QDS |
262 | bool "Support T2081QDS" | |
0f3d80e9 | 263 | select ARCH_T2081 |
638d5be0 YS |
264 | select SUPPORT_SPL |
265 | select PHYS_64BIT | |
266 | ||
9c21d06c YS |
267 | config TARGET_T4160QDS |
268 | bool "Support T4160QDS" | |
652a7bbd | 269 | select ARCH_T4160 |
9c21d06c YS |
270 | select SUPPORT_SPL |
271 | select PHYS_64BIT | |
272 | ||
12ffdb3b YS |
273 | config TARGET_T4160RDB |
274 | bool "Support T4160RDB" | |
652a7bbd | 275 | select ARCH_T4160 |
12ffdb3b YS |
276 | select SUPPORT_SPL |
277 | select PHYS_64BIT | |
278 | ||
dd84058d MY |
279 | config TARGET_T4240QDS |
280 | bool "Support T4240QDS" | |
26bc57da | 281 | select ARCH_T4240 |
02627356 | 282 | select SUPPORT_SPL |
bb6b142f | 283 | select PHYS_64BIT |
dd84058d MY |
284 | |
285 | config TARGET_T4240RDB | |
286 | bool "Support T4240RDB" | |
26bc57da | 287 | select ARCH_T4240 |
373762c3 | 288 | select SUPPORT_SPL |
bb6b142f | 289 | select PHYS_64BIT |
dd84058d MY |
290 | |
291 | config TARGET_CONTROLCENTERD | |
292 | bool "Support controlcenterd" | |
feb9e25b | 293 | select ARCH_P1022 |
dd84058d MY |
294 | |
295 | config TARGET_KMP204X | |
296 | bool "Support kmp204x" | |
ce040c83 | 297 | select ARCH_P2041 |
bb6b142f | 298 | select PHYS_64BIT |
dd84058d | 299 | |
dd84058d MY |
300 | config TARGET_XPEDITE520X |
301 | bool "Support xpedite520x" | |
281ed4c7 | 302 | select ARCH_MPC8548 |
dd84058d MY |
303 | |
304 | config TARGET_XPEDITE537X | |
305 | bool "Support xpedite537x" | |
c8f48474 | 306 | select ARCH_MPC8572 |
d26e34c4 YS |
307 | # Use DDR3 controller with DDR2 DIMMs on this board |
308 | select SYS_FSL_DDRC_GEN3 | |
dd84058d MY |
309 | |
310 | config TARGET_XPEDITE550X | |
311 | bool "Support xpedite550x" | |
4593637b | 312 | select ARCH_P2020 |
dd84058d | 313 | |
8b0044ff OZ |
314 | config TARGET_UCP1020 |
315 | bool "Support uCP1020" | |
484fff64 | 316 | select ARCH_P1020 |
8b0044ff | 317 | |
22a1b99a YS |
318 | config TARGET_CYRUS_P5020 |
319 | bool "Support Varisys Cyrus P5020" | |
320 | select ARCH_P5020 | |
321 | select PHYS_64BIT | |
322 | ||
323 | config TARGET_CYRUS_P5040 | |
324 | bool "Support Varisys Cyrus P5040" | |
325 | select ARCH_P5040 | |
bb6b142f | 326 | select PHYS_64BIT |
87e29878 | 327 | |
dd84058d MY |
328 | endchoice |
329 | ||
b41f192b YS |
330 | config ARCH_B4420 |
331 | bool | |
f8dee360 | 332 | select E500MC |
05cb79a7 | 333 | select FSL_LAW |
d26e34c4 | 334 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 335 | select SYS_FSL_HAS_SEC |
90b80386 | 336 | select SYS_FSL_SEC_BE |
2c2e2c9e | 337 | select SYS_FSL_SEC_COMPAT_4 |
b41f192b | 338 | |
3006ebc3 YS |
339 | config ARCH_B4860 |
340 | bool | |
f8dee360 | 341 | select E500MC |
05cb79a7 | 342 | select FSL_LAW |
d26e34c4 | 343 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 344 | select SYS_FSL_HAS_SEC |
90b80386 | 345 | select SYS_FSL_SEC_BE |
2c2e2c9e | 346 | select SYS_FSL_SEC_COMPAT_4 |
3006ebc3 | 347 | |
115d60c0 YS |
348 | config ARCH_BSC9131 |
349 | bool | |
05cb79a7 | 350 | select FSL_LAW |
c01e4a1a | 351 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 352 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 353 | select SYS_FSL_HAS_SEC |
90b80386 | 354 | select SYS_FSL_SEC_BE |
2c2e2c9e | 355 | select SYS_FSL_SEC_COMPAT_4 |
115d60c0 YS |
356 | |
357 | config ARCH_BSC9132 | |
358 | bool | |
05cb79a7 | 359 | select FSL_LAW |
c01e4a1a | 360 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 361 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 362 | select SYS_FSL_HAS_SEC |
90b80386 | 363 | select SYS_FSL_SEC_BE |
2c2e2c9e | 364 | select SYS_FSL_SEC_COMPAT_4 |
53c95384 | 365 | select SYS_PPC_E500_USE_DEBUG_TLB |
115d60c0 | 366 | |
4fd64746 YS |
367 | config ARCH_C29X |
368 | bool | |
05cb79a7 | 369 | select FSL_LAW |
c01e4a1a | 370 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 371 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 372 | select SYS_FSL_HAS_SEC |
90b80386 | 373 | select SYS_FSL_SEC_BE |
2c2e2c9e | 374 | select SYS_FSL_SEC_COMPAT_6 |
53c95384 | 375 | select SYS_PPC_E500_USE_DEBUG_TLB |
4fd64746 | 376 | |
24ad75ae YS |
377 | config ARCH_MPC8536 |
378 | bool | |
05cb79a7 | 379 | select FSL_LAW |
d26e34c4 YS |
380 | select SYS_FSL_HAS_DDR2 |
381 | select SYS_FSL_HAS_DDR3 | |
2c2e2c9e | 382 | select SYS_FSL_HAS_SEC |
90b80386 | 383 | select SYS_FSL_SEC_BE |
2c2e2c9e | 384 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 385 | select SYS_PPC_E500_USE_DEBUG_TLB |
24ad75ae | 386 | |
7f825218 YS |
387 | config ARCH_MPC8540 |
388 | bool | |
05cb79a7 | 389 | select FSL_LAW |
d26e34c4 | 390 | select SYS_FSL_HAS_DDR1 |
7f825218 | 391 | |
3aff3082 YS |
392 | config ARCH_MPC8541 |
393 | bool | |
05cb79a7 | 394 | select FSL_LAW |
d26e34c4 | 395 | select SYS_FSL_HAS_DDR1 |
2c2e2c9e | 396 | select SYS_FSL_HAS_SEC |
90b80386 | 397 | select SYS_FSL_SEC_BE |
2c2e2c9e | 398 | select SYS_FSL_SEC_COMPAT_2 |
3aff3082 | 399 | |
25cb74b3 YS |
400 | config ARCH_MPC8544 |
401 | bool | |
05cb79a7 | 402 | select FSL_LAW |
d26e34c4 | 403 | select SYS_FSL_HAS_DDR2 |
2c2e2c9e | 404 | select SYS_FSL_HAS_SEC |
90b80386 | 405 | select SYS_FSL_SEC_BE |
2c2e2c9e | 406 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 407 | select SYS_PPC_E500_USE_DEBUG_TLB |
25cb74b3 | 408 | |
281ed4c7 YS |
409 | config ARCH_MPC8548 |
410 | bool | |
05cb79a7 | 411 | select FSL_LAW |
d26e34c4 YS |
412 | select SYS_FSL_HAS_DDR2 |
413 | select SYS_FSL_HAS_DDR1 | |
2c2e2c9e | 414 | select SYS_FSL_HAS_SEC |
90b80386 | 415 | select SYS_FSL_SEC_BE |
2c2e2c9e | 416 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 417 | select SYS_PPC_E500_USE_DEBUG_TLB |
281ed4c7 | 418 | |
3c3d8ab5 YS |
419 | config ARCH_MPC8555 |
420 | bool | |
05cb79a7 | 421 | select FSL_LAW |
d26e34c4 | 422 | select SYS_FSL_HAS_DDR1 |
2c2e2c9e | 423 | select SYS_FSL_HAS_SEC |
90b80386 | 424 | select SYS_FSL_SEC_BE |
2c2e2c9e | 425 | select SYS_FSL_SEC_COMPAT_2 |
3c3d8ab5 | 426 | |
99d0a312 YS |
427 | config ARCH_MPC8560 |
428 | bool | |
05cb79a7 | 429 | select FSL_LAW |
d26e34c4 | 430 | select SYS_FSL_HAS_DDR1 |
99d0a312 | 431 | |
d07c3843 YS |
432 | config ARCH_MPC8568 |
433 | bool | |
05cb79a7 | 434 | select FSL_LAW |
d26e34c4 | 435 | select SYS_FSL_HAS_DDR2 |
2c2e2c9e | 436 | select SYS_FSL_HAS_SEC |
90b80386 | 437 | select SYS_FSL_SEC_BE |
2c2e2c9e | 438 | select SYS_FSL_SEC_COMPAT_2 |
d07c3843 | 439 | |
23b36a7d YS |
440 | config ARCH_MPC8569 |
441 | bool | |
05cb79a7 | 442 | select FSL_LAW |
d26e34c4 | 443 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 444 | select SYS_FSL_HAS_SEC |
90b80386 | 445 | select SYS_FSL_SEC_BE |
2c2e2c9e | 446 | select SYS_FSL_SEC_COMPAT_2 |
23b36a7d | 447 | |
c8f48474 YS |
448 | config ARCH_MPC8572 |
449 | bool | |
05cb79a7 | 450 | select FSL_LAW |
d26e34c4 YS |
451 | select SYS_FSL_HAS_DDR2 |
452 | select SYS_FSL_HAS_DDR3 | |
2c2e2c9e | 453 | select SYS_FSL_HAS_SEC |
90b80386 | 454 | select SYS_FSL_SEC_BE |
2c2e2c9e | 455 | select SYS_FSL_SEC_COMPAT_2 |
d26e34c4 | 456 | select SYS_PPC_E500_USE_DEBUG_TLB |
c8f48474 | 457 | |
7d5f9f84 YS |
458 | config ARCH_P1010 |
459 | bool | |
05cb79a7 | 460 | select FSL_LAW |
c01e4a1a | 461 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 462 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 463 | select SYS_FSL_HAS_SEC |
90b80386 | 464 | select SYS_FSL_SEC_BE |
2c2e2c9e | 465 | select SYS_FSL_SEC_COMPAT_4 |
53c95384 | 466 | select SYS_PPC_E500_USE_DEBUG_TLB |
7d5f9f84 | 467 | |
1cdd96f3 YS |
468 | config ARCH_P1011 |
469 | bool | |
05cb79a7 | 470 | select FSL_LAW |
c01e4a1a | 471 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 472 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 473 | select SYS_FSL_HAS_SEC |
90b80386 | 474 | select SYS_FSL_SEC_BE |
2c2e2c9e | 475 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 476 | select SYS_PPC_E500_USE_DEBUG_TLB |
1cdd96f3 | 477 | |
484fff64 YS |
478 | config ARCH_P1020 |
479 | bool | |
05cb79a7 | 480 | select FSL_LAW |
c01e4a1a | 481 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 482 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 483 | select SYS_FSL_HAS_SEC |
90b80386 | 484 | select SYS_FSL_SEC_BE |
2c2e2c9e | 485 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 486 | select SYS_PPC_E500_USE_DEBUG_TLB |
484fff64 | 487 | |
a990799d YS |
488 | config ARCH_P1021 |
489 | bool | |
05cb79a7 | 490 | select FSL_LAW |
c01e4a1a | 491 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 492 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 493 | select SYS_FSL_HAS_SEC |
90b80386 | 494 | select SYS_FSL_SEC_BE |
2c2e2c9e | 495 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 496 | select SYS_PPC_E500_USE_DEBUG_TLB |
a990799d | 497 | |
feb9e25b YS |
498 | config ARCH_P1022 |
499 | bool | |
05cb79a7 | 500 | select FSL_LAW |
c01e4a1a | 501 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 502 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 503 | select SYS_FSL_HAS_SEC |
90b80386 | 504 | select SYS_FSL_SEC_BE |
2c2e2c9e | 505 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 506 | select SYS_PPC_E500_USE_DEBUG_TLB |
feb9e25b | 507 | |
9bb1d6bc YS |
508 | config ARCH_P1023 |
509 | bool | |
05cb79a7 | 510 | select FSL_LAW |
d26e34c4 | 511 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 512 | select SYS_FSL_HAS_SEC |
90b80386 | 513 | select SYS_FSL_SEC_BE |
2c2e2c9e | 514 | select SYS_FSL_SEC_COMPAT_4 |
9bb1d6bc | 515 | |
52b6f13d YS |
516 | config ARCH_P1024 |
517 | bool | |
05cb79a7 | 518 | select FSL_LAW |
c01e4a1a | 519 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 520 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 521 | select SYS_FSL_HAS_SEC |
90b80386 | 522 | select SYS_FSL_SEC_BE |
2c2e2c9e | 523 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 524 | select SYS_PPC_E500_USE_DEBUG_TLB |
52b6f13d | 525 | |
4167a67d YS |
526 | config ARCH_P1025 |
527 | bool | |
05cb79a7 | 528 | select FSL_LAW |
c01e4a1a | 529 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 530 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 531 | select SYS_FSL_HAS_SEC |
90b80386 | 532 | select SYS_FSL_SEC_BE |
2c2e2c9e | 533 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 534 | select SYS_PPC_E500_USE_DEBUG_TLB |
4167a67d | 535 | |
4593637b YS |
536 | config ARCH_P2020 |
537 | bool | |
05cb79a7 | 538 | select FSL_LAW |
c01e4a1a YS |
539 | select SYS_FSL_ERRATUM_ESDHC111 |
540 | select SYS_FSL_ERRATUM_ESDHC_A001 | |
d26e34c4 | 541 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 542 | select SYS_FSL_HAS_SEC |
90b80386 | 543 | select SYS_FSL_SEC_BE |
2c2e2c9e | 544 | select SYS_FSL_SEC_COMPAT_2 |
53c95384 | 545 | select SYS_PPC_E500_USE_DEBUG_TLB |
4593637b | 546 | |
ce040c83 YS |
547 | config ARCH_P2041 |
548 | bool | |
f8dee360 | 549 | select E500MC |
05cb79a7 | 550 | select FSL_LAW |
c01e4a1a | 551 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 552 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 553 | select SYS_FSL_HAS_SEC |
90b80386 | 554 | select SYS_FSL_SEC_BE |
2c2e2c9e | 555 | select SYS_FSL_SEC_COMPAT_4 |
ce040c83 | 556 | |
5e5fdd2d YS |
557 | config ARCH_P3041 |
558 | bool | |
f8dee360 | 559 | select E500MC |
05cb79a7 | 560 | select FSL_LAW |
c01e4a1a | 561 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 562 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 563 | select SYS_FSL_HAS_SEC |
90b80386 | 564 | select SYS_FSL_SEC_BE |
2c2e2c9e | 565 | select SYS_FSL_SEC_COMPAT_4 |
5e5fdd2d | 566 | |
e71372cb YS |
567 | config ARCH_P4080 |
568 | bool | |
f8dee360 | 569 | select E500MC |
05cb79a7 | 570 | select FSL_LAW |
c01e4a1a YS |
571 | select SYS_FSL_ERRATUM_ESDHC111 |
572 | select SYS_FSL_ERRATUM_ESDHC13 | |
573 | select SYS_FSL_ERRATUM_ESDHC135 | |
d26e34c4 | 574 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 575 | select SYS_FSL_HAS_SEC |
90b80386 | 576 | select SYS_FSL_SEC_BE |
2c2e2c9e | 577 | select SYS_FSL_SEC_COMPAT_4 |
e71372cb | 578 | |
cefe11cd YS |
579 | config ARCH_P5020 |
580 | bool | |
f8dee360 | 581 | select E500MC |
05cb79a7 | 582 | select FSL_LAW |
c01e4a1a | 583 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 584 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 585 | select SYS_FSL_HAS_SEC |
90b80386 | 586 | select SYS_FSL_SEC_BE |
2c2e2c9e | 587 | select SYS_FSL_SEC_COMPAT_4 |
cefe11cd | 588 | |
95390360 YS |
589 | config ARCH_P5040 |
590 | bool | |
f8dee360 | 591 | select E500MC |
05cb79a7 | 592 | select FSL_LAW |
c01e4a1a | 593 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 594 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 595 | select SYS_FSL_HAS_SEC |
90b80386 | 596 | select SYS_FSL_SEC_BE |
2c2e2c9e | 597 | select SYS_FSL_SEC_COMPAT_4 |
95390360 | 598 | |
10343403 YS |
599 | config ARCH_QEMU_E500 |
600 | bool | |
601 | ||
5ff3f41d YS |
602 | config ARCH_T1023 |
603 | bool | |
f8dee360 | 604 | select E500MC |
05cb79a7 | 605 | select FSL_LAW |
c01e4a1a | 606 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 YS |
607 | select SYS_FSL_HAS_DDR3 |
608 | select SYS_FSL_HAS_DDR4 | |
2c2e2c9e | 609 | select SYS_FSL_HAS_SEC |
90b80386 | 610 | select SYS_FSL_SEC_BE |
2c2e2c9e | 611 | select SYS_FSL_SEC_COMPAT_5 |
5ff3f41d | 612 | |
e5d5f5a8 YS |
613 | config ARCH_T1024 |
614 | bool | |
f8dee360 | 615 | select E500MC |
05cb79a7 | 616 | select FSL_LAW |
c01e4a1a | 617 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 YS |
618 | select SYS_FSL_HAS_DDR3 |
619 | select SYS_FSL_HAS_DDR4 | |
2c2e2c9e | 620 | select SYS_FSL_HAS_SEC |
90b80386 | 621 | select SYS_FSL_SEC_BE |
2c2e2c9e | 622 | select SYS_FSL_SEC_COMPAT_5 |
e5d5f5a8 | 623 | |
5d737010 YS |
624 | config ARCH_T1040 |
625 | bool | |
f8dee360 | 626 | select E500MC |
05cb79a7 | 627 | select FSL_LAW |
c01e4a1a | 628 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 YS |
629 | select SYS_FSL_HAS_DDR3 |
630 | select SYS_FSL_HAS_DDR4 | |
2c2e2c9e | 631 | select SYS_FSL_HAS_SEC |
90b80386 | 632 | select SYS_FSL_SEC_BE |
2c2e2c9e | 633 | select SYS_FSL_SEC_COMPAT_5 |
5d737010 | 634 | |
5449c98a YS |
635 | config ARCH_T1042 |
636 | bool | |
f8dee360 | 637 | select E500MC |
05cb79a7 | 638 | select FSL_LAW |
c01e4a1a | 639 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 YS |
640 | select SYS_FSL_HAS_DDR3 |
641 | select SYS_FSL_HAS_DDR4 | |
2c2e2c9e | 642 | select SYS_FSL_HAS_SEC |
90b80386 | 643 | select SYS_FSL_SEC_BE |
2c2e2c9e | 644 | select SYS_FSL_SEC_COMPAT_5 |
5449c98a | 645 | |
0f3d80e9 YS |
646 | config ARCH_T2080 |
647 | bool | |
f8dee360 | 648 | select E500MC |
05cb79a7 | 649 | select FSL_LAW |
c01e4a1a | 650 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 651 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 652 | select SYS_FSL_HAS_SEC |
90b80386 | 653 | select SYS_FSL_SEC_BE |
2c2e2c9e | 654 | select SYS_FSL_SEC_COMPAT_4 |
0f3d80e9 YS |
655 | |
656 | config ARCH_T2081 | |
657 | bool | |
f8dee360 | 658 | select E500MC |
05cb79a7 | 659 | select FSL_LAW |
c01e4a1a | 660 | select SYS_FSL_ERRATUM_ESDHC111 |
d26e34c4 | 661 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 662 | select SYS_FSL_HAS_SEC |
90b80386 | 663 | select SYS_FSL_SEC_BE |
2c2e2c9e | 664 | select SYS_FSL_SEC_COMPAT_4 |
0f3d80e9 | 665 | |
652a7bbd YS |
666 | config ARCH_T4160 |
667 | bool | |
f8dee360 | 668 | select E500MC |
05cb79a7 | 669 | select FSL_LAW |
d26e34c4 | 670 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 671 | select SYS_FSL_HAS_SEC |
90b80386 | 672 | select SYS_FSL_SEC_BE |
2c2e2c9e | 673 | select SYS_FSL_SEC_COMPAT_4 |
652a7bbd | 674 | |
26bc57da YS |
675 | config ARCH_T4240 |
676 | bool | |
f8dee360 | 677 | select E500MC |
05cb79a7 | 678 | select FSL_LAW |
d26e34c4 | 679 | select SYS_FSL_HAS_DDR3 |
2c2e2c9e | 680 | select SYS_FSL_HAS_SEC |
90b80386 | 681 | select SYS_FSL_SEC_BE |
2c2e2c9e | 682 | select SYS_FSL_SEC_COMPAT_4 |
05cb79a7 | 683 | |
f8dee360 YS |
684 | config BOOKE |
685 | bool | |
686 | default y | |
687 | ||
688 | config E500 | |
689 | bool | |
690 | default y | |
691 | help | |
692 | Enable PowerPC E500 cores, including e500v1, e500v2, e500mc | |
693 | ||
694 | config E500MC | |
695 | bool | |
696 | help | |
697 | Enble PowerPC E500MC core | |
698 | ||
05cb79a7 YS |
699 | config FSL_LAW |
700 | bool | |
701 | help | |
702 | Use Freescale common code for Local Access Window | |
26bc57da | 703 | |
c6e6bda3 YS |
704 | config SECURE_BOOT |
705 | bool "Secure Boot" | |
706 | help | |
707 | Enable Freescale Secure Boot feature. Normally selected | |
708 | by defconfig. If unsure, do not change. | |
709 | ||
3f82b56d YS |
710 | config MAX_CPUS |
711 | int "Maximum number of CPUs permitted for MPC85xx" | |
712 | default 12 if ARCH_T4240 | |
713 | default 8 if ARCH_P4080 || \ | |
714 | ARCH_T4160 | |
715 | default 4 if ARCH_B4860 || \ | |
716 | ARCH_P2041 || \ | |
717 | ARCH_P3041 || \ | |
718 | ARCH_P5040 || \ | |
719 | ARCH_T1040 || \ | |
720 | ARCH_T1042 || \ | |
721 | ARCH_T2080 || \ | |
722 | ARCH_T2081 | |
723 | default 2 if ARCH_B4420 || \ | |
724 | ARCH_BSC9132 || \ | |
725 | ARCH_MPC8572 || \ | |
726 | ARCH_P1020 || \ | |
727 | ARCH_P1021 || \ | |
728 | ARCH_P1022 || \ | |
729 | ARCH_P1023 || \ | |
730 | ARCH_P1024 || \ | |
731 | ARCH_P1025 || \ | |
732 | ARCH_P2020 || \ | |
733 | ARCH_P5020 || \ | |
3f82b56d YS |
734 | ARCH_T1023 || \ |
735 | ARCH_T1024 | |
736 | default 1 | |
737 | help | |
738 | Set this number to the maximum number of possible CPUs in the SoC. | |
739 | SoCs may have multiple clusters with each cluster may have multiple | |
740 | ports. If some ports are reserved but higher ports are used for | |
741 | cores, count the reserved ports. This will allocate enough memory | |
742 | in spin table to properly handle all cores. | |
743 | ||
830fc1bf YS |
744 | config SYS_CCSRBAR_DEFAULT |
745 | hex "Default CCSRBAR address" | |
746 | default 0xff700000 if ARCH_BSC9131 || \ | |
747 | ARCH_BSC9132 || \ | |
748 | ARCH_C29X || \ | |
749 | ARCH_MPC8536 || \ | |
750 | ARCH_MPC8540 || \ | |
751 | ARCH_MPC8541 || \ | |
752 | ARCH_MPC8544 || \ | |
753 | ARCH_MPC8548 || \ | |
754 | ARCH_MPC8555 || \ | |
755 | ARCH_MPC8560 || \ | |
756 | ARCH_MPC8568 || \ | |
757 | ARCH_MPC8569 || \ | |
758 | ARCH_MPC8572 || \ | |
759 | ARCH_P1010 || \ | |
760 | ARCH_P1011 || \ | |
761 | ARCH_P1020 || \ | |
762 | ARCH_P1021 || \ | |
763 | ARCH_P1022 || \ | |
764 | ARCH_P1024 || \ | |
765 | ARCH_P1025 || \ | |
766 | ARCH_P2020 | |
767 | default 0xff600000 if ARCH_P1023 | |
768 | default 0xfe000000 if ARCH_B4420 || \ | |
769 | ARCH_B4860 || \ | |
770 | ARCH_P2041 || \ | |
771 | ARCH_P3041 || \ | |
772 | ARCH_P4080 || \ | |
773 | ARCH_P5020 || \ | |
774 | ARCH_P5040 || \ | |
830fc1bf YS |
775 | ARCH_T1023 || \ |
776 | ARCH_T1024 || \ | |
777 | ARCH_T1040 || \ | |
778 | ARCH_T1042 || \ | |
779 | ARCH_T2080 || \ | |
780 | ARCH_T2081 || \ | |
781 | ARCH_T4160 || \ | |
782 | ARCH_T4240 | |
783 | default 0xe0000000 if ARCH_QEMU_E500 | |
784 | help | |
785 | Default value of CCSRBAR comes from power-on-reset. It | |
786 | is fixed on each SoC. Some SoCs can have different value | |
787 | if changed by pre-boot regime. The value here must match | |
788 | the current value in SoC. If not sure, do not change. | |
789 | ||
8303acbc YS |
790 | config SYS_FSL_NUM_LAWS |
791 | int "Number of local access windows" | |
792 | depends on FSL_LAW | |
793 | default 32 if ARCH_B4420 || \ | |
794 | ARCH_B4860 || \ | |
795 | ARCH_P2041 || \ | |
796 | ARCH_P3041 || \ | |
797 | ARCH_P4080 || \ | |
798 | ARCH_P5020 || \ | |
799 | ARCH_P5040 || \ | |
800 | ARCH_T2080 || \ | |
801 | ARCH_T2081 || \ | |
802 | ARCH_T4160 || \ | |
803 | ARCH_T4240 | |
08a37fd1 | 804 | default 16 if ARCH_T1023 || \ |
8303acbc YS |
805 | ARCH_T1024 || \ |
806 | ARCH_T1040 || \ | |
807 | ARCH_T1042 | |
808 | default 12 if ARCH_BSC9131 || \ | |
809 | ARCH_BSC9132 || \ | |
810 | ARCH_C29X || \ | |
811 | ARCH_MPC8536 || \ | |
812 | ARCH_MPC8572 || \ | |
813 | ARCH_P1010 || \ | |
814 | ARCH_P1011 || \ | |
815 | ARCH_P1020 || \ | |
816 | ARCH_P1021 || \ | |
817 | ARCH_P1022 || \ | |
818 | ARCH_P1023 || \ | |
819 | ARCH_P1024 || \ | |
820 | ARCH_P1025 || \ | |
821 | ARCH_P2020 | |
822 | default 10 if ARCH_MPC8544 || \ | |
823 | ARCH_MPC8548 || \ | |
824 | ARCH_MPC8568 || \ | |
825 | ARCH_MPC8569 | |
826 | default 8 if ARCH_MPC8540 || \ | |
827 | ARCH_MPC8541 || \ | |
828 | ARCH_MPC8555 || \ | |
829 | ARCH_MPC8560 | |
830 | help | |
831 | Number of local access windows. This is fixed per SoC. | |
832 | If not sure, do not change. | |
833 | ||
26e79b65 YS |
834 | config SYS_NUM_TLBCAMS |
835 | int "Number of TLB CAM entries" | |
836 | default 64 if E500MC | |
837 | default 16 | |
838 | help | |
839 | Number of TLB CAM entries for Book-E chips. 64 for E500MC, | |
840 | 16 for other E500 SoCs. | |
841 | ||
53c95384 YS |
842 | config SYS_PPC_E500_USE_DEBUG_TLB |
843 | bool | |
844 | ||
845 | config SYS_PPC_E500_DEBUG_TLB | |
846 | int "Temporary TLB entry for external debugger" | |
847 | depends on SYS_PPC_E500_USE_DEBUG_TLB | |
848 | default 0 if ARCH_MPC8544 || ARCH_MPC8548 | |
849 | default 1 if ARCH_MPC8536 | |
850 | default 2 if ARCH_MPC8572 || \ | |
851 | ARCH_P1011 || \ | |
852 | ARCH_P1020 || \ | |
853 | ARCH_P1021 || \ | |
854 | ARCH_P1022 || \ | |
855 | ARCH_P1024 || \ | |
856 | ARCH_P1025 || \ | |
857 | ARCH_P2020 | |
858 | default 3 if ARCH_P1010 || \ | |
859 | ARCH_BSC9132 || \ | |
860 | ARCH_C29X | |
861 | help | |
862 | Select a temporary TLB entry to be used during boot to work | |
863 | around limitations in e500v1 and e500v2 external debugger | |
864 | support. This reduces the portions of the boot code where | |
865 | breakpoints and single stepping do not work. The value of this | |
866 | symbol should be set to the TLB1 entry to be used for this | |
867 | purpose. If unsure, do not change. | |
868 | ||
dd84058d MY |
869 | source "board/freescale/b4860qds/Kconfig" |
870 | source "board/freescale/bsc9131rdb/Kconfig" | |
871 | source "board/freescale/bsc9132qds/Kconfig" | |
872 | source "board/freescale/c29xpcie/Kconfig" | |
873 | source "board/freescale/corenet_ds/Kconfig" | |
874 | source "board/freescale/mpc8536ds/Kconfig" | |
875 | source "board/freescale/mpc8540ads/Kconfig" | |
876 | source "board/freescale/mpc8541cds/Kconfig" | |
877 | source "board/freescale/mpc8544ds/Kconfig" | |
878 | source "board/freescale/mpc8548cds/Kconfig" | |
879 | source "board/freescale/mpc8555cds/Kconfig" | |
880 | source "board/freescale/mpc8560ads/Kconfig" | |
881 | source "board/freescale/mpc8568mds/Kconfig" | |
882 | source "board/freescale/mpc8569mds/Kconfig" | |
883 | source "board/freescale/mpc8572ds/Kconfig" | |
884 | source "board/freescale/p1010rdb/Kconfig" | |
885 | source "board/freescale/p1022ds/Kconfig" | |
886 | source "board/freescale/p1023rdb/Kconfig" | |
dd84058d MY |
887 | source "board/freescale/p1_p2_rdb_pc/Kconfig" |
888 | source "board/freescale/p1_twr/Kconfig" | |
dd84058d MY |
889 | source "board/freescale/p2041rdb/Kconfig" |
890 | source "board/freescale/qemu-ppce500/Kconfig" | |
aba80048 | 891 | source "board/freescale/t102xqds/Kconfig" |
48c6f328 | 892 | source "board/freescale/t102xrdb/Kconfig" |
dd84058d MY |
893 | source "board/freescale/t1040qds/Kconfig" |
894 | source "board/freescale/t104xrdb/Kconfig" | |
895 | source "board/freescale/t208xqds/Kconfig" | |
896 | source "board/freescale/t208xrdb/Kconfig" | |
897 | source "board/freescale/t4qds/Kconfig" | |
898 | source "board/freescale/t4rdb/Kconfig" | |
899 | source "board/gdsys/p1022/Kconfig" | |
900 | source "board/keymile/kmp204x/Kconfig" | |
901 | source "board/sbc8548/Kconfig" | |
902 | source "board/socrates/Kconfig" | |
87e29878 | 903 | source "board/varisys/cyrus/Kconfig" |
dd84058d MY |
904 | source "board/xes/xpedite520x/Kconfig" |
905 | source "board/xes/xpedite537x/Kconfig" | |
906 | source "board/xes/xpedite550x/Kconfig" | |
8b0044ff | 907 | source "board/Arcturus/ucp1020/Kconfig" |
dd84058d MY |
908 | |
909 | endmenu |