]> git.ipfire.org Git - thirdparty/u-boot.git/blame - arch/powerpc/cpu/mpc85xx/cmd_errata.c
projects / thirdparty / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc85xx / cmd_errata.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
79ee3448 2/*
d621da00 3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
79ee3448
KG		 4 */
5
d678a59d 6#include <common.h>
79ee3448 7#include <command.h>
691d719d 8#include <init.h>
79ee3448 9#include <linux/compiler.h>
a07bdad7 10#include <fsl_errata.h>
79ee3448 11#include <asm/processor.h>
c26c80a1 12#include <fsl_usb.h>
d607b968 13#include "fsl_corenet_serdes.h"
79ee3448 14
0118033b
TT		 15#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
16/*
17 * This work-around is implemented in PBI, so just check to see if the
18 * work-around was actually applied. To do this, we check for specific data
19 * at specific addresses in DCSR.
20 *
21 * Array offsets[] contains a list of offsets within DCSR. According to the
22 * erratum document, the value at each offset should be 2.
23 */
24static void check_erratum_a4849(uint32_t svr)
25{
65cc0e2a 26 void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
0118033b
TT		 27 unsigned int i;
28
5e5fdd2d 29#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
0118033b
TT		 30 static const uint8_t offsets[] = {
31 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
32 };
33#endif
e71372cb 34#ifdef CONFIG_ARCH_P4080
0118033b
TT		 35 static const uint8_t offsets[] = {
36 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
37 };
38#endif
39 uint32_t x108; /* The value that should be at offset 0x108 */
40
41 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
42 if (in_be32(dcsr + offsets[i]) != 2) {
43 printf("Work-around for Erratum A004849 is not enabled\n");
44 return;
45 }
46 }
47
5e5fdd2d 48#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
0118033b
TT		 49 x108 = 0x12;
50#endif
51
e71372cb 52#ifdef CONFIG_ARCH_P4080
0118033b
TT		 53 /*
54 * For P4080, the erratum document says that the value at offset 0x108
55 * should be 0x12 on rev2, or 0x1c on rev3.
56 */
57 if (SVR_MAJ(svr) == 2)
58 x108 = 0x12;
59 if (SVR_MAJ(svr) == 3)
60 x108 = 0x1c;
61#endif
62
63 if (in_be32(dcsr + 0x108) != x108) {
64 printf("Work-around for Erratum A004849 is not enabled\n");
65 return;
66 }
67
68 /* Everything matches, so the erratum work-around was applied */
69
70 printf("Work-around for Erratum A004849 enabled\n");
71}
72#endif
73
d607b968
TT		 74#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
75/*
76 * This work-around is implemented in PBI, so just check to see if the
77 * work-around was actually applied. To do this, we check for specific data
78 * at specific addresses in the SerDes register block.
79 *
80 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
81 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
82
83 */
84static void check_erratum_a4580(uint32_t svr)
85{
86 const serdes_corenet_t __iomem *srds_regs =
6cc04547 87 (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
d607b968
TT		 88 unsigned int lane;
89
90 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
91 if (serdes_lane_enabled(lane)) {
92 const struct serdes_lane __iomem *srds_lane =
93 &srds_regs->lane[serdes_get_lane_idx(lane)];
94
95 /*
96 * Verify that the values we were supposed to write in
97 * the PBI are actually there. Also, the lower 15
98 * bits of res4[3] should be the same as the upper 15
99 * bits of res4[1].
100 */
101 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
102 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
103 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
104 printf("Work-around for Erratum A004580 is "
105 "not enabled\n");
106 return;
107 }
108 }
109 }
110
111 /* Everything matches, so the erratum work-around was applied */
112
113 printf("Work-around for Erratum A004580 enabled\n");
114}
115#endif
116
c3678b09
YS		 117#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
118/*
119 * This workaround can be implemented in PBI, or by u-boot.
120 */
121static void check_erratum_a007212(void)
122{
65cc0e2a 123 u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
c3678b09
YS		 124
125 if (in_be32(plldgdcr) & 0x1fe) {
126 /* check if PLL ratio is set by workaround */
127 puts("Work-around for Erratum A007212 enabled\n");
128 }
129}
130#endif
131
09140113
SG		 132static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
133 char *const argv[])
79ee3448 134{
57125f22
YS		 135#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
136 extern int enable_cpu_a011_workaround;
137#endif
79ee3448
KG		 138 __maybe_unused u32 svr = get_svr();
139
63659ff3 140#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
79ee3448
KG		 141 if (IS_SVR_REV(svr, 1, 0)) {
142 switch (SVR_SOC_VER(svr)) {
143 case SVR_P1013:
79ee3448 144 case SVR_P1022:
79ee3448
KG		 145 puts("Work-around for Erratum SATA A001 enabled\n");
146 }
147 }
148#endif
149
61054ffa
KG		 150#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
151 puts("Work-around for Erratum SERDES8 enabled\n");
152#endif
df8af0b4
EM		 153#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
154 puts("Work-around for Erratum SERDES9 enabled\n");
155#endif
da30b9fd
TT		 156#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
157 puts("Work-around for Erratum SERDES-A005 enabled\n");
158#endif
fd3c9bef 159#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
1e9ea85f
YS		 160 if (SVR_MAJ(svr) < 3)
161 puts("Work-around for Erratum CPU22 enabled\n");
810c4427 162#endif
5e23ab0a
YS		 163#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
164 /*
165 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
166 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
57125f22 167 * The SVR has been checked by cpu_init_r().
5e23ab0a 168 */
57125f22 169 if (enable_cpu_a011_workaround)
5e23ab0a
YS		 170 puts("Work-around for Erratum CPU-A011 enabled\n");
171#endif
43f082bb
KG		 172#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
173 puts("Work-around for Erratum CPU-A003999 enabled\n");
174#endif
4108508a 175#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
b5188164 176 puts("Work-around for Erratum DDR-A003474 enabled\n");
4108508a 177#endif
810c4427
BB		 178#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
179 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
d621da00
JH		 180#endif
181#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
182 puts("Work-around for Erratum ESDHC111 enabled\n");
3b4456ec 183#endif
eb539412
YS		 184#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
185 puts("Work-around for Erratum A004468 enabled\n");
186#endif
3b4456ec
RZ		 187#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
188 puts("Work-around for Erratum ESDHC135 enabled\n");
ae026ffd 189#endif
4e0be34a
ZRR		 190#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
191 if (SVR_MAJ(svr) < 3)
192 puts("Work-around for Erratum ESDHC13 enabled\n");
fd3c9bef 193#endif
5103a03a
KG		 194#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
195 puts("Work-around for Erratum ESDHC-A001 enabled\n");
196#endif
1d2c2a62
KG		 197#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
198 puts("Work-around for Erratum CPC-A002 enabled\n");
199#endif
868da593
KG		 200#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
201 puts("Work-around for Erratum CPC-A003 enabled\n");
202#endif
f133796d
KG		 203#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
204 puts("Work-around for Erratum ELBC-A001 enabled\n");
205#endif
fa8d23c0
YS		 206#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
207 puts("Work-around for Erratum DDR-A003 enabled\n");
208#endif
eb0aff77
YS		 209#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
210 puts("Work-around for Erratum DDR115 enabled\n");
91671913
YS		 211#endif
212#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
213 puts("Work-around for Erratum DDR111 enabled\n");
214 puts("Work-around for Erratum DDR134 enabled\n");
42aee64b
PA		 215#endif
216#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
217 puts("Work-around for Erratum IFC-A002769 enabled\n");
fb855f43
PA		 218#endif
219#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
220 puts("Work-around for Erratum P1010-A003549 enabled\n");
bc6bbd6b
PA		 221#endif
222#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
223 puts("Work-around for Erratum IFC A-003399 enabled\n");
5ace2992
KG		 224#endif
225#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
226 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
227 puts("Work-around for Erratum NMG DDR120 enabled\n");
2b3a1cdd
KG		 228#endif
229#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
230 puts("Work-around for Erratum NMG_LBC103 enabled\n");
aada81de 231#endif
232#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
233 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
234 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
33eee330 235#endif
9855b3be
YS		 236#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
237 puts("Work-around for Erratum A004508 enabled\n");
238#endif
33eee330
SW		 239#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
240 puts("Work-around for Erratum A004510 enabled\n");
d59c5570
LG		 241#endif
242#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
243 puts("Work-around for Erratum SRIO-A004034 enabled\n");
a1d558a2
YS		 244#endif
245#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
246 puts("Work-around for Erratum A004934 enabled\n");
0118033b 247#endif
72bd83cd
SL		 248#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
249 if (IS_SVR_REV(svr, 1, 0))
250 puts("Work-around for Erratum A005871 enabled\n");
251#endif
7af9a074
SL		 252#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
253 if (SVR_MAJ(get_svr()) == 1)
254 puts("Work-around for Erratum A006475 enabled\n");
255#endif
256#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
257 if (SVR_MAJ(get_svr()) == 1)
258 puts("Work-around for Erratum A006384 enabled\n");
259#endif
0118033b
TT		 260#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
261 /* This work-around is implemented in PBI, so just check for it */
262 check_erratum_a4849(svr);
d607b968
TT		 263#endif
264#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
265 /* This work-around is implemented in PBI, so just check for it */
266 check_erratum_a4580(svr);
c0a4e6b8
YC		 267#endif
268#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
269 puts("Work-around for Erratum PCIe-A003 enabled\n");
99d7b0a4
X		 270#endif
271#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
272 puts("Work-around for Erratum USB14 enabled\n");
82125192 273#endif
b6808cd8 274#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
e7f533cd
ZQ		 275 if (has_erratum_a007186())
276 puts("Work-around for Erratum A007186 enabled\n");
b6808cd8 277#endif
82125192
SW		 278#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
279 puts("Work-around for Erratum A006593 enabled\n");
d217a9ad 280#endif
133fbfa9
YS		 281#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
282 if (has_erratum_a006379())
283 puts("Work-around for Erratum A006379 enabled\n");
284#endif
424bf942
SL		 285#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
286 if (IS_SVR_REV(svr, 1, 0))
287 puts("Work-around for Erratum A003571 enabled\n");
288#endif
d217a9ad
YS		 289#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
290 puts("Work-around for Erratum A-005812 enabled\n");
9c3f77eb 291#endif
954a1a47
YS		 292#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
293 puts("Work-around for Erratum A005125 enabled\n");
294#endif
11856919
NB		 295#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
296 if (has_erratum_a007075())
297 puts("Work-around for Erratum A007075 enabled\n");
298#endif
f3dff695
NB		 299#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
300 if (has_erratum_a007798())
301 puts("Work-around for Erratum A007798 enabled\n");
302#endif
0dc78ff8
NB		 303#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
304 if (has_erratum_a004477())
305 puts("Work-around for Erratum A004477 enabled\n");
306#endif
9c3f77eb
CL		 307#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
308 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
309 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
310 puts("Work-around for Erratum I2C-A004447 enabled\n");
9c641a87 311#endif
4eaf7f52
CP		 312#ifdef CONFIG_SYS_FSL_ERRATUM_A005275
313 if (has_erratum_a005275())
314 puts("Work-around for Erratum A005275 enabled\n");
315#endif
9c641a87
SG		 316#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
317 if (has_erratum_a006261())
318 puts("Work-around for Erratum A006261 enabled\n");
eb0aff77 319#endif
c3678b09
YS		 320#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
321 check_erratum_a007212();
322#endif
f1a96ec1
CL		 323#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
324 puts("Work-around for Erratum A-005434 enabled\n");
325#endif
9f074e67
PK		 326#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
327 defined(CONFIG_A008044_WORKAROUND)
31530e0b
PK		 328 if (IS_SVR_REV(svr, 1, 0))
329 puts("Work-around for Erratum A-008044 enabled\n");
9f074e67 330#endif
d46a4a13
YS		 331#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
332 (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
b24f6d40
SX		 333 puts("Work-around for Erratum XFI on B4860QDS enabled\n");
334#endif
a994b3de
SL		 335#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
336 puts("Work-around for Erratum A009663 enabled\n");
337#endif
06ad970b
DD		 338#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
339 puts("Work-around for Erratum A007907 enabled\n");
340#endif
09bfd962
TB		 341#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
342 puts("Work-around for Erratum A007815 enabled\n");
343#endif
344
79ee3448
KG		 345 return 0;
346}
347
348U_BOOT_CMD(
349 errata, 1, 0, do_errata,
350 "Report errata workarounds",
351 ""
352);
"Das U-Boot" Source Tree