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42d1f039 | 1 | /* |
18bacc20 | 2 | * Copyright 2004,2007-2009 Freescale Semiconductor, Inc. |
42d1f039 WD |
3 | * (C) Copyright 2002, 2003 Motorola Inc. |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
75b9d4ae | 28 | #include <config.h> |
42d1f039 WD |
29 | #include <common.h> |
30 | #include <watchdog.h> | |
31 | #include <command.h> | |
80522dc8 | 32 | #include <fsl_esdhc.h> |
42d1f039 | 33 | #include <asm/cache.h> |
740280e6 | 34 | #include <asm/io.h> |
42d1f039 | 35 | |
591933ca JY |
36 | DECLARE_GLOBAL_DATA_PTR; |
37 | ||
42d1f039 WD |
38 | int checkcpu (void) |
39 | { | |
97d80fc3 | 40 | sys_info_t sysinfo; |
97d80fc3 | 41 | uint pvr, svr; |
d9b94f28 | 42 | uint fam; |
97d80fc3 WD |
43 | uint ver; |
44 | uint major, minor; | |
4dbdb768 | 45 | struct cpu_type *cpu; |
08ef89ec | 46 | char buf1[32], buf2[32]; |
ee1e35be | 47 | #ifdef CONFIG_DDR_CLK_FREQ |
6d0f6bcf | 48 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
39aaca1f KG |
49 | #ifdef CONFIG_FSL_CORENET |
50 | u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) | |
51 | >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; | |
52 | #else | |
c0391111 JJ |
53 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
54 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; | |
39aaca1f KG |
55 | #endif |
56 | #else | |
57 | #ifdef CONFIG_FSL_CORENET | |
58 | u32 ddr_sync = 0; | |
ee1e35be KG |
59 | #else |
60 | u32 ddr_ratio = 0; | |
61 | #endif | |
39aaca1f | 62 | #endif /* CONFIG_DDR_CLK_FREQ */ |
2fc7eb0c | 63 | int i; |
97d80fc3 | 64 | |
97d80fc3 | 65 | svr = get_svr(); |
97d80fc3 | 66 | major = SVR_MAJ(svr); |
ef50d6c0 KG |
67 | #ifdef CONFIG_MPC8536 |
68 | major &= 0x7; /* the msb of this nibble is a mfg code */ | |
69 | #endif | |
97d80fc3 | 70 | minor = SVR_MIN(svr); |
42d1f039 | 71 | |
0e870980 | 72 | if (cpu_numcores() > 1) { |
21170c80 PA |
73 | #ifndef CONFIG_MP |
74 | puts("Unicore software on multiprocessor system!!\n" | |
75 | "To enable mutlticore build define CONFIG_MP\n"); | |
76 | #endif | |
0e870980 PA |
77 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); |
78 | printf("CPU%d: ", pic->whoami); | |
79 | } else { | |
80 | puts("CPU: "); | |
81 | } | |
1ced1216 | 82 | |
0e870980 | 83 | cpu = gd->cpu; |
1ced1216 | 84 | |
58442dc0 PA |
85 | puts(cpu->name); |
86 | if (IS_E_PROCESSOR(svr)) | |
87 | puts("E"); | |
1ced1216 | 88 | |
97d80fc3 WD |
89 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
90 | ||
6c9e789e | 91 | pvr = get_pvr(); |
d9b94f28 | 92 | fam = PVR_FAM(pvr); |
6c9e789e WD |
93 | ver = PVR_VER(pvr); |
94 | major = PVR_MAJ(pvr); | |
95 | minor = PVR_MIN(pvr); | |
96 | ||
97 | printf("Core: "); | |
d9b94f28 JL |
98 | switch (fam) { |
99 | case PVR_FAM(PVR_85xx): | |
6c9e789e WD |
100 | puts("E500"); |
101 | break; | |
102 | default: | |
103 | puts("Unknown"); | |
104 | break; | |
105 | } | |
0f060c3b KG |
106 | |
107 | if (PVR_MEM(pvr) == 0x03) | |
108 | puts("MC"); | |
109 | ||
6c9e789e WD |
110 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
111 | ||
97d80fc3 WD |
112 | get_sys_info(&sysinfo); |
113 | ||
b29dee3c | 114 | puts("Clock Configuration:"); |
0e870980 | 115 | for (i = 0; i < cpu_numcores(); i++) { |
1bba30ef WD |
116 | if (!(i & 3)) |
117 | printf ("\n "); | |
2fc7eb0c HW |
118 | printf("CPU%d:%-4s MHz, ", |
119 | i,strmhz(buf1, sysinfo.freqProcessor[i])); | |
b29dee3c KG |
120 | } |
121 | printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); | |
ee1e35be | 122 | |
39aaca1f KG |
123 | #ifdef CONFIG_FSL_CORENET |
124 | if (ddr_sync == 1) { | |
125 | printf(" DDR:%-4s MHz (%s MT/s data rate) " | |
126 | "(Synchronous), ", | |
127 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
128 | strmhz(buf2, sysinfo.freqDDRBus)); | |
129 | } else { | |
130 | printf(" DDR:%-4s MHz (%s MT/s data rate) " | |
131 | "(Asynchronous), ", | |
132 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
133 | strmhz(buf2, sysinfo.freqDDRBus)); | |
134 | } | |
135 | #else | |
d4357932 KG |
136 | switch (ddr_ratio) { |
137 | case 0x0: | |
08ef89ec WD |
138 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
139 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
140 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
141 | break; |
142 | case 0x7: | |
39aaca1f KG |
143 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
144 | "(Synchronous), ", | |
08ef89ec WD |
145 | strmhz(buf1, sysinfo.freqDDRBus/2), |
146 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
147 | break; |
148 | default: | |
39aaca1f KG |
149 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
150 | "(Asynchronous), ", | |
08ef89ec WD |
151 | strmhz(buf1, sysinfo.freqDDRBus/2), |
152 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
153 | break; |
154 | } | |
39aaca1f | 155 | #endif |
97d80fc3 | 156 | |
39aaca1f | 157 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) { |
ada591d2 | 158 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
39aaca1f | 159 | } else { |
ada591d2 TP |
160 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
161 | sysinfo.freqLocalBus); | |
39aaca1f | 162 | } |
42d1f039 | 163 | |
1ced1216 | 164 | #ifdef CONFIG_CPM2 |
08ef89ec | 165 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); |
1ced1216 | 166 | #endif |
97d80fc3 | 167 | |
b3d7f20f HW |
168 | #ifdef CONFIG_QE |
169 | printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); | |
170 | #endif | |
171 | ||
39aaca1f KG |
172 | #ifdef CONFIG_SYS_DPAA_FMAN |
173 | for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { | |
174 | printf(" FMAN%d: %s MHz\n", i, | |
175 | strmhz(buf1, sysinfo.freqFMan[i])); | |
176 | } | |
177 | #endif | |
178 | ||
179 | #ifdef CONFIG_SYS_DPAA_PME | |
180 | printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); | |
181 | #endif | |
182 | ||
6c9e789e | 183 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
42d1f039 WD |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
188 | ||
189 | /* ------------------------------------------------------------------------- */ | |
190 | ||
191 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) | |
192 | { | |
c348322a KG |
193 | /* Everything after the first generation of PQ3 parts has RSTCR */ |
194 | #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ | |
195 | defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) | |
793670c3 SP |
196 | unsigned long val, msr; |
197 | ||
42d1f039 WD |
198 | /* |
199 | * Initiate hard reset in debug control register DBCR0 | |
c348322a | 200 | * Make sure MSR[DE] = 1. This only resets the core. |
42d1f039 | 201 | */ |
793670c3 SP |
202 | msr = mfmsr (); |
203 | msr |= MSR_DE; | |
204 | mtmsr (msr); | |
205 | ||
206 | val = mfspr(DBCR0); | |
207 | val |= 0x70000000; | |
208 | mtspr(DBCR0,val); | |
c348322a KG |
209 | #else |
210 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
211 | out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ | |
212 | udelay(100); | |
213 | #endif | |
df90968b | 214 | |
42d1f039 WD |
215 | return 1; |
216 | } | |
217 | ||
218 | ||
219 | /* | |
220 | * Get timebase clock frequency | |
221 | */ | |
222 | unsigned long get_tbclk (void) | |
223 | { | |
3c2a67ee KG |
224 | #ifdef CONFIG_FSL_CORENET |
225 | return (gd->bus_clk + 8) / 16; | |
226 | #else | |
591933ca | 227 | return (gd->bus_clk + 4UL)/8UL; |
3c2a67ee | 228 | #endif |
42d1f039 WD |
229 | } |
230 | ||
231 | ||
232 | #if defined(CONFIG_WATCHDOG) | |
233 | void | |
234 | watchdog_reset(void) | |
235 | { | |
236 | int re_enable = disable_interrupts(); | |
237 | reset_85xx_watchdog(); | |
238 | if (re_enable) enable_interrupts(); | |
239 | } | |
240 | ||
241 | void | |
242 | reset_85xx_watchdog(void) | |
243 | { | |
244 | /* | |
245 | * Clear TSR(WIS) bit by writing 1 | |
246 | */ | |
247 | unsigned long val; | |
03b81b48 AF |
248 | val = mfspr(SPRN_TSR); |
249 | val |= TSR_WIS; | |
250 | mtspr(SPRN_TSR, val); | |
42d1f039 WD |
251 | } |
252 | #endif /* CONFIG_WATCHDOG */ | |
253 | ||
740280e6 | 254 | /* |
59f63058 SP |
255 | * Configures a UPM. The function requires the respective MxMR to be set |
256 | * before calling this function. "size" is the number or entries, not a sizeof. | |
740280e6 SP |
257 | */ |
258 | void upmconfig (uint upm, uint * table, uint size) | |
259 | { | |
260 | int i, mdr, mad, old_mad = 0; | |
261 | volatile u32 *mxmr; | |
6d0f6bcf | 262 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
740280e6 SP |
263 | volatile u32 *brp,*orp; |
264 | volatile u8* dummy = NULL; | |
265 | int upmmask; | |
266 | ||
267 | switch (upm) { | |
268 | case UPMA: | |
269 | mxmr = &lbc->mamr; | |
270 | upmmask = BR_MS_UPMA; | |
271 | break; | |
272 | case UPMB: | |
273 | mxmr = &lbc->mbmr; | |
274 | upmmask = BR_MS_UPMB; | |
275 | break; | |
276 | case UPMC: | |
277 | mxmr = &lbc->mcmr; | |
278 | upmmask = BR_MS_UPMC; | |
279 | break; | |
280 | default: | |
281 | printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); | |
282 | hang(); | |
283 | } | |
284 | ||
285 | /* Find the address for the dummy write transaction */ | |
286 | for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; | |
287 | i++, brp += 2, orp += 2) { | |
e093a247 | 288 | |
740280e6 | 289 | /* Look for a valid BR with selected UPM */ |
59f63058 SP |
290 | if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { |
291 | dummy = (volatile u8*)(in_be32(brp) & BR_BA); | |
740280e6 SP |
292 | break; |
293 | } | |
294 | } | |
295 | ||
296 | if (i == 8) { | |
297 | printf("Error: %s() could not find matching BR\n", __FUNCTION__); | |
298 | hang(); | |
299 | } | |
300 | ||
301 | for (i = 0; i < size; i++) { | |
302 | /* 1 */ | |
59f63058 | 303 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); |
740280e6 SP |
304 | /* 2 */ |
305 | out_be32(&lbc->mdr, table[i]); | |
306 | /* 3 */ | |
307 | mdr = in_be32(&lbc->mdr); | |
308 | /* 4 */ | |
309 | *(volatile u8 *)dummy = 0; | |
310 | /* 5 */ | |
311 | do { | |
59f63058 | 312 | mad = in_be32(mxmr) & MxMR_MAD_MSK; |
740280e6 SP |
313 | } while (mad <= old_mad && !(!mad && i == (size-1))); |
314 | old_mad = mad; | |
315 | } | |
59f63058 | 316 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); |
740280e6 | 317 | } |
dd35479a | 318 | |
80522dc8 AF |
319 | /* |
320 | * Initializes on-chip MMC controllers. | |
321 | * to override, implement board_mmc_init() | |
322 | */ | |
323 | int cpu_mmc_init(bd_t *bis) | |
324 | { | |
325 | #ifdef CONFIG_FSL_ESDHC | |
326 | return fsl_esdhc_mmc_init(bis); | |
327 | #else | |
328 | return 0; | |
329 | #endif | |
330 | } |