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bc48d0d5 KG |
1 | /* |
2 | * Copyright 2010 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
bc48d0d5 KG |
5 | */ |
6 | ||
7 | #include <config.h> | |
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/immap_85xx.h> | |
11 | #include <asm/fsl_serdes.h> | |
12 | ||
13 | #define SRDS1_MAX_LANES 8 | |
14 | ||
15 | static u32 serdes1_prtcl_map; | |
16 | ||
17 | static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { | |
18 | [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, | |
19 | [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, | |
20 | [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, | |
21 | [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, | |
22 | [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, | |
23 | }; | |
24 | ||
25 | int is_serdes_configured(enum srds_prtcl prtcl) | |
26 | { | |
27 | return (1 << prtcl) & serdes1_prtcl_map; | |
28 | } | |
29 | ||
30 | void fsl_serdes_init(void) | |
31 | { | |
32 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
33 | u32 pordevsr = in_be32(&gur->pordevsr); | |
34 | u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> | |
35 | MPC85xx_PORDEVSR_IO_SEL_SHIFT; | |
36 | int lane; | |
37 | ||
38 | debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); | |
39 | ||
e51e47d3 | 40 | if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { |
bc48d0d5 KG |
41 | printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); |
42 | return ; | |
43 | } | |
44 | ||
45 | for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { | |
46 | enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; | |
47 | serdes1_prtcl_map |= (1 << lane_prtcl); | |
48 | } | |
49 | } |