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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc85xx / t4240_serdes.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
9e758758
YS		 2/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
9e758758
YS		 4 */
5
d678a59d 6#include <common.h>
9e758758
YS		 7#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
10#include "fsl_corenet2_serdes.h"
11
12struct serdes_config {
13 u32 protocol;
14 u8 lanes[SRDS_MAX_LANES];
15};
16
26bc57da 17#ifdef CONFIG_ARCH_T4240
924859ac 18static const struct serdes_config serdes1_cfg_tbl[] = {
9e758758
YS		 19 /* SerDes 1 */
20 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
21 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
22 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
23 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
24 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
25 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
26 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
28 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
29 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
30 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
94752f60
SX		 32 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
33 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
34 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
35 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
9e758758
YS		 36 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
37 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
38 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
39 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
94752f60
SX		 40 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
41 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
42 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
43 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
9e758758
YS		 44 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
45 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
46 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
94752f60
SX		 48 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
49 NONE, NONE, QSGMII_FM1_A, NONE} },
9e758758
YS		 50 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
51 NONE, NONE, QSGMII_FM1_A, NONE}},
94752f60
SX		 52 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
53 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
54 NONE, NONE, QSGMII_FM1_A, NONE} },
9e758758
YS		 55 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
56 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
57 NONE, NONE, QSGMII_FM1_A, NONE}},
94752f60
SX		 58 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
59 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
60 NONE, NONE, QSGMII_FM1_A, NONE} },
9e758758
YS		 61 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
62 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
63 NONE, NONE, QSGMII_FM1_A, NONE}},
94752f60
SX		 64 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
65 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
66 NONE, NONE, QSGMII_FM1_A, NONE} },
9e758758
YS		 67 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
68 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
69 NONE, NONE, QSGMII_FM1_A, NONE}},
70 {}
71};
924859ac 72static const struct serdes_config serdes2_cfg_tbl[] = {
9e758758
YS		 73 /* SerDes 2 */
74 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
75 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
76 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
77 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
78 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
79 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
80 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
82 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
83 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
84 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
85 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
94752f60
SX		 86 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
87 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
88 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
89 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 90 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
91 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
92 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
93 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 94 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
95 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
96 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
97 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 98 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
99 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
100 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
101 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
102 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
103 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
104 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
105 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 106 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
107 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
108 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
109 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 110 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
111 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
112 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
113 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 114 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
115 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
116 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
117 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 118 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
119 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
120 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
121 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
122 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
123 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
124 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
125 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 126 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
127 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
128 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
129 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 130 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
131 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
132 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
133 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
134 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
135 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
136 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
137 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 138 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
139 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
140 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
141 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 142 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
143 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
144 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
145 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 146 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
147 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
148 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
149 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 150 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
151 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
152 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
153 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94752f60
SX		 154 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
155 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758 156 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
1c68d01e 157 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 158 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
159 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
160 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 161 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
162 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
1c68d01e 163 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 164 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
165 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
166 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 167 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
168 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
1c68d01e 169 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 170 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
171 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
172 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 173 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
174 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
1c68d01e 175 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 176 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
177 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
178 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 179 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
180 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
1c68d01e 181 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 182 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
183 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
184 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 185 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
186 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
1c68d01e 187 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 188 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
189 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
190 NONE, NONE, QSGMII_FM2_A, NONE} },
9e758758
YS		 191 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
192 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
1c68d01e 193 NONE, NONE, QSGMII_FM2_A, NONE} },
94752f60
SX		 194 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
195 XFI_FM2_MAC10, XFI_FM2_MAC9,
196 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
197 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
9e758758
YS		 198 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
199 XFI_FM2_MAC10, XFI_FM2_MAC9,
200 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
201 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
202 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
203 XFI_FM2_MAC10, XFI_FM2_MAC9,
204 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
205 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
206 {}
207};
924859ac 208static const struct serdes_config serdes3_cfg_tbl[] = {
9e758758 209 /* SerDes 3 */
94752f60 210 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
9e758758 211 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
94752f60 212 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
9e758758 213 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
94752f60 214 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
9e758758 215 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
4bf7f908
SX		 216 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
217 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
9e758758
YS		 218 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
219 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
220 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
221 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
94752f60
SX		 222 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
223 PCIE2, PCIE2, PCIE2, PCIE2} },
9e758758
YS		 224 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
225 PCIE2, PCIE2, PCIE2, PCIE2}},
94752f60
SX		 226 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
227 PCIE2, PCIE2, PCIE2, PCIE2} },
9e758758
YS		 228 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
229 PCIE2, PCIE2, PCIE2, PCIE2}},
94752f60
SX		 230 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
231 SRIO1, SRIO1, SRIO1, SRIO1} },
9e758758
YS		 232 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
233 SRIO1, SRIO1, SRIO1, SRIO1}},
234 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
235 SRIO1, SRIO1, SRIO1, SRIO1}},
94752f60
SX		 236 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
237 SRIO1, SRIO1, SRIO1, SRIO1} },
9e758758
YS		 238 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
239 SRIO1, SRIO1, SRIO1, SRIO1}},
240 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
241 SRIO1, SRIO1, SRIO1, SRIO1}},
242 {}
243};
924859ac 244static const struct serdes_config serdes4_cfg_tbl[] = {
9e758758 245 /* SerDes 4 */
94752f60 246 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
9e758758 247 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
94752f60 248 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
9e758758 249 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
94752f60 250 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
9e758758 251 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
94752f60 252 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
9e758758 253 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
94752f60 254 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
f9772444 255 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
94752f60 256 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
f9772444 257 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
94752f60 258 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
9e758758 259 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
94752f60 260 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
9e758758
YS		 261 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
262 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
263 {}
264};
b6240846
YS		 265#else
266#error "Need to define SerDes protocol"
267#endif
924859ac 268static const struct serdes_config *serdes_cfg_tbl[] = {
9e758758
YS		 269 serdes1_cfg_tbl,
270 serdes2_cfg_tbl,
271 serdes3_cfg_tbl,
272 serdes4_cfg_tbl,
273};
274
275enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
276{
924859ac 277 const struct serdes_config *ptr;
9e758758
YS		 278
279 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
280 return 0;
281
282 ptr = serdes_cfg_tbl[serdes];
283 while (ptr->protocol) {
284 if (ptr->protocol == cfg)
285 return ptr->lanes[lane];
286 ptr++;
287 }
288 return 0;
289}
290
291int is_serdes_prtcl_valid(int serdes, u32 prtcl)
292{
293 int i;
924859ac 294 const struct serdes_config *ptr;
9e758758
YS		 295
296 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
297 return 0;
298
299 ptr = serdes_cfg_tbl[serdes];
300 while (ptr->protocol) {
301 if (ptr->protocol == prtcl)
302 break;
303 ptr++;
304 }
305
306 if (!ptr->protocol)
307 return 0;
308
309 for (i = 0; i < SRDS_MAX_LANES; i++) {
310 if (ptr->lanes[i] != NONE)
311 return 1;
312 }
313
314 return 0;
315}
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