[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / start.S

/*
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*  U-Boot - Startup Code for PowerPC based Embedded Boards
 *
 *
 *  The processor starts at 0x00000100 and the code is executed
 *  from flash. The code is organized to be at an other address
 *  in memory, but as long we don't jump around before relocating,
 *  board_init lies at a quite high address and when the cpu has
 *  jumped there, everything is ok.
 *  This works because the cpu gives the FLASH (CS0) the whole
 *  address space at startup, and board_init lies as a echo of
 *  the flash somewhere up there in the memory map.
 *
 *  board_init will change CS0 to be positioned at the correct
 *  address and (s)dram will be positioned at address 0
 */
#include <config.h>
#include <mpc8xx.h>
#include <timestamp.h>
#include <version.h>

#define CONFIG_8xx 1		/* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't want the  MMU yet.
*/
#undef	MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */

/*
 * Set up GOT: Global Offset Table
 *
 * Use r12 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956		/* U-Boot Magic Number			*/
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
	mtspr	638, r3

	/* Initialize machine status; enable machine check interrupt		*/
	/*----------------------------------------------------------------------*/
	li	r3, MSR_KERNEL		/* Set ME, RI flags */
	mtmsr	r3
	mtspr	SRR1, r3		/* Make SRR1 match MSR */

	mfspr	r3, ICR			/* clear Interrupt Cause Register */

	/* Initialize debug port registers					*/
	/*----------------------------------------------------------------------*/
	xor	r0, r0, r0		/* Clear R0 */
	mtspr	LCTRL1, r0		/* Initialize debug port regs */
	mtspr	LCTRL2, r0
	mtspr	COUNTA, r0
	mtspr	COUNTB, r0

	/* Reset the caches							*/
	/*----------------------------------------------------------------------*/

	mfspr	r3, IC_CST		/* Clear error bits */
	mfspr	r3, DC_CST

	lis	r3, IDC_UNALL@h		/* Unlock all */
	mtspr	IC_CST, r3
	mtspr	DC_CST, r3

	lis	r3, IDC_INVALL@h	/* Invalidate all */
	mtspr	IC_CST, r3
	mtspr	DC_CST, r3

	lis	r3, IDC_DISABLE@h	/* Disable data cache */
	mtspr	DC_CST, r3

#if !defined(CONFIG_SYS_DELAYED_ICACHE)
					/* On IP860 and PCU E,
					 * we cannot enable IC yet
					 */
	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
#endif
	mtspr	IC_CST, r3

	/* invalidate all tlb's							*/
	/*----------------------------------------------------------------------*/

	tlbia
	isync

	/*
	 * Calculate absolute address in FLASH and jump there
	 *----------------------------------------------------------------------*/

	lis	r3, CONFIG_SYS_MONITOR_BASE@h
	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:

	/* initialize some SPRs that are hard to access from C			*/
	/*----------------------------------------------------------------------*/

	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
	/* Note: R0 is still 0 here */
	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/

	/*
	 * Disable serialized ifetch and show cycles
	 * (i.e. set processor to normal mode).
	 * This is also a silicon bug workaround, see errata
	 */

	li	r2, 0x0007
	mtspr	ICTRL, r2

	/* Set up debug mode entry */

	lis	r2, CONFIG_SYS_DER@h
	ori	r2, r2, CONFIG_SYS_DER@l
	mtspr	DER, r2

	/* let the C-code set up the rest					*/
	/*									*/
	/* Be careful to keep code relocatable !				*/
	/*----------------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access			*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/

	bl	board_init_f	/* run 1st part of board init code (from Flash) */

	/* NOTREACHED - board_init_f() does not return */


	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
		MSR_KERNEL, COPY_EE)

	/* No FPU on MPC8xx.  This exception is not supposed to happen.
	*/
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
	 * for all unimplemented and illegal instructions.
	 */
	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)

	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)

	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)

	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)


	.globl	_end_of_vectors
_end_of_vectors:


	. = 0x2000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28			/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC				/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)		/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/* Cache functions.
*/
	.globl	icache_enable
icache_enable:
	SYNC
	lis	r3, IDC_INVALL@h
	mtspr	IC_CST, r3
	lis	r3, IDC_ENABLE@h
	mtspr	IC_CST, r3
	blr

	.globl	icache_disable
icache_disable:
	SYNC
	lis	r3, IDC_DISABLE@h
	mtspr	IC_CST, r3
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, IC_CST
	srwi	r3, r3, 31	/* >>31 => select bit 0 */
	blr

	.globl	dcache_enable
dcache_enable:
#if 0
	SYNC
#endif
#if 1
	lis	r3, 0x0400		/* Set cache mode with MMU off */
	mtspr	MD_CTR, r3
#endif

	lis	r3, IDC_INVALL@h
	mtspr	DC_CST, r3
#if 0
	lis	r3, DC_SFWT@h
	mtspr	DC_CST, r3
#endif
	lis	r3, IDC_ENABLE@h
	mtspr	DC_CST, r3
	blr

	.globl	dcache_disable
dcache_disable:
	SYNC
	lis	r3, IDC_DISABLE@h
	mtspr	DC_CST, r3
	lis	r3, IDC_INVALL@h
	mtspr	DC_CST, r3
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, DC_CST
	srwi	r3, r3, 31	/* >>31 => select bit 0 */
	blr

	.globl	dc_read
dc_read:
	mtspr	DC_ADR, r3
	mfspr	r3, DC_DAT
	blr

/*
 * unsigned int get_immr (unsigned int mask)
 *
 * return (mask ? (IMMR & mask) : IMMR);
 */
	.globl	get_immr
get_immr:
	mr	r4,r3		/* save mask */
	mfspr	r3, IMMR	/* IMMR */
	cmpwi	0,r4,0		/* mask != 0 ? */
	beq	4f
	and	r3,r3,r4	/* IMMR & mask */
4:
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr


	.globl wr_ic_cst
wr_ic_cst:
	mtspr	IC_CST, r3
	blr

	.globl rd_ic_cst
rd_ic_cst:
	mfspr	r3, IC_CST
	blr

	.globl wr_ic_adr
wr_ic_adr:
	mtspr	IC_ADR, r3
	blr


	.globl wr_dc_cst
wr_dc_cst:
	mtspr	DC_CST, r3
	blr

	.globl rd_dc_cst
rd_dc_cst:
	mfspr	r3, DC_CST
	blr

	.globl wr_dc_adr
wr_dc_adr:
	mtspr	DC_ADR, r3
	blr

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer		*/
	mr	r9,  r4		/* Save copy of Global Data pointer	*/
	mr	r10, r5		/* Save copy of Destination Address	*/

	GET_GOT
	mr	r3,  r5				/* Destination Address	*/
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r12, r12, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */

	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	7f		/* Protect against 0 count		*/
	mtctr	r0
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */

	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:

	/*
	 * Relocation Function, r12 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	cmpwi	r0,0
	beq-	2f
	add	r0,r0,r11
	stw	r0,0(r3)
2:	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:

	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	mflr	r4			/* save link register		*/
	GET_GOT
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/* U-Boot - Startup Code for PowerPC based Embedded Boards
	26	*
	27	*
	28	* The processor starts at 0x00000100 and the code is executed
	29	* from flash. The code is organized to be at an other address
7e780369	30	* in memory, but as long we don't jump around before relocating,
5b1d7137 WD	31	* board_init lies at a quite high address and when the cpu has
	32	* jumped there, everything is ok.
	33	* This works because the cpu gives the FLASH (CS0) the whole
	34	* address space at startup, and board_init lies as a echo of
7e780369	35	* the flash somewhere up there in the memory map.
5b1d7137 WD	36	*
	37	* board_init will change CS0 to be positioned at the correct
	38	* address and (s)dram will be positioned at address 0
	39	*/
	40	#include <config.h>
	41	#include <mpc8xx.h>
561858ee	42	#include <timestamp.h>
5b1d7137 WD	43	#include <version.h>
	44
	45	#define CONFIG_8xx 1 /* needed for Linux kernel header files */
	46	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	47
	48	#include <ppc_asm.tmpl>
	49	#include <ppc_defs.h>
	50
	51	#include <asm/cache.h>
	52	#include <asm/mmu.h>
	53
	54	#ifndef CONFIG_IDENT_STRING
	55	#define CONFIG_IDENT_STRING ""
	56	#endif
	57
	58	/* We don't want the MMU yet.
	59	*/
	60	#undef MSR_KERNEL
	61	#define MSR_KERNEL ( MSR_ME \| MSR_RI ) /* Machine Check and Recoverable Interr. */
	62
	63	/*
	64	* Set up GOT: Global Offset Table
	65	*
0f8aa159	66	* Use r12 to access the GOT
5b1d7137 WD	67	*/
	68	START_GOT
	69	GOT_ENTRY(_GOT2_TABLE_)
	70	GOT_ENTRY(_FIXUP_TABLE_)
	71
	72	GOT_ENTRY(_start)
	73	GOT_ENTRY(_start_of_vectors)
	74	GOT_ENTRY(_end_of_vectors)
	75	GOT_ENTRY(transfer_to_handler)
	76
3b57fe0a	77	GOT_ENTRY(__init_end)
5b1d7137	78	GOT_ENTRY(_end)
5d232d0e	79	GOT_ENTRY(__bss_start)
5b1d7137 WD	80	END_GOT
	81
	82	/*
	83	* r3 - 1st arg to board_init(): IMMP pointer
	84	* r4 - 2nd arg to board_init(): boot flag
	85	*/
	86	.text
	87	.long 0x27051956 /* U-Boot Magic Number */
	88	.globl version_string
	89	version_string:
	90	.ascii U_BOOT_VERSION
561858ee	91	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
5b1d7137 WD	92	.ascii CONFIG_IDENT_STRING, "\0"
	93
	94	. = EXC_OFF_SYS_RESET
	95	.globl _start
	96	_start:
6d0f6bcf	97	lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
5b1d7137	98	mtspr 638, r3
5b1d7137 WD	99
	100	/* Initialize machine status; enable machine check interrupt */
	101	/----------------------------------------------------------------------/
	102	li r3, MSR_KERNEL /* Set ME, RI flags */
	103	mtmsr r3
	104	mtspr SRR1, r3 /* Make SRR1 match MSR */
	105
	106	mfspr r3, ICR /* clear Interrupt Cause Register */
	107
	108	/* Initialize debug port registers */
	109	/----------------------------------------------------------------------/
	110	xor r0, r0, r0 /* Clear R0 */
	111	mtspr LCTRL1, r0 /* Initialize debug port regs */
	112	mtspr LCTRL2, r0
	113	mtspr COUNTA, r0
	114	mtspr COUNTB, r0
	115
	116	/* Reset the caches */
	117	/----------------------------------------------------------------------/
	118
	119	mfspr r3, IC_CST /* Clear error bits */
	120	mfspr r3, DC_CST
	121
	122	lis r3, IDC_UNALL@h /* Unlock all */
	123	mtspr IC_CST, r3
	124	mtspr DC_CST, r3
	125
	126	lis r3, IDC_INVALL@h /* Invalidate all */
	127	mtspr IC_CST, r3
	128	mtspr DC_CST, r3
	129
	130	lis r3, IDC_DISABLE@h /* Disable data cache */
	131	mtspr DC_CST, r3
	132
506f3918	133	#if !defined(CONFIG_SYS_DELAYED_ICACHE)
5b1d7137 WD	134	/* On IP860 and PCU E,
	135	* we cannot enable IC yet
	136	*/
	137	lis r3, IDC_ENABLE@h /* Enable instruction cache */
	138	#endif
	139	mtspr IC_CST, r3
	140
	141	/* invalidate all tlb's */
	142	/----------------------------------------------------------------------/
	143
	144	tlbia
	145	isync
	146
	147	/*
	148	* Calculate absolute address in FLASH and jump there
	149	----------------------------------------------------------------------/
	150
6d0f6bcf JCPV	151	lis r3, CONFIG_SYS_MONITOR_BASE@h
6d0f6bcf JCPV	152	ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
5b1d7137 WD	153	addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	154	mtlr r3
	155	blr
	156
	157	in_flash:
	158
	159	/* initialize some SPRs that are hard to access from C */
	160	/----------------------------------------------------------------------/
	161
6d0f6bcf JCPV	162	lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
6d0f6bcf JCPV	163	ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
5b1d7137 WD	164	/* Note: R0 is still 0 here */
	165	stwu r0, -4(r1) /* clear final stack frame so that */
	166	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	167
	168	/*
	169	* Disable serialized ifetch and show cycles
	170	* (i.e. set processor to normal mode).
	171	* This is also a silicon bug workaround, see errata
	172	*/
	173
	174	li r2, 0x0007
	175	mtspr ICTRL, r2
	176
	177	/* Set up debug mode entry */
	178
6d0f6bcf JCPV	179	lis r2, CONFIG_SYS_DER@h
6d0f6bcf JCPV	180	ori r2, r2, CONFIG_SYS_DER@l
5b1d7137 WD	181	mtspr DER, r2
	182
	183	/* let the C-code set up the rest */
	184	/* */
	185	/* Be careful to keep code relocatable ! */
	186	/----------------------------------------------------------------------/
	187
	188	GET_GOT /* initialize GOT access */
	189
	190	/* r3: IMMR */
	191	bl cpu_init_f /* run low-level CPU init code (from Flash) */
	192
5b1d7137 WD	193	bl board_init_f /* run 1st part of board init code (from Flash) */
5b1d7137 WD	194
52ebd9c1 PT	195	/* NOTREACHED - board_init_f() does not return */
52ebd9c1 PT	196
5b1d7137	197
5b1d7137 WD	198	.globl _start_of_vectors
	199	_start_of_vectors:
	200
	201	/* Machine check */
	202	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	203
	204	/* Data Storage exception. "Never" generated on the 860. */
	205	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	206
	207	/* Instruction Storage exception. "Never" generated on the 860. */
	208	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	209
	210	/* External Interrupt exception. */
	211	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
	212
	213	/* Alignment exception. */
	214	. = 0x600
	215	Alignment:
02032e8f	216	EXCEPTION_PROLOG(SRR0, SRR1)
5b1d7137 WD	217	mfspr r4,DAR
	218	stw r4,_DAR(r21)
	219	mfspr r5,DSISR
	220	stw r5,_DSISR(r21)
	221	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887	222	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
5b1d7137 WD	223
	224	/* Program check exception */
	225	. = 0x700
	226	ProgramCheck:
02032e8f	227	EXCEPTION_PROLOG(SRR0, SRR1)
5b1d7137	228	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887 JT	229	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
fc4e1887 JT	230	MSR_KERNEL, COPY_EE)
5b1d7137 WD	231
	232	/* No FPU on MPC8xx. This exception is not supposed to happen.
	233	*/
	234	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	235
	236	/* I guess we could implement decrementer, and may have
	237	* to someday for timekeeping.
	238	*/
	239	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	240	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	241	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
27b207fd	242	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
5b1d7137 WD	243	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
	244
	245	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	246	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
	247
	248	/* On the MPC8xx, this is a software emulation interrupt. It occurs
	249	* for all unimplemented and illegal instructions.
	250	*/
	251	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	252
	253	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	254	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	255	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	256	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
	257
	258	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	259	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	260	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	261	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	262	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	263	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	264	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	265
	266	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	267	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	268	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	269	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
	270
	271
	272	.globl _end_of_vectors
	273	_end_of_vectors:
	274
	275
	276	. = 0x2000
	277
	278	/*
	279	* This code finishes saving the registers to the exception frame
	280	* and jumps to the appropriate handler for the exception.
	281	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	282	*/
	283	.globl transfer_to_handler
	284	transfer_to_handler:
	285	stw r22,_NIP(r21)
	286	lis r22,MSR_POW@h
	287	andc r23,r23,r22
	288	stw r23,_MSR(r21)
	289	SAVE_GPR(7, r21)
	290	SAVE_4GPRS(8, r21)
	291	SAVE_8GPRS(12, r21)
	292	SAVE_8GPRS(24, r21)
	293	mflr r23
	294	andi. r24,r23,0x3f00 /* get vector offset */
	295	stw r24,TRAP(r21)
	296	li r22,0
	297	stw r22,RESULT(r21)
	298	mtspr SPRG2,r22 /* r1 is now kernel sp */
	299	lwz r24,0(r23) /* virtual address of handler */
	300	lwz r23,4(r23) /* where to go when done */
	301	mtspr SRR0,r24
	302	mtspr SRR1,r20
	303	mtlr r23
	304	SYNC
	305	rfi /* jump to handler, enable MMU */
	306
307	int_return:
308	mfmsr r28 /* Disable interrupts */
309	li r4,0
310	ori r4,r4,MSR_EE
311	andc r28,r28,r4
312	SYNC /* Some chip revs need this... */
313	mtmsr r28
314	SYNC
315	lwz r2,_CTR(r1)
316	lwz r0,_LINK(r1)
317	mtctr r2
318	mtlr r0
319	lwz r2,_XER(r1)
320	lwz r0,_CCR(r1)
321	mtspr XER,r2
322	mtcrf 0xFF,r0
323	REST_10GPRS(3, r1)
324	REST_10GPRS(13, r1)
325	REST_8GPRS(23, r1)
326	REST_GPR(31, r1)
327	lwz r2,_NIP(r1) /* Restore environment */
328	lwz r0,_MSR(r1)
329	mtspr SRR0,r2
330	mtspr SRR1,r0
331	lwz r0,GPR0(r1)
332	lwz r2,GPR2(r1)
333	lwz r1,GPR1(r1)
334	SYNC
335	rfi
336
337	/* Cache functions.
338	*/
339	.globl icache_enable
340	icache_enable:
341	SYNC
342	lis r3, IDC_INVALL@h
343	mtspr IC_CST, r3
344	lis r3, IDC_ENABLE@h
345	mtspr IC_CST, r3
346	blr
347
348	.globl icache_disable
349	icache_disable:
350	SYNC
351	lis r3, IDC_DISABLE@h
352	mtspr IC_CST, r3
353	blr
354
355	.globl icache_status
356	icache_status:
357	mfspr r3, IC_CST
358	srwi r3, r3, 31 /* >>31 => select bit 0 */
359	blr
360
361	.globl dcache_enable
362	dcache_enable:
363	#if 0
364	SYNC
365	#endif
366	#if 1
367	lis r3, 0x0400 /* Set cache mode with MMU off */
368	mtspr MD_CTR, r3
369	#endif
370
371	lis r3, IDC_INVALL@h
372	mtspr DC_CST, r3
373	#if 0
374	lis r3, DC_SFWT@h
375	mtspr DC_CST, r3
376	#endif
377	lis r3, IDC_ENABLE@h
378	mtspr DC_CST, r3
379	blr
380
381	.globl dcache_disable
382	dcache_disable:
383	SYNC
384	lis r3, IDC_DISABLE@h
385	mtspr DC_CST, r3
386	lis r3, IDC_INVALL@h
387	mtspr DC_CST, r3
388	blr
389
390	.globl dcache_status
391	dcache_status:
392	mfspr r3, DC_CST
393	srwi r3, r3, 31 /* >>31 => select bit 0 */
394	blr
395
396	.globl dc_read
397	dc_read:
398	mtspr DC_ADR, r3
399	mfspr r3, DC_DAT
400	blr
401
402	/*
403	* unsigned int get_immr (unsigned int mask)
404	*
405	* return (mask ? (IMMR & mask) : IMMR);
406	*/
407	.globl get_immr
408	get_immr:
409	mr r4,r3 /* save mask */
410	mfspr r3, IMMR /* IMMR */
411	cmpwi 0,r4,0 /* mask != 0 ? */
412	beq 4f
413	and r3,r3,r4 /* IMMR & mask */
414	4:
415	blr
416
417	.globl get_pvr
418	get_pvr:
419	mfspr r3, PVR
420	blr
421
422
423	.globl wr_ic_cst
424	wr_ic_cst:
425	mtspr IC_CST, r3
426	blr
427
428	.globl rd_ic_cst
429	rd_ic_cst:
430	mfspr r3, IC_CST
431	blr
432
433	.globl wr_ic_adr
434	wr_ic_adr:
435	mtspr IC_ADR, r3
436	blr
437
438
439	.globl wr_dc_cst
440	wr_dc_cst:
441	mtspr DC_CST, r3
442	blr
443
444	.globl rd_dc_cst
445	rd_dc_cst:
446	mfspr r3, DC_CST
447	blr
448
449	.globl wr_dc_adr
450	wr_dc_adr:
451	mtspr DC_ADR, r3
452	blr
453
454	/------------------------------------------------------------------------------/
455
456	/*
457	* void relocate_code (addr_sp, gd, addr_moni)
458	*
459	* This "function" does not return, instead it continues in RAM
460	* after relocating the monitor code.
461	*
462	* r3 = dest
463	* r4 = src
464	* r5 = length in bytes
465	* r6 = cachelinesize
466	*/
467	.globl relocate_code
468	relocate_code:
469	mr r1, r3 /* Set new stack pointer */
470	mr r9, r4 /* Save copy of Global Data pointer */
471	mr r10, r5 /* Save copy of Destination Address */
472
0f8aa159	473	GET_GOT
5b1d7137	474	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	475	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	476	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
3b57fe0a WD	477	lwz r5, GOT(__init_end)
3b57fe0a WD	478	sub r5, r5, r4
6d0f6bcf	479	li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
5b1d7137 WD	480
	481	/*
	482	* Fix GOT pointer:
	483	*
6d0f6bcf	484	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
5b1d7137 WD	485	*
	486	* Offset:
	487	*/
	488	sub r15, r10, r4
	489
	490	/* First our own GOT */
0f8aa159	491	add r12, r12, r15
d0fb80c3	492	/* then the one used by the C code */
5b1d7137 WD	493	add r30, r30, r15
	494
	495	/*
	496	* Now relocate code
	497	*/
	498
	499	cmplw cr1,r3,r4
	500	addi r0,r5,3
	501	srwi. r0,r0,2
	502	beq cr1,4f /* In place copy is not necessary */
	503	beq 7f /* Protect against 0 count */
	504	mtctr r0
	505	bge cr1,2f
	506
	507	la r8,-4(r4)
	508	la r7,-4(r3)
	509	1: lwzu r0,4(r8)
	510	stwu r0,4(r7)
	511	bdnz 1b
	512	b 4f
	513
	514	2: slwi r0,r0,2
	515	add r8,r4,r0
	516	add r7,r3,r0
	517	3: lwzu r0,-4(r8)
	518	stwu r0,-4(r7)
	519	bdnz 3b
	520
	521	/*
	522	* Now flush the cache: note that we must start from a cache aligned
	523	* address. Otherwise we might miss one cache line.
	524	*/
	525	4: cmpwi r6,0
	526	add r5,r3,r5
	527	beq 7f /* Always flush prefetch queue in any case */
	528	subi r0,r6,1
	529	andc r3,r3,r0
	530	mr r4,r3
	531	5: dcbst 0,r4
	532	add r4,r4,r6
	533	cmplw r4,r5
	534	blt 5b
	535	sync /* Wait for all dcbst to complete on bus */
	536	mr r4,r3
	537	6: icbi 0,r4
	538	add r4,r4,r6
	539	cmplw r4,r5
	540	blt 6b
	541	7: sync /* Wait for all icbi to complete on bus */
	542	isync
	543
	544	/*
	545	* We are done. Do not return, instead branch to second part of board
	546	* initialization, now running from RAM.
	547	*/
	548
	549	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	550	mtlr r0
	551	blr
	552
	553	in_ram:
	554
	555	/*
0f8aa159	556	* Relocation Function, r12 point to got2+0x8000
5b1d7137	557	*
8bde7f77 WD	558	* Adjust got2 pointers, no need to check for 0, this code
8bde7f77 WD	559	* already puts a few entries in the table.
5b1d7137 WD	560	*/
	561	li r0,__got2_entries@sectoff@l
	562	la r3,GOT(_GOT2_TABLE_)
	563	lwz r11,GOT(_GOT2_TABLE_)
	564	mtctr r0
	565	sub r11,r3,r11
	566	addi r3,r3,-4
	567	1: lwzu r0,4(r3)
afc3ba0f JT	568	cmpwi r0,0
afc3ba0f JT	569	beq- 2f
5b1d7137 WD	570	add r0,r0,r11
5b1d7137 WD	571	stw r0,0(r3)
afc3ba0f	572	2: bdnz 1b
5b1d7137 WD	573
5b1d7137 WD	574	/*
8bde7f77	575	* Now adjust the fixups and the pointers to the fixups
5b1d7137 WD	576	* in case we need to move ourselves again.
5b1d7137 WD	577	*/
afc3ba0f	578	li r0,__fixup_entries@sectoff@l
5b1d7137 WD	579	lwz r3,GOT(_FIXUP_TABLE_)
	580	cmpwi r0,0
	581	mtctr r0
	582	addi r3,r3,-4
	583	beq 4f
	584	3: lwzu r4,4(r3)
	585	lwzux r0,r4,r11
	586	add r0,r0,r11
	587	stw r10,0(r3)
	588	stw r0,0(r4)
	589	bdnz 3b
	590	4:
	591	clear_bss:
	592	/*
	593	* Now clear BSS segment
	594	*/
5d232d0e	595	lwz r3,GOT(__bss_start)
5b1d7137	596	lwz r4,GOT(_end)
5b1d7137 WD	597
	598	cmplw 0, r3, r4
	599	beq 6f
	600
	601	li r0, 0
	602	5:
	603	stw r0, 0(r3)
	604	addi r3, r3, 4
	605	cmplw 0, r3, r4
	606	bne 5b
	607	6:
	608
	609	mr r3, r9 /* Global Data pointer */
	610	mr r4, r10 /* Destination Address */
	611	bl board_init_r
	612
5b1d7137 WD	613	/*
	614	* Copy exception vector code to low memory
	615	*
	616	* r3: dest_addr
	617	* r7: source address, r8: end address, r9: target address
	618	*/
	619	.globl trap_init
	620	trap_init:
0f8aa159 JT	621	mflr r4 /* save link register */
0f8aa159 JT	622	GET_GOT
5b1d7137 WD	623	lwz r7, GOT(_start)
	624	lwz r8, GOT(_end_of_vectors)
	625
682011ff	626	li r9, 0x100 /* reset vector always at 0x100 */
5b1d7137 WD	627
	628	cmplw 0, r7, r8
	629	bgelr /* return if r7>=r8 - just in case */
5b1d7137 WD	630	1:
	631	lwz r0, 0(r7)
	632	stw r0, 0(r9)
	633	addi r7, r7, 4
	634	addi r9, r9, 4
	635	cmplw 0, r7, r8
	636	bne 1b
	637
	638	/*
	639	* relocate `hdlr' and `int_return' entries
	640	*/
	641	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	642	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	643	2:
	644	bl trap_reloc
	645	addi r7, r7, 0x100 /* next exception vector */
	646	cmplw 0, r7, r8
	647	blt 2b
	648
	649	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	650	bl trap_reloc
	651
	652	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	653	bl trap_reloc
	654
	655	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	656	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	657	3:
	658	bl trap_reloc
	659	addi r7, r7, 0x100 /* next exception vector */
	660	cmplw 0, r7, r8
	661	blt 3b
	662
	663	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	664	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	665	4:
	666	bl trap_reloc
	667	addi r7, r7, 0x100 /* next exception vector */
	668	cmplw 0, r7, r8
	669	blt 4b
	670
	671	mtlr r4 /* restore link register */
	672	blr