]>
Commit | Line | Data |
---|---|---|
18bacc20 | 1 | /* |
b8cdd014 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
18bacc20 | 3 | * |
a47a12be SR |
4 | * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and |
5 | * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains | |
8d1f2682 | 6 | * cpu specific common code for 85xx/86xx processors. |
18bacc20 PA |
7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include <common.h> | |
28 | #include <command.h> | |
29 | #include <tsec.h> | |
30 | #include <netdev.h> | |
31 | #include <asm/cache.h> | |
32 | #include <asm/io.h> | |
33 | ||
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | struct cpu_type cpu_type_list [] = { | |
37 | #if defined(CONFIG_MPC85xx) | |
0e870980 PA |
38 | CPU_TYPE_ENTRY(8533, 8533, 1), |
39 | CPU_TYPE_ENTRY(8533, 8533_E, 1), | |
40 | CPU_TYPE_ENTRY(8535, 8535, 1), | |
41 | CPU_TYPE_ENTRY(8535, 8535_E, 1), | |
42 | CPU_TYPE_ENTRY(8536, 8536, 1), | |
43 | CPU_TYPE_ENTRY(8536, 8536_E, 1), | |
44 | CPU_TYPE_ENTRY(8540, 8540, 1), | |
45 | CPU_TYPE_ENTRY(8541, 8541, 1), | |
46 | CPU_TYPE_ENTRY(8541, 8541_E, 1), | |
47 | CPU_TYPE_ENTRY(8543, 8543, 1), | |
48 | CPU_TYPE_ENTRY(8543, 8543_E, 1), | |
49 | CPU_TYPE_ENTRY(8544, 8544, 1), | |
50 | CPU_TYPE_ENTRY(8544, 8544_E, 1), | |
51 | CPU_TYPE_ENTRY(8545, 8545, 1), | |
52 | CPU_TYPE_ENTRY(8545, 8545_E, 1), | |
53 | CPU_TYPE_ENTRY(8547, 8547_E, 1), | |
54 | CPU_TYPE_ENTRY(8548, 8548, 1), | |
55 | CPU_TYPE_ENTRY(8548, 8548_E, 1), | |
56 | CPU_TYPE_ENTRY(8555, 8555, 1), | |
57 | CPU_TYPE_ENTRY(8555, 8555_E, 1), | |
58 | CPU_TYPE_ENTRY(8560, 8560, 1), | |
59 | CPU_TYPE_ENTRY(8567, 8567, 1), | |
60 | CPU_TYPE_ENTRY(8567, 8567_E, 1), | |
61 | CPU_TYPE_ENTRY(8568, 8568, 1), | |
62 | CPU_TYPE_ENTRY(8568, 8568_E, 1), | |
63 | CPU_TYPE_ENTRY(8569, 8569, 1), | |
64 | CPU_TYPE_ENTRY(8569, 8569_E, 1), | |
65 | CPU_TYPE_ENTRY(8572, 8572, 2), | |
66 | CPU_TYPE_ENTRY(8572, 8572_E, 2), | |
b8cdd014 PA |
67 | CPU_TYPE_ENTRY(P1010, P1010, 1), |
68 | CPU_TYPE_ENTRY(P1010, P1010_E, 1), | |
a713ba92 PA |
69 | CPU_TYPE_ENTRY(P1011, P1011, 1), |
70 | CPU_TYPE_ENTRY(P1011, P1011_E, 1), | |
21608275 KG |
71 | CPU_TYPE_ENTRY(P1012, P1012, 1), |
72 | CPU_TYPE_ENTRY(P1012, P1012_E, 1), | |
73 | CPU_TYPE_ENTRY(P1013, P1013, 1), | |
67a719da | 74 | CPU_TYPE_ENTRY(P1013, P1013_E, 1), |
b5debec5 PA |
75 | CPU_TYPE_ENTRY(P1014, P1014_E, 1), |
76 | CPU_TYPE_ENTRY(P1014, P1014, 1), | |
093cffbe KG |
77 | CPU_TYPE_ENTRY(P1015, P1015_E, 1), |
78 | CPU_TYPE_ENTRY(P1015, P1015, 1), | |
79 | CPU_TYPE_ENTRY(P1016, P1016_E, 1), | |
80 | CPU_TYPE_ENTRY(P1016, P1016, 1), | |
67a719da RZ |
81 | CPU_TYPE_ENTRY(P1017, P1017, 1), |
82 | CPU_TYPE_ENTRY(P1017, P1017, 1), | |
87c7661b PA |
83 | CPU_TYPE_ENTRY(P1020, P1020, 2), |
84 | CPU_TYPE_ENTRY(P1020, P1020_E, 2), | |
21608275 KG |
85 | CPU_TYPE_ENTRY(P1021, P1021, 2), |
86 | CPU_TYPE_ENTRY(P1021, P1021_E, 2), | |
87 | CPU_TYPE_ENTRY(P1022, P1022, 2), | |
88 | CPU_TYPE_ENTRY(P1022, P1022_E, 2), | |
67a719da RZ |
89 | CPU_TYPE_ENTRY(P1023, P1023, 2), |
90 | CPU_TYPE_ENTRY(P1023, P1023_E, 2), | |
093cffbe KG |
91 | CPU_TYPE_ENTRY(P1024, P1024, 2), |
92 | CPU_TYPE_ENTRY(P1024, P1024_E, 2), | |
93 | CPU_TYPE_ENTRY(P1025, P1025, 2), | |
94 | CPU_TYPE_ENTRY(P1025, P1025_E, 2), | |
a713ba92 PA |
95 | CPU_TYPE_ENTRY(P2010, P2010, 1), |
96 | CPU_TYPE_ENTRY(P2010, P2010_E, 1), | |
97 | CPU_TYPE_ENTRY(P2020, P2020, 2), | |
98 | CPU_TYPE_ENTRY(P2020, P2020_E, 2), | |
f193e3da KG |
99 | CPU_TYPE_ENTRY(P2040, P2040, 4), |
100 | CPU_TYPE_ENTRY(P2040, P2040_E, 4), | |
c26de2d8 KG |
101 | CPU_TYPE_ENTRY(P3041, P3041, 4), |
102 | CPU_TYPE_ENTRY(P3041, P3041_E, 4), | |
7e4259bb KG |
103 | CPU_TYPE_ENTRY(P4040, P4040, 4), |
104 | CPU_TYPE_ENTRY(P4040, P4040_E, 4), | |
105 | CPU_TYPE_ENTRY(P4080, P4080, 8), | |
106 | CPU_TYPE_ENTRY(P4080, P4080_E, 8), | |
19dbcc96 KG |
107 | CPU_TYPE_ENTRY(P5010, P5010, 1), |
108 | CPU_TYPE_ENTRY(P5010, P5010_E, 1), | |
109 | CPU_TYPE_ENTRY(P5020, P5020, 2), | |
110 | CPU_TYPE_ENTRY(P5020, P5020_E, 2), | |
18bacc20 | 111 | #elif defined(CONFIG_MPC86xx) |
0e870980 PA |
112 | CPU_TYPE_ENTRY(8610, 8610, 1), |
113 | CPU_TYPE_ENTRY(8641, 8641, 2), | |
114 | CPU_TYPE_ENTRY(8641D, 8641D, 2), | |
18bacc20 PA |
115 | #endif |
116 | }; | |
117 | ||
58442dc0 PA |
118 | struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); |
119 | ||
18bacc20 PA |
120 | struct cpu_type *identify_cpu(u32 ver) |
121 | { | |
122 | int i; | |
123 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { | |
124 | if (cpu_type_list[i].soc_ver == ver) | |
125 | return &cpu_type_list[i]; | |
126 | } | |
58442dc0 | 127 | return &cpu_type_unknown; |
18bacc20 PA |
128 | } |
129 | ||
0e870980 | 130 | int cpu_numcores() { |
680c613a | 131 | ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; |
a37c36f4 KP |
132 | struct cpu_type *cpu = gd->cpu; |
133 | ||
134 | /* better to query feature reporting register than just assume 1 */ | |
680c613a KP |
135 | #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 |
136 | #define MPC8xxx_PICFRR_NCPU_SHIFT 8 | |
a37c36f4 | 137 | if (cpu == &cpu_type_unknown) |
680c613a KP |
138 | return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> |
139 | MPC8xxx_PICFRR_NCPU_SHIFT) + 1; | |
a37c36f4 | 140 | |
0e870980 PA |
141 | return cpu->num_cores; |
142 | } | |
143 | ||
144 | int probecpu (void) | |
145 | { | |
146 | uint svr; | |
147 | uint ver; | |
148 | ||
149 | svr = get_svr(); | |
150 | ver = SVR_SOC_VER(svr); | |
151 | ||
152 | gd->cpu = identify_cpu(ver); | |
153 | ||
0e870980 PA |
154 | return 0; |
155 | } | |
156 | ||
18bacc20 PA |
157 | /* |
158 | * Initializes on-chip ethernet controllers. | |
159 | * to override, implement board_eth_init() | |
160 | */ | |
161 | int cpu_eth_init(bd_t *bis) | |
162 | { | |
163 | #if defined(CONFIG_ETHER_ON_FCC) | |
164 | fec_initialize(bis); | |
165 | #endif | |
166 | ||
167 | #if defined(CONFIG_UEC_ETH) | |
168 | uec_standard_init(bis); | |
169 | #endif | |
170 | ||
171 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) | |
172 | tsec_standard_init(bis); | |
173 | #endif | |
174 | ||
175 | return 0; | |
176 | } |