[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc8xxx / srio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <config.h>
#include <log.h>
#include <time.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#include <linux/delay.h>
#include <linux/errno.h>

#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
#define SRIO_OB_ATMU_AR_RW 0x80045000
#define SRIO_LCSBA1CSR_OFFSET 0x5c
#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
#define SRIO_LCSBA1CSR 0x60000000
#endif

#if defined(CONFIG_FSL_CORENET)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
#else
	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
#endif
	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
	#define _DEVDISR_RMU   MPC86xx_DEVDISR_RMSG
	#define CFG_SYS_MPC8xxx_GUTS_ADDR \
		(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
#error "No defines for DEVDISR_SRIO"
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
/*
 * Erratum A-004034
 * Affects: SRIO
 * Description: During port initialization, the SRIO port performs
 * lane synchronization (detecting valid symbols on a lane) and
 * lane alignment (coordinating multiple lanes to receive valid data
 * across lanes). Internal errors in lane synchronization and lane
 * alignment may cause failure to achieve link initialization at
 * the configured port width.
 * An SRIO port configured as a 4x port may see one of these scenarios:
 * 1. One or more lanes fails to achieve lane synchronization. Depending
 * on which lanes fail, this may result in downtraining from 4x to 1x
 * on lane 0, 4x to 1x on lane R (redundant lane).
 * 2. The link may fail to achieve lane alignment as a 4x, even though
 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
 * An SRIO port configured as a 1x port may fail to complete port
 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
 * Impact: SRIO port may downtrain to 1x, or may fail to complete
 * link initialization. Once a port completes link initialization
 * successfully, it will operate normally.
 */
static int srio_erratum_a004034(u8 port)
{
	serdes_corenet_t *srds_regs;
	u32 conf_lane;
	u32 init_lane;
	int idx, first, last;
	u32 i;
	unsigned long long end_tick;
	struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;

	srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
	conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
			>> (12 - port * 4)) & 0x3;
	init_lane = (in_be32((void *)&srio_regs->lp_serial
			.port[port].pccsr) >> 27) & 0x7;

	/*
	 * Start a counter set to ~2 ms after the SERDES reset is
	 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
	 * corresponding to the SERDES bank/PLL for the SRIO port).
	 */
	 if (in_be32((void *)&srds_regs->bank[0].rstctl)
		& SRDS_RSTCTL_RSTDONE) {
		/*
		 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
		 * PO=1 or the counter expires. If the counter expires, the
		 * port has failed initialization: go to recover steps. If PO=1
		 * and the desired port width is 1x, go to normal steps. If
		 * PO = 1 and the desired port width is 4x, go to recover steps.
		 */
		end_tick = usec2ticks(2000) + get_ticks();
		do {
			if (in_be32((void *)&srio_regs->lp_serial
				.port[port].pescsr) & 0x2) {
				if (conf_lane == 0x1)
					goto host_ok;
				else {
					if (init_lane == 0x2)
						goto host_ok;
					else
						break;
				}
			}
		} while (end_tick > get_ticks());

		/* recover at most 3 times */
		for (i = 0; i < 3; i++) {
			/* Set SRIO PnCCSR[PD]=1 */
			setbits_be32((void *)&srio_regs->lp_serial
					.port[port].pccsr,
					0x800000);
			/*
			* Set SRIO PnPCR[OBDEN] on the host to
			* enable the discarding of any pending packets.
			*/
			setbits_be32((void *)&srio_regs->impl.port[port].pcr,
				0x04);
			/* Wait 50 us */
			udelay(50);
			/* Run sync command */
			isync();

			if (port)
				first = serdes_get_first_lane(SRIO2);
			else
				first = serdes_get_first_lane(SRIO1);
			if (unlikely(first < 0))
				return -ENODEV;
			if (conf_lane == 0x1)
				last = first;
			else
				last = first + 3;
			/*
			 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
			 * bank n and lane m.
			 */
			for (idx = first; idx <= last; idx++)
				clrbits_be32(&srds_regs->lane[idx].gcr0,
				SRDS_GCR0_RRST);
			/*
			 * Read SERDES BnGCRm0 for each SRIO
			 * bank n and lane m
			 */
			for (idx = first; idx <= last; idx++)
				in_be32(&srds_regs->lane[idx].gcr0);
			/* Run sync command */
			isync();
			/* Wait >= 100 ns */
			udelay(1);
			/*
			 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
			 * bank n and lane m.
			 */
			for (idx = first; idx <= last; idx++)
				setbits_be32(&srds_regs->lane[idx].gcr0,
				SRDS_GCR0_RRST);
			/*
			 * Read SERDES BnGCRm0 for each SRIO
			 * bank n and lane m
			 */
			for (idx = first; idx <= last; idx++)
				in_be32(&srds_regs->lane[idx].gcr0);
			/* Run sync command */
			isync();
			/* Wait >= 300 ns */
			udelay(1);

			/* Write 1 to clear all bits in SRIO PnSLCSR */
			out_be32((void *)&srio_regs->impl.port[port].slcsr,
				0xffffffff);
			/* Clear SRIO PnPCR[OBDEN] on the host */
			clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
				0x04);
			/* Set SRIO PnCCSR[PD]=0 */
			clrbits_be32((void *)&srio_regs->lp_serial
				.port[port].pccsr,
				0x800000);
			/* Wait >= 24 ms */
			udelay(24000);
			/* Poll the state of the port again */
			init_lane =
				(in_be32((void *)&srio_regs->lp_serial
					.port[port].pccsr) >> 27) & 0x7;
			if (in_be32((void *)&srio_regs->lp_serial
				.port[port].pescsr) & 0x2) {
				if (conf_lane == 0x1)
					goto host_ok;
				else {
					if (init_lane == 0x2)
						goto host_ok;
				}
			}
			if (i == 2)
				return -ENODEV;
		}
	} else
		return -ENODEV;

host_ok:
	/* Poll PnESCSR[OES] on the host until it is clear */
	end_tick = usec2ticks(1000000) + get_ticks();
	do {
		if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
			& 0x10000)) {
			out_be32(((void *)&srio_regs->lp_serial
				.port[port].pescsr), 0xffffffff);
			out_be32(((void *)&srio_regs->phys_err
				.port[port].edcsr), 0);
			out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
			return 0;
		}
	} while (end_tick > get_ticks());

	return -ENODEV;
}
#endif

void srio_init(void)
{
	ccsr_gur_t *gur = (void *)CFG_SYS_MPC8xxx_GUTS_ADDR;
	int srio1_used = 0, srio2_used = 0;
	u32 *devdisr;

#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	devdisr = &gur->devdisr3;
#else
	devdisr = &gur->devdisr;
#endif
	if (is_serdes_configured(SRIO1)) {
		set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
				law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
				LAW_TRGT_IF_RIO_1);
		srio1_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
		if (srio_erratum_a004034(0) < 0)
			printf("SRIO1: enabled but port error\n");
		else
#endif
		printf("SRIO1: enabled\n");
	} else {
		printf("SRIO1: disabled\n");
	}

#ifdef CONFIG_SRIO2
	if (is_serdes_configured(SRIO2)) {
		set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
				law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
				LAW_TRGT_IF_RIO_2);
		srio2_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
		if (srio_erratum_a004034(1) < 0)
			printf("SRIO2: enabled but port error\n");
		else
#endif
		printf("SRIO2: enabled\n");

	} else {
		printf("SRIO2: disabled\n");
	}
#endif

#ifdef CONFIG_FSL_CORENET
	/* On FSL_CORENET devices we can disable individual ports */
	if (!srio1_used)
		setbits_be32(devdisr, _DEVDISR_SRIO1);
	if (!srio2_used)
		setbits_be32(devdisr, _DEVDISR_SRIO2);
#endif

	/* neither port is used - disable everything */
	if (!srio1_used && !srio2_used) {
		setbits_be32(devdisr, _DEVDISR_SRIO1);
		setbits_be32(devdisr, _DEVDISR_SRIO2);
		setbits_be32(devdisr, _DEVDISR_RMU);
	}
}

#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
	struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;

	/* set port accept-all */
	out_be32((void *)&srio->impl.port[port - 1].ptaacr,
				SRIO_PORT_ACCEPT_ALL);

	debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
	/* configure inbound window for slave's u-boot image */
	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
			SRIO_IB_ATMU_AR
			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));

	/* configure inbound window for slave's u-boot image */
	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
			SRIO_IB_ATMU_AR
			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));

	/* configure inbound window for slave's ucode and ENV */
	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
			CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
			SRIO_IB_ATMU_AR
			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
}

void srio_boot_master_release_slave(int port)
{
	struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
	u32 escsr;
	debug("SRIOBOOT - MASTER: "
			"Check the port status and release slave core ...\n");

	escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
	if (escsr & 0x2) {
		if (escsr & 0x10100) {
			debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
				port);
		} else {
			debug("SRIOBOOT - MASTER: "
				"Port [ %d ] is ready, now release slave's core ...\n",
				port);
			/*
			 * configure outbound window
			 * with maintenance attribute to set slave's LCSBA1CSR
			 */
			out_be32((void *)&srio->atmu.port[port - 1]
				.outbw[1].rowtar, 0);
			out_be32((void *)&srio->atmu.port[port - 1]
				.outbw[1].rowtear, 0);
			if (port - 1)
				out_be32((void *)&srio->atmu.port[port - 1]
					.outbw[1].rowbar,
					CFG_SYS_SRIO2_MEM_PHYS >> 12);
			else
				out_be32((void *)&srio->atmu.port[port - 1]
					.outbw[1].rowbar,
					CFG_SYS_SRIO1_MEM_PHYS >> 12);
			out_be32((void *)&srio->atmu.port[port - 1]
					.outbw[1].rowar,
					SRIO_OB_ATMU_AR_MAINT
					| atmu_size_mask(SRIO_MAINT_WIN_SIZE));

			/*
			 * configure outbound window
			 * with R/W attribute to set slave's BRR
			 */
			out_be32((void *)&srio->atmu.port[port - 1]
				.outbw[2].rowtar,
				SRIO_LCSBA1CSR >> 9);
			out_be32((void *)&srio->atmu.port[port - 1]
				.outbw[2].rowtear, 0);
			if (port - 1)
				out_be32((void *)&srio->atmu.port[port - 1]
					.outbw[2].rowbar,
					(CFG_SYS_SRIO2_MEM_PHYS
					+ SRIO_MAINT_WIN_SIZE) >> 12);
			else
				out_be32((void *)&srio->atmu.port[port - 1]
					.outbw[2].rowbar,
					(CFG_SYS_SRIO1_MEM_PHYS
					+ SRIO_MAINT_WIN_SIZE) >> 12);
			out_be32((void *)&srio->atmu.port[port - 1]
				.outbw[2].rowar,
				SRIO_OB_ATMU_AR_RW
				| atmu_size_mask(SRIO_RW_WIN_SIZE));

			/*
			 * Set the LCSBA1CSR register in slave
			 * by the maint-outbound window
			 */
			if (port - 1) {
				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
					+ SRIO_LCSBA1CSR_OFFSET,
					SRIO_LCSBA1CSR);
				while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
					+ SRIO_LCSBA1CSR_OFFSET)
					!= SRIO_LCSBA1CSR)
					;
				/*
				 * And then set the BRR register
				 * to release slave core
				 */
				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
					+ SRIO_MAINT_WIN_SIZE
					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
			} else {
				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
					+ SRIO_LCSBA1CSR_OFFSET,
					SRIO_LCSBA1CSR);
				while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
					+ SRIO_LCSBA1CSR_OFFSET)
					!= SRIO_LCSBA1CSR)
					;
				/*
				 * And then set the BRR register
				 * to release slave core
				 */
				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
					+ SRIO_MAINT_WIN_SIZE
					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
			}
			debug("SRIOBOOT - MASTER: "
					"Release slave successfully! Now the slave should start up!\n");
		}
	} else
		debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a09b9b68 KG	2	/*
a09b9b68 KG	3	* Copyright 2011 Freescale Semiconductor, Inc.
a09b9b68 KG	4	*/
a09b9b68 KG	5
d678a59d	6	#include <common.h>
6a718588	7	#include <config.h>
f7ae49fc	8	#include <log.h>
6887c5be	9	#include <time.h>
a09b9b68 KG	10	#include <asm/fsl_law.h>
a09b9b68 KG	11	#include <asm/fsl_serdes.h>
5ffa88ec	12	#include <asm/fsl_srio.h>
c05ed00a	13	#include <linux/delay.h>
1221ce45	14	#include <linux/errno.h>
5ffa88ec	15
c8b28152	16	#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
5ffa88ec LG	17	#define SRIO_PORT_ACCEPT_ALL 0x10000001
5ffa88ec LG	18	#define SRIO_IB_ATMU_AR 0x80f55000
5056c8e0 LG	19	#define SRIO_OB_ATMU_AR_MAINT 0x80077000
	20	#define SRIO_OB_ATMU_AR_RW 0x80045000
	21	#define SRIO_LCSBA1CSR_OFFSET 0x5c
	22	#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
	23	#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
	24	#define SRIO_LCSBA1CSR 0x60000000
19e4a009	25	#endif
a09b9b68 KG	26
a09b9b68 KG	27	#if defined(CONFIG_FSL_CORENET)
9e758758 YS	28	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	29	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
	30	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
	31	#else
a09b9b68 KG	32	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
a09b9b68 KG	33	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
9e758758	34	#endif
a09b9b68	35	#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
f3b51685	36	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
a09b9b68 KG	37	#elif defined(CONFIG_MPC85xx)
	38	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
	39	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
	40	#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
f3b51685	41	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
a09b9b68 KG	42	#elif defined(CONFIG_MPC86xx)
	43	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
	44	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
	45	#define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
f3b51685	46	#define CFG_SYS_MPC8xxx_GUTS_ADDR \
a09b9b68 KG	47	(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
	48	#else
	49	#error "No defines for DEVDISR_SRIO"
	50	#endif
	51
d59c5570 LG	52	#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
	53	/*
	54	* Erratum A-004034
	55	* Affects: SRIO
	56	* Description: During port initialization, the SRIO port performs
	57	* lane synchronization (detecting valid symbols on a lane) and
	58	* lane alignment (coordinating multiple lanes to receive valid data
	59	* across lanes). Internal errors in lane synchronization and lane
	60	* alignment may cause failure to achieve link initialization at
	61	* the configured port width.
	62	* An SRIO port configured as a 4x port may see one of these scenarios:
	63	* 1. One or more lanes fails to achieve lane synchronization. Depending
	64	* on which lanes fail, this may result in downtraining from 4x to 1x
	65	* on lane 0, 4x to 1x on lane R (redundant lane).
	66	* 2. The link may fail to achieve lane alignment as a 4x, even though
	67	* all 4 lanes achieve lane synchronization, and downtrain to a 1x.
	68	* An SRIO port configured as a 1x port may fail to complete port
	69	* initialization (PnESCSR[PU] never deasserts) because of scenario 1.
	70	* Impact: SRIO port may downtrain to 1x, or may fail to complete
	71	* link initialization. Once a port completes link initialization
	72	* successfully, it will operate normally.
	73	*/
	74	static int srio_erratum_a004034(u8 port)
	75	{
	76	serdes_corenet_t *srds_regs;
	77	u32 conf_lane;
	78	u32 init_lane;
	79	int idx, first, last;
	80	u32 i;
	81	unsigned long long end_tick;
6cc04547	82	struct ccsr_rio srio_regs = (void )CFG_SYS_FSL_SRIO_ADDR;
d59c5570	83
6cc04547	84	srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
d59c5570 LG	85	conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
	86	>> (12 - port * 4)) & 0x3;
	87	init_lane = (in_be32((void *)&srio_regs->lp_serial
	88	.port[port].pccsr) >> 27) & 0x7;
	89
	90	/*
	91	* Start a counter set to ~2 ms after the SERDES reset is
	92	* complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
	93	* corresponding to the SERDES bank/PLL for the SRIO port).
	94	*/
	95	if (in_be32((void *)&srds_regs->bank[0].rstctl)
	96	& SRDS_RSTCTL_RSTDONE) {
	97	/*
	98	* Poll the port uninitialized status (SRIO PnESCSR[PO]) until
	99	* PO=1 or the counter expires. If the counter expires, the
	100	* port has failed initialization: go to recover steps. If PO=1
	101	* and the desired port width is 1x, go to normal steps. If
	102	* PO = 1 and the desired port width is 4x, go to recover steps.
	103	*/
	104	end_tick = usec2ticks(2000) + get_ticks();
	105	do {
	106	if (in_be32((void *)&srio_regs->lp_serial
	107	.port[port].pescsr) & 0x2) {
	108	if (conf_lane == 0x1)
	109	goto host_ok;
	110	else {
	111	if (init_lane == 0x2)
	112	goto host_ok;
	113	else
	114	break;
	115	}
	116	}
	117	} while (end_tick > get_ticks());
	118
	119	/* recover at most 3 times */
	120	for (i = 0; i < 3; i++) {
	121	/* Set SRIO PnCCSR[PD]=1 */
	122	setbits_be32((void *)&srio_regs->lp_serial
	123	.port[port].pccsr,
	124	0x800000);
	125	/*
	126	* Set SRIO PnPCR[OBDEN] on the host to
	127	* enable the discarding of any pending packets.
	128	*/
	129	setbits_be32((void *)&srio_regs->impl.port[port].pcr,
	130	0x04);
	131	/* Wait 50 us */
	132	udelay(50);
	133	/* Run sync command */
	134	isync();
	135
	136	if (port)
	137	first = serdes_get_first_lane(SRIO2);
	138	else
	139	first = serdes_get_first_lane(SRIO1);
	140	if (unlikely(first < 0))
	141	return -ENODEV;
	142	if (conf_lane == 0x1)
	143	last = first;
	144	else
	145	last = first + 3;
	146	/*
	147	* Set SERDES BnGCRm0[RRST]=0 for each SRIO
	148	* bank n and lane m.
149	*/
150	for (idx = first; idx <= last; idx++)
151	clrbits_be32(&srds_regs->lane[idx].gcr0,
152	SRDS_GCR0_RRST);
153	/*
154	* Read SERDES BnGCRm0 for each SRIO
155	* bank n and lane m
156	*/
157	for (idx = first; idx <= last; idx++)
158	in_be32(&srds_regs->lane[idx].gcr0);
159	/* Run sync command */
160	isync();
161	/* Wait >= 100 ns */
162	udelay(1);
163	/*
164	* Set SERDES BnGCRm0[RRST]=1 for each SRIO
165	* bank n and lane m.
166	*/
167	for (idx = first; idx <= last; idx++)
168	setbits_be32(&srds_regs->lane[idx].gcr0,
169	SRDS_GCR0_RRST);
170	/*
171	* Read SERDES BnGCRm0 for each SRIO
172	* bank n and lane m
173	*/
174	for (idx = first; idx <= last; idx++)
175	in_be32(&srds_regs->lane[idx].gcr0);
176	/* Run sync command */
177	isync();
178	/* Wait >= 300 ns */
179	udelay(1);
180
181	/* Write 1 to clear all bits in SRIO PnSLCSR */
182	out_be32((void *)&srio_regs->impl.port[port].slcsr,
183	0xffffffff);
184	/* Clear SRIO PnPCR[OBDEN] on the host */
185	clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
186	0x04);
187	/* Set SRIO PnCCSR[PD]=0 */
188	clrbits_be32((void *)&srio_regs->lp_serial
189	.port[port].pccsr,
190	0x800000);
191	/* Wait >= 24 ms */
192	udelay(24000);
193	/* Poll the state of the port again */
194	init_lane =
195	(in_be32((void *)&srio_regs->lp_serial
196	.port[port].pccsr) >> 27) & 0x7;
197	if (in_be32((void *)&srio_regs->lp_serial
198	.port[port].pescsr) & 0x2) {
199	if (conf_lane == 0x1)
200	goto host_ok;
201	else {
202	if (init_lane == 0x2)
203	goto host_ok;
204	}
205	}
206	if (i == 2)
207	return -ENODEV;
208	}
209	} else
210	return -ENODEV;
211
212	host_ok:
213	/* Poll PnESCSR[OES] on the host until it is clear */
214	end_tick = usec2ticks(1000000) + get_ticks();
215	do {
216	if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
217	& 0x10000)) {
218	out_be32(((void *)&srio_regs->lp_serial
219	.port[port].pescsr), 0xffffffff);
220	out_be32(((void *)&srio_regs->phys_err
221	.port[port].edcsr), 0);
222	out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
223	return 0;
224	}
225	} while (end_tick > get_ticks());
226
227	return -ENODEV;
228	}
229	#endif
230
a09b9b68 KG	231	void srio_init(void)
a09b9b68 KG	232	{
f3b51685	233	ccsr_gur_t gur = (void )CFG_SYS_MPC8xxx_GUTS_ADDR;
a09b9b68	234	int srio1_used = 0, srio2_used = 0;
9e758758	235	u32 *devdisr;
a09b9b68	236
9e758758 YS	237	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	238	devdisr = &gur->devdisr3;
	239	#else
	240	devdisr = &gur->devdisr;
	241	#endif
a09b9b68	242	if (is_serdes_configured(SRIO1)) {
a322afc9 TR	243	set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
a322afc9 TR	244	law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
a09b9b68 KG	245	LAW_TRGT_IF_RIO_1);
a09b9b68 KG	246	srio1_used = 1;
d59c5570 LG	247	#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
	248	if (srio_erratum_a004034(0) < 0)
	249	printf("SRIO1: enabled but port error\n");
	250	else
	251	#endif
a09b9b68 KG	252	printf("SRIO1: enabled\n");
	253	} else {
	254	printf("SRIO1: disabled\n");
	255	}
	256
	257	#ifdef CONFIG_SRIO2
	258	if (is_serdes_configured(SRIO2)) {
a322afc9 TR	259	set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
a322afc9 TR	260	law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
a09b9b68 KG	261	LAW_TRGT_IF_RIO_2);
a09b9b68 KG	262	srio2_used = 1;
d59c5570 LG	263	#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
	264	if (srio_erratum_a004034(1) < 0)
	265	printf("SRIO2: enabled but port error\n");
	266	else
	267	#endif
a09b9b68	268	printf("SRIO2: enabled\n");
d59c5570	269
a09b9b68 KG	270	} else {
	271	printf("SRIO2: disabled\n");
	272	}
	273	#endif
	274
	275	#ifdef CONFIG_FSL_CORENET
	276	/* On FSL_CORENET devices we can disable individual ports */
	277	if (!srio1_used)
9e758758	278	setbits_be32(devdisr, _DEVDISR_SRIO1);
a09b9b68	279	if (!srio2_used)
9e758758	280	setbits_be32(devdisr, _DEVDISR_SRIO2);
a09b9b68 KG	281	#endif
	282
	283	/* neither port is used - disable everything */
	284	if (!srio1_used && !srio2_used) {
9e758758 YS	285	setbits_be32(devdisr, _DEVDISR_SRIO1);
	286	setbits_be32(devdisr, _DEVDISR_SRIO2);
	287	setbits_be32(devdisr, _DEVDISR_RMU);
a09b9b68 KG	288	}
a09b9b68 KG	289	}
5ffa88ec	290
c8b28152	291	#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
ff65f126	292	void srio_boot_master(int port)
5ffa88ec	293	{
6cc04547	294	struct ccsr_rio srio = (void )CFG_SYS_FSL_SRIO_ADDR;
5ffa88ec LG	295
5ffa88ec LG	296	/* set port accept-all */
ff65f126	297	out_be32((void *)&srio->impl.port[port - 1].ptaacr,
5ffa88ec LG	298	SRIO_PORT_ACCEPT_ALL);
5ffa88ec LG	299
ff65f126	300	debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
3f1af81b LG	301	/* configure inbound window for slave's u-boot image */
3f1af81b LG	302	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
5ffa88ec	303	"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
a322afc9 TR	304	(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
	305	(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
	306	CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
ff65f126	307	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
a322afc9	308	CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
ff65f126	309	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
a322afc9	310	CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
ff65f126	311	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
5ffa88ec	312	SRIO_IB_ATMU_AR
a322afc9	313	\| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
5ffa88ec	314
3f1af81b LG	315	/* configure inbound window for slave's u-boot image */
3f1af81b LG	316	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
5ffa88ec	317	"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
a322afc9 TR	318	(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
	319	(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
	320	CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
ff65f126	321	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
a322afc9	322	CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
ff65f126	323	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
a322afc9	324	CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
ff65f126	325	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
5ffa88ec	326	SRIO_IB_ATMU_AR
a322afc9	327	\| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
3f1af81b	328
ff65f126 LG	329	/* configure inbound window for slave's ucode and ENV */
ff65f126 LG	330	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
3f1af81b	331	"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
a322afc9 TR	332	(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
	333	(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
	334	CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
ff65f126	335	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
a322afc9	336	CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
ff65f126	337	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
a322afc9	338	CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
ff65f126	339	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
0a85a9e7	340	SRIO_IB_ATMU_AR
a322afc9	341	\| atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
5ffa88ec	342	}
5056c8e0	343
ff65f126	344	void srio_boot_master_release_slave(int port)
5056c8e0	345	{
6cc04547	346	struct ccsr_rio srio = (void )CFG_SYS_FSL_SRIO_ADDR;
5056c8e0 LG	347	u32 escsr;
	348	debug("SRIOBOOT - MASTER: "
	349	"Check the port status and release slave core ...\n");
	350
ff65f126	351	escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
5056c8e0 LG	352	if (escsr & 0x2) {
	353	if (escsr & 0x10100) {
	354	debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
ff65f126	355	port);
5056c8e0 LG	356	} else {
5056c8e0 LG	357	debug("SRIOBOOT - MASTER: "
ff65f126 LG	358	"Port [ %d ] is ready, now release slave's core ...\n",
ff65f126 LG	359	port);
5056c8e0 LG	360	/*
	361	* configure outbound window
	362	* with maintenance attribute to set slave's LCSBA1CSR
	363	*/
ff65f126	364	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	365	.outbw[1].rowtar, 0);
ff65f126	366	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	367	.outbw[1].rowtear, 0);
ff65f126 LG	368	if (port - 1)
ff65f126 LG	369	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	370	.outbw[1].rowbar,
a322afc9	371	CFG_SYS_SRIO2_MEM_PHYS >> 12);
5056c8e0	372	else
ff65f126	373	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	374	.outbw[1].rowbar,
a322afc9	375	CFG_SYS_SRIO1_MEM_PHYS >> 12);
ff65f126	376	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0 LG	377	.outbw[1].rowar,
	378	SRIO_OB_ATMU_AR_MAINT
	379	\| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
	380
	381	/*
	382	* configure outbound window
	383	* with R/W attribute to set slave's BRR
	384	*/
ff65f126	385	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0 LG	386	.outbw[2].rowtar,
5056c8e0 LG	387	SRIO_LCSBA1CSR >> 9);
ff65f126	388	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	389	.outbw[2].rowtear, 0);
ff65f126 LG	390	if (port - 1)
ff65f126 LG	391	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	392	.outbw[2].rowbar,
a322afc9	393	(CFG_SYS_SRIO2_MEM_PHYS
5056c8e0 LG	394	+ SRIO_MAINT_WIN_SIZE) >> 12);
5056c8e0 LG	395	else
ff65f126	396	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0	397	.outbw[2].rowbar,
a322afc9	398	(CFG_SYS_SRIO1_MEM_PHYS
5056c8e0	399	+ SRIO_MAINT_WIN_SIZE) >> 12);
ff65f126	400	out_be32((void *)&srio->atmu.port[port - 1]
5056c8e0 LG	401	.outbw[2].rowar,
	402	SRIO_OB_ATMU_AR_RW
	403	\| atmu_size_mask(SRIO_RW_WIN_SIZE));
	404
	405	/*
	406	* Set the LCSBA1CSR register in slave
	407	* by the maint-outbound window
	408	*/
ff65f126	409	if (port - 1) {
a322afc9	410	out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
5056c8e0 LG	411	+ SRIO_LCSBA1CSR_OFFSET,
5056c8e0 LG	412	SRIO_LCSBA1CSR);
a322afc9	413	while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
5056c8e0 LG	414	+ SRIO_LCSBA1CSR_OFFSET)
	415	!= SRIO_LCSBA1CSR)
	416	;
	417	/*
	418	* And then set the BRR register
	419	* to release slave core
	420	*/
a322afc9	421	out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
5056c8e0	422	+ SRIO_MAINT_WIN_SIZE
a322afc9 TR	423	+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
a322afc9 TR	424	CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
5056c8e0	425	} else {
a322afc9	426	out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
5056c8e0 LG	427	+ SRIO_LCSBA1CSR_OFFSET,
5056c8e0 LG	428	SRIO_LCSBA1CSR);
a322afc9	429	while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
5056c8e0 LG	430	+ SRIO_LCSBA1CSR_OFFSET)
	431	!= SRIO_LCSBA1CSR)
	432	;
	433	/*
	434	* And then set the BRR register
	435	* to release slave core
	436	*/
a322afc9	437	out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
5056c8e0	438	+ SRIO_MAINT_WIN_SIZE
a322afc9 TR	439	+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
a322afc9 TR	440	CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
5056c8e0 LG	441	}
	442	debug("SRIOBOOT - MASTER: "
	443	"Release slave successfully! Now the slave should start up!\n");
	444	}
	445	} else
ff65f126	446	debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
5056c8e0 LG	447	}
5056c8e0 LG	448	#endif