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[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c
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4037ed3b 1/*
a47a12be 2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
4037ed3b 3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
ea9202a6
SR		 4 * DDR2 controller (non Denali Core). Those currently are:
5 *
c821b5f1 6 * 405: 405EX(r)
ea9202a6 7 * 440/460: 440SP/440SPe/460EX/460GT
4037ed3b 8 *
c821b5f1
GE		 9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
11
fb95169e 12 * (C) Copyright 2007-2009
4037ed3b
SR		 13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
15 * COPYRIGHT AMCC CORPORATION 2004
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 *
35 */
36
37/* define DEBUG for debugging output (obviously ;-)) */
38#if 0
39#define DEBUG
40#endif
41
42#include <common.h>
ba58e4c9 43#include <command.h>
b36df561 44#include <asm/ppc4xx.h>
4037ed3b
SR		 45#include <i2c.h>
46#include <asm/io.h>
47#include <asm/processor.h>
48#include <asm/mmu.h>
85ad184b 49#include <asm/cache.h>
4037ed3b 50
fb95169e
SR		 51#include "ecc.h"
52
08250eb2
SR		 53#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
54 do { \
55 u32 data; \
56 mfsdram(SDRAM_##mnemonic, data); \
57 printf("%20s[%02x] = 0x%08X\n", \
58 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
59 } while (0)
60
48e2b535
FR		 61#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
62 do { \
63 u32 data; \
64 data = mfdcr(SDRAM_##mnemonic); \
65 printf("%20s[%02x] = 0x%08X\n", \
66 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
67 } while (0)
68
e9c020df
SR		 69#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
70static void update_rdcc(void)
71{
72 u32 val;
73
74 /*
75 * Complete RDSS configuration as mentioned on page 7 of the AMCC
76 * PowerPC440SP/SPe DDR2 application note:
77 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
78 *
79 * Or item #10 "10. Complete RDSS configuration" in chapter
80 * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
81 * manual.
82 */
83 mfsdram(SDRAM_RTSR, val);
84 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
85 mfsdram(SDRAM_RDCC, val);
86 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
87 val += 0x40000000;
88 mtsdram(SDRAM_RDCC, val);
89 }
90 }
91}
92#endif
93
59217bae
AG		 94#if defined(CONFIG_440)
95/*
96 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
97 * memory region. Right now the cache should still be disabled in U-Boot
98 * because of the EMAC driver, that need its buffer descriptor to be located
99 * in non cached memory.
100 *
101 * If at some time this restriction doesn't apply anymore, just define
102 * CONFIG_4xx_DCACHE in the board config file and this code should setup
103 * everything correctly.
104 */
105#ifdef CONFIG_4xx_DCACHE
106/* enable caching on SDRAM */
107#define MY_TLB_WORD2_I_ENABLE 0
108#else
109/* disable caching on SDRAM */
110#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
111#endif /* CONFIG_4xx_DCACHE */
d24bd251
FR		 112
113void dcbz_area(u32 start_address, u32 num_bytes);
59217bae
AG		 114#endif /* CONFIG_440 */
115
d24bd251
FR		 116#define MAXRANKS 4
117#define MAXBXCF 4
118
119#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
120
fb95169e 121#if !defined(CONFIG_NAND_SPL)
d24bd251
FR		 122/*-----------------------------------------------------------------------------+
123 * sdram_memsize
124 *-----------------------------------------------------------------------------*/
fb95169e 125phys_size_t sdram_memsize(void)
d24bd251
FR		 126{
127 phys_size_t mem_size;
128 unsigned long mcopt2;
129 unsigned long mcstat;
130 unsigned long mb0cf;
131 unsigned long sdsz;
132 unsigned long i;
133
134 mem_size = 0;
135
136 mfsdram(SDRAM_MCOPT2, mcopt2);
137 mfsdram(SDRAM_MCSTAT, mcstat);
138
139 /* DDR controller must be enabled and not in self-refresh. */
140 /* Otherwise memsize is zero. */
141 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
142 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
143 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
144 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
145 for (i = 0; i < MAXBXCF; i++) {
146 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
147 /* Banks enabled */
148 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
149#if defined(CONFIG_440)
150 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
151#else
152 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
153#endif
154 switch(sdsz) {
155 case SDRAM_RXBAS_SDSZ_8:
156 mem_size+=8;
157 break;
158 case SDRAM_RXBAS_SDSZ_16:
159 mem_size+=16;
160 break;
161 case SDRAM_RXBAS_SDSZ_32:
162 mem_size+=32;
163 break;
164 case SDRAM_RXBAS_SDSZ_64:
165 mem_size+=64;
166 break;
167 case SDRAM_RXBAS_SDSZ_128:
168 mem_size+=128;
169 break;
170 case SDRAM_RXBAS_SDSZ_256:
171 mem_size+=256;
172 break;
173 case SDRAM_RXBAS_SDSZ_512:
174 mem_size+=512;
175 break;
176 case SDRAM_RXBAS_SDSZ_1024:
177 mem_size+=1024;
178 break;
179 case SDRAM_RXBAS_SDSZ_2048:
180 mem_size+=2048;
181 break;
182 case SDRAM_RXBAS_SDSZ_4096:
183 mem_size+=4096;
184 break;
185 default:
186 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
187 , sdsz);
188 mem_size=0;
189 break;
190 }
191 }
192 }
193 }
194
195 return mem_size << 20;
196}
197
fb95169e
SR		 198/*-----------------------------------------------------------------------------+
199 * is_ecc_enabled
200 *-----------------------------------------------------------------------------*/
201static unsigned long is_ecc_enabled(void)
202{
203 unsigned long val;
204
205 mfsdram(SDRAM_MCOPT1, val);
206
207 return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
208}
209
d24bd251
FR		 210/*-----------------------------------------------------------------------------+
211 * board_add_ram_info
212 *-----------------------------------------------------------------------------*/
213void board_add_ram_info(int use_default)
214{
215 PPC4xx_SYS_INFO board_cfg;
216 u32 val;
217
218 if (is_ecc_enabled())
219 puts(" (ECC");
220 else
221 puts(" (ECC not");
222
223 get_sys_info(&board_cfg);
224
fb95169e
SR		 225#if defined(CONFIG_405EX)
226 val = board_cfg.freqPLB;
227#else
d24bd251
FR		 228 mfsdr(SDR0_DDR0, val);
229 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
d24bd251
FR		 230#endif
231 printf(" enabled, %d MHz", (val * 2) / 1000000);
232
233 mfsdram(SDRAM_MMODE, val);
234 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
235 printf(", CL%d)", val);
236}
fb95169e 237#endif /* !CONFIG_NAND_SPL */
d24bd251 238
08250eb2 239#if defined(CONFIG_SPD_EEPROM)
4037ed3b 240
ba58e4c9
SR		 241/*-----------------------------------------------------------------------------+
242 * Defines
243 *-----------------------------------------------------------------------------*/
4037ed3b 244#ifndef TRUE
74357114 245#define TRUE 1
4037ed3b
SR		 246#endif
247#ifndef FALSE
74357114 248#define FALSE 0
4037ed3b
SR		 249#endif
250
251#define SDRAM_DDR1 1
252#define SDRAM_DDR2 2
253#define SDRAM_NONE 0
254
1636d1c8 255#define MAXDIMMS 2
4037ed3b
SR		 256#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
257
258#define ONE_BILLION 1000000000
259
ba58e4c9
SR		 260#define CMD_NOP (7 << 19)
261#define CMD_PRECHARGE (2 << 19)
262#define CMD_REFRESH (1 << 19)
263#define CMD_EMR (0 << 19)
264#define CMD_READ (5 << 19)
265#define CMD_WRITE (4 << 19)
266
267#define SELECT_MR (0 << 16)
268#define SELECT_EMR (1 << 16)
269#define SELECT_EMR2 (2 << 16)
270#define SELECT_EMR3 (3 << 16)
271
272/* MR */
273#define DLL_RESET 0x00000100
274
275#define WRITE_RECOV_2 (1 << 9)
276#define WRITE_RECOV_3 (2 << 9)
277#define WRITE_RECOV_4 (3 << 9)
278#define WRITE_RECOV_5 (4 << 9)
279#define WRITE_RECOV_6 (5 << 9)
280
281#define BURST_LEN_4 0x00000002
282
283/* EMR */
284#define ODT_0_OHM 0x00000000
285#define ODT_50_OHM 0x00000044
286#define ODT_75_OHM 0x00000004
287#define ODT_150_OHM 0x00000040
288
289#define ODS_FULL 0x00000000
290#define ODS_REDUCED 0x00000002
04737d5f 291#define OCD_CALIB_DEF 0x00000380
ba58e4c9
SR		 292
293/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
294#define ODT_EB0R (0x80000000 >> 8)
295#define ODT_EB0W (0x80000000 >> 7)
296#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
297#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
298#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
4037ed3b 299
4037ed3b 300/* Defines for the Read Cycle Delay test */
94f54703
SR		 301#define NUMMEMTESTS 8
302#define NUMMEMWORDS 8
6ed14add 303#define NUMLOOPS 64 /* memory test loops */
4037ed3b 304
5d812b8b
SR		 305/*
306 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
307 * To support such configurations, we "only" map the first 2GB via the TLB's. We
308 * need some free virtual address space for the remaining peripherals like, SoC
309 * devices, FLASH etc.
310 *
311 * Note that ECC is currently not supported on configurations with more than 2GB
312 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
313 * the ECC parity byte of the remaining area can't be written.
314 */
5d812b8b 315
a5d71e29
HS		 316/*
317 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
318 */
319void __spd_ddr_init_hang (void)
320{
321 hang ();
322}
323void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
324
6ed14add
SR		 325/*
326 * To provide an interface for board specific config values in this common
327 * DDR setup code, we implement he "weak" default functions here. They return
328 * the default value back to the caller.
329 *
330 * Please see include/configs/yucca.h for an example fora board specific
331 * implementation.
332 */
333u32 __ddr_wrdtr(u32 default_val)
334{
335 return default_val;
336}
337u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
338
339u32 __ddr_clktr(u32 default_val)
340{
341 return default_val;
342}
343u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
344
566a494f 345
4037ed3b
SR		 346/* Private Structure Definitions */
347
348/* enum only to ease code for cas latency setting */
349typedef enum ddr_cas_id {
350 DDR_CAS_2 = 20,
351 DDR_CAS_2_5 = 25,
352 DDR_CAS_3 = 30,
353 DDR_CAS_4 = 40,
354 DDR_CAS_5 = 50
355} ddr_cas_id_t;
356
357/*-----------------------------------------------------------------------------+
358 * Prototypes
359 *-----------------------------------------------------------------------------*/
4037ed3b
SR		 360static void get_spd_info(unsigned long *dimm_populated,
361 unsigned char *iic0_dimm_addr,
362 unsigned long num_dimm_banks);
363static void check_mem_type(unsigned long *dimm_populated,
364 unsigned char *iic0_dimm_addr,
365 unsigned long num_dimm_banks);
366static void check_frequency(unsigned long *dimm_populated,
367 unsigned char *iic0_dimm_addr,
368 unsigned long num_dimm_banks);
369static void check_rank_number(unsigned long *dimm_populated,
370 unsigned char *iic0_dimm_addr,
371 unsigned long num_dimm_banks);
372static void check_voltage_type(unsigned long *dimm_populated,
373 unsigned char *iic0_dimm_addr,
374 unsigned long num_dimm_banks);
375static void program_memory_queue(unsigned long *dimm_populated,
376 unsigned char *iic0_dimm_addr,
377 unsigned long num_dimm_banks);
378static void program_codt(unsigned long *dimm_populated,
379 unsigned char *iic0_dimm_addr,
380 unsigned long num_dimm_banks);
381static void program_mode(unsigned long *dimm_populated,
382 unsigned char *iic0_dimm_addr,
383 unsigned long num_dimm_banks,
ad5bb451
WD		 384 ddr_cas_id_t *selected_cas,
385 int *write_recovery);
4037ed3b
SR		 386static void program_tr(unsigned long *dimm_populated,
387 unsigned char *iic0_dimm_addr,
388 unsigned long num_dimm_banks);
389static void program_rtr(unsigned long *dimm_populated,
390 unsigned char *iic0_dimm_addr,
391 unsigned long num_dimm_banks);
392static void program_bxcf(unsigned long *dimm_populated,
393 unsigned char *iic0_dimm_addr,
394 unsigned long num_dimm_banks);
395static void program_copt1(unsigned long *dimm_populated,
396 unsigned char *iic0_dimm_addr,
397 unsigned long num_dimm_banks);
398static void program_initplr(unsigned long *dimm_populated,
399 unsigned char *iic0_dimm_addr,
400 unsigned long num_dimm_banks,
ad5bb451 401 ddr_cas_id_t selected_cas,
ba58e4c9 402 int write_recovery);
df294497 403#ifdef CONFIG_DDR_ECC
4037ed3b
SR		 404static void program_ecc(unsigned long *dimm_populated,
405 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 406 unsigned long num_dimm_banks,
407 unsigned long tlb_word2_i_value);
df294497 408#endif
f6b6c458 409#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
ba58e4c9 410static void program_DQS_calibration(unsigned long *dimm_populated,
f6b6c458
AG		 411 unsigned char *iic0_dimm_addr,
412 unsigned long num_dimm_banks);
4037ed3b 413#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
74357114 414static void test(void);
4037ed3b 415#else
74357114 416static void DQS_calibration_process(void);
4037ed3b 417#endif
f6b6c458 418#endif
54841ab5 419int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
4037ed3b 420
4037ed3b
SR		 421static unsigned char spd_read(uchar chip, uint addr)
422{
423 unsigned char data[2];
424
425 if (i2c_probe(chip) == 0)
426 if (i2c_read(chip, addr, 1, data, 1) == 0)
427 return data[0];
428
429 return 0;
430}
431
4037ed3b
SR		 432/*-----------------------------------------------------------------------------+
433 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
434 * Note: This routine runs from flash with a stack set up in the chip's
435 * sram space. It is important that the routine does not require .sbss, .bss or
436 * .data sections. It also cannot call routines that require these sections.
437 *-----------------------------------------------------------------------------*/
438/*-----------------------------------------------------------------------------
74357114 439 * Function: initdram
4037ed3b 440 * Description: Configures SDRAM memory banks for DDR operation.
74357114
WD		 441 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
442 * via the IIC bus and then configures the DDR SDRAM memory
443 * banks appropriately. If Auto Memory Configuration is
444 * not used, it is assumed that no DIMM is plugged
4037ed3b 445 *-----------------------------------------------------------------------------*/
9973e3c6 446phys_size_t initdram(int board_type)
4037ed3b 447{
ba58e4c9 448 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
4037ed3b
SR		 449 unsigned char spd0[MAX_SPD_BYTES];
450 unsigned char spd1[MAX_SPD_BYTES];
451 unsigned char *dimm_spd[MAXDIMMS];
33c8c664 452 unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
9adfc9fb 453 unsigned long num_dimm_banks; /* on board dimm banks */
4037ed3b 454 unsigned long val;
9adfc9fb 455 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
ba58e4c9 456 int write_recovery;
5d812b8b 457 phys_size_t dram_size = 0;
4037ed3b
SR		 458
459 num_dimm_banks = sizeof(iic0_dimm_addr);
460
461 /*------------------------------------------------------------------
462 * Set up an array of SPD matrixes.
463 *-----------------------------------------------------------------*/
464 dimm_spd[0] = spd0;
465 dimm_spd[1] = spd1;
466
4037ed3b
SR		 467 /*------------------------------------------------------------------
468 * Reset the DDR-SDRAM controller.
469 *-----------------------------------------------------------------*/
5e7abce9 470 mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
4037ed3b
SR		 471 mtsdr(SDR0_SRST, 0x00000000);
472
473 /*
474 * Make sure I2C controller is initialized
475 * before continuing.
476 */
477
478 /* switch to correct I2C bus */
6d0f6bcf
JCPV		 479 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
480 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
4037ed3b
SR		 481
482 /*------------------------------------------------------------------
483 * Clear out the serial presence detect buffers.
484 * Perform IIC reads from the dimm. Fill in the spds.
485 * Check to see if the dimm slots are populated
486 *-----------------------------------------------------------------*/
487 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
488
489 /*------------------------------------------------------------------
490 * Check the memory type for the dimms plugged.
491 *-----------------------------------------------------------------*/
492 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
493
494 /*------------------------------------------------------------------
495 * Check the frequency supported for the dimms plugged.
496 *-----------------------------------------------------------------*/
497 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
498
499 /*------------------------------------------------------------------
500 * Check the total rank number.
501 *-----------------------------------------------------------------*/
502 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
503
504 /*------------------------------------------------------------------
505 * Check the voltage type for the dimms plugged.
506 *-----------------------------------------------------------------*/
507 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
508
509 /*------------------------------------------------------------------
510 * Program SDRAM controller options 2 register
511 * Except Enabling of the memory controller.
512 *-----------------------------------------------------------------*/
513 mfsdram(SDRAM_MCOPT2, val);
514 mtsdram(SDRAM_MCOPT2,
515 (val &
516 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
517 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
518 SDRAM_MCOPT2_ISIE_MASK))
519 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
520 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
521 SDRAM_MCOPT2_ISIE_ENABLE));
522
523 /*------------------------------------------------------------------
524 * Program SDRAM controller options 1 register
525 * Note: Does not enable the memory controller.
526 *-----------------------------------------------------------------*/
527 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
528
529 /*------------------------------------------------------------------
530 * Set the SDRAM Controller On Die Termination Register
531 *-----------------------------------------------------------------*/
532 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
533
534 /*------------------------------------------------------------------
535 * Program SDRAM refresh register.
536 *-----------------------------------------------------------------*/
537 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
538
539 /*------------------------------------------------------------------
540 * Program SDRAM mode register.
541 *-----------------------------------------------------------------*/
ba58e4c9
SR		 542 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
543 &selected_cas, &write_recovery);
4037ed3b
SR		 544
545 /*------------------------------------------------------------------
546 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
547 *-----------------------------------------------------------------*/
548 mfsdram(SDRAM_WRDTR, val);
549 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
6ed14add 550 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
4037ed3b
SR		 551
552 /*------------------------------------------------------------------
553 * Set the SDRAM Clock Timing Register
554 *-----------------------------------------------------------------*/
555 mfsdram(SDRAM_CLKTR, val);
6ed14add
SR		 556 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
557 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
4037ed3b
SR		 558
559 /*------------------------------------------------------------------
560 * Program the BxCF registers.
561 *-----------------------------------------------------------------*/
562 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
563
564 /*------------------------------------------------------------------
565 * Program SDRAM timing registers.
566 *-----------------------------------------------------------------*/
567 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
568
569 /*------------------------------------------------------------------
570 * Set the Extended Mode register
571 *-----------------------------------------------------------------*/
572 mfsdram(SDRAM_MEMODE, val);
573 mtsdram(SDRAM_MEMODE,
574 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
575 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
576 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
df294497 577 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
4037ed3b
SR		 578
579 /*------------------------------------------------------------------
580 * Program Initialization preload registers.
581 *-----------------------------------------------------------------*/
582 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
ba58e4c9 583 selected_cas, write_recovery);
4037ed3b
SR		 584
585 /*------------------------------------------------------------------
586 * Delay to ensure 200usec have elapsed since reset.
587 *-----------------------------------------------------------------*/
588 udelay(400);
589
590 /*------------------------------------------------------------------
591 * Set the memory queue core base addr.
592 *-----------------------------------------------------------------*/
593 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
594
595 /*------------------------------------------------------------------
596 * Program SDRAM controller options 2 register
597 * Enable the memory controller.
598 *-----------------------------------------------------------------*/
599 mfsdram(SDRAM_MCOPT2, val);
600 mtsdram(SDRAM_MCOPT2,
601 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
602 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
04737d5f 603 SDRAM_MCOPT2_IPTR_EXECUTE);
4037ed3b
SR		 604
605 /*------------------------------------------------------------------
04737d5f 606 * Wait for IPTR_EXECUTE init sequence to complete.
4037ed3b
SR		 607 *-----------------------------------------------------------------*/
608 do {
609 mfsdram(SDRAM_MCSTAT, val);
610 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
611
04737d5f
PH		 612 /* enable the controller only after init sequence completes */
613 mfsdram(SDRAM_MCOPT2, val);
614 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
615
616 /* Make sure delay-line calibration is done before proceeding */
617 do {
618 mfsdram(SDRAM_DLCR, val);
619 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
620
4037ed3b
SR		 621 /* get installed memory size */
622 dram_size = sdram_memsize();
623
5d812b8b
SR		 624 /*
625 * Limit size to 2GB
626 */
627 if (dram_size > CONFIG_MAX_MEM_MAPPED)
628 dram_size = CONFIG_MAX_MEM_MAPPED;
629
4037ed3b 630 /* and program tlb entries for this size (dynamic) */
6ed14add
SR		 631
632 /*
633 * Program TLB entries with caches enabled, for best performace
634 * while auto-calibrating and ECC generation
635 */
636 program_tlb(0, 0, dram_size, 0);
4037ed3b 637
4037ed3b 638 /*------------------------------------------------------------------
ba58e4c9 639 * DQS calibration.
4037ed3b 640 *-----------------------------------------------------------------*/
f6b6c458
AG		 641#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
642 DQS_autocalibration();
643#else
ba58e4c9 644 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
f6b6c458 645#endif
e9c020df
SR		 646 /*
647 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
648 * PowerPC440SP/SPe DDR2 application note:
649 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
650 */
651 update_rdcc();
4037ed3b 652
df294497 653#ifdef CONFIG_DDR_ECC
4037ed3b 654 /*------------------------------------------------------------------
ba58e4c9 655 * If ecc is enabled, initialize the parity bits.
4037ed3b 656 *-----------------------------------------------------------------*/
6ed14add 657 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
df294497 658#endif
4037ed3b 659
6ed14add
SR		 660 /*
661 * Now after initialization (auto-calibration and ECC generation)
662 * remove the TLB entries with caches enabled and program again with
663 * desired cache functionality
664 */
665 remove_tlb(0, dram_size);
666 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
667
2e205084 668 ppc4xx_ibm_ddr2_register_dump();
4037ed3b 669
8ac41e3e
SR		 670 /*
671 * Clear potential errors resulting from auto-calibration.
672 * If not done, then we could get an interrupt later on when
673 * exceptions are enabled.
674 */
675 set_mcsr(get_mcsr());
676
5d812b8b 677 return sdram_memsize();
4037ed3b
SR		 678}
679
680static void get_spd_info(unsigned long *dimm_populated,
681 unsigned char *iic0_dimm_addr,
682 unsigned long num_dimm_banks)
683{
684 unsigned long dimm_num;
685 unsigned long dimm_found;
686 unsigned char num_of_bytes;
687 unsigned char total_size;
688
689 dimm_found = FALSE;
690 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
691 num_of_bytes = 0;
692 total_size = 0;
693
694 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
695 debug("\nspd_read(0x%x) returned %d\n",
696 iic0_dimm_addr[dimm_num], num_of_bytes);
697 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
698 debug("spd_read(0x%x) returned %d\n",
699 iic0_dimm_addr[dimm_num], total_size);
700
701 if ((num_of_bytes != 0) && (total_size != 0)) {
702 dimm_populated[dimm_num] = TRUE;
703 dimm_found = TRUE;
704 debug("DIMM slot %lu: populated\n", dimm_num);
705 } else {
706 dimm_populated[dimm_num] = FALSE;
707 debug("DIMM slot %lu: Not populated\n", dimm_num);
708 }
709 }
710
711 if (dimm_found == FALSE) {
712 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
a5d71e29 713 spd_ddr_init_hang ();
4037ed3b
SR		 714 }
715}
716
4037ed3b
SR		 717
718/*------------------------------------------------------------------
719 * For the memory DIMMs installed, this routine verifies that they
720 * really are DDR specific DIMMs.
721 *-----------------------------------------------------------------*/
722static void check_mem_type(unsigned long *dimm_populated,
723 unsigned char *iic0_dimm_addr,
724 unsigned long num_dimm_banks)
725{
726 unsigned long dimm_num;
727 unsigned long dimm_type;
728
729 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
730 if (dimm_populated[dimm_num] == TRUE) {
731 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
732 switch (dimm_type) {
733 case 1:
734 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
735 "slot %d.\n", (unsigned int)dimm_num);
736 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
737 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 738 spd_ddr_init_hang ();
4037ed3b
SR		 739 break;
740 case 2:
741 printf("ERROR: EDO DIMM detected in slot %d.\n",
742 (unsigned int)dimm_num);
743 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
744 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 745 spd_ddr_init_hang ();
4037ed3b
SR		 746 break;
747 case 3:
748 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
749 (unsigned int)dimm_num);
750 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
751 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 752 spd_ddr_init_hang ();
4037ed3b
SR		 753 break;
754 case 4:
755 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
756 (unsigned int)dimm_num);
757 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
758 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 759 spd_ddr_init_hang ();
4037ed3b
SR		 760 break;
761 case 5:
762 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
763 (unsigned int)dimm_num);
764 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
765 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 766 spd_ddr_init_hang ();
4037ed3b
SR		 767 break;
768 case 6:
769 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
770 (unsigned int)dimm_num);
771 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
772 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 773 spd_ddr_init_hang ();
4037ed3b
SR		 774 break;
775 case 7:
48e2b535 776 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
4037ed3b
SR		 777 dimm_populated[dimm_num] = SDRAM_DDR1;
778 break;
779 case 8:
48e2b535 780 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
4037ed3b
SR		 781 dimm_populated[dimm_num] = SDRAM_DDR2;
782 break;
783 default:
784 printf("ERROR: Unknown DIMM detected in slot %d.\n",
785 (unsigned int)dimm_num);
786 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
787 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 788 spd_ddr_init_hang ();
4037ed3b
SR		 789 break;
790 }
791 }
792 }
793 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
794 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
795 && (dimm_populated[dimm_num] != SDRAM_NONE)
796 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
797 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
a5d71e29 798 spd_ddr_init_hang ();
4037ed3b
SR		 799 }
800 }
801}
802
803/*------------------------------------------------------------------
804 * For the memory DIMMs installed, this routine verifies that
805 * frequency previously calculated is supported.
806 *-----------------------------------------------------------------*/
807static void check_frequency(unsigned long *dimm_populated,
808 unsigned char *iic0_dimm_addr,
809 unsigned long num_dimm_banks)
810{
811 unsigned long dimm_num;
812 unsigned long tcyc_reg;
813 unsigned long cycle_time;
814 unsigned long calc_cycle_time;
815 unsigned long sdram_freq;
816 unsigned long sdr_ddrpll;
087dfdb7 817 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 818
819 /*------------------------------------------------------------------
820 * Get the board configuration info.
821 *-----------------------------------------------------------------*/
822 get_sys_info(&board_cfg);
823
df294497 824 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 825 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
826
827 /*
828 * calc_cycle_time is calculated from DDR frequency set by board/chip
829 * and is expressed in multiple of 10 picoseconds
830 * to match the way DIMM cycle time is calculated below.
831 */
832 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
833
834 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
835 if (dimm_populated[dimm_num] != SDRAM_NONE) {
836 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
837 /*
838 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
839 * the higher order nibble (bits 4-7) designates the cycle time
840 * to a granularity of 1ns;
841 * the value presented by the lower order nibble (bits 0-3)
842 * has a granularity of .1ns and is added to the value designated
843 * by the higher nibble. In addition, four lines of the lower order
844 * nibble are assigned to support +.25,+.33, +.66 and +.75.
845 */
846 /* Convert from hex to decimal */
847 if ((tcyc_reg & 0x0F) == 0x0D)
848 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
849 else if ((tcyc_reg & 0x0F) == 0x0C)
850 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
851 else if ((tcyc_reg & 0x0F) == 0x0B)
852 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
853 else if ((tcyc_reg & 0x0F) == 0x0A)
854 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
855 else
856 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
857 ((tcyc_reg & 0x0F)*10);
48e2b535 858 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
4037ed3b
SR		 859
860 if (cycle_time > (calc_cycle_time + 10)) {
861 /*
862 * the provided sdram cycle_time is too small
863 * for the available DIMM cycle_time.
864 * The additionnal 100ps is here to accept a small incertainty.
865 */
866 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
867 "slot %d \n while calculated cycle time is %d ps.\n",
868 (unsigned int)(cycle_time*10),
869 (unsigned int)dimm_num,
870 (unsigned int)(calc_cycle_time*10));
871 printf("Replace the DIMM, or change DDR frequency via "
872 "strapping bits.\n\n");
a5d71e29 873 spd_ddr_init_hang ();
4037ed3b
SR		 874 }
875 }
876 }
877}
878
879/*------------------------------------------------------------------
880 * For the memory DIMMs installed, this routine verifies two
881 * ranks/banks maximum are availables.
882 *-----------------------------------------------------------------*/
883static void check_rank_number(unsigned long *dimm_populated,
884 unsigned char *iic0_dimm_addr,
885 unsigned long num_dimm_banks)
886{
887 unsigned long dimm_num;
888 unsigned long dimm_rank;
889 unsigned long total_rank = 0;
890
891 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
892 if (dimm_populated[dimm_num] != SDRAM_NONE) {
893 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
894 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
895 dimm_rank = (dimm_rank & 0x0F) +1;
896 else
897 dimm_rank = dimm_rank & 0x0F;
898
899
900 if (dimm_rank > MAXRANKS) {
b002144e
SR		 901 printf("ERROR: DRAM DIMM detected with %lu ranks in "
902 "slot %lu is not supported.\n", dimm_rank, dimm_num);
4037ed3b
SR		 903 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
904 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 905 spd_ddr_init_hang ();
4037ed3b
SR		 906 } else
907 total_rank += dimm_rank;
908 }
909 if (total_rank > MAXRANKS) {
910 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
911 "for all slots.\n", (unsigned int)total_rank);
912 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
913 printf("Remove one of the DIMM modules.\n\n");
a5d71e29 914 spd_ddr_init_hang ();
4037ed3b
SR		 915 }
916 }
917}
918
919/*------------------------------------------------------------------
920 * only support 2.5V modules.
921 * This routine verifies this.
922 *-----------------------------------------------------------------*/
923static void check_voltage_type(unsigned long *dimm_populated,
924 unsigned char *iic0_dimm_addr,
925 unsigned long num_dimm_banks)
926{
927 unsigned long dimm_num;
928 unsigned long voltage_type;
929
930 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
931 if (dimm_populated[dimm_num] != SDRAM_NONE) {
932 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
933 switch (voltage_type) {
934 case 0x00:
935 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
936 printf("This DIMM is 5.0 Volt/TTL.\n");
937 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
938 (unsigned int)dimm_num);
a5d71e29 939 spd_ddr_init_hang ();
4037ed3b
SR		 940 break;
941 case 0x01:
942 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
943 printf("This DIMM is LVTTL.\n");
944 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
945 (unsigned int)dimm_num);
a5d71e29 946 spd_ddr_init_hang ();
4037ed3b
SR		 947 break;
948 case 0x02:
949 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
950 printf("This DIMM is 1.5 Volt.\n");
951 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
952 (unsigned int)dimm_num);
a5d71e29 953 spd_ddr_init_hang ();
4037ed3b
SR		 954 break;
955 case 0x03:
956 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
957 printf("This DIMM is 3.3 Volt/TTL.\n");
958 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
959 (unsigned int)dimm_num);
a5d71e29 960 spd_ddr_init_hang ();
4037ed3b
SR		 961 break;
962 case 0x04:
963 /* 2.5 Voltage only for DDR1 */
964 break;
965 case 0x05:
966 /* 1.8 Voltage only for DDR2 */
967 break;
968 default:
969 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
970 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
971 (unsigned int)dimm_num);
a5d71e29 972 spd_ddr_init_hang ();
4037ed3b
SR		 973 break;
974 }
975 }
976 }
977}
978
979/*-----------------------------------------------------------------------------+
980 * program_copt1.
981 *-----------------------------------------------------------------------------*/
982static void program_copt1(unsigned long *dimm_populated,
983 unsigned char *iic0_dimm_addr,
984 unsigned long num_dimm_banks)
985{
986 unsigned long dimm_num;
987 unsigned long mcopt1;
988 unsigned long ecc_enabled;
989 unsigned long ecc = 0;
990 unsigned long data_width = 0;
991 unsigned long dimm_32bit;
992 unsigned long dimm_64bit;
993 unsigned long registered = 0;
994 unsigned long attribute = 0;
995 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
996 unsigned long bankcount;
997 unsigned long ddrtype;
998 unsigned long val;
999
df294497 1000#ifdef CONFIG_DDR_ECC
4037ed3b 1001 ecc_enabled = TRUE;
df294497
SR		 1002#else
1003 ecc_enabled = FALSE;
1004#endif
4037ed3b
SR		 1005 dimm_32bit = FALSE;
1006 dimm_64bit = FALSE;
1007 buf0 = FALSE;
1008 buf1 = FALSE;
1009
1010 /*------------------------------------------------------------------
1011 * Set memory controller options reg 1, SDRAM_MCOPT1.
1012 *-----------------------------------------------------------------*/
1013 mfsdram(SDRAM_MCOPT1, val);
1014 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1015 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
1016 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1017 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1018 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1019 SDRAM_MCOPT1_DREF_MASK);
1020
1021 mcopt1 |= SDRAM_MCOPT1_QDEP;
1022 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1023 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1024 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1025 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1026 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1027
1028 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1029 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1030 /* test ecc support */
1031 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1032 if (ecc != 0x02) /* ecc not supported */
1033 ecc_enabled = FALSE;
1034
1035 /* test bank count */
1036 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1037 if (bankcount == 0x04) /* bank count = 4 */
1038 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1039 else /* bank count = 8 */
1040 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1041
1042 /* test DDR type */
1043 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1044 /* test for buffered/unbuffered, registered, differential clocks */
1045 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1046 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1047
1048 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1049 if (dimm_num == 0) {
1050 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1051 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1052 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1053 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1054 if (registered == 1) { /* DDR2 always buffered */
1055 /* TODO: what about above comments ? */
1056 mcopt1 |= SDRAM_MCOPT1_RDEN;
1057 buf0 = TRUE;
1058 } else {
1059 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1060 if ((attribute & 0x02) == 0x00) {
1061 /* buffered not supported */
1062 buf0 = FALSE;
1063 } else {
1064 mcopt1 |= SDRAM_MCOPT1_RDEN;
1065 buf0 = TRUE;
1066 }
1067 }
1068 }
1069 else if (dimm_num == 1) {
1070 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1071 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1072 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1073 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1074 if (registered == 1) {
1075 /* DDR2 always buffered */
1076 mcopt1 |= SDRAM_MCOPT1_RDEN;
1077 buf1 = TRUE;
1078 } else {
1079 if ((attribute & 0x02) == 0x00) {
1080 /* buffered not supported */
1081 buf1 = FALSE;
1082 } else {
1083 mcopt1 |= SDRAM_MCOPT1_RDEN;
1084 buf1 = TRUE;
1085 }
1086 }
1087 }
1088
1089 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1090 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1091 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1092
1093 switch (data_width) {
1094 case 72:
1095 case 64:
1096 dimm_64bit = TRUE;
1097 break;
1098 case 40:
1099 case 32:
1100 dimm_32bit = TRUE;
1101 break;
1102 default:
b002144e 1103 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
4037ed3b
SR		 1104 data_width);
1105 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1106 break;
1107 }
1108 }
1109 }
1110
1111 /* verify matching properties */
1112 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1113 if (buf0 != buf1) {
1114 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
a5d71e29 1115 spd_ddr_init_hang ();
4037ed3b
SR		 1116 }
1117 }
1118
1119 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1120 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
a5d71e29 1121 spd_ddr_init_hang ();
4037ed3b
SR		 1122 }
1123 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1124 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1125 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1126 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1127 } else {
1128 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
a5d71e29 1129 spd_ddr_init_hang ();
4037ed3b
SR		 1130 }
1131
1132 if (ecc_enabled == TRUE)
1133 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1134 else
1135 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1136
1137 mtsdram(SDRAM_MCOPT1, mcopt1);
1138}
1139
1140/*-----------------------------------------------------------------------------+
1141 * program_codt.
1142 *-----------------------------------------------------------------------------*/
1143static void program_codt(unsigned long *dimm_populated,
1144 unsigned char *iic0_dimm_addr,
1145 unsigned long num_dimm_banks)
1146{
1147 unsigned long codt;
1148 unsigned long modt0 = 0;
1149 unsigned long modt1 = 0;
1150 unsigned long modt2 = 0;
1151 unsigned long modt3 = 0;
1152 unsigned char dimm_num;
1153 unsigned char dimm_rank;
1154 unsigned char total_rank = 0;
1155 unsigned char total_dimm = 0;
1156 unsigned char dimm_type = 0;
1157 unsigned char firstSlot = 0;
1158
1159 /*------------------------------------------------------------------
1160 * Set the SDRAM Controller On Die Termination Register
1161 *-----------------------------------------------------------------*/
1162 mfsdram(SDRAM_CODT, codt);
7369f0e3
CS		 1163 codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1164 codt |= SDRAM_CODT_IO_NMODE;
4037ed3b
SR		 1165
1166 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1167 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1168 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1169 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1170 dimm_rank = (dimm_rank & 0x0F) + 1;
1171 dimm_type = SDRAM_DDR2;
1172 } else {
1173 dimm_rank = dimm_rank & 0x0F;
1174 dimm_type = SDRAM_DDR1;
1175 }
1176
ba58e4c9
SR		 1177 total_rank += dimm_rank;
1178 total_dimm++;
4037ed3b
SR		 1179 if ((dimm_num == 0) && (total_dimm == 1))
1180 firstSlot = TRUE;
1181 else
1182 firstSlot = FALSE;
1183 }
1184 }
1185 if (dimm_type == SDRAM_DDR2) {
1186 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1187 if ((total_dimm == 1) && (firstSlot == TRUE)) {
f2302d44 1188 if (total_rank == 1) { /* PUUU */
ba58e4c9
SR		 1189 codt |= CALC_ODT_R(0);
1190 modt0 = CALC_ODT_W(0);
4037ed3b
SR		 1191 modt1 = 0x00000000;
1192 modt2 = 0x00000000;
1193 modt3 = 0x00000000;
1194 }
f2302d44 1195 if (total_rank == 2) { /* PPUU */
ba58e4c9 1196 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
f2302d44
SR		 1197 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1198 modt1 = 0x00000000;
4037ed3b
SR		 1199 modt2 = 0x00000000;
1200 modt3 = 0x00000000;
1201 }
ba58e4c9 1202 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
f2302d44 1203 if (total_rank == 1) { /* UUPU */
ba58e4c9
SR		 1204 codt |= CALC_ODT_R(2);
1205 modt0 = 0x00000000;
4037ed3b 1206 modt1 = 0x00000000;
ba58e4c9 1207 modt2 = CALC_ODT_W(2);
4037ed3b
SR		 1208 modt3 = 0x00000000;
1209 }
f2302d44 1210 if (total_rank == 2) { /* UUPP */
ba58e4c9
SR		 1211 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1212 modt0 = 0x00000000;
1213 modt1 = 0x00000000;
f2302d44
SR		 1214 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1215 modt3 = 0x00000000;
4037ed3b
SR		 1216 }
1217 }
1218 if (total_dimm == 2) {
f2302d44 1219 if (total_rank == 2) { /* PUPU */
ba58e4c9
SR		 1220 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1221 modt0 = CALC_ODT_RW(2);
4037ed3b 1222 modt1 = 0x00000000;
ba58e4c9 1223 modt2 = CALC_ODT_RW(0);
4037ed3b
SR		 1224 modt3 = 0x00000000;
1225 }
f2302d44 1226 if (total_rank == 4) { /* PPPP */
7187db73
SR		 1227 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1228 CALC_ODT_R(2) | CALC_ODT_R(3);
f2302d44 1229 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
ba58e4c9 1230 modt1 = 0x00000000;
f2302d44 1231 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
ba58e4c9 1232 modt3 = 0x00000000;
4037ed3b
SR		 1233 }
1234 }
647d3c3e 1235 } else {
4037ed3b
SR		 1236 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1237 modt0 = 0x00000000;
1238 modt1 = 0x00000000;
1239 modt2 = 0x00000000;
1240 modt3 = 0x00000000;
1241
1242 if (total_dimm == 1) {
1243 if (total_rank == 1)
1244 codt |= 0x00800000;
1245 if (total_rank == 2)
1246 codt |= 0x02800000;
1247 }
1248 if (total_dimm == 2) {
1249 if (total_rank == 2)
1250 codt |= 0x08800000;
1251 if (total_rank == 4)
1252 codt |= 0x2a800000;
1253 }
1254 }
1255
1256 debug("nb of dimm %d\n", total_dimm);
1257 debug("nb of rank %d\n", total_rank);
1258 if (total_dimm == 1)
1259 debug("dimm in slot %d\n", firstSlot);
1260
1261 mtsdram(SDRAM_CODT, codt);
1262 mtsdram(SDRAM_MODT0, modt0);
1263 mtsdram(SDRAM_MODT1, modt1);
1264 mtsdram(SDRAM_MODT2, modt2);
1265 mtsdram(SDRAM_MODT3, modt3);
1266}
1267
1268/*-----------------------------------------------------------------------------+
1269 * program_initplr.
1270 *-----------------------------------------------------------------------------*/
1271static void program_initplr(unsigned long *dimm_populated,
1272 unsigned char *iic0_dimm_addr,
1273 unsigned long num_dimm_banks,
ad5bb451 1274 ddr_cas_id_t selected_cas,
ba58e4c9 1275 int write_recovery)
4037ed3b 1276{
ba58e4c9
SR		 1277 u32 cas = 0;
1278 u32 odt = 0;
1279 u32 ods = 0;
1280 u32 mr;
1281 u32 wr;
1282 u32 emr;
1283 u32 emr2;
1284 u32 emr3;
1285 int dimm_num;
1286 int total_dimm = 0;
4037ed3b
SR		 1287
1288 /******************************************************
1289 ** Assumption: if more than one DIMM, all DIMMs are the same
74357114 1290 ** as already checked in check_memory_type
4037ed3b
SR		 1291 ******************************************************/
1292
1293 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1294 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1295 mtsdram(SDRAM_INITPLR1, 0x81900400);
1296 mtsdram(SDRAM_INITPLR2, 0x81810000);
1297 mtsdram(SDRAM_INITPLR3, 0xff800162);
1298 mtsdram(SDRAM_INITPLR4, 0x81900400);
1299 mtsdram(SDRAM_INITPLR5, 0x86080000);
1300 mtsdram(SDRAM_INITPLR6, 0x86080000);
1301 mtsdram(SDRAM_INITPLR7, 0x81000062);
1302 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1303 switch (selected_cas) {
4037ed3b 1304 case DDR_CAS_3:
ba58e4c9 1305 cas = 3 << 4;
4037ed3b
SR		 1306 break;
1307 case DDR_CAS_4:
ba58e4c9 1308 cas = 4 << 4;
4037ed3b
SR		 1309 break;
1310 case DDR_CAS_5:
ba58e4c9 1311 cas = 5 << 4;
4037ed3b
SR		 1312 break;
1313 default:
ba58e4c9 1314 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
a5d71e29 1315 spd_ddr_init_hang ();
4037ed3b
SR		 1316 break;
1317 }
1318
ba58e4c9
SR		 1319#if 0
1320 /*
1321 * ToDo - Still a problem with the write recovery:
1322 * On the Corsair CM2X512-5400C4 module, setting write recovery
1323 * in the INITPLR reg to the value calculated in program_mode()
1324 * results in not correctly working DDR2 memory (crash after
1325 * relocation).
1326 *
1327 * So for now, set the write recovery to 3. This seems to work
1328 * on the Corair module too.
1329 *
1330 * 2007-03-01, sr
1331 */
1332 switch (write_recovery) {
1333 case 3:
1334 wr = WRITE_RECOV_3;
1335 break;
1336 case 4:
1337 wr = WRITE_RECOV_4;
1338 break;
1339 case 5:
1340 wr = WRITE_RECOV_5;
1341 break;
1342 case 6:
1343 wr = WRITE_RECOV_6;
1344 break;
1345 default:
1346 printf("ERROR: write recovery not support (%d)", write_recovery);
a5d71e29 1347 spd_ddr_init_hang ();
ba58e4c9
SR		 1348 break;
1349 }
1350#else
1351 wr = WRITE_RECOV_3; /* test-only, see description above */
1352#endif
1353
1354 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1355 if (dimm_populated[dimm_num] != SDRAM_NONE)
1356 total_dimm++;
1357 if (total_dimm == 1) {
1358 odt = ODT_150_OHM;
1359 ods = ODS_FULL;
1360 } else if (total_dimm == 2) {
1361 odt = ODT_75_OHM;
1362 ods = ODS_REDUCED;
1363 } else {
1364 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
a5d71e29 1365 spd_ddr_init_hang ();
ba58e4c9
SR		 1366 }
1367
1368 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1369 emr = CMD_EMR | SELECT_EMR | odt | ods;
1370 emr2 = CMD_EMR | SELECT_EMR2;
1371 emr3 = CMD_EMR | SELECT_EMR3;
04737d5f
PH		 1372 /* NOP - Wait 106 MemClk cycles */
1373 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1374 SDRAM_INITPLR_IMWT_ENCODE(106));
ba58e4c9 1375 udelay(1000);
04737d5f
PH		 1376 /* precharge 4 MemClk cycles */
1377 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1378 SDRAM_INITPLR_IMWT_ENCODE(4));
1379 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1380 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1381 SDRAM_INITPLR_IMWT_ENCODE(2));
1382 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1383 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1384 SDRAM_INITPLR_IMWT_ENCODE(2));
1385 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1386 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1387 SDRAM_INITPLR_IMWT_ENCODE(2));
1388 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1389 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1390 SDRAM_INITPLR_IMWT_ENCODE(200));
ba58e4c9 1391 udelay(1000);
04737d5f
PH		 1392 /* precharge 4 MemClk cycles */
1393 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1394 SDRAM_INITPLR_IMWT_ENCODE(4));
1395 /* Refresh 25 MemClk cycles */
1396 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1397 SDRAM_INITPLR_IMWT_ENCODE(25));
1398 /* Refresh 25 MemClk cycles */
1399 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1400 SDRAM_INITPLR_IMWT_ENCODE(25));
1401 /* Refresh 25 MemClk cycles */
1402 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1403 SDRAM_INITPLR_IMWT_ENCODE(25));
1404 /* Refresh 25 MemClk cycles */
1405 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1406 SDRAM_INITPLR_IMWT_ENCODE(25));
1407 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1408 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1409 SDRAM_INITPLR_IMWT_ENCODE(2));
1410 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1411 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1412 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1413 /* EMR OCD Exit */
1414 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1415 SDRAM_INITPLR_IMWT_ENCODE(2));
4037ed3b
SR		 1416 } else {
1417 printf("ERROR: ucode error as unknown DDR type in program_initplr");
a5d71e29 1418 spd_ddr_init_hang ();
4037ed3b
SR		 1419 }
1420}
1421
1422/*------------------------------------------------------------------
1423 * This routine programs the SDRAM_MMODE register.
1424 * the selected_cas is an output parameter, that will be passed
1425 * by caller to call the above program_initplr( )
1426 *-----------------------------------------------------------------*/
1427static void program_mode(unsigned long *dimm_populated,
1428 unsigned char *iic0_dimm_addr,
1429 unsigned long num_dimm_banks,
ba58e4c9
SR		 1430 ddr_cas_id_t *selected_cas,
1431 int *write_recovery)
4037ed3b
SR		 1432{
1433 unsigned long dimm_num;
1434 unsigned long sdram_ddr1;
1435 unsigned long t_wr_ns;
1436 unsigned long t_wr_clk;
1437 unsigned long cas_bit;
1438 unsigned long cas_index;
1439 unsigned long sdram_freq;
1440 unsigned long ddr_check;
1441 unsigned long mmode;
1442 unsigned long tcyc_reg;
1443 unsigned long cycle_2_0_clk;
1444 unsigned long cycle_2_5_clk;
1445 unsigned long cycle_3_0_clk;
1446 unsigned long cycle_4_0_clk;
1447 unsigned long cycle_5_0_clk;
1448 unsigned long max_2_0_tcyc_ns_x_100;
1449 unsigned long max_2_5_tcyc_ns_x_100;
1450 unsigned long max_3_0_tcyc_ns_x_100;
1451 unsigned long max_4_0_tcyc_ns_x_100;
1452 unsigned long max_5_0_tcyc_ns_x_100;
1453 unsigned long cycle_time_ns_x_100[3];
087dfdb7 1454 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1455 unsigned char cas_2_0_available;
1456 unsigned char cas_2_5_available;
1457 unsigned char cas_3_0_available;
1458 unsigned char cas_4_0_available;
1459 unsigned char cas_5_0_available;
1460 unsigned long sdr_ddrpll;
1461
1462 /*------------------------------------------------------------------
1463 * Get the board configuration info.
1464 *-----------------------------------------------------------------*/
1465 get_sys_info(&board_cfg);
1466
df294497 1467 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b 1468 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
48e2b535 1469 debug("sdram_freq=%lu\n", sdram_freq);
4037ed3b
SR		 1470
1471 /*------------------------------------------------------------------
1472 * Handle the timing. We need to find the worst case timing of all
1473 * the dimm modules installed.
1474 *-----------------------------------------------------------------*/
1475 t_wr_ns = 0;
1476 cas_2_0_available = TRUE;
1477 cas_2_5_available = TRUE;
1478 cas_3_0_available = TRUE;
1479 cas_4_0_available = TRUE;
1480 cas_5_0_available = TRUE;
1481 max_2_0_tcyc_ns_x_100 = 10;
1482 max_2_5_tcyc_ns_x_100 = 10;
1483 max_3_0_tcyc_ns_x_100 = 10;
1484 max_4_0_tcyc_ns_x_100 = 10;
1485 max_5_0_tcyc_ns_x_100 = 10;
1486 sdram_ddr1 = TRUE;
1487
1488 /* loop through all the DIMM slots on the board */
1489 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1490 /* If a dimm is installed in a particular slot ... */
1491 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1492 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1493 sdram_ddr1 = TRUE;
1494 else
1495 sdram_ddr1 = FALSE;
1496
1497 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1498 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
48e2b535 1499 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
4037ed3b
SR		 1500
1501 /* For a particular DIMM, grab the three CAS values it supports */
1502 for (cas_index = 0; cas_index < 3; cas_index++) {
1503 switch (cas_index) {
1504 case 0:
1505 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1506 break;
1507 case 1:
1508 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1509 break;
1510 default:
1511 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1512 break;
1513 }
1514
1515 if ((tcyc_reg & 0x0F) >= 10) {
1516 if ((tcyc_reg & 0x0F) == 0x0D) {
1517 /* Convert from hex to decimal */
cabee756
SR		 1518 cycle_time_ns_x_100[cas_index] =
1519 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
4037ed3b
SR		 1520 } else {
1521 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1522 "in slot %d\n", (unsigned int)dimm_num);
a5d71e29 1523 spd_ddr_init_hang ();
4037ed3b
SR		 1524 }
1525 } else {
1526 /* Convert from hex to decimal */
cabee756
SR		 1527 cycle_time_ns_x_100[cas_index] =
1528 (((tcyc_reg & 0xF0) >> 4) * 100) +
4037ed3b
SR		 1529 ((tcyc_reg & 0x0F)*10);
1530 }
48e2b535 1531 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
cabee756 1532 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1533 }
1534
1535 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1536 /* supported for a particular DIMM. */
1537 cas_index = 0;
1538
1539 if (sdram_ddr1) {
1540 /*
1541 * DDR devices use the following bitmask for CAS latency:
1542 * Bit 7 6 5 4 3 2 1 0
1543 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1544 */
cabee756
SR		 1545 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1546 (cycle_time_ns_x_100[cas_index] != 0)) {
1547 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1548 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1549 cas_index++;
1550 } else {
1551 if (cas_index != 0)
1552 cas_index++;
1553 cas_4_0_available = FALSE;
1554 }
1555
cabee756
SR		 1556 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1557 (cycle_time_ns_x_100[cas_index] != 0)) {
1558 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1559 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1560 cas_index++;
1561 } else {
1562 if (cas_index != 0)
1563 cas_index++;
1564 cas_3_0_available = FALSE;
1565 }
1566
cabee756
SR		 1567 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1568 (cycle_time_ns_x_100[cas_index] != 0)) {
1569 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1570 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1571 cas_index++;
1572 } else {
1573 if (cas_index != 0)
1574 cas_index++;
1575 cas_2_5_available = FALSE;
1576 }
1577
cabee756
SR		 1578 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1579 (cycle_time_ns_x_100[cas_index] != 0)) {
1580 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1581 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1582 cas_index++;
1583 } else {
1584 if (cas_index != 0)
1585 cas_index++;
1586 cas_2_0_available = FALSE;
1587 }
1588 } else {
1589 /*
1590 * DDR2 devices use the following bitmask for CAS latency:
1591 * Bit 7 6 5 4 3 2 1 0
1592 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1593 */
cabee756
SR		 1594 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1595 (cycle_time_ns_x_100[cas_index] != 0)) {
1596 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1597 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1598 cas_index++;
1599 } else {
1600 if (cas_index != 0)
1601 cas_index++;
1602 cas_5_0_available = FALSE;
1603 }
1604
cabee756
SR		 1605 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1606 (cycle_time_ns_x_100[cas_index] != 0)) {
1607 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1608 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1609 cas_index++;
1610 } else {
1611 if (cas_index != 0)
1612 cas_index++;
1613 cas_4_0_available = FALSE;
1614 }
1615
cabee756
SR		 1616 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1617 (cycle_time_ns_x_100[cas_index] != 0)) {
1618 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1619 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1620 cas_index++;
1621 } else {
1622 if (cas_index != 0)
1623 cas_index++;
1624 cas_3_0_available = FALSE;
1625 }
1626 }
1627 }
1628 }
1629
1630 /*------------------------------------------------------------------
1631 * Set the SDRAM mode, SDRAM_MMODE
1632 *-----------------------------------------------------------------*/
1633 mfsdram(SDRAM_MMODE, mmode);
1634 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1635
df294497
SR		 1636 /* add 10 here because of rounding problems */
1637 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1638 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1639 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1640 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1641 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
48e2b535
FR		 1642 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1643 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1644 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
4037ed3b
SR		 1645
1646 if (sdram_ddr1 == TRUE) { /* DDR1 */
1647 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1648 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1649 *selected_cas = DDR_CAS_2;
1650 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1651 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1652 *selected_cas = DDR_CAS_2_5;
1653 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1654 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1655 *selected_cas = DDR_CAS_3;
1656 } else {
1657 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1658 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1659 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
a5d71e29 1660 spd_ddr_init_hang ();
4037ed3b
SR		 1661 }
1662 } else { /* DDR2 */
94f54703
SR		 1663 debug("cas_3_0_available=%d\n", cas_3_0_available);
1664 debug("cas_4_0_available=%d\n", cas_4_0_available);
1665 debug("cas_5_0_available=%d\n", cas_5_0_available);
4037ed3b
SR		 1666 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1667 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1668 *selected_cas = DDR_CAS_3;
1669 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1670 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1671 *selected_cas = DDR_CAS_4;
1672 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1673 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1674 *selected_cas = DDR_CAS_5;
1675 } else {
1676 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1677 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
df294497
SR		 1678 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1679 printf("cas3=%d cas4=%d cas5=%d\n",
1680 cas_3_0_available, cas_4_0_available, cas_5_0_available);
b002144e 1681 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
df294497 1682 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
a5d71e29 1683 spd_ddr_init_hang ();
4037ed3b
SR		 1684 }
1685 }
1686
1687 if (sdram_ddr1 == TRUE)
1688 mmode |= SDRAM_MMODE_WR_DDR1;
1689 else {
1690
1691 /* loop through all the DIMM slots on the board */
1692 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1693 /* If a dimm is installed in a particular slot ... */
1694 if (dimm_populated[dimm_num] != SDRAM_NONE)
1695 t_wr_ns = max(t_wr_ns,
1696 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1697 }
1698
1699 /*
1700 * convert from nanoseconds to ddr clocks
1701 * round up if necessary
1702 */
1703 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1704 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1705 if (sdram_freq != ddr_check)
1706 t_wr_clk++;
1707
1708 switch (t_wr_clk) {
1709 case 0:
1710 case 1:
1711 case 2:
1712 case 3:
1713 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1714 break;
1715 case 4:
1716 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1717 break;
1718 case 5:
1719 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1720 break;
1721 default:
1722 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1723 break;
1724 }
ba58e4c9 1725 *write_recovery = t_wr_clk;
4037ed3b
SR		 1726 }
1727
ba58e4c9
SR		 1728 debug("CAS latency = %d\n", *selected_cas);
1729 debug("Write recovery = %d\n", *write_recovery);
1730
4037ed3b
SR		 1731 mtsdram(SDRAM_MMODE, mmode);
1732}
1733
1734/*-----------------------------------------------------------------------------+
1735 * program_rtr.
1736 *-----------------------------------------------------------------------------*/
1737static void program_rtr(unsigned long *dimm_populated,
1738 unsigned char *iic0_dimm_addr,
1739 unsigned long num_dimm_banks)
1740{
087dfdb7 1741 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1742 unsigned long max_refresh_rate;
1743 unsigned long dimm_num;
1744 unsigned long refresh_rate_type;
1745 unsigned long refresh_rate;
1746 unsigned long rint;
1747 unsigned long sdram_freq;
1748 unsigned long sdr_ddrpll;
1749 unsigned long val;
1750
1751 /*------------------------------------------------------------------
1752 * Get the board configuration info.
1753 *-----------------------------------------------------------------*/
1754 get_sys_info(&board_cfg);
1755
1756 /*------------------------------------------------------------------
1757 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1758 *-----------------------------------------------------------------*/
df294497 1759 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 1760 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1761
1762 max_refresh_rate = 0;
1763 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1764 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1765
1766 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1767 refresh_rate_type &= 0x7F;
1768 switch (refresh_rate_type) {
1769 case 0:
1770 refresh_rate = 15625;
1771 break;
1772 case 1:
1773 refresh_rate = 3906;
1774 break;
1775 case 2:
1776 refresh_rate = 7812;
1777 break;
1778 case 3:
1779 refresh_rate = 31250;
1780 break;
1781 case 4:
1782 refresh_rate = 62500;
1783 break;
1784 case 5:
1785 refresh_rate = 125000;
1786 break;
1787 default:
1788 refresh_rate = 0;
1789 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1790 (unsigned int)dimm_num);
1791 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 1792 spd_ddr_init_hang ();
4037ed3b
SR		 1793 break;
1794 }
1795
1796 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1797 }
1798 }
1799
1800 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1801 mfsdram(SDRAM_RTR, val);
1802 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1803 (SDRAM_RTR_RINT_ENCODE(rint)));
1804}
1805
1806/*------------------------------------------------------------------
1807 * This routine programs the SDRAM_TRx registers.
1808 *-----------------------------------------------------------------*/
1809static void program_tr(unsigned long *dimm_populated,
1810 unsigned char *iic0_dimm_addr,
1811 unsigned long num_dimm_banks)
1812{
1813 unsigned long dimm_num;
1814 unsigned long sdram_ddr1;
1815 unsigned long t_rp_ns;
1816 unsigned long t_rcd_ns;
1817 unsigned long t_rrd_ns;
1818 unsigned long t_ras_ns;
1819 unsigned long t_rc_ns;
1820 unsigned long t_rfc_ns;
1821 unsigned long t_wpc_ns;
1822 unsigned long t_wtr_ns;
1823 unsigned long t_rpc_ns;
1824 unsigned long t_rp_clk;
1825 unsigned long t_rcd_clk;
1826 unsigned long t_rrd_clk;
1827 unsigned long t_ras_clk;
1828 unsigned long t_rc_clk;
1829 unsigned long t_rfc_clk;
1830 unsigned long t_wpc_clk;
1831 unsigned long t_wtr_clk;
1832 unsigned long t_rpc_clk;
1833 unsigned long sdtr1, sdtr2, sdtr3;
1834 unsigned long ddr_check;
1835 unsigned long sdram_freq;
1836 unsigned long sdr_ddrpll;
1837
087dfdb7 1838 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1839
1840 /*------------------------------------------------------------------
1841 * Get the board configuration info.
1842 *-----------------------------------------------------------------*/
1843 get_sys_info(&board_cfg);
1844
df294497 1845 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 1846 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1847
1848 /*------------------------------------------------------------------
1849 * Handle the timing. We need to find the worst case timing of all
1850 * the dimm modules installed.
1851 *-----------------------------------------------------------------*/
1852 t_rp_ns = 0;
1853 t_rrd_ns = 0;
1854 t_rcd_ns = 0;
1855 t_ras_ns = 0;
1856 t_rc_ns = 0;
1857 t_rfc_ns = 0;
1858 t_wpc_ns = 0;
1859 t_wtr_ns = 0;
1860 t_rpc_ns = 0;
1861 sdram_ddr1 = TRUE;
1862
1863 /* loop through all the DIMM slots on the board */
1864 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1865 /* If a dimm is installed in a particular slot ... */
1866 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1867 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1868 sdram_ddr1 = TRUE;
1869 else
1870 sdram_ddr1 = FALSE;
1871
1872 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1873 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1874 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1875 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1876 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1877 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1878 }
1879 }
1880
1881 /*------------------------------------------------------------------
1882 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1883 *-----------------------------------------------------------------*/
1884 mfsdram(SDRAM_SDTR1, sdtr1);
1885 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1886 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1887
1888 /* default values */
1889 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1890 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1891
1892 /* normal operations */
1893 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1894 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1895
1896 mtsdram(SDRAM_SDTR1, sdtr1);
1897
1898 /*------------------------------------------------------------------
1899 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1900 *-----------------------------------------------------------------*/
1901 mfsdram(SDRAM_SDTR2, sdtr2);
1902 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1903 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1904 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1905 SDRAM_SDTR2_RRD_MASK);
1906
1907 /*
1908 * convert t_rcd from nanoseconds to ddr clocks
1909 * round up if necessary
1910 */
1911 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1912 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1913 if (sdram_freq != ddr_check)
1914 t_rcd_clk++;
1915
1916 switch (t_rcd_clk) {
1917 case 0:
1918 case 1:
1919 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1920 break;
1921 case 2:
1922 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1923 break;
1924 case 3:
1925 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1926 break;
1927 case 4:
1928 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1929 break;
1930 default:
1931 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1932 break;
1933 }
1934
1935 if (sdram_ddr1 == TRUE) { /* DDR1 */
1936 if (sdram_freq < 200000000) {
1937 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1938 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1939 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1940 } else {
1941 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1942 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1943 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1944 }
1945 } else { /* DDR2 */
1946 /* loop through all the DIMM slots on the board */
1947 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1948 /* If a dimm is installed in a particular slot ... */
1949 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1950 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1951 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1952 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1953 }
1954 }
1955
1956 /*
1957 * convert from nanoseconds to ddr clocks
1958 * round up if necessary
1959 */
1960 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1961 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1962 if (sdram_freq != ddr_check)
1963 t_wpc_clk++;
1964
1965 switch (t_wpc_clk) {
1966 case 0:
1967 case 1:
1968 case 2:
1969 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1970 break;
1971 case 3:
1972 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1973 break;
1974 case 4:
1975 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1976 break;
1977 case 5:
1978 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1979 break;
1980 default:
1981 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1982 break;
1983 }
1984
1985 /*
1986 * convert from nanoseconds to ddr clocks
1987 * round up if necessary
1988 */
1989 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1990 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1991 if (sdram_freq != ddr_check)
1992 t_wtr_clk++;
1993
1994 switch (t_wtr_clk) {
1995 case 0:
1996 case 1:
1997 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1998 break;
1999 case 2:
2000 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2001 break;
2002 case 3:
2003 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
2004 break;
2005 default:
2006 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2007 break;
2008 }
2009
2010 /*
2011 * convert from nanoseconds to ddr clocks
2012 * round up if necessary
2013 */
2014 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2015 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2016 if (sdram_freq != ddr_check)
2017 t_rpc_clk++;
2018
2019 switch (t_rpc_clk) {
2020 case 0:
2021 case 1:
2022 case 2:
2023 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2024 break;
2025 case 3:
2026 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2027 break;
2028 default:
2029 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2030 break;
2031 }
2032 }
2033
2034 /* default value */
2035 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2036
2037 /*
2038 * convert t_rrd from nanoseconds to ddr clocks
2039 * round up if necessary
2040 */
2041 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2042 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2043 if (sdram_freq != ddr_check)
2044 t_rrd_clk++;
2045
2046 if (t_rrd_clk == 3)
2047 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2048 else
2049 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2050
2051 /*
2052 * convert t_rp from nanoseconds to ddr clocks
2053 * round up if necessary
2054 */
2055 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2056 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2057 if (sdram_freq != ddr_check)
2058 t_rp_clk++;
2059
2060 switch (t_rp_clk) {
2061 case 0:
2062 case 1:
2063 case 2:
2064 case 3:
2065 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2066 break;
2067 case 4:
2068 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2069 break;
2070 case 5:
2071 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2072 break;
2073 case 6:
2074 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2075 break;
2076 default:
2077 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2078 break;
2079 }
2080
2081 mtsdram(SDRAM_SDTR2, sdtr2);
2082
2083 /*------------------------------------------------------------------
2084 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2085 *-----------------------------------------------------------------*/
2086 mfsdram(SDRAM_SDTR3, sdtr3);
2087 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2088 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2089
2090 /*
2091 * convert t_ras from nanoseconds to ddr clocks
2092 * round up if necessary
2093 */
2094 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2095 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2096 if (sdram_freq != ddr_check)
2097 t_ras_clk++;
2098
2099 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2100
2101 /*
2102 * convert t_rc from nanoseconds to ddr clocks
2103 * round up if necessary
2104 */
2105 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2106 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2107 if (sdram_freq != ddr_check)
2108 t_rc_clk++;
2109
2110 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2111
2112 /* default xcs value */
2113 sdtr3 |= SDRAM_SDTR3_XCS;
2114
2115 /*
2116 * convert t_rfc from nanoseconds to ddr clocks
2117 * round up if necessary
2118 */
2119 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2120 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2121 if (sdram_freq != ddr_check)
2122 t_rfc_clk++;
2123
2124 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2125
2126 mtsdram(SDRAM_SDTR3, sdtr3);
2127}
2128
2129/*-----------------------------------------------------------------------------+
2130 * program_bxcf.
2131 *-----------------------------------------------------------------------------*/
2132static void program_bxcf(unsigned long *dimm_populated,
2133 unsigned char *iic0_dimm_addr,
2134 unsigned long num_dimm_banks)
2135{
2136 unsigned long dimm_num;
2137 unsigned long num_col_addr;
2138 unsigned long num_ranks;
2139 unsigned long num_banks;
2140 unsigned long mode;
2141 unsigned long ind_rank;
2142 unsigned long ind;
2143 unsigned long ind_bank;
2144 unsigned long bank_0_populated;
2145
2146 /*------------------------------------------------------------------
2147 * Set the BxCF regs. First, wipe out the bank config registers.
2148 *-----------------------------------------------------------------*/
087dfdb7
SR		 2149 mtsdram(SDRAM_MB0CF, 0x00000000);
2150 mtsdram(SDRAM_MB1CF, 0x00000000);
2151 mtsdram(SDRAM_MB2CF, 0x00000000);
2152 mtsdram(SDRAM_MB3CF, 0x00000000);
4037ed3b
SR		 2153
2154 mode = SDRAM_BXCF_M_BE_ENABLE;
2155
2156 bank_0_populated = 0;
2157
2158 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2159 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2160 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2161 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2162 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2163 num_ranks = (num_ranks & 0x0F) +1;
2164 else
2165 num_ranks = num_ranks & 0x0F;
2166
2167 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2168
2169 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2170 if (num_banks == 4)
2171 ind = 0;
2172 else
ea9202a6 2173 ind = 5 << 8;
4037ed3b
SR		 2174 switch (num_col_addr) {
2175 case 0x08:
2176 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2177 break;
2178 case 0x09:
2179 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2180 break;
2181 case 0x0A:
2182 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2183 break;
2184 case 0x0B:
2185 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2186 break;
2187 case 0x0C:
2188 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2189 break;
2190 default:
2191 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2192 (unsigned int)dimm_num);
2193 printf("ERROR: Unsupported value for number of "
2194 "column addresses: %d.\n", (unsigned int)num_col_addr);
2195 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 2196 spd_ddr_init_hang ();
4037ed3b
SR		 2197 }
2198 }
2199
2200 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2201 bank_0_populated = 1;
2202
2203 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
087dfdb7
SR		 2204 mtsdram(SDRAM_MB0CF +
2205 ((dimm_num + bank_0_populated + ind_rank) << 2),
2206 mode);
4037ed3b
SR		 2207 }
2208 }
2209 }
2210}
2211
2212/*------------------------------------------------------------------
2213 * program memory queue.
2214 *-----------------------------------------------------------------*/
2215static void program_memory_queue(unsigned long *dimm_populated,
2216 unsigned char *iic0_dimm_addr,
2217 unsigned long num_dimm_banks)
2218{
2219 unsigned long dimm_num;
5d812b8b 2220 phys_size_t rank_base_addr;
4037ed3b 2221 unsigned long rank_reg;
5d812b8b 2222 phys_size_t rank_size_bytes;
4037ed3b
SR		 2223 unsigned long rank_size_id;
2224 unsigned long num_ranks;
2225 unsigned long baseadd_size;
2226 unsigned long i;
2227 unsigned long bank_0_populated = 0;
5d812b8b 2228 phys_size_t total_size = 0;
4037ed3b
SR		 2229
2230 /*------------------------------------------------------------------
2231 * Reset the rank_base_address.
2232 *-----------------------------------------------------------------*/
2233 rank_reg = SDRAM_R0BAS;
2234
2235 rank_base_addr = 0x00000000;
2236
2237 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2238 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2239 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2240 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2241 num_ranks = (num_ranks & 0x0F) + 1;
2242 else
2243 num_ranks = num_ranks & 0x0F;
2244
2245 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2246
2247 /*------------------------------------------------------------------
2248 * Set the sizes
2249 *-----------------------------------------------------------------*/
2250 baseadd_size = 0;
4037ed3b 2251 switch (rank_size_id) {
8ac41e3e
SR		 2252 case 0x01:
2253 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2254 total_size = 1024;
2255 break;
4037ed3b 2256 case 0x02:
8ac41e3e
SR		 2257 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2258 total_size = 2048;
4037ed3b
SR		 2259 break;
2260 case 0x04:
8ac41e3e
SR		 2261 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2262 total_size = 4096;
4037ed3b
SR		 2263 break;
2264 case 0x08:
2265 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
8ac41e3e 2266 total_size = 32;
4037ed3b
SR		 2267 break;
2268 case 0x10:
2269 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
8ac41e3e 2270 total_size = 64;
4037ed3b
SR		 2271 break;
2272 case 0x20:
2273 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
8ac41e3e 2274 total_size = 128;
4037ed3b
SR		 2275 break;
2276 case 0x40:
2277 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
8ac41e3e 2278 total_size = 256;
4037ed3b
SR		 2279 break;
2280 case 0x80:
2281 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
8ac41e3e 2282 total_size = 512;
4037ed3b
SR		 2283 break;
2284 default:
2285 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2286 (unsigned int)dimm_num);
2287 printf("ERROR: Unsupported value for the banksize: %d.\n",
2288 (unsigned int)rank_size_id);
2289 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 2290 spd_ddr_init_hang ();
4037ed3b 2291 }
8ac41e3e 2292 rank_size_bytes = total_size << 20;
4037ed3b
SR		 2293
2294 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2295 bank_0_populated = 1;
2296
2297 for (i = 0; i < num_ranks; i++) {
2298 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
df294497
SR		 2299 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2300 baseadd_size));
4037ed3b
SR		 2301 rank_base_addr += rank_size_bytes;
2302 }
2303 }
2304 }
8ac41e3e 2305
079589bc
PH		 2306#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2307 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2308 defined(CONFIG_460SX)
8ac41e3e 2309 /*
079589bc 2310 * Enable high bandwidth access
8ac41e3e
SR		 2311 * This is currently not used, but with this setup
2312 * it is possible to use it later on in e.g. the Linux
2313 * EMAC driver for performance gain.
2314 */
2315 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2316 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
079589bc
PH		 2317
2318 /*
2319 * Set optimal value for Memory Queue HB/LL Configuration registers
2320 */
bf29e0ea
YT		 2321 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2322 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2323 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2324 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2325 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2326 SDRAM_CONF1LL_RPLM);
f5564837 2327 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
8ac41e3e 2328#endif
4037ed3b
SR		 2329}
2330
df294497 2331#ifdef CONFIG_DDR_ECC
4037ed3b
SR		 2332/*-----------------------------------------------------------------------------+
2333 * program_ecc.
2334 *-----------------------------------------------------------------------------*/
2335static void program_ecc(unsigned long *dimm_populated,
2336 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 2337 unsigned long num_dimm_banks,
2338 unsigned long tlb_word2_i_value)
4037ed3b 2339{
4037ed3b
SR		 2340 unsigned long dimm_num;
2341 unsigned long ecc;
2342
2343 ecc = 0;
2344 /* loop through all the DIMM slots on the board */
2345 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2346 /* If a dimm is installed in a particular slot ... */
2347 if (dimm_populated[dimm_num] != SDRAM_NONE)
2348 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2349 }
2350 if (ecc == 0)
2351 return;
2352
d24bd251 2353 do_program_ecc(tlb_word2_i_value);
4037ed3b 2354}
df294497 2355#endif
4037ed3b 2356
f6b6c458 2357#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
4037ed3b
SR		 2358/*-----------------------------------------------------------------------------+
2359 * program_DQS_calibration.
2360 *-----------------------------------------------------------------------------*/
2361static void program_DQS_calibration(unsigned long *dimm_populated,
2362 unsigned char *iic0_dimm_addr,
2363 unsigned long num_dimm_banks)
2364{
2365 unsigned long val;
2366
2367#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2368 mtsdram(SDRAM_RQDC, 0x80000037);
2369 mtsdram(SDRAM_RDCC, 0x40000000);
2370 mtsdram(SDRAM_RFDC, 0x000001DF);
2371
2372 test();
2373#else
2374 /*------------------------------------------------------------------
2375 * Program RDCC register
2376 * Read sample cycle auto-update enable
2377 *-----------------------------------------------------------------*/
2378
4037ed3b
SR		 2379 mfsdram(SDRAM_RDCC, val);
2380 mtsdram(SDRAM_RDCC,
2381 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
845c6c95 2382 | SDRAM_RDCC_RSAE_ENABLE);
4037ed3b
SR		 2383
2384 /*------------------------------------------------------------------
2385 * Program RQDC register
2386 * Internal DQS delay mechanism enable
2387 *-----------------------------------------------------------------*/
2388 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2389
2390 /*------------------------------------------------------------------
2391 * Program RFDC register
2392 * Set Feedback Fractional Oversample
2393 * Auto-detect read sample cycle enable
04737d5f 2394 * Set RFOS to 1/4 of memclk cycle (0x3f)
4037ed3b
SR		 2395 *-----------------------------------------------------------------*/
2396 mfsdram(SDRAM_RFDC, val);
2397 mtsdram(SDRAM_RFDC,
2398 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2399 SDRAM_RFDC_RFFD_MASK))
04737d5f 2400 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
4037ed3b
SR		 2401 SDRAM_RFDC_RFFD_ENCODE(0)));
2402
2403 DQS_calibration_process();
2404#endif
2405}
2406
94f54703 2407static int short_mem_test(void)
4037ed3b
SR		 2408{
2409 u32 *membase;
2410 u32 bxcr_num;
2411 u32 bxcf;
2412 int i;
2413 int j;
5d812b8b 2414 phys_size_t base_addr;
4037ed3b
SR		 2415 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2416 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2417 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2418 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2419 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2420 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2421 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2422 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2423 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2424 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2425 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2426 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2427 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2428 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2429 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2430 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2431 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
94f54703 2432 int l;
4037ed3b
SR		 2433
2434 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2435 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2436
2437 /* Banks enabled */
2438 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
4037ed3b 2439 /* Bank is enabled */
4037ed3b 2440
5d812b8b
SR		 2441 /*
2442 * Only run test on accessable memory (below 2GB)
2443 */
2444 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2445 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2446 continue;
2447
4037ed3b
SR		 2448 /*------------------------------------------------------------------
2449 * Run the short memory test.
2450 *-----------------------------------------------------------------*/
5d812b8b 2451 membase = (u32 *)(u32)base_addr;
94f54703 2452
4037ed3b
SR		 2453 for (i = 0; i < NUMMEMTESTS; i++) {
2454 for (j = 0; j < NUMMEMWORDS; j++) {
2455 membase[j] = test[i][j];
2456 ppcDcbf((u32)&(membase[j]));
2457 }
2458 sync();
94f54703
SR		 2459 for (l=0; l<NUMLOOPS; l++) {
2460 for (j = 0; j < NUMMEMWORDS; j++) {
2461 if (membase[j] != test[i][j]) {
2462 ppcDcbf((u32)&(membase[j]));
2463 return 0;
2464 }
4037ed3b 2465 ppcDcbf((u32)&(membase[j]));
4037ed3b 2466 }
94f54703 2467 sync();
4037ed3b 2468 }
4037ed3b 2469 }
4037ed3b
SR		 2470 } /* if bank enabled */
2471 } /* for bxcf_num */
2472
94f54703 2473 return 1;
4037ed3b
SR		 2474}
2475
2476#ifndef HARD_CODED_DQS
2477/*-----------------------------------------------------------------------------+
2478 * DQS_calibration_process.
2479 *-----------------------------------------------------------------------------*/
2480static void DQS_calibration_process(void)
2481{
4037ed3b
SR		 2482 unsigned long rfdc_reg;
2483 unsigned long rffd;
4037ed3b 2484 unsigned long val;
4037ed3b
SR		 2485 long rffd_average;
2486 long max_start;
2487 long min_end;
2488 unsigned long begin_rqfd[MAXRANKS];
2489 unsigned long begin_rffd[MAXRANKS];
2490 unsigned long end_rqfd[MAXRANKS];
2491 unsigned long end_rffd[MAXRANKS];
2492 char window_found;
2493 unsigned long dlycal;
2494 unsigned long dly_val;
2495 unsigned long max_pass_length;
2496 unsigned long current_pass_length;
2497 unsigned long current_fail_length;
2498 unsigned long current_start;
2499 long max_end;
2500 unsigned char fail_found;
2501 unsigned char pass_found;
845c6c95
SR		 2502#if !defined(CONFIG_DDR_RQDC_FIXED)
2503 u32 rqdc_reg;
2504 u32 rqfd;
94f54703 2505 u32 rqfd_start;
845c6c95
SR		 2506 u32 rqfd_average;
2507 int loopi = 0;
94f54703
SR		 2508 char str[] = "Auto calibration -";
2509 char slash[] = "\\|/-\\|/-";
4037ed3b
SR		 2510
2511 /*------------------------------------------------------------------
2512 * Test to determine the best read clock delay tuning bits.
2513 *
2514 * Before the DDR controller can be used, the read clock delay needs to be
2515 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2516 * This value cannot be hardcoded into the program because it changes
2517 * depending on the board's setup and environment.
2518 * To do this, all delay values are tested to see if they
2519 * work or not. By doing this, you get groups of fails with groups of
2520 * passing values. The idea is to find the start and end of a passing
2521 * window and take the center of it to use as the read clock delay.
2522 *
2523 * A failure has to be seen first so that when we hit a pass, we know
2524 * that it is truely the start of the window. If we get passing values
2525 * to start off with, we don't know if we are at the start of the window.
2526 *
2527 * The code assumes that a failure will always be found.
2528 * If a failure is not found, there is no easy way to get the middle
2529 * of the passing window. I guess we can pretty much pick any value
2530 * but some values will be better than others. Since the lowest speed
2531 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2532 * from experimentation it is safe to say you will always have a failure.
2533 *-----------------------------------------------------------------*/
94f54703
SR		 2534
2535 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2536 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2537
2538 puts(str);
2539
2540calibration_loop:
2541 mfsdram(SDRAM_RQDC, rqdc_reg);
2542 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2543 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
845c6c95
SR		 2544#else /* CONFIG_DDR_RQDC_FIXED */
2545 /*
2546 * On Katmai the complete auto-calibration somehow doesn't seem to
2547 * produce the best results, meaning optimal values for RQFD/RFFD.
2548 * This was discovered by GDA using a high bandwidth scope,
2549 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2550 * so now on Katmai "only" RFFD is auto-calibrated.
2551 */
2552 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2553#endif /* CONFIG_DDR_RQDC_FIXED */
4037ed3b
SR		 2554
2555 max_start = 0;
2556 min_end = 0;
2557 begin_rqfd[0] = 0;
2558 begin_rffd[0] = 0;
2559 begin_rqfd[1] = 0;
2560 begin_rffd[1] = 0;
2561 end_rqfd[0] = 0;
2562 end_rffd[0] = 0;
2563 end_rqfd[1] = 0;
2564 end_rffd[1] = 0;
2565 window_found = FALSE;
2566
2567 max_pass_length = 0;
2568 max_start = 0;
2569 max_end = 0;
2570 current_pass_length = 0;
2571 current_fail_length = 0;
2572 current_start = 0;
2573 window_found = FALSE;
2574 fail_found = FALSE;
2575 pass_found = FALSE;
2576
4037ed3b
SR		 2577 /*
2578 * get the delay line calibration register value
2579 */
2580 mfsdram(SDRAM_DLCR, dlycal);
2581 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2582
2583 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2584 mfsdram(SDRAM_RFDC, rfdc_reg);
2585 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2586
2587 /*------------------------------------------------------------------
2588 * Set the timing reg for the test.
2589 *-----------------------------------------------------------------*/
2590 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2591
4037ed3b
SR		 2592 /*------------------------------------------------------------------
2593 * See if the rffd value passed.
2594 *-----------------------------------------------------------------*/
94f54703 2595 if (short_mem_test()) {
4037ed3b
SR		 2596 if (fail_found == TRUE) {
2597 pass_found = TRUE;
2598 if (current_pass_length == 0)
2599 current_start = rffd;
2600
2601 current_fail_length = 0;
2602 current_pass_length++;
2603
2604 if (current_pass_length > max_pass_length) {
2605 max_pass_length = current_pass_length;
2606 max_start = current_start;
2607 max_end = rffd;
2608 }
2609 }
2610 } else {
2611 current_pass_length = 0;
2612 current_fail_length++;
2613
2614 if (current_fail_length >= (dly_val >> 2)) {
2615 if (fail_found == FALSE) {
2616 fail_found = TRUE;
2617 } else if (pass_found == TRUE) {
2618 window_found = TRUE;
2619 break;
2620 }
2621 }
2622 }
2623 } /* for rffd */
2624
4037ed3b
SR		 2625 /*------------------------------------------------------------------
2626 * Set the average RFFD value
2627 *-----------------------------------------------------------------*/
2628 rffd_average = ((max_start + max_end) >> 1);
2629
2630 if (rffd_average < 0)
2631 rffd_average = 0;
2632
2633 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2634 rffd_average = SDRAM_RFDC_RFFD_MAX;
2635 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2636 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2637
845c6c95 2638#if !defined(CONFIG_DDR_RQDC_FIXED)
4037ed3b
SR		 2639 max_pass_length = 0;
2640 max_start = 0;
2641 max_end = 0;
2642 current_pass_length = 0;
2643 current_fail_length = 0;
2644 current_start = 0;
2645 window_found = FALSE;
2646 fail_found = FALSE;
2647 pass_found = FALSE;
2648
2649 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2650 mfsdram(SDRAM_RQDC, rqdc_reg);
2651 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2652
2653 /*------------------------------------------------------------------
2654 * Set the timing reg for the test.
2655 *-----------------------------------------------------------------*/
2656 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2657
4037ed3b
SR		 2658 /*------------------------------------------------------------------
2659 * See if the rffd value passed.
2660 *-----------------------------------------------------------------*/
94f54703 2661 if (short_mem_test()) {
4037ed3b
SR		 2662 if (fail_found == TRUE) {
2663 pass_found = TRUE;
2664 if (current_pass_length == 0)
2665 current_start = rqfd;
2666
2667 current_fail_length = 0;
2668 current_pass_length++;
2669
2670 if (current_pass_length > max_pass_length) {
2671 max_pass_length = current_pass_length;
2672 max_start = current_start;
2673 max_end = rqfd;
2674 }
2675 }
2676 } else {
2677 current_pass_length = 0;
2678 current_fail_length++;
2679
2680 if (fail_found == FALSE) {
2681 fail_found = TRUE;
2682 } else if (pass_found == TRUE) {
2683 window_found = TRUE;
2684 break;
2685 }
2686 }
2687 }
2688
94f54703
SR		 2689 rqfd_average = ((max_start + max_end) >> 1);
2690
4037ed3b
SR		 2691 /*------------------------------------------------------------------
2692 * Make sure we found the valid read passing window. Halt if not
2693 *-----------------------------------------------------------------*/
2694 if (window_found == FALSE) {
94f54703
SR		 2695 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2696 putc('\b');
2697 putc(slash[loopi++ % 8]);
2698
2699 /* try again from with a different RQFD start value */
2700 rqfd_start++;
2701 goto calibration_loop;
2702 }
2703
2704 printf("\nERROR: Cannot determine a common read delay for the "
4037ed3b
SR		 2705 "DIMM(s) installed.\n");
2706 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2e205084 2707 ppc4xx_ibm_ddr2_register_dump();
a5d71e29 2708 spd_ddr_init_hang ();
4037ed3b
SR		 2709 }
2710
4037ed3b
SR		 2711 if (rqfd_average < 0)
2712 rqfd_average = 0;
2713
2714 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2715 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2716
4037ed3b
SR		 2717 mtsdram(SDRAM_RQDC,
2718 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2719 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2720
845c6c95
SR		 2721 blank_string(strlen(str));
2722#endif /* CONFIG_DDR_RQDC_FIXED */
2723
4037ed3b 2724 mfsdram(SDRAM_DLCR, val);
48e2b535 2725 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b 2726 mfsdram(SDRAM_RQDC, val);
48e2b535 2727 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b 2728 mfsdram(SDRAM_RFDC, val);
48e2b535 2729 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
845c6c95 2730 mfsdram(SDRAM_RDCC, val);
48e2b535 2731 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b
SR		 2732}
2733#else /* calibration test with hardvalues */
2734/*-----------------------------------------------------------------------------+
2735 * DQS_calibration_process.
2736 *-----------------------------------------------------------------------------*/
2737static void test(void)
2738{
2739 unsigned long dimm_num;
2740 unsigned long ecc_temp;
2741 unsigned long i, j;
2742 unsigned long *membase;
2743 unsigned long bxcf[MAXRANKS];
2744 unsigned long val;
2745 char window_found;
2746 char begin_found[MAXDIMMS];
2747 char end_found[MAXDIMMS];
2748 char search_end[MAXDIMMS];
2749 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2750 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2751 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2752 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2753 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2754 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2755 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2756 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2757 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2758 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2759 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2760 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2761 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2762 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2763 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2764 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2765 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2766
2767 /*------------------------------------------------------------------
2768 * Test to determine the best read clock delay tuning bits.
2769 *
2770 * Before the DDR controller can be used, the read clock delay needs to be
2771 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2772 * This value cannot be hardcoded into the program because it changes
2773 * depending on the board's setup and environment.
2774 * To do this, all delay values are tested to see if they
2775 * work or not. By doing this, you get groups of fails with groups of
2776 * passing values. The idea is to find the start and end of a passing
2777 * window and take the center of it to use as the read clock delay.
2778 *
2779 * A failure has to be seen first so that when we hit a pass, we know
2780 * that it is truely the start of the window. If we get passing values
2781 * to start off with, we don't know if we are at the start of the window.
2782 *
2783 * The code assumes that a failure will always be found.
2784 * If a failure is not found, there is no easy way to get the middle
2785 * of the passing window. I guess we can pretty much pick any value
2786 * but some values will be better than others. Since the lowest speed
2787 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2788 * from experimentation it is safe to say you will always have a failure.
2789 *-----------------------------------------------------------------*/
2790 mfsdram(SDRAM_MCOPT1, ecc_temp);
2791 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2792 mfsdram(SDRAM_MCOPT1, val);
2793 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2794 SDRAM_MCOPT1_MCHK_NON);
2795
2796 window_found = FALSE;
2797 begin_found[0] = FALSE;
2798 end_found[0] = FALSE;
2799 search_end[0] = FALSE;
2800 begin_found[1] = FALSE;
2801 end_found[1] = FALSE;
2802 search_end[1] = FALSE;
2803
2804 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2805 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2806
2807 /* Banks enabled */
2808 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2809
2810 /* Bank is enabled */
2811 membase =
2812 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2813
2814 /*------------------------------------------------------------------
2815 * Run the short memory test.
2816 *-----------------------------------------------------------------*/
2817 for (i = 0; i < NUMMEMTESTS; i++) {
2818 for (j = 0; j < NUMMEMWORDS; j++) {
2819 membase[j] = test[i][j];
2820 ppcDcbf((u32)&(membase[j]));
2821 }
2822 sync();
2823 for (j = 0; j < NUMMEMWORDS; j++) {
2824 if (membase[j] != test[i][j]) {
2825 ppcDcbf((u32)&(membase[j]));
2826 break;
2827 }
2828 ppcDcbf((u32)&(membase[j]));
2829 }
2830 sync();
2831 if (j < NUMMEMWORDS)
2832 break;
2833 }
2834
2835 /*------------------------------------------------------------------
2836 * See if the rffd value passed.
2837 *-----------------------------------------------------------------*/
2838 if (i < NUMMEMTESTS) {
2839 if ((end_found[dimm_num] == FALSE) &&
2840 (search_end[dimm_num] == TRUE)) {
2841 end_found[dimm_num] = TRUE;
2842 }
2843 if ((end_found[0] == TRUE) &&
2844 (end_found[1] == TRUE))
2845 break;
2846 } else {
2847 if (begin_found[dimm_num] == FALSE) {
2848 begin_found[dimm_num] = TRUE;
2849 search_end[dimm_num] = TRUE;
2850 }
2851 }
2852 } else {
2853 begin_found[dimm_num] = TRUE;
2854 end_found[dimm_num] = TRUE;
2855 }
2856 }
2857
2858 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2859 window_found = TRUE;
2860
2861 /*------------------------------------------------------------------
2862 * Make sure we found the valid read passing window. Halt if not
2863 *-----------------------------------------------------------------*/
2864 if (window_found == FALSE) {
2865 printf("ERROR: Cannot determine a common read delay for the "
2866 "DIMM(s) installed.\n");
a5d71e29 2867 spd_ddr_init_hang ();
4037ed3b
SR		 2868 }
2869
2870 /*------------------------------------------------------------------
2871 * Restore the ECC variable to what it originally was
2872 *-----------------------------------------------------------------*/
2873 mtsdram(SDRAM_MCOPT1,
2874 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2875 | ecc_temp);
2876}
f6b6c458
AG		 2877#endif /* !HARD_CODED_DQS */
2878#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
4037ed3b 2879
08250eb2
SR		 2880#else /* CONFIG_SPD_EEPROM */
2881
c821b5f1
GE		 2882/*-----------------------------------------------------------------------------
2883 * Function: initdram
59217bae
AG		 2884 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2885 * The configuration is performed using static, compile-
c821b5f1 2886 * time parameters.
59217bae 2887 * Configures the PPC405EX(r) and PPC460EX/GT
c821b5f1 2888 *---------------------------------------------------------------------------*/
9973e3c6 2889phys_size_t initdram(int board_type)
c821b5f1 2890{
ec724f88
SR		 2891 /*
2892 * Only run this SDRAM init code once. For NAND booting
2893 * targets like Kilauea, we call initdram() early from the
2894 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2895 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2896 * which calls initdram() again. This time the controller
2897 * mustn't be reconfigured again since we're already running
2898 * from SDRAM.
2899 */
2900#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
c821b5f1
GE		 2901 unsigned long val;
2902
59217bae
AG		 2903#if defined(CONFIG_440)
2904 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2905 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2906 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2907 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2908 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2909 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2910 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2911 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2912 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2913#endif
2914
c821b5f1
GE		 2915 /* Set Memory Bank Configuration Registers */
2916
6d0f6bcf
JCPV		 2917 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2918 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2919 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2920 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
c821b5f1
GE		 2921
2922 /* Set Memory Clock Timing Register */
2923
6d0f6bcf 2924 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
c821b5f1
GE		 2925
2926 /* Set Refresh Time Register */
2927
6d0f6bcf 2928 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
c821b5f1
GE		 2929
2930 /* Set SDRAM Timing Registers */
2931
6d0f6bcf
JCPV		 2932 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2933 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2934 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
c821b5f1
GE		 2935
2936 /* Set Mode and Extended Mode Registers */
2937
6d0f6bcf
JCPV		 2938 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2939 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
c821b5f1
GE		 2940
2941 /* Set Memory Controller Options 1 Register */
2942
6d0f6bcf 2943 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
c821b5f1
GE		 2944
2945 /* Set Manual Initialization Control Registers */
2946
6d0f6bcf
JCPV		 2947 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2948 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2949 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2950 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2951 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2952 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2953 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2954 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2955 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2956 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2957 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2958 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2959 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2960 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2961 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2962 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
c821b5f1
GE		 2963
2964 /* Set On-Die Termination Registers */
2965
6d0f6bcf
JCPV		 2966 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2967 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2968 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
c821b5f1
GE		 2969
2970 /* Set Write Timing Register */
2971
6d0f6bcf 2972 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
c821b5f1
GE		 2973
2974 /*
2975 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2976 * SDRAM0_MCOPT2[IPTR] = 1
2977 */
2978
2979 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2980 SDRAM_MCOPT2_IPTR_EXECUTE));
2981
2982 /*
2983 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2984 * completion of initialization.
2985 */
2986
2987 do {
2988 mfsdram(SDRAM_MCSTAT, val);
2989 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2990
2991 /* Set Delay Control Registers */
2992
6d0f6bcf 2993 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
f6b6c458
AG		 2994
2995#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
6d0f6bcf
JCPV		 2996 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2997 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2998 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
f6b6c458 2999#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
c821b5f1
GE		 3000
3001 /*
3002 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3003 */
3004
3005 mfsdram(SDRAM_MCOPT2, val);
3006 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3007
59217bae
AG		 3008#if defined(CONFIG_440)
3009 /*
3010 * Program TLB entries with caches enabled, for best performace
3011 * while auto-calibrating and ECC generation
3012 */
3013 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3014#endif
3015
f6b6c458
AG		 3016#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3017#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3018 /*------------------------------------------------------------------
3019 | DQS calibration.
3020 +-----------------------------------------------------------------*/
3021 DQS_autocalibration();
3022#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3023#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3024
e9c020df
SR		 3025 /*
3026 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
3027 * PowerPC440SP/SPe DDR2 application note:
3028 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3029 */
3030 update_rdcc();
3031
c821b5f1 3032#if defined(CONFIG_DDR_ECC)
d24bd251 3033 do_program_ecc(0);
c821b5f1 3034#endif /* defined(CONFIG_DDR_ECC) */
2e205084 3035
59217bae
AG		 3036#if defined(CONFIG_440)
3037 /*
3038 * Now after initialization (auto-calibration and ECC generation)
3039 * remove the TLB entries with caches enabled and program again with
3040 * desired cache functionality
3041 */
3042 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3043 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3044#endif
3045
2e205084 3046 ppc4xx_ibm_ddr2_register_dump();
f6b6c458
AG		 3047
3048#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3049 /*
3050 * Clear potential errors resulting from auto-calibration.
3051 * If not done, then we could get an interrupt later on when
3052 * exceptions are enabled.
3053 */
3054 set_mcsr(get_mcsr());
3055#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3056
ec724f88 3057#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
c821b5f1 3058
6d0f6bcf 3059 return (CONFIG_SYS_MBYTES_SDRAM << 20);
c821b5f1 3060}
08250eb2 3061#endif /* CONFIG_SPD_EEPROM */
2e205084 3062
f6b6c458
AG		 3063#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3064#if defined(CONFIG_440)
3065u32 mfdcr_any(u32 dcr)
3066{
3067 u32 val;
3068
3069 switch (dcr) {
3070 case SDRAM_R0BAS + 0:
3071 val = mfdcr(SDRAM_R0BAS + 0);
3072 break;
3073 case SDRAM_R0BAS + 1:
3074 val = mfdcr(SDRAM_R0BAS + 1);
3075 break;
3076 case SDRAM_R0BAS + 2:
3077 val = mfdcr(SDRAM_R0BAS + 2);
3078 break;
3079 case SDRAM_R0BAS + 3:
3080 val = mfdcr(SDRAM_R0BAS + 3);
3081 break;
3082 default:
3083 printf("DCR %d not defined in case statement!!!\n", dcr);
3084 val = 0; /* just to satisfy the compiler */
3085 }
3086
3087 return val;
3088}
3089
3090void mtdcr_any(u32 dcr, u32 val)
3091{
3092 switch (dcr) {
3093 case SDRAM_R0BAS + 0:
3094 mtdcr(SDRAM_R0BAS + 0, val);
3095 break;
3096 case SDRAM_R0BAS + 1:
3097 mtdcr(SDRAM_R0BAS + 1, val);
3098 break;
3099 case SDRAM_R0BAS + 2:
3100 mtdcr(SDRAM_R0BAS + 2, val);
3101 break;
3102 case SDRAM_R0BAS + 3:
3103 mtdcr(SDRAM_R0BAS + 3, val);
3104 break;
3105 default:
3106 printf("DCR %d not defined in case statement!!!\n", dcr);
3107 }
3108}
3109#endif /* defined(CONFIG_440) */
f6b6c458
AG		 3110#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3111
3112inline void ppc4xx_ibm_ddr2_register_dump(void)
2e205084 3113{
08250eb2 3114#if defined(DEBUG)
2e205084
GE		 3115 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3116
3117#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3118 defined(CONFIG_460EX) || defined(CONFIG_460GT))
48e2b535
FR		 3119 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3120 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3121 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3122 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
2e205084
GE		 3123#endif /* (defined(CONFIG_440SP) || ... */
3124#if defined(CONFIG_405EX)
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3130 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3131#endif /* defined(CONFIG_405EX) */
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3144#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3145 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3148 /*
3149 * OPART is only used as a trigger register.
3150 *
3151 * No data is contained in this register, and reading or writing
3152 * to is can cause bad things to happen (hangs). Just skip it and
3153 * report "N/A".
3154 */
3155 printf("%20s = N/A\n", "SDRAM_OPART");
3156#endif /* defined(CONFIG_440SP) || ... */
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3158 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3162 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3163 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3164 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3165 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3166 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3167 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3168 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3169 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3170 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3171 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3172 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3173 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3174 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3175 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3176 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3177 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3178 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3179 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3180 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3181 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3182 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3183 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3184 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
4fe5193d 3185 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
2e205084
GE		 3186#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3187 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3188 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3189#endif /* defined(CONFIG_440SP) || ... */
3190 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3191 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3192 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
08250eb2
SR		 3193#endif /* defined(DEBUG) */
3194}
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