]>
Commit | Line | Data |
---|---|---|
0442ed86 WD |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> | |
3cb86f3e | 5 | * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering |
c821b5f1 GE |
6 | * Copyright (c) 2008 Nuovation System Designs, LLC |
7 | * Grant Erickson <gerickson@nuovations.com> | |
0442ed86 WD |
8 | * |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
83b4cfa3 | 27 | /*------------------------------------------------------------------------------+ |
31773496 JB |
28 | * This source code is dual-licensed. You may use it under the terms of the |
29 | * GNU General Public License version 2, or under the license below. | |
83b4cfa3 WD |
30 | * |
31 | * This source code has been made available to you by IBM on an AS-IS | |
32 | * basis. Anyone receiving this source is licensed under IBM | |
33 | * copyrights to use it in any way he or she deems fit, including | |
34 | * copying it, modifying it, compiling it, and redistributing it either | |
35 | * with or without modifications. No license under IBM patents or | |
36 | * patent applications is to be implied by the copyright license. | |
37 | * | |
38 | * Any user of this software should understand that IBM cannot provide | |
39 | * technical support for this software and will not be responsible for | |
40 | * any consequences resulting from the use of this software. | |
41 | * | |
42 | * Any person who transfers this source code or any derivative work | |
43 | * must include the IBM copyright notice, this paragraph, and the | |
44 | * preceding two paragraphs in the transferred software. | |
45 | * | |
46 | * COPYRIGHT I B M CORPORATION 1995 | |
47 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
48 | *------------------------------------------------------------------------------- | |
49 | */ | |
0442ed86 | 50 | |
0c8721a4 | 51 | /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards |
0442ed86 WD |
52 | * |
53 | * | |
54 | * The processor starts at 0xfffffffc and the code is executed | |
55 | * from flash/rom. | |
56 | * in memory, but as long we don't jump around before relocating. | |
57 | * board_init lies at a quite high address and when the cpu has | |
58 | * jumped there, everything is ok. | |
59 | * This works because the cpu gives the FLASH (CS0) the whole | |
60 | * address space at startup, and board_init lies as a echo of | |
61 | * the flash somewhere up there in the memorymap. | |
62 | * | |
63 | * board_init will change CS0 to be positioned at the correct | |
64 | * address and (s)dram will be positioned at address 0 | |
65 | */ | |
25ddd1fb | 66 | #include <asm-offsets.h> |
0442ed86 | 67 | #include <config.h> |
b36df561 | 68 | #include <asm/ppc4xx.h> |
561858ee | 69 | #include <timestamp.h> |
0442ed86 WD |
70 | #include <version.h> |
71 | ||
72 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
73 | ||
74 | #include <ppc_asm.tmpl> | |
75 | #include <ppc_defs.h> | |
76 | ||
77 | #include <asm/cache.h> | |
78 | #include <asm/mmu.h> | |
b14ca4b6 | 79 | #include <asm/ppc4xx-isram.h> |
0442ed86 WD |
80 | |
81 | #ifndef CONFIG_IDENT_STRING | |
82 | #define CONFIG_IDENT_STRING "" | |
83 | #endif | |
84 | ||
6d0f6bcf JCPV |
85 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
86 | # if (CONFIG_SYS_INIT_DCACHE_CS == 0) | |
d1c3b275 SR |
87 | # define PBxAP PB1AP |
88 | # define PBxCR PB0CR | |
6d0f6bcf JCPV |
89 | # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
90 | # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP | |
91 | # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR | |
c821b5f1 | 92 | # endif |
0442ed86 | 93 | # endif |
6d0f6bcf | 94 | # if (CONFIG_SYS_INIT_DCACHE_CS == 1) |
d1c3b275 SR |
95 | # define PBxAP PB1AP |
96 | # define PBxCR PB1CR | |
6d0f6bcf JCPV |
97 | # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) |
98 | # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP | |
99 | # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR | |
c821b5f1 | 100 | # endif |
0442ed86 | 101 | # endif |
6d0f6bcf | 102 | # if (CONFIG_SYS_INIT_DCACHE_CS == 2) |
d1c3b275 SR |
103 | # define PBxAP PB2AP |
104 | # define PBxCR PB2CR | |
6d0f6bcf JCPV |
105 | # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) |
106 | # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP | |
107 | # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR | |
c821b5f1 | 108 | # endif |
0442ed86 | 109 | # endif |
6d0f6bcf | 110 | # if (CONFIG_SYS_INIT_DCACHE_CS == 3) |
d1c3b275 SR |
111 | # define PBxAP PB3AP |
112 | # define PBxCR PB3CR | |
6d0f6bcf JCPV |
113 | # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) |
114 | # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP | |
115 | # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR | |
c821b5f1 | 116 | # endif |
0442ed86 | 117 | # endif |
6d0f6bcf | 118 | # if (CONFIG_SYS_INIT_DCACHE_CS == 4) |
d1c3b275 SR |
119 | # define PBxAP PB4AP |
120 | # define PBxCR PB4CR | |
6d0f6bcf JCPV |
121 | # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) |
122 | # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP | |
123 | # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR | |
c821b5f1 | 124 | # endif |
0442ed86 | 125 | # endif |
6d0f6bcf | 126 | # if (CONFIG_SYS_INIT_DCACHE_CS == 5) |
d1c3b275 SR |
127 | # define PBxAP PB5AP |
128 | # define PBxCR PB5CR | |
6d0f6bcf JCPV |
129 | # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) |
130 | # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP | |
131 | # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR | |
c821b5f1 | 132 | # endif |
0442ed86 | 133 | # endif |
6d0f6bcf | 134 | # if (CONFIG_SYS_INIT_DCACHE_CS == 6) |
d1c3b275 SR |
135 | # define PBxAP PB6AP |
136 | # define PBxCR PB6CR | |
6d0f6bcf JCPV |
137 | # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) |
138 | # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP | |
139 | # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR | |
c821b5f1 | 140 | # endif |
0442ed86 | 141 | # endif |
6d0f6bcf | 142 | # if (CONFIG_SYS_INIT_DCACHE_CS == 7) |
d1c3b275 SR |
143 | # define PBxAP PB7AP |
144 | # define PBxCR PB7CR | |
6d0f6bcf JCPV |
145 | # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) |
146 | # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP | |
147 | # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR | |
c821b5f1 GE |
148 | # endif |
149 | # endif | |
150 | # ifndef PBxAP_VAL | |
151 | # define PBxAP_VAL 0 | |
152 | # endif | |
153 | # ifndef PBxCR_VAL | |
154 | # define PBxCR_VAL 0 | |
155 | # endif | |
156 | /* | |
6d0f6bcf | 157 | * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB |
c821b5f1 GE |
158 | * used as temporary stack pointer for the primordial stack |
159 | */ | |
6d0f6bcf JCPV |
160 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR |
161 | # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ | |
c821b5f1 GE |
162 | EBC_BXAP_TWT_ENCODE(7) | \ |
163 | EBC_BXAP_BCE_DISABLE | \ | |
164 | EBC_BXAP_BCT_2TRANS | \ | |
165 | EBC_BXAP_CSN_ENCODE(0) | \ | |
166 | EBC_BXAP_OEN_ENCODE(0) | \ | |
167 | EBC_BXAP_WBN_ENCODE(0) | \ | |
168 | EBC_BXAP_WBF_ENCODE(0) | \ | |
169 | EBC_BXAP_TH_ENCODE(2) | \ | |
170 | EBC_BXAP_RE_DISABLED | \ | |
171 | EBC_BXAP_SOR_NONDELAYED | \ | |
172 | EBC_BXAP_BEM_WRITEONLY | \ | |
173 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf JCPV |
174 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ |
175 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR | |
176 | # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ | |
c821b5f1 GE |
177 | EBC_BXCR_BS_64MB | \ |
178 | EBC_BXCR_BU_RW | \ | |
179 | EBC_BXCR_BW_16BIT) | |
6d0f6bcf JCPV |
180 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ |
181 | # ifndef CONFIG_SYS_INIT_RAM_PATTERN | |
182 | # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD | |
0442ed86 | 183 | # endif |
6d0f6bcf | 184 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 185 | |
553f0982 WD |
186 | #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10))) |
187 | #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE! | |
28d77d96 SR |
188 | #endif |
189 | ||
c821b5f1 GE |
190 | /* |
191 | * Unless otherwise overriden, enable two 128MB cachable instruction regions | |
6d0f6bcf JCPV |
192 | * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering |
193 | * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. | |
c821b5f1 | 194 | */ |
6d0f6bcf | 195 | #if !defined(CONFIG_SYS_FLASH_BASE) |
64852d09 | 196 | /* If not already defined, set it to the "last" 128MByte region */ |
6d0f6bcf | 197 | # define CONFIG_SYS_FLASH_BASE 0xf8000000 |
64852d09 | 198 | #endif |
6d0f6bcf JCPV |
199 | #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) |
200 | # define CONFIG_SYS_ICACHE_SACR_VALUE \ | |
201 | (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ | |
202 | PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ | |
203 | PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) | |
204 | #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ | |
205 | ||
206 | #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) | |
207 | # define CONFIG_SYS_DCACHE_SACR_VALUE \ | |
c821b5f1 | 208 | (0x00000000) |
6d0f6bcf | 209 | #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ |
c821b5f1 | 210 | |
4978e605 SR |
211 | #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH) |
212 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */ | |
213 | #endif | |
214 | ||
83b4cfa3 | 215 | #define function_prolog(func_name) .text; \ |
cf959c7d SR |
216 | .align 2; \ |
217 | .globl func_name; \ | |
218 | func_name: | |
83b4cfa3 | 219 | #define function_epilog(func_name) .type func_name,@function; \ |
cf959c7d SR |
220 | .size func_name,.-func_name |
221 | ||
0442ed86 WD |
222 | /* We don't want the MMU yet. |
223 | */ | |
224 | #undef MSR_KERNEL | |
225 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ | |
226 | ||
227 | ||
228 | .extern ext_bus_cntlr_init | |
887e2ec9 SR |
229 | #ifdef CONFIG_NAND_U_BOOT |
230 | .extern reconfig_tlb0 | |
231 | #endif | |
0442ed86 WD |
232 | |
233 | /* | |
234 | * Set up GOT: Global Offset Table | |
235 | * | |
0f8aa159 | 236 | * Use r12 to access the GOT |
0442ed86 | 237 | */ |
887e2ec9 | 238 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 WD |
239 | START_GOT |
240 | GOT_ENTRY(_GOT2_TABLE_) | |
241 | GOT_ENTRY(_FIXUP_TABLE_) | |
242 | ||
243 | GOT_ENTRY(_start) | |
244 | GOT_ENTRY(_start_of_vectors) | |
245 | GOT_ENTRY(_end_of_vectors) | |
246 | GOT_ENTRY(transfer_to_handler) | |
247 | ||
3b57fe0a | 248 | GOT_ENTRY(__init_end) |
0442ed86 | 249 | GOT_ENTRY(_end) |
5d232d0e | 250 | GOT_ENTRY(__bss_start) |
0442ed86 | 251 | END_GOT |
887e2ec9 SR |
252 | #endif /* CONFIG_NAND_SPL */ |
253 | ||
254 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
255 | /* | |
256 | * NAND U-Boot image is started from offset 0 | |
257 | */ | |
258 | .text | |
c440bfe6 | 259 | #if defined(CONFIG_440) |
887e2ec9 | 260 | bl reconfig_tlb0 |
c440bfe6 | 261 | #endif |
887e2ec9 SR |
262 | GET_GOT |
263 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
264 | bl board_init_f | |
52ebd9c1 | 265 | /* NOTREACHED - board_init_f() does not return */ |
887e2ec9 | 266 | #endif |
0442ed86 | 267 | |
d873133f SR |
268 | #if defined(CONFIG_SYS_RAMBOOT) |
269 | /* | |
270 | * 4xx RAM-booting U-Boot image is started from offset 0 | |
271 | */ | |
272 | .text | |
273 | bl _start_440 | |
274 | #endif | |
275 | ||
0442ed86 WD |
276 | /* |
277 | * 440 Startup -- on reset only the top 4k of the effective | |
278 | * address space is mapped in by an entry in the instruction | |
279 | * and data shadow TLB. The .bootpg section is located in the | |
280 | * top 4k & does only what's necessary to map in the the rest | |
281 | * of the boot rom. Once the boot rom is mapped in we can | |
282 | * proceed with normal startup. | |
283 | * | |
284 | * NOTE: CS0 only covers the top 2MB of the effective address | |
285 | * space after reset. | |
286 | */ | |
287 | ||
288 | #if defined(CONFIG_440) | |
887e2ec9 | 289 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 | 290 | .section .bootpg,"ax" |
887e2ec9 | 291 | #endif |
0442ed86 WD |
292 | .globl _start_440 |
293 | ||
294 | /**************************************************************************/ | |
295 | _start_440: | |
511d0c72 WD |
296 | /*--------------------------------------------------------------------+ |
297 | | 440EPX BUP Change - Hardware team request | |
298 | +--------------------------------------------------------------------*/ | |
887e2ec9 SR |
299 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
300 | sync | |
301 | nop | |
302 | nop | |
303 | #endif | |
6c5879f3 MB |
304 | /*----------------------------------------------------------------+ |
305 | | Core bug fix. Clear the esr | |
306 | +-----------------------------------------------------------------*/ | |
edd6cf20 | 307 | li r0,0 |
58ea142f | 308 | mtspr SPRN_ESR,r0 |
0442ed86 WD |
309 | /*----------------------------------------------------------------*/ |
310 | /* Clear and set up some registers. */ | |
311 | /*----------------------------------------------------------------*/ | |
f901a83b WD |
312 | iccci r0,r0 /* NOTE: operands not used for 440 */ |
313 | dccci r0,r0 /* NOTE: operands not used for 440 */ | |
0442ed86 WD |
314 | sync |
315 | li r0,0 | |
58ea142f MF |
316 | mtspr SPRN_SRR0,r0 |
317 | mtspr SPRN_SRR1,r0 | |
318 | mtspr SPRN_CSRR0,r0 | |
319 | mtspr SPRN_CSRR1,r0 | |
887e2ec9 SR |
320 | /* NOTE: 440GX adds machine check status regs */ |
321 | #if defined(CONFIG_440) && !defined(CONFIG_440GP) | |
58ea142f MF |
322 | mtspr SPRN_MCSRR0,r0 |
323 | mtspr SPRN_MCSRR1,r0 | |
324 | mfspr r1,SPRN_MCSR | |
325 | mtspr SPRN_MCSR,r1 | |
ba56f625 | 326 | #endif |
20532833 SR |
327 | |
328 | /*----------------------------------------------------------------*/ | |
329 | /* CCR0 init */ | |
330 | /*----------------------------------------------------------------*/ | |
331 | /* Disable store gathering & broadcast, guarantee inst/data | |
332 | * cache block touch, force load/store alignment | |
333 | * (see errata 1.12: 440_33) | |
334 | */ | |
335 | lis r1,0x0030 /* store gathering & broadcast disable */ | |
336 | ori r1,r1,0x6000 /* cache touch */ | |
58ea142f | 337 | mtspr SPRN_CCR0,r1 |
20532833 | 338 | |
0442ed86 WD |
339 | /*----------------------------------------------------------------*/ |
340 | /* Initialize debug */ | |
341 | /*----------------------------------------------------------------*/ | |
58ea142f | 342 | mfspr r1,SPRN_DBCR0 |
887e2ec9 SR |
343 | andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ |
344 | bne skip_debug_init /* if set, don't clear debug register */ | |
ad876fff VG |
345 | mfspr r1,SPRN_CCR0 |
346 | ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ | |
347 | mtspr SPRN_CCR0,r1 | |
58ea142f MF |
348 | mtspr SPRN_DBCR0,r0 |
349 | mtspr SPRN_DBCR1,r0 | |
350 | mtspr SPRN_DBCR2,r0 | |
351 | mtspr SPRN_IAC1,r0 | |
352 | mtspr SPRN_IAC2,r0 | |
353 | mtspr SPRN_IAC3,r0 | |
354 | mtspr SPRN_DAC1,r0 | |
355 | mtspr SPRN_DAC2,r0 | |
356 | mtspr SPRN_DVC1,r0 | |
357 | mtspr SPRN_DVC2,r0 | |
358 | ||
359 | mfspr r1,SPRN_DBSR | |
360 | mtspr SPRN_DBSR,r1 /* Clear all valid bits */ | |
887e2ec9 | 361 | skip_debug_init: |
0442ed86 | 362 | |
6c5879f3 MB |
363 | #if defined (CONFIG_440SPE) |
364 | /*----------------------------------------------------------------+ | |
365 | | Initialize Core Configuration Reg1. | |
366 | | a. ICDPEI: Record even parity. Normal operation. | |
367 | | b. ICTPEI: Record even parity. Normal operation. | |
368 | | c. DCTPEI: Record even parity. Normal operation. | |
369 | | d. DCDPEI: Record even parity. Normal operation. | |
370 | | e. DCUPEI: Record even parity. Normal operation. | |
371 | | f. DCMPEI: Record even parity. Normal operation. | |
372 | | g. FCOM: Normal operation | |
373 | | h. MMUPEI: Record even parity. Normal operation. | |
374 | | i. FFF: Flush only as much data as necessary. | |
edd6cf20 | 375 | | j. TCS: Timebase increments from CPU clock. |
6c5879f3 | 376 | +-----------------------------------------------------------------*/ |
edd6cf20 | 377 | li r0,0 |
58ea142f | 378 | mtspr SPRN_CCR1, r0 |
6c5879f3 MB |
379 | |
380 | /*----------------------------------------------------------------+ | |
381 | | Reset the timebase. | |
382 | | The previous write to CCR1 sets the timebase source. | |
383 | +-----------------------------------------------------------------*/ | |
58ea142f MF |
384 | mtspr SPRN_TBWL, r0 |
385 | mtspr SPRN_TBWU, r0 | |
6c5879f3 MB |
386 | #endif |
387 | ||
0442ed86 WD |
388 | /*----------------------------------------------------------------*/ |
389 | /* Setup interrupt vectors */ | |
390 | /*----------------------------------------------------------------*/ | |
58ea142f | 391 | mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ |
f901a83b | 392 | li r1,0x0100 |
58ea142f | 393 | mtspr SPRN_IVOR0,r1 /* Critical input */ |
f901a83b | 394 | li r1,0x0200 |
58ea142f | 395 | mtspr SPRN_IVOR1,r1 /* Machine check */ |
f901a83b | 396 | li r1,0x0300 |
58ea142f | 397 | mtspr SPRN_IVOR2,r1 /* Data storage */ |
f901a83b | 398 | li r1,0x0400 |
58ea142f | 399 | mtspr SPRN_IVOR3,r1 /* Instruction storage */ |
0442ed86 | 400 | li r1,0x0500 |
58ea142f | 401 | mtspr SPRN_IVOR4,r1 /* External interrupt */ |
0442ed86 | 402 | li r1,0x0600 |
58ea142f | 403 | mtspr SPRN_IVOR5,r1 /* Alignment */ |
0442ed86 | 404 | li r1,0x0700 |
58ea142f | 405 | mtspr SPRN_IVOR6,r1 /* Program check */ |
0442ed86 | 406 | li r1,0x0800 |
58ea142f | 407 | mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ |
0442ed86 | 408 | li r1,0x0c00 |
58ea142f | 409 | mtspr SPRN_IVOR8,r1 /* System call */ |
efa35cf1 | 410 | li r1,0x0a00 |
58ea142f | 411 | mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ |
efa35cf1 | 412 | li r1,0x0900 |
58ea142f | 413 | mtspr SPRN_IVOR10,r1 /* Decrementer */ |
0442ed86 | 414 | li r1,0x1300 |
58ea142f | 415 | mtspr SPRN_IVOR13,r1 /* Data TLB error */ |
efa35cf1 | 416 | li r1,0x1400 |
58ea142f | 417 | mtspr SPRN_IVOR14,r1 /* Instr TLB error */ |
0442ed86 | 418 | li r1,0x2000 |
58ea142f | 419 | mtspr SPRN_IVOR15,r1 /* Debug */ |
0442ed86 WD |
420 | |
421 | /*----------------------------------------------------------------*/ | |
422 | /* Configure cache regions */ | |
423 | /*----------------------------------------------------------------*/ | |
58ea142f MF |
424 | mtspr SPRN_INV0,r0 |
425 | mtspr SPRN_INV1,r0 | |
426 | mtspr SPRN_INV2,r0 | |
427 | mtspr SPRN_INV3,r0 | |
428 | mtspr SPRN_DNV0,r0 | |
429 | mtspr SPRN_DNV1,r0 | |
430 | mtspr SPRN_DNV2,r0 | |
431 | mtspr SPRN_DNV3,r0 | |
432 | mtspr SPRN_ITV0,r0 | |
433 | mtspr SPRN_ITV1,r0 | |
434 | mtspr SPRN_ITV2,r0 | |
435 | mtspr SPRN_ITV3,r0 | |
436 | mtspr SPRN_DTV0,r0 | |
437 | mtspr SPRN_DTV1,r0 | |
438 | mtspr SPRN_DTV2,r0 | |
439 | mtspr SPRN_DTV3,r0 | |
0442ed86 WD |
440 | |
441 | /*----------------------------------------------------------------*/ | |
442 | /* Cache victim limits */ | |
443 | /*----------------------------------------------------------------*/ | |
444 | /* floors 0, ceiling max to use the entire cache -- nothing locked | |
445 | */ | |
446 | lis r1,0x0001 | |
447 | ori r1,r1,0xf800 | |
58ea142f MF |
448 | mtspr SPRN_IVLIM,r1 |
449 | mtspr SPRN_DVLIM,r1 | |
0442ed86 | 450 | |
6c5879f3 MB |
451 | /*----------------------------------------------------------------+ |
452 | |Initialize MMUCR[STID] = 0. | |
453 | +-----------------------------------------------------------------*/ | |
58ea142f | 454 | mfspr r0,SPRN_MMUCR |
6c5879f3 MB |
455 | addis r1,0,0xFFFF |
456 | ori r1,r1,0xFF00 | |
457 | and r0,r0,r1 | |
58ea142f | 458 | mtspr SPRN_MMUCR,r0 |
6c5879f3 | 459 | |
0442ed86 WD |
460 | /*----------------------------------------------------------------*/ |
461 | /* Clear all TLB entries -- TID = 0, TS = 0 */ | |
462 | /*----------------------------------------------------------------*/ | |
6c5879f3 | 463 | addis r0,0,0x0000 |
0a371ca0 | 464 | #ifdef CONFIG_SYS_RAMBOOT |
d873133f | 465 | li r4,0 /* Start with TLB #0 */ |
0a371ca0 SR |
466 | #else |
467 | li r4,1 /* Start with TLB #1 */ | |
468 | #endif | |
469 | li r1,64 /* 64 TLB entries */ | |
470 | sub r1,r1,r4 /* calculate last TLB # */ | |
471 | mtctr r1 | |
d873133f SR |
472 | rsttlb: |
473 | #ifdef CONFIG_SYS_RAMBOOT | |
474 | tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ | |
475 | rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ | |
476 | beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ | |
477 | #endif | |
478 | tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ | |
479 | tlbwe r0,r4,1 | |
480 | tlbwe r0,r4,2 | |
481 | tlbnxt: addi r4,r4,1 /* Next TLB */ | |
6c5879f3 | 482 | bdnz rsttlb |
0442ed86 WD |
483 | |
484 | /*----------------------------------------------------------------*/ | |
485 | /* TLB entry setup -- step thru tlbtab */ | |
486 | /*----------------------------------------------------------------*/ | |
2a72e9ed | 487 | #if defined(CONFIG_440SPE_REVA) |
692519b1 RJ |
488 | /*----------------------------------------------------------------*/ |
489 | /* We have different TLB tables for revA and rev B of 440SPe */ | |
490 | /*----------------------------------------------------------------*/ | |
491 | mfspr r1, PVR | |
492 | lis r0,0x5342 | |
493 | ori r0,r0,0x1891 | |
494 | cmpw r7,r1,r0 | |
495 | bne r7,..revA | |
496 | bl tlbtabB | |
497 | b ..goon | |
498 | ..revA: | |
499 | bl tlbtabA | |
500 | ..goon: | |
501 | #else | |
0442ed86 | 502 | bl tlbtab /* Get tlbtab pointer */ |
692519b1 | 503 | #endif |
0442ed86 WD |
504 | mr r5,r0 |
505 | li r1,0x003f /* 64 TLB entries max */ | |
506 | mtctr r1 | |
507 | li r4,0 /* TLB # */ | |
508 | ||
509 | addi r5,r5,-4 | |
d873133f SR |
510 | 1: |
511 | #ifdef CONFIG_SYS_RAMBOOT | |
512 | tlbre r3,r4,0 /* Read contents from TLB word #0 */ | |
513 | rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ | |
514 | bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ | |
515 | #endif | |
516 | lwzu r0,4(r5) | |
0442ed86 WD |
517 | cmpwi r0,0 |
518 | beq 2f /* 0 marks end */ | |
519 | lwzu r1,4(r5) | |
520 | lwzu r2,4(r5) | |
521 | tlbwe r0,r4,0 /* TLB Word 0 */ | |
522 | tlbwe r1,r4,1 /* TLB Word 1 */ | |
523 | tlbwe r2,r4,2 /* TLB Word 2 */ | |
d873133f | 524 | tlbnx2: addi r4,r4,1 /* Next TLB */ |
0442ed86 WD |
525 | bdnz 1b |
526 | ||
527 | /*----------------------------------------------------------------*/ | |
528 | /* Continue from 'normal' start */ | |
529 | /*----------------------------------------------------------------*/ | |
887e2ec9 | 530 | 2: |
887e2ec9 | 531 | bl 3f |
0442ed86 WD |
532 | b _start |
533 | ||
534 | 3: li r0,0 | |
58ea142f | 535 | mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ |
0442ed86 | 536 | mflr r1 |
58ea142f | 537 | mtspr SPRN_SRR0,r1 |
0442ed86 | 538 | rfi |
b867d705 | 539 | #endif /* CONFIG_440 */ |
0442ed86 WD |
540 | |
541 | /* | |
542 | * r3 - 1st arg to board_init(): IMMP pointer | |
543 | * r4 - 2nd arg to board_init(): boot flag | |
544 | */ | |
887e2ec9 | 545 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
546 | .text |
547 | .long 0x27051956 /* U-Boot Magic Number */ | |
548 | .globl version_string | |
549 | version_string: | |
550 | .ascii U_BOOT_VERSION | |
561858ee | 551 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
0442ed86 WD |
552 | .ascii CONFIG_IDENT_STRING, "\0" |
553 | ||
0442ed86 | 554 | . = EXC_OFF_SYS_RESET |
efa35cf1 GB |
555 | .globl _start_of_vectors |
556 | _start_of_vectors: | |
557 | ||
558 | /* Critical input. */ | |
559 | CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) | |
560 | ||
561 | #ifdef CONFIG_440 | |
562 | /* Machine check */ | |
83b4cfa3 | 563 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 | 564 | #else |
83b4cfa3 | 565 | CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 GB |
566 | #endif /* CONFIG_440 */ |
567 | ||
568 | /* Data Storage exception. */ | |
569 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
570 | ||
571 | /* Instruction Storage exception. */ | |
572 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
573 | ||
574 | /* External Interrupt exception. */ | |
575 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
576 | ||
577 | /* Alignment exception. */ | |
578 | . = 0x600 | |
579 | Alignment: | |
580 | EXCEPTION_PROLOG(SRR0, SRR1) | |
581 | mfspr r4,DAR | |
582 | stw r4,_DAR(r21) | |
583 | mfspr r5,DSISR | |
584 | stw r5,_DSISR(r21) | |
585 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 | 586 | EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) |
efa35cf1 GB |
587 | |
588 | /* Program check exception */ | |
589 | . = 0x700 | |
590 | ProgramCheck: | |
591 | EXCEPTION_PROLOG(SRR0, SRR1) | |
592 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 JT |
593 | EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, |
594 | MSR_KERNEL, COPY_EE) | |
efa35cf1 GB |
595 | |
596 | #ifdef CONFIG_440 | |
597 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
598 | STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) | |
599 | STD_EXCEPTION(0xa00, APU, UnknownException) | |
df8a24cd | 600 | #endif |
efa35cf1 GB |
601 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) |
602 | ||
603 | #ifdef CONFIG_440 | |
604 | STD_EXCEPTION(0x1300, DataTLBError, UnknownException) | |
605 | STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) | |
606 | #else | |
607 | STD_EXCEPTION(0x1000, PIT, DecrementerPITException) | |
608 | STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) | |
609 | STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) | |
610 | #endif | |
611 | CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) | |
612 | ||
613 | .globl _end_of_vectors | |
614 | _end_of_vectors: | |
615 | . = _START_OFFSET | |
887e2ec9 | 616 | #endif |
0442ed86 WD |
617 | .globl _start |
618 | _start: | |
619 | ||
620 | /*****************************************************************************/ | |
621 | #if defined(CONFIG_440) | |
622 | ||
623 | /*----------------------------------------------------------------*/ | |
624 | /* Clear and set up some registers. */ | |
625 | /*----------------------------------------------------------------*/ | |
626 | li r0,0x0000 | |
627 | lis r1,0xffff | |
58ea142f MF |
628 | mtspr SPRN_DEC,r0 /* prevent dec exceptions */ |
629 | mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ | |
630 | mtspr SPRN_TBWU,r0 | |
631 | mtspr SPRN_TSR,r1 /* clear all timer exception status */ | |
632 | mtspr SPRN_TCR,r0 /* disable all */ | |
633 | mtspr SPRN_ESR,r0 /* clear exception syndrome register */ | |
0442ed86 | 634 | mtxer r0 /* clear integer exception register */ |
0442ed86 WD |
635 | |
636 | /*----------------------------------------------------------------*/ | |
637 | /* Debug setup -- some (not very good) ice's need an event*/ | |
6d0f6bcf | 638 | /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ |
0442ed86 WD |
639 | /* value you need in this case 0x8cff 0000 should do the trick */ |
640 | /*----------------------------------------------------------------*/ | |
6d0f6bcf | 641 | #if defined(CONFIG_SYS_INIT_DBCR) |
0442ed86 WD |
642 | lis r1,0xffff |
643 | ori r1,r1,0xffff | |
58ea142f | 644 | mtspr SPRN_DBSR,r1 /* Clear all status bits */ |
6d0f6bcf JCPV |
645 | lis r0,CONFIG_SYS_INIT_DBCR@h |
646 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
58ea142f | 647 | mtspr SPRN_DBCR0,r0 |
0442ed86 WD |
648 | isync |
649 | #endif | |
650 | ||
651 | /*----------------------------------------------------------------*/ | |
652 | /* Setup the internal SRAM */ | |
653 | /*----------------------------------------------------------------*/ | |
654 | li r0,0 | |
887e2ec9 | 655 | |
6d0f6bcf | 656 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
c157d8e2 | 657 | /* Clear Dcache to use as RAM */ |
6d0f6bcf JCPV |
658 | addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
659 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
553f0982 WD |
660 | addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h |
661 | ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l | |
c157d8e2 | 662 | rlwinm. r5,r4,0,27,31 |
f901a83b WD |
663 | rlwinm r5,r4,27,5,31 |
664 | beq ..d_ran | |
665 | addi r5,r5,0x0001 | |
c157d8e2 | 666 | ..d_ran: |
f901a83b | 667 | mtctr r5 |
c157d8e2 | 668 | ..d_ag: |
f901a83b WD |
669 | dcbz r0,r3 |
670 | addi r3,r3,32 | |
671 | bdnz ..d_ag | |
e02c521d SR |
672 | |
673 | /* | |
674 | * Lock the init-ram/stack in d-cache, so that other regions | |
675 | * may use d-cache as well | |
676 | * Note, that this current implementation locks exactly 4k | |
677 | * of d-cache, so please make sure that you don't define a | |
678 | * bigger init-ram area. Take a look at the lwmon5 440EPx | |
679 | * implementation as a reference. | |
680 | */ | |
681 | msync | |
682 | isync | |
683 | /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ | |
684 | lis r1,0x0201 | |
685 | ori r1,r1,0xf808 | |
58ea142f | 686 | mtspr SPRN_DVLIM,r1 |
e02c521d SR |
687 | lis r1,0x0808 |
688 | ori r1,r1,0x0808 | |
58ea142f MF |
689 | mtspr SPRN_DNV0,r1 |
690 | mtspr SPRN_DNV1,r1 | |
691 | mtspr SPRN_DNV2,r1 | |
692 | mtspr SPRN_DNV3,r1 | |
693 | mtspr SPRN_DTV0,r1 | |
694 | mtspr SPRN_DTV1,r1 | |
695 | mtspr SPRN_DTV2,r1 | |
696 | mtspr SPRN_DTV3,r1 | |
e02c521d SR |
697 | msync |
698 | isync | |
6d0f6bcf | 699 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
887e2ec9 SR |
700 | |
701 | /* 440EP & 440GR are only 440er PPC's without internal SRAM */ | |
702 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) | |
703 | /* not all PPC's have internal SRAM usable as L2-cache */ | |
2801b2d2 SR |
704 | #if defined(CONFIG_440GX) || \ |
705 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
7d307936 | 706 | defined(CONFIG_460SX) |
b14ca4b6 | 707 | mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ |
1b8fec13 TM |
708 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
709 | defined(CONFIG_APM821XX) | |
ddf45cc7 DM |
710 | lis r1, 0x0000 |
711 | ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ | |
712 | mtdcr L2_CACHE_CFG,r1 | |
ba56f625 | 713 | #endif |
0442ed86 | 714 | |
887e2ec9 | 715 | lis r2,0x7fff |
0442ed86 | 716 | ori r2,r2,0xffff |
b14ca4b6 | 717 | mfdcr r1,ISRAM0_DPC |
0442ed86 | 718 | and r1,r1,r2 /* Disable parity check */ |
b14ca4b6 DM |
719 | mtdcr ISRAM0_DPC,r1 |
720 | mfdcr r1,ISRAM0_PMEG | |
887e2ec9 | 721 | and r1,r1,r2 /* Disable pwr mgmt */ |
b14ca4b6 | 722 | mtdcr ISRAM0_PMEG,r1 |
0442ed86 WD |
723 | |
724 | lis r1,0x8000 /* BAS = 8000_0000 */ | |
6e7fb6ea | 725 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
ba56f625 | 726 | ori r1,r1,0x0980 /* first 64k */ |
b14ca4b6 | 727 | mtdcr ISRAM0_SB0CR,r1 |
ba56f625 WD |
728 | lis r1,0x8001 |
729 | ori r1,r1,0x0980 /* second 64k */ | |
b14ca4b6 | 730 | mtdcr ISRAM0_SB1CR,r1 |
ba56f625 WD |
731 | lis r1, 0x8002 |
732 | ori r1,r1, 0x0980 /* third 64k */ | |
b14ca4b6 | 733 | mtdcr ISRAM0_SB2CR,r1 |
ba56f625 WD |
734 | lis r1, 0x8003 |
735 | ori r1,r1, 0x0980 /* fourth 64k */ | |
b14ca4b6 | 736 | mtdcr ISRAM0_SB3CR,r1 |
1b8fec13 TM |
737 | #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ |
738 | defined(CONFIG_460GT) || defined(CONFIG_APM821XX) | |
ddf45cc7 | 739 | lis r1,0x0000 /* BAS = X_0000_0000 */ |
6c5879f3 | 740 | ori r1,r1,0x0984 /* first 64k */ |
b14ca4b6 | 741 | mtdcr ISRAM0_SB0CR,r1 |
6c5879f3 MB |
742 | lis r1,0x0001 |
743 | ori r1,r1,0x0984 /* second 64k */ | |
b14ca4b6 | 744 | mtdcr ISRAM0_SB1CR,r1 |
6c5879f3 MB |
745 | lis r1, 0x0002 |
746 | ori r1,r1, 0x0984 /* third 64k */ | |
b14ca4b6 | 747 | mtdcr ISRAM0_SB2CR,r1 |
6c5879f3 MB |
748 | lis r1, 0x0003 |
749 | ori r1,r1, 0x0984 /* fourth 64k */ | |
b14ca4b6 | 750 | mtdcr ISRAM0_SB3CR,r1 |
1b8fec13 TM |
751 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
752 | defined(CONFIG_APM821XX) | |
ddf45cc7 DM |
753 | lis r2,0x7fff |
754 | ori r2,r2,0xffff | |
755 | mfdcr r1,ISRAM1_DPC | |
756 | and r1,r1,r2 /* Disable parity check */ | |
455ae7e8 | 757 | mtdcr ISRAM1_DPC,r1 |
ddf45cc7 DM |
758 | mfdcr r1,ISRAM1_PMEG |
759 | and r1,r1,r2 /* Disable pwr mgmt */ | |
760 | mtdcr ISRAM1_PMEG,r1 | |
761 | ||
762 | lis r1,0x0004 /* BAS = 4_0004_0000 */ | |
1b8fec13 | 763 | ori r1,r1,ISRAM1_SIZE /* ocm size */ |
ddf45cc7 DM |
764 | mtdcr ISRAM1_SB0CR,r1 |
765 | #endif | |
7d307936 FK |
766 | #elif defined(CONFIG_460SX) |
767 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
768 | ori r1,r1,0x0B84 /* first 128k */ | |
b14ca4b6 | 769 | mtdcr ISRAM0_SB0CR,r1 |
7d307936 FK |
770 | lis r1,0x0001 |
771 | ori r1,r1,0x0B84 /* second 128k */ | |
b14ca4b6 | 772 | mtdcr ISRAM0_SB1CR,r1 |
7d307936 FK |
773 | lis r1, 0x0002 |
774 | ori r1,r1, 0x0B84 /* third 128k */ | |
b14ca4b6 | 775 | mtdcr ISRAM0_SB2CR,r1 |
7d307936 FK |
776 | lis r1, 0x0003 |
777 | ori r1,r1, 0x0B84 /* fourth 128k */ | |
b14ca4b6 | 778 | mtdcr ISRAM0_SB3CR,r1 |
887e2ec9 | 779 | #elif defined(CONFIG_440GP) |
0442ed86 | 780 | ori r1,r1,0x0380 /* 8k rw */ |
b14ca4b6 DM |
781 | mtdcr ISRAM0_SB0CR,r1 |
782 | mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ | |
c157d8e2 | 783 | #endif |
887e2ec9 | 784 | #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |
0442ed86 WD |
785 | |
786 | /*----------------------------------------------------------------*/ | |
787 | /* Setup the stack in internal SRAM */ | |
788 | /*----------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
789 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
790 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
0442ed86 WD |
791 | li r0,0 |
792 | stwu r0,-4(r1) | |
793 | stwu r0,-4(r1) /* Terminate call chain */ | |
794 | ||
795 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
796 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
797 | ori r0,r0, RESET_VECTOR@l | |
798 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
799 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
800 | ||
887e2ec9 | 801 | #ifdef CONFIG_NAND_SPL |
64852d09 | 802 | bl nand_boot_common /* will not return */ |
887e2ec9 | 803 | #else |
0442ed86 | 804 | GET_GOT |
5568e613 SR |
805 | |
806 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
0442ed86 | 807 | bl board_init_f |
52ebd9c1 | 808 | /* NOTREACHED - board_init_f() does not return */ |
887e2ec9 | 809 | #endif |
0442ed86 WD |
810 | |
811 | #endif /* CONFIG_440 */ | |
812 | ||
813 | /*****************************************************************************/ | |
814 | #ifdef CONFIG_IOP480 | |
815 | /*----------------------------------------------------------------------- */ | |
816 | /* Set up some machine state registers. */ | |
817 | /*----------------------------------------------------------------------- */ | |
818 | addi r0,r0,0x0000 /* initialize r0 to zero */ | |
58ea142f | 819 | mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ |
0442ed86 WD |
820 | mttcr r0 /* timer control register */ |
821 | mtexier r0 /* disable all interrupts */ | |
0442ed86 WD |
822 | addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ |
823 | ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ | |
824 | mtdbsr r4 /* clear/reset the dbsr */ | |
825 | mtexisr r4 /* clear all pending interrupts */ | |
826 | addis r4,r0,0x8000 | |
827 | mtexier r4 /* enable critical exceptions */ | |
828 | addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ | |
829 | ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ | |
830 | mtiocr r4 /* since bit not used) & DRC to latch */ | |
831 | /* data bus on rising edge of CAS */ | |
832 | /*----------------------------------------------------------------------- */ | |
833 | /* Clear XER. */ | |
834 | /*----------------------------------------------------------------------- */ | |
835 | mtxer r0 | |
836 | /*----------------------------------------------------------------------- */ | |
837 | /* Invalidate i-cache and d-cache TAG arrays. */ | |
838 | /*----------------------------------------------------------------------- */ | |
839 | addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ | |
840 | addi r4,0,1024 /* 1/4 of I-cache */ | |
841 | ..cloop: | |
842 | iccci 0,r3 | |
843 | iccci r4,r3 | |
844 | dccci 0,r3 | |
845 | addic. r3,r3,-16 /* move back one cache line */ | |
846 | bne ..cloop /* loop back to do rest until r3 = 0 */ | |
847 | ||
848 | /* */ | |
849 | /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ | |
850 | /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ | |
851 | /* */ | |
852 | ||
853 | /* first copy IOP480 register base address into r3 */ | |
854 | addis r3,0,0x5000 /* IOP480 register base address hi */ | |
855 | /* ori r3,r3,0x0000 / IOP480 register base address lo */ | |
856 | ||
857 | #ifdef CONFIG_ADCIOP | |
858 | /* use r4 as the working variable */ | |
859 | /* turn on CS3 (LOCCTL.7) */ | |
860 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
861 | andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ | |
862 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
863 | #endif | |
864 | ||
865 | #ifdef CONFIG_DASA_SIM | |
866 | /* use r4 as the working variable */ | |
867 | /* turn on MA17 (LOCCTL.7) */ | |
868 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
869 | ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ | |
870 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
871 | #endif | |
872 | ||
873 | /* turn on MA16..13 (LCS0BRD.12 = 0) */ | |
874 | lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
875 | andi. r4,r4,0xefff /* make bit 12 = 0 */ | |
876 | stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
877 | ||
878 | /* make sure above stores all comlete before going on */ | |
879 | sync | |
880 | ||
881 | /* last thing, set local init status done bit (DEVINIT.31) */ | |
882 | lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
883 | oris r4,r4,0x8000 /* make bit 31 = 1 */ | |
884 | stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
885 | ||
886 | /* clear all pending interrupts and disable all interrupts */ | |
887 | li r4,-1 /* set p1 to 0xffffffff */ | |
888 | stw r4,0x1b0(r3) /* clear all pending interrupts */ | |
889 | stw r4,0x1b8(r3) /* clear all pending interrupts */ | |
890 | li r4,0 /* set r4 to 0 */ | |
891 | stw r4,0x1b4(r3) /* disable all interrupts */ | |
892 | stw r4,0x1bc(r3) /* disable all interrupts */ | |
893 | ||
894 | /* make sure above stores all comlete before going on */ | |
895 | sync | |
896 | ||
c821b5f1 | 897 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
898 | lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h |
899 | ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 GE |
900 | mticcr r1 |
901 | isync | |
0442ed86 | 902 | |
c821b5f1 | 903 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
904 | lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h |
905 | ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 906 | mtdccr r1 |
0442ed86 | 907 | |
6d0f6bcf JCPV |
908 | addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
909 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ | |
0442ed86 WD |
910 | li r0, 0 /* Make room for stack frame header and */ |
911 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
912 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
913 | ||
914 | GET_GOT /* initialize GOT access */ | |
915 | ||
916 | bl board_init_f /* run first part of init code (from Flash) */ | |
52ebd9c1 | 917 | /* NOTREACHED - board_init_f() does not return */ |
0442ed86 WD |
918 | |
919 | #endif /* CONFIG_IOP480 */ | |
920 | ||
921 | /*****************************************************************************/ | |
e01bd218 SR |
922 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
923 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ | |
dbbd1257 | 924 | defined(CONFIG_405EX) || defined(CONFIG_405) |
0442ed86 WD |
925 | /*----------------------------------------------------------------------- */ |
926 | /* Clear and set up some registers. */ | |
927 | /*----------------------------------------------------------------------- */ | |
928 | addi r4,r0,0x0000 | |
dbbd1257 | 929 | #if !defined(CONFIG_405EX) |
58ea142f | 930 | mtspr SPRN_SGR,r4 |
dbbd1257 SR |
931 | #else |
932 | /* | |
933 | * On 405EX, completely clearing the SGR leads to PPC hangup | |
934 | * upon PCIe configuration access. The PCIe memory regions | |
935 | * need to be guarded! | |
936 | */ | |
937 | lis r3,0x0000 | |
938 | ori r3,r3,0x7FFC | |
58ea142f | 939 | mtspr SPRN_SGR,r3 |
dbbd1257 | 940 | #endif |
58ea142f | 941 | mtspr SPRN_DCWR,r4 |
0442ed86 WD |
942 | mtesr r4 /* clear Exception Syndrome Reg */ |
943 | mttcr r4 /* clear Timer Control Reg */ | |
944 | mtxer r4 /* clear Fixed-Point Exception Reg */ | |
945 | mtevpr r4 /* clear Exception Vector Prefix Reg */ | |
0442ed86 WD |
946 | addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ |
947 | /* dbsr is cleared by setting bits to 1) */ | |
948 | mtdbsr r4 /* clear/reset the dbsr */ | |
949 | ||
c821b5f1 | 950 | /* Invalidate the i- and d-caches. */ |
0442ed86 WD |
951 | bl invalidate_icache |
952 | bl invalidate_dcache | |
953 | ||
c821b5f1 | 954 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
955 | lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h |
956 | ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 | 957 | mticcr r4 |
0442ed86 WD |
958 | isync |
959 | ||
c821b5f1 | 960 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
961 | lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h |
962 | ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 963 | mtdccr r4 |
0442ed86 | 964 | |
1f4d5326 RR |
965 | #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ |
966 | && !defined (CONFIG_XILINX_405) | |
0442ed86 WD |
967 | /*----------------------------------------------------------------------- */ |
968 | /* Tune the speed and size for flash CS0 */ | |
969 | /*----------------------------------------------------------------------- */ | |
970 | bl ext_bus_cntlr_init | |
971 | #endif | |
64852d09 | 972 | |
6d0f6bcf | 973 | #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) |
dbbd1257 | 974 | /* |
c821b5f1 GE |
975 | * For boards that don't have OCM and can't use the data cache |
976 | * for their primordial stack, setup stack here directly after the | |
977 | * SDRAM is initialized in ext_bus_cntlr_init. | |
dbbd1257 | 978 | */ |
6d0f6bcf JCPV |
979 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
980 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ | |
dbbd1257 SR |
981 | |
982 | li r0, 0 /* Make room for stack frame header and */ | |
983 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
984 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
985 | /* | |
986 | * Set up a dummy frame to store reset vector as return address. | |
987 | * this causes stack underflow to reset board. | |
988 | */ | |
989 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
990 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
991 | ori r0, r0, RESET_VECTOR@l | |
992 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
993 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 994 | #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ |
0442ed86 | 995 | |
b867d705 SR |
996 | #if defined(CONFIG_405EP) |
997 | /*----------------------------------------------------------------------- */ | |
998 | /* DMA Status, clear to come up clean */ | |
999 | /*----------------------------------------------------------------------- */ | |
53677ef1 | 1000 | addis r3,r0, 0xFFFF /* Clear all existing DMA status */ |
f901a83b | 1001 | ori r3,r3, 0xFFFF |
d1c3b275 | 1002 | mtdcr DMASR, r3 |
b867d705 | 1003 | |
53677ef1 | 1004 | bl ppc405ep_init /* do ppc405ep specific init */ |
b867d705 SR |
1005 | #endif /* CONFIG_405EP */ |
1006 | ||
6d0f6bcf | 1007 | #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) |
e01bd218 SR |
1008 | #if defined(CONFIG_405EZ) |
1009 | /******************************************************************** | |
1010 | * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 | |
1011 | *******************************************************************/ | |
1012 | /* | |
1013 | * We can map the OCM on the PLB3, so map it at | |
6d0f6bcf | 1014 | * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 |
e01bd218 | 1015 | */ |
6d0f6bcf JCPV |
1016 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1017 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
df8a24cd | 1018 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 | 1019 | mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ |
e01bd218 | 1020 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 | 1021 | mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ |
e01bd218 SR |
1022 | isync |
1023 | ||
6d0f6bcf JCPV |
1024 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1025 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
83b4cfa3 | 1026 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 SR |
1027 | mtdcr OCM0_DSRC1, r3 /* Set Data Side */ |
1028 | mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ | |
e01bd218 | 1029 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 SR |
1030 | mtdcr OCM0_DSRC2, r3 /* Set Data Side */ |
1031 | mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ | |
83b4cfa3 | 1032 | addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ |
d1c3b275 | 1033 | mtdcr OCM0_DISDPC,r3 |
e01bd218 SR |
1034 | |
1035 | isync | |
3cb86f3e | 1036 | #else /* CONFIG_405EZ */ |
0442ed86 WD |
1037 | /******************************************************************** |
1038 | * Setup OCM - On Chip Memory | |
1039 | *******************************************************************/ | |
1040 | /* Setup OCM */ | |
8bde7f77 WD |
1041 | lis r0, 0x7FFF |
1042 | ori r0, r0, 0xFFFF | |
d1c3b275 SR |
1043 | mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ |
1044 | mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ | |
3cb86f3e SR |
1045 | and r3, r3, r0 /* disable data-side IRAM */ |
1046 | and r4, r4, r0 /* disable data-side IRAM */ | |
d1c3b275 SR |
1047 | mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ |
1048 | mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ | |
8bde7f77 | 1049 | isync |
0442ed86 | 1050 | |
6d0f6bcf JCPV |
1051 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1052 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
d1c3b275 | 1053 | mtdcr OCM0_DSARC, r3 |
0442ed86 | 1054 | addis r4, 0, 0xC000 /* OCM data area enabled */ |
d1c3b275 | 1055 | mtdcr OCM0_DSCNTL, r4 |
8bde7f77 | 1056 | isync |
e01bd218 | 1057 | #endif /* CONFIG_405EZ */ |
0442ed86 WD |
1058 | #endif |
1059 | ||
1060 | /*----------------------------------------------------------------------- */ | |
1061 | /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ | |
1062 | /*----------------------------------------------------------------------- */ | |
6d0f6bcf | 1063 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
c821b5f1 | 1064 | li r4, PBxAP |
d1c3b275 | 1065 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
1066 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h |
1067 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l | |
d1c3b275 | 1068 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
1069 | |
1070 | addi r4, 0, PBxCR | |
d1c3b275 | 1071 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
1072 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h |
1073 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l | |
d1c3b275 | 1074 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
1075 | |
1076 | /* | |
1077 | * Enable the data cache for the 128MB storage access control region | |
6d0f6bcf | 1078 | * at CONFIG_SYS_INIT_RAM_ADDR. |
c821b5f1 GE |
1079 | */ |
1080 | mfdccr r4 | |
6d0f6bcf JCPV |
1081 | oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1082 | ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
0442ed86 WD |
1083 | mtdccr r4 |
1084 | ||
c821b5f1 GE |
1085 | /* |
1086 | * Preallocate data cache lines to be used to avoid a subsequent | |
1087 | * cache miss and an ensuing machine check exception when exceptions | |
1088 | * are enabled. | |
1089 | */ | |
1090 | li r0, 0 | |
0442ed86 | 1091 | |
6d0f6bcf JCPV |
1092 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1093 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
0442ed86 | 1094 | |
553f0982 WD |
1095 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
1096 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
1097 | |
1098 | /* | |
1099 | * Convert the size, in bytes, to the number of cache lines/blocks | |
1100 | * to preallocate. | |
1101 | */ | |
1102 | clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) | |
1103 | srwi r5, r4, L1_CACHE_SHIFT | |
1104 | beq ..load_counter | |
1105 | addi r5, r5, 0x0001 | |
1106 | ..load_counter: | |
1107 | mtctr r5 | |
1108 | ||
1109 | /* Preallocate the computed number of cache blocks. */ | |
1110 | ..alloc_dcache_block: | |
1111 | dcba r0, r3 | |
1112 | addi r3, r3, L1_CACHE_BYTES | |
1113 | bdnz ..alloc_dcache_block | |
1114 | sync | |
1115 | ||
1116 | /* | |
1117 | * Load the initial stack pointer and data area and convert the size, | |
1118 | * in bytes, to the number of words to initialize to a known value. | |
1119 | */ | |
6d0f6bcf JCPV |
1120 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
1121 | ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l | |
c821b5f1 | 1122 | |
553f0982 WD |
1123 | lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h |
1124 | ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l | |
0442ed86 WD |
1125 | mtctr r4 |
1126 | ||
6d0f6bcf | 1127 | lis r2, CONFIG_SYS_INIT_RAM_ADDR@h |
553f0982 | 1128 | ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l |
0442ed86 | 1129 | |
6d0f6bcf JCPV |
1130 | lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h |
1131 | ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l | |
0442ed86 WD |
1132 | |
1133 | ..stackloop: | |
c821b5f1 | 1134 | stwu r4, -4(r2) |
0442ed86 WD |
1135 | bdnz ..stackloop |
1136 | ||
c821b5f1 GE |
1137 | /* |
1138 | * Make room for stack frame header and clear final stack frame so | |
1139 | * that stack backtraces terminate cleanly. | |
1140 | */ | |
1141 | stwu r0, -4(r1) | |
1142 | stwu r0, -4(r1) | |
1143 | ||
0442ed86 WD |
1144 | /* |
1145 | * Set up a dummy frame to store reset vector as return address. | |
1146 | * this causes stack underflow to reset board. | |
1147 | */ | |
1148 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1149 | addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ | |
1150 | ori r0, r0, RESET_VECTOR@l | |
1151 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1152 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
1153 | ||
6d0f6bcf JCPV |
1154 | #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ |
1155 | (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) | |
0442ed86 WD |
1156 | /* |
1157 | * Stack in OCM. | |
1158 | */ | |
1159 | ||
1160 | /* Set up Stack at top of OCM */ | |
6d0f6bcf JCPV |
1161 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h |
1162 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l | |
0442ed86 WD |
1163 | |
1164 | /* Set up a zeroized stack frame so that backtrace works right */ | |
1165 | li r0, 0 | |
1166 | stwu r0, -4(r1) | |
1167 | stwu r0, -4(r1) | |
1168 | ||
1169 | /* | |
1170 | * Set up a dummy frame to store reset vector as return address. | |
1171 | * this causes stack underflow to reset board. | |
1172 | */ | |
1173 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1174 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1175 | ori r0, r0, RESET_VECTOR@l | |
1176 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1177 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1178 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 1179 | |
c440bfe6 | 1180 | #ifdef CONFIG_NAND_SPL |
64852d09 | 1181 | bl nand_boot_common /* will not return */ |
c440bfe6 | 1182 | #else |
0442ed86 WD |
1183 | GET_GOT /* initialize GOT access */ |
1184 | ||
f901a83b | 1185 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
0442ed86 | 1186 | |
0442ed86 | 1187 | bl board_init_f /* run first part of init code (from Flash) */ |
52ebd9c1 PT |
1188 | /* NOTREACHED - board_init_f() does not return */ |
1189 | ||
c440bfe6 | 1190 | #endif /* CONFIG_NAND_SPL */ |
0442ed86 | 1191 | |
12f34241 WD |
1192 | #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ |
1193 | /*----------------------------------------------------------------------- */ | |
0442ed86 WD |
1194 | |
1195 | ||
887e2ec9 | 1196 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
1197 | /* |
1198 | * This code finishes saving the registers to the exception frame | |
1199 | * and jumps to the appropriate handler for the exception. | |
1200 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
1201 | */ | |
1202 | .globl transfer_to_handler | |
1203 | transfer_to_handler: | |
1204 | stw r22,_NIP(r21) | |
1205 | lis r22,MSR_POW@h | |
1206 | andc r23,r23,r22 | |
1207 | stw r23,_MSR(r21) | |
1208 | SAVE_GPR(7, r21) | |
1209 | SAVE_4GPRS(8, r21) | |
1210 | SAVE_8GPRS(12, r21) | |
1211 | SAVE_8GPRS(24, r21) | |
0442ed86 WD |
1212 | mflr r23 |
1213 | andi. r24,r23,0x3f00 /* get vector offset */ | |
1214 | stw r24,TRAP(r21) | |
1215 | li r22,0 | |
1216 | stw r22,RESULT(r21) | |
1217 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
0442ed86 WD |
1218 | lwz r24,0(r23) /* virtual address of handler */ |
1219 | lwz r23,4(r23) /* where to go when done */ | |
1220 | mtspr SRR0,r24 | |
1221 | mtspr SRR1,r20 | |
1222 | mtlr r23 | |
1223 | SYNC | |
1224 | rfi /* jump to handler, enable MMU */ | |
1225 | ||
1226 | int_return: | |
1227 | mfmsr r28 /* Disable interrupts */ | |
1228 | li r4,0 | |
1229 | ori r4,r4,MSR_EE | |
1230 | andc r28,r28,r4 | |
1231 | SYNC /* Some chip revs need this... */ | |
1232 | mtmsr r28 | |
1233 | SYNC | |
1234 | lwz r2,_CTR(r1) | |
1235 | lwz r0,_LINK(r1) | |
1236 | mtctr r2 | |
1237 | mtlr r0 | |
1238 | lwz r2,_XER(r1) | |
1239 | lwz r0,_CCR(r1) | |
1240 | mtspr XER,r2 | |
1241 | mtcrf 0xFF,r0 | |
1242 | REST_10GPRS(3, r1) | |
1243 | REST_10GPRS(13, r1) | |
1244 | REST_8GPRS(23, r1) | |
1245 | REST_GPR(31, r1) | |
1246 | lwz r2,_NIP(r1) /* Restore environment */ | |
1247 | lwz r0,_MSR(r1) | |
1248 | mtspr SRR0,r2 | |
1249 | mtspr SRR1,r0 | |
1250 | lwz r0,GPR0(r1) | |
1251 | lwz r2,GPR2(r1) | |
1252 | lwz r1,GPR1(r1) | |
1253 | SYNC | |
1254 | rfi | |
1255 | ||
1256 | crit_return: | |
1257 | mfmsr r28 /* Disable interrupts */ | |
1258 | li r4,0 | |
1259 | ori r4,r4,MSR_EE | |
1260 | andc r28,r28,r4 | |
1261 | SYNC /* Some chip revs need this... */ | |
1262 | mtmsr r28 | |
1263 | SYNC | |
1264 | lwz r2,_CTR(r1) | |
1265 | lwz r0,_LINK(r1) | |
1266 | mtctr r2 | |
1267 | mtlr r0 | |
1268 | lwz r2,_XER(r1) | |
1269 | lwz r0,_CCR(r1) | |
1270 | mtspr XER,r2 | |
1271 | mtcrf 0xFF,r0 | |
1272 | REST_10GPRS(3, r1) | |
1273 | REST_10GPRS(13, r1) | |
1274 | REST_8GPRS(23, r1) | |
1275 | REST_GPR(31, r1) | |
1276 | lwz r2,_NIP(r1) /* Restore environment */ | |
1277 | lwz r0,_MSR(r1) | |
58ea142f MF |
1278 | mtspr SPRN_CSRR0,r2 |
1279 | mtspr SPRN_CSRR1,r0 | |
0442ed86 WD |
1280 | lwz r0,GPR0(r1) |
1281 | lwz r2,GPR2(r1) | |
1282 | lwz r1,GPR1(r1) | |
1283 | SYNC | |
1284 | rfci | |
1285 | ||
efa35cf1 GB |
1286 | #ifdef CONFIG_440 |
1287 | mck_return: | |
83b4cfa3 WD |
1288 | mfmsr r28 /* Disable interrupts */ |
1289 | li r4,0 | |
1290 | ori r4,r4,MSR_EE | |
1291 | andc r28,r28,r4 | |
1292 | SYNC /* Some chip revs need this... */ | |
1293 | mtmsr r28 | |
1294 | SYNC | |
1295 | lwz r2,_CTR(r1) | |
1296 | lwz r0,_LINK(r1) | |
1297 | mtctr r2 | |
1298 | mtlr r0 | |
1299 | lwz r2,_XER(r1) | |
1300 | lwz r0,_CCR(r1) | |
1301 | mtspr XER,r2 | |
1302 | mtcrf 0xFF,r0 | |
1303 | REST_10GPRS(3, r1) | |
1304 | REST_10GPRS(13, r1) | |
1305 | REST_8GPRS(23, r1) | |
1306 | REST_GPR(31, r1) | |
1307 | lwz r2,_NIP(r1) /* Restore environment */ | |
1308 | lwz r0,_MSR(r1) | |
58ea142f MF |
1309 | mtspr SPRN_MCSRR0,r2 |
1310 | mtspr SPRN_MCSRR1,r0 | |
83b4cfa3 WD |
1311 | lwz r0,GPR0(r1) |
1312 | lwz r2,GPR2(r1) | |
1313 | lwz r1,GPR1(r1) | |
1314 | SYNC | |
1315 | rfmci | |
efa35cf1 GB |
1316 | #endif /* CONFIG_440 */ |
1317 | ||
1318 | ||
0442ed86 WD |
1319 | .globl get_pvr |
1320 | get_pvr: | |
1321 | mfspr r3, PVR | |
1322 | blr | |
1323 | ||
0442ed86 WD |
1324 | /*------------------------------------------------------------------------------- */ |
1325 | /* Function: out16 */ | |
1326 | /* Description: Output 16 bits */ | |
1327 | /*------------------------------------------------------------------------------- */ | |
1328 | .globl out16 | |
1329 | out16: | |
1330 | sth r4,0x0000(r3) | |
1331 | blr | |
1332 | ||
1333 | /*------------------------------------------------------------------------------- */ | |
1334 | /* Function: out16r */ | |
1335 | /* Description: Byte reverse and output 16 bits */ | |
1336 | /*------------------------------------------------------------------------------- */ | |
1337 | .globl out16r | |
1338 | out16r: | |
1339 | sthbrx r4,r0,r3 | |
1340 | blr | |
1341 | ||
0442ed86 WD |
1342 | /*------------------------------------------------------------------------------- */ |
1343 | /* Function: out32r */ | |
1344 | /* Description: Byte reverse and output 32 bits */ | |
1345 | /*------------------------------------------------------------------------------- */ | |
1346 | .globl out32r | |
1347 | out32r: | |
1348 | stwbrx r4,r0,r3 | |
1349 | blr | |
1350 | ||
1351 | /*------------------------------------------------------------------------------- */ | |
1352 | /* Function: in16 */ | |
1353 | /* Description: Input 16 bits */ | |
1354 | /*------------------------------------------------------------------------------- */ | |
1355 | .globl in16 | |
1356 | in16: | |
1357 | lhz r3,0x0000(r3) | |
1358 | blr | |
1359 | ||
1360 | /*------------------------------------------------------------------------------- */ | |
1361 | /* Function: in16r */ | |
1362 | /* Description: Input 16 bits and byte reverse */ | |
1363 | /*------------------------------------------------------------------------------- */ | |
1364 | .globl in16r | |
1365 | in16r: | |
1366 | lhbrx r3,r0,r3 | |
1367 | blr | |
1368 | ||
0442ed86 WD |
1369 | /*------------------------------------------------------------------------------- */ |
1370 | /* Function: in32r */ | |
1371 | /* Description: Input 32 bits and byte reverse */ | |
1372 | /*------------------------------------------------------------------------------- */ | |
1373 | .globl in32r | |
1374 | in32r: | |
1375 | lwbrx r3,r0,r3 | |
1376 | blr | |
1377 | ||
0442ed86 WD |
1378 | /* |
1379 | * void relocate_code (addr_sp, gd, addr_moni) | |
1380 | * | |
1381 | * This "function" does not return, instead it continues in RAM | |
1382 | * after relocating the monitor code. | |
1383 | * | |
c821b5f1 GE |
1384 | * r3 = Relocated stack pointer |
1385 | * r4 = Relocated global data pointer | |
1386 | * r5 = Relocated text pointer | |
0442ed86 WD |
1387 | */ |
1388 | .globl relocate_code | |
1389 | relocate_code: | |
6d0f6bcf | 1390 | #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) |
9b94ac61 | 1391 | /* |
c821b5f1 GE |
1392 | * We need to flush the initial global data (gd_t) before the dcache |
1393 | * will be invalidated. | |
9b94ac61 SR |
1394 | */ |
1395 | ||
c821b5f1 GE |
1396 | /* Save registers */ |
1397 | mr r9, r3 | |
1398 | mr r10, r4 | |
1399 | mr r11, r5 | |
9b94ac61 | 1400 | |
c821b5f1 GE |
1401 | /* Flush initial global data range */ |
1402 | mr r3, r4 | |
25ddd1fb | 1403 | addi r4, r4, GENERATED_GBL_DATA_SIZE@l |
9b94ac61 SR |
1404 | bl flush_dcache_range |
1405 | ||
6d0f6bcf | 1406 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
c821b5f1 GE |
1407 | /* |
1408 | * Undo the earlier data cache set-up for the primordial stack and | |
1409 | * data area. First, invalidate the data cache and then disable data | |
1410 | * cacheability for that area. Finally, restore the EBC values, if | |
1411 | * any. | |
1412 | */ | |
1413 | ||
1414 | /* Invalidate the primordial stack and data area in cache */ | |
6d0f6bcf JCPV |
1415 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1416 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
c821b5f1 | 1417 | |
553f0982 WD |
1418 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
1419 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
1420 | add r4, r4, r3 |
1421 | ||
1422 | bl invalidate_dcache_range | |
1423 | ||
1424 | /* Disable cacheability for the region */ | |
1425 | mfdccr r3 | |
6d0f6bcf JCPV |
1426 | lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1427 | ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
c821b5f1 GE |
1428 | and r3, r3, r4 |
1429 | mtdccr r3 | |
1430 | ||
1431 | /* Restore the EBC parameters */ | |
1432 | li r3, PBxAP | |
d1c3b275 | 1433 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1434 | lis r3, PBxAP_VAL@h |
1435 | ori r3, r3, PBxAP_VAL@l | |
d1c3b275 | 1436 | mtdcr EBC0_CFGDATA, r3 |
c821b5f1 GE |
1437 | |
1438 | li r3, PBxCR | |
d1c3b275 | 1439 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1440 | lis r3, PBxCR_VAL@h |
1441 | ori r3, r3, PBxCR_VAL@l | |
d1c3b275 | 1442 | mtdcr EBC0_CFGDATA, r3 |
6d0f6bcf | 1443 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
c821b5f1 GE |
1444 | |
1445 | /* Restore registers */ | |
1446 | mr r3, r9 | |
1447 | mr r4, r10 | |
1448 | mr r5, r11 | |
6d0f6bcf | 1449 | #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
e02c521d | 1450 | |
6d0f6bcf | 1451 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
e02c521d SR |
1452 | /* |
1453 | * Unlock the previously locked d-cache | |
1454 | */ | |
1455 | msync | |
1456 | isync | |
1457 | /* set TFLOOR/NFLOOR to 0 again */ | |
1458 | lis r6,0x0001 | |
1459 | ori r6,r6,0xf800 | |
58ea142f | 1460 | mtspr SPRN_DVLIM,r6 |
e02c521d SR |
1461 | lis r6,0x0000 |
1462 | ori r6,r6,0x0000 | |
58ea142f MF |
1463 | mtspr SPRN_DNV0,r6 |
1464 | mtspr SPRN_DNV1,r6 | |
1465 | mtspr SPRN_DNV2,r6 | |
1466 | mtspr SPRN_DNV3,r6 | |
1467 | mtspr SPRN_DTV0,r6 | |
1468 | mtspr SPRN_DTV1,r6 | |
1469 | mtspr SPRN_DTV2,r6 | |
1470 | mtspr SPRN_DTV3,r6 | |
e02c521d SR |
1471 | msync |
1472 | isync | |
f3cac538 SR |
1473 | |
1474 | /* Invalidate data cache, now no longer our stack */ | |
1475 | dccci 0,0 | |
1476 | sync | |
1477 | isync | |
6d0f6bcf | 1478 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
e02c521d | 1479 | |
a4c8d138 SR |
1480 | /* |
1481 | * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) | |
1482 | * to speed up the boot process. Now this cache needs to be disabled. | |
1483 | */ | |
4978e605 | 1484 | #if defined(CONFIG_440) |
25fb4eaa | 1485 | /* Clear all potential pending exceptions */ |
58ea142f MF |
1486 | mfspr r1,SPRN_MCSR |
1487 | mtspr SPRN_MCSR,r1 | |
6d0f6bcf | 1488 | addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ |
c157d8e2 | 1489 | tlbre r0,r1,0x0002 /* Read contents */ |
6e7fb6ea | 1490 | ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ |
f901a83b | 1491 | tlbwe r0,r1,0x0002 /* Save it out */ |
a4c8d138 | 1492 | sync |
c157d8e2 | 1493 | isync |
4978e605 | 1494 | #endif /* defined(CONFIG_440) */ |
0442ed86 WD |
1495 | mr r1, r3 /* Set new stack pointer */ |
1496 | mr r9, r4 /* Save copy of Init Data pointer */ | |
1497 | mr r10, r5 /* Save copy of Destination Address */ | |
1498 | ||
0f8aa159 | 1499 | GET_GOT |
0442ed86 | 1500 | mr r3, r5 /* Destination Address */ |
6d0f6bcf JCPV |
1501 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
1502 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
3b57fe0a WD |
1503 | lwz r5, GOT(__init_end) |
1504 | sub r5, r5, r4 | |
9b94ac61 | 1505 | li r6, L1_CACHE_BYTES /* Cache Line Size */ |
0442ed86 WD |
1506 | |
1507 | /* | |
1508 | * Fix GOT pointer: | |
1509 | * | |
6d0f6bcf | 1510 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
0442ed86 WD |
1511 | * |
1512 | * Offset: | |
1513 | */ | |
1514 | sub r15, r10, r4 | |
1515 | ||
1516 | /* First our own GOT */ | |
0f8aa159 | 1517 | add r12, r12, r15 |
c821b5f1 | 1518 | /* then the one used by the C code */ |
0442ed86 WD |
1519 | add r30, r30, r15 |
1520 | ||
1521 | /* | |
1522 | * Now relocate code | |
1523 | */ | |
1524 | ||
1525 | cmplw cr1,r3,r4 | |
1526 | addi r0,r5,3 | |
1527 | srwi. r0,r0,2 | |
1528 | beq cr1,4f /* In place copy is not necessary */ | |
1529 | beq 7f /* Protect against 0 count */ | |
1530 | mtctr r0 | |
1531 | bge cr1,2f | |
1532 | ||
1533 | la r8,-4(r4) | |
1534 | la r7,-4(r3) | |
1535 | 1: lwzu r0,4(r8) | |
1536 | stwu r0,4(r7) | |
1537 | bdnz 1b | |
1538 | b 4f | |
1539 | ||
1540 | 2: slwi r0,r0,2 | |
1541 | add r8,r4,r0 | |
1542 | add r7,r3,r0 | |
1543 | 3: lwzu r0,-4(r8) | |
1544 | stwu r0,-4(r7) | |
1545 | bdnz 3b | |
1546 | ||
1547 | /* | |
1548 | * Now flush the cache: note that we must start from a cache aligned | |
1549 | * address. Otherwise we might miss one cache line. | |
1550 | */ | |
1551 | 4: cmpwi r6,0 | |
1552 | add r5,r3,r5 | |
1553 | beq 7f /* Always flush prefetch queue in any case */ | |
1554 | subi r0,r6,1 | |
1555 | andc r3,r3,r0 | |
1556 | mr r4,r3 | |
1557 | 5: dcbst 0,r4 | |
1558 | add r4,r4,r6 | |
1559 | cmplw r4,r5 | |
1560 | blt 5b | |
1561 | sync /* Wait for all dcbst to complete on bus */ | |
1562 | mr r4,r3 | |
1563 | 6: icbi 0,r4 | |
1564 | add r4,r4,r6 | |
1565 | cmplw r4,r5 | |
1566 | blt 6b | |
1567 | 7: sync /* Wait for all icbi to complete on bus */ | |
1568 | isync | |
1569 | ||
1570 | /* | |
1571 | * We are done. Do not return, instead branch to second part of board | |
1572 | * initialization, now running from RAM. | |
1573 | */ | |
1574 | ||
efa35cf1 | 1575 | addi r0, r10, in_ram - _start + _START_OFFSET |
0442ed86 WD |
1576 | mtlr r0 |
1577 | blr /* NEVER RETURNS! */ | |
1578 | ||
1579 | in_ram: | |
1580 | ||
1581 | /* | |
0f8aa159 | 1582 | * Relocation Function, r12 point to got2+0x8000 |
0442ed86 WD |
1583 | * |
1584 | * Adjust got2 pointers, no need to check for 0, this code | |
1585 | * already puts a few entries in the table. | |
1586 | */ | |
1587 | li r0,__got2_entries@sectoff@l | |
1588 | la r3,GOT(_GOT2_TABLE_) | |
1589 | lwz r11,GOT(_GOT2_TABLE_) | |
1590 | mtctr r0 | |
1591 | sub r11,r3,r11 | |
1592 | addi r3,r3,-4 | |
1593 | 1: lwzu r0,4(r3) | |
afc3ba0f JT |
1594 | cmpwi r0,0 |
1595 | beq- 2f | |
0442ed86 WD |
1596 | add r0,r0,r11 |
1597 | stw r0,0(r3) | |
afc3ba0f | 1598 | 2: bdnz 1b |
0442ed86 WD |
1599 | |
1600 | /* | |
1601 | * Now adjust the fixups and the pointers to the fixups | |
1602 | * in case we need to move ourselves again. | |
1603 | */ | |
afc3ba0f | 1604 | li r0,__fixup_entries@sectoff@l |
0442ed86 WD |
1605 | lwz r3,GOT(_FIXUP_TABLE_) |
1606 | cmpwi r0,0 | |
1607 | mtctr r0 | |
1608 | addi r3,r3,-4 | |
1609 | beq 4f | |
1610 | 3: lwzu r4,4(r3) | |
1611 | lwzux r0,r4,r11 | |
d1e0b10a | 1612 | cmpwi r0,0 |
0442ed86 | 1613 | add r0,r0,r11 |
34bbf618 | 1614 | stw r4,0(r3) |
d1e0b10a | 1615 | beq- 5f |
0442ed86 | 1616 | stw r0,0(r4) |
d1e0b10a | 1617 | 5: bdnz 3b |
0442ed86 WD |
1618 | 4: |
1619 | clear_bss: | |
1620 | /* | |
1621 | * Now clear BSS segment | |
1622 | */ | |
5d232d0e | 1623 | lwz r3,GOT(__bss_start) |
0442ed86 WD |
1624 | lwz r4,GOT(_end) |
1625 | ||
1626 | cmplw 0, r3, r4 | |
42ed33ff | 1627 | beq 7f |
0442ed86 WD |
1628 | |
1629 | li r0, 0 | |
42ed33ff AG |
1630 | |
1631 | andi. r5, r4, 3 | |
1632 | beq 6f | |
1633 | sub r4, r4, r5 | |
1634 | mtctr r5 | |
1635 | mr r5, r4 | |
1636 | 5: stb r0, 0(r5) | |
1637 | addi r5, r5, 1 | |
1638 | bdnz 5b | |
1639 | 6: | |
0442ed86 WD |
1640 | stw r0, 0(r3) |
1641 | addi r3, r3, 4 | |
1642 | cmplw 0, r3, r4 | |
42ed33ff | 1643 | bne 6b |
0442ed86 | 1644 | |
42ed33ff | 1645 | 7: |
0442ed86 WD |
1646 | mr r3, r9 /* Init Data pointer */ |
1647 | mr r4, r10 /* Destination Address */ | |
1648 | bl board_init_r | |
1649 | ||
0442ed86 WD |
1650 | /* |
1651 | * Copy exception vector code to low memory | |
1652 | * | |
1653 | * r3: dest_addr | |
1654 | * r7: source address, r8: end address, r9: target address | |
1655 | */ | |
1656 | .globl trap_init | |
1657 | trap_init: | |
0f8aa159 JT |
1658 | mflr r4 /* save link register */ |
1659 | GET_GOT | |
efa35cf1 | 1660 | lwz r7, GOT(_start_of_vectors) |
0442ed86 WD |
1661 | lwz r8, GOT(_end_of_vectors) |
1662 | ||
682011ff | 1663 | li r9, 0x100 /* reset vector always at 0x100 */ |
0442ed86 WD |
1664 | |
1665 | cmplw 0, r7, r8 | |
1666 | bgelr /* return if r7>=r8 - just in case */ | |
0442ed86 WD |
1667 | 1: |
1668 | lwz r0, 0(r7) | |
1669 | stw r0, 0(r9) | |
1670 | addi r7, r7, 4 | |
1671 | addi r9, r9, 4 | |
1672 | cmplw 0, r7, r8 | |
1673 | bne 1b | |
1674 | ||
1675 | /* | |
1676 | * relocate `hdlr' and `int_return' entries | |
1677 | */ | |
efa35cf1 GB |
1678 | li r7, .L_MachineCheck - _start + _START_OFFSET |
1679 | li r8, Alignment - _start + _START_OFFSET | |
0442ed86 WD |
1680 | 2: |
1681 | bl trap_reloc | |
efa35cf1 | 1682 | addi r7, r7, 0x100 /* next exception vector */ |
0442ed86 WD |
1683 | cmplw 0, r7, r8 |
1684 | blt 2b | |
1685 | ||
efa35cf1 | 1686 | li r7, .L_Alignment - _start + _START_OFFSET |
0442ed86 WD |
1687 | bl trap_reloc |
1688 | ||
efa35cf1 | 1689 | li r7, .L_ProgramCheck - _start + _START_OFFSET |
0442ed86 WD |
1690 | bl trap_reloc |
1691 | ||
efa35cf1 GB |
1692 | #ifdef CONFIG_440 |
1693 | li r7, .L_FPUnavailable - _start + _START_OFFSET | |
83b4cfa3 | 1694 | bl trap_reloc |
0442ed86 | 1695 | |
efa35cf1 | 1696 | li r7, .L_Decrementer - _start + _START_OFFSET |
83b4cfa3 | 1697 | bl trap_reloc |
efa35cf1 GB |
1698 | |
1699 | li r7, .L_APU - _start + _START_OFFSET | |
83b4cfa3 | 1700 | bl trap_reloc |
df8a24cd | 1701 | |
83b4cfa3 WD |
1702 | li r7, .L_InstructionTLBError - _start + _START_OFFSET |
1703 | bl trap_reloc | |
efa35cf1 | 1704 | |
83b4cfa3 WD |
1705 | li r7, .L_DataTLBError - _start + _START_OFFSET |
1706 | bl trap_reloc | |
efa35cf1 GB |
1707 | #else /* CONFIG_440 */ |
1708 | li r7, .L_PIT - _start + _START_OFFSET | |
83b4cfa3 | 1709 | bl trap_reloc |
efa35cf1 GB |
1710 | |
1711 | li r7, .L_InstructionTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1712 | bl trap_reloc |
efa35cf1 GB |
1713 | |
1714 | li r7, .L_DataTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1715 | bl trap_reloc |
efa35cf1 GB |
1716 | #endif /* CONFIG_440 */ |
1717 | ||
83b4cfa3 WD |
1718 | li r7, .L_DebugBreakpoint - _start + _START_OFFSET |
1719 | bl trap_reloc | |
0442ed86 | 1720 | |
887e2ec9 | 1721 | #if !defined(CONFIG_440) |
9a7b408c SR |
1722 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1723 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1724 | mtmsr r7 /* change MSR */ | |
1725 | #else | |
887e2ec9 SR |
1726 | bl __440_msr_set |
1727 | b __440_msr_continue | |
9a7b408c | 1728 | |
887e2ec9 | 1729 | __440_msr_set: |
9a7b408c SR |
1730 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1731 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
58ea142f | 1732 | mtspr SPRN_SRR1,r7 |
9a7b408c | 1733 | mflr r7 |
58ea142f | 1734 | mtspr SPRN_SRR0,r7 |
9a7b408c | 1735 | rfi |
887e2ec9 | 1736 | __440_msr_continue: |
9a7b408c SR |
1737 | #endif |
1738 | ||
0442ed86 WD |
1739 | mtlr r4 /* restore link register */ |
1740 | blr | |
1741 | ||
cf959c7d SR |
1742 | #if defined(CONFIG_440) |
1743 | /*----------------------------------------------------------------------------+ | |
1744 | | dcbz_area. | |
1745 | +----------------------------------------------------------------------------*/ | |
1746 | function_prolog(dcbz_area) | |
1747 | rlwinm. r5,r4,0,27,31 | |
83b4cfa3 WD |
1748 | rlwinm r5,r4,27,5,31 |
1749 | beq ..d_ra2 | |
1750 | addi r5,r5,0x0001 | |
1751 | ..d_ra2:mtctr r5 | |
1752 | ..d_ag2:dcbz r0,r3 | |
1753 | addi r3,r3,32 | |
1754 | bdnz ..d_ag2 | |
cf959c7d SR |
1755 | sync |
1756 | blr | |
1757 | function_epilog(dcbz_area) | |
cf959c7d | 1758 | #endif /* CONFIG_440 */ |
887e2ec9 | 1759 | #endif /* CONFIG_NAND_SPL */ |
b867d705 | 1760 | |
cf959c7d SR |
1761 | /*------------------------------------------------------------------------------- */ |
1762 | /* Function: in8 */ | |
1763 | /* Description: Input 8 bits */ | |
1764 | /*------------------------------------------------------------------------------- */ | |
1765 | .globl in8 | |
1766 | in8: | |
1767 | lbz r3,0x0000(r3) | |
1768 | blr | |
1769 | ||
1770 | /*------------------------------------------------------------------------------- */ | |
1771 | /* Function: out8 */ | |
1772 | /* Description: Output 8 bits */ | |
1773 | /*------------------------------------------------------------------------------- */ | |
1774 | .globl out8 | |
1775 | out8: | |
1776 | stb r4,0x0000(r3) | |
1777 | blr | |
1778 | ||
1779 | /*------------------------------------------------------------------------------- */ | |
1780 | /* Function: out32 */ | |
1781 | /* Description: Output 32 bits */ | |
1782 | /*------------------------------------------------------------------------------- */ | |
1783 | .globl out32 | |
1784 | out32: | |
1785 | stw r4,0x0000(r3) | |
1786 | blr | |
1787 | ||
1788 | /*------------------------------------------------------------------------------- */ | |
1789 | /* Function: in32 */ | |
1790 | /* Description: Input 32 bits */ | |
1791 | /*------------------------------------------------------------------------------- */ | |
1792 | .globl in32 | |
1793 | in32: | |
1794 | lwz 3,0x0000(3) | |
1795 | blr | |
b867d705 SR |
1796 | |
1797 | /**************************************************************************/ | |
f901a83b | 1798 | /* PPC405EP specific stuff */ |
b867d705 SR |
1799 | /**************************************************************************/ |
1800 | #ifdef CONFIG_405EP | |
1801 | ppc405ep_init: | |
b828dda6 | 1802 | |
c157d8e2 | 1803 | #ifdef CONFIG_BUBINGA |
b828dda6 SR |
1804 | /* |
1805 | * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate | |
1806 | * function) to support FPGA and NVRAM accesses below. | |
1807 | */ | |
1808 | ||
1809 | lis r3,GPIO0_OSRH@h /* config GPIO output select */ | |
1810 | ori r3,r3,GPIO0_OSRH@l | |
6d0f6bcf JCPV |
1811 | lis r4,CONFIG_SYS_GPIO0_OSRH@h |
1812 | ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l | |
b828dda6 SR |
1813 | stw r4,0(r3) |
1814 | lis r3,GPIO0_OSRL@h | |
1815 | ori r3,r3,GPIO0_OSRL@l | |
6d0f6bcf JCPV |
1816 | lis r4,CONFIG_SYS_GPIO0_OSRL@h |
1817 | ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l | |
b828dda6 SR |
1818 | stw r4,0(r3) |
1819 | ||
1820 | lis r3,GPIO0_ISR1H@h /* config GPIO input select */ | |
1821 | ori r3,r3,GPIO0_ISR1H@l | |
6d0f6bcf JCPV |
1822 | lis r4,CONFIG_SYS_GPIO0_ISR1H@h |
1823 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l | |
b828dda6 SR |
1824 | stw r4,0(r3) |
1825 | lis r3,GPIO0_ISR1L@h | |
1826 | ori r3,r3,GPIO0_ISR1L@l | |
6d0f6bcf JCPV |
1827 | lis r4,CONFIG_SYS_GPIO0_ISR1L@h |
1828 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l | |
b828dda6 SR |
1829 | stw r4,0(r3) |
1830 | ||
1831 | lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ | |
1832 | ori r3,r3,GPIO0_TSRH@l | |
6d0f6bcf JCPV |
1833 | lis r4,CONFIG_SYS_GPIO0_TSRH@h |
1834 | ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l | |
b828dda6 SR |
1835 | stw r4,0(r3) |
1836 | lis r3,GPIO0_TSRL@h | |
1837 | ori r3,r3,GPIO0_TSRL@l | |
6d0f6bcf JCPV |
1838 | lis r4,CONFIG_SYS_GPIO0_TSRL@h |
1839 | ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l | |
b828dda6 SR |
1840 | stw r4,0(r3) |
1841 | ||
1842 | lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ | |
1843 | ori r3,r3,GPIO0_TCR@l | |
6d0f6bcf JCPV |
1844 | lis r4,CONFIG_SYS_GPIO0_TCR@h |
1845 | ori r4,r4,CONFIG_SYS_GPIO0_TCR@l | |
b828dda6 SR |
1846 | stw r4,0(r3) |
1847 | ||
d1c3b275 SR |
1848 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1849 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1850 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1851 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1852 | mtdcr EBC0_CFGDATA,r3 |
1853 | li r3,PB1CR | |
1854 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1855 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1856 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1857 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1858 | |
d1c3b275 SR |
1859 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1860 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1861 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1862 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1863 | mtdcr EBC0_CFGDATA,r3 |
1864 | li r3,PB1CR | |
1865 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1866 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1867 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1868 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1869 | |
d1c3b275 SR |
1870 | li r3,PB4AP /* program EBC bank 4 for FPGA access */ |
1871 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1872 | lis r3,CONFIG_SYS_EBC_PB4AP@h |
1873 | ori r3,r3,CONFIG_SYS_EBC_PB4AP@l | |
d1c3b275 SR |
1874 | mtdcr EBC0_CFGDATA,r3 |
1875 | li r3,PB4CR | |
1876 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1877 | lis r3,CONFIG_SYS_EBC_PB4CR@h |
1878 | ori r3,r3,CONFIG_SYS_EBC_PB4CR@l | |
d1c3b275 | 1879 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1880 | #endif |
8bde7f77 WD |
1881 | |
1882 | /* | |
1883 | !----------------------------------------------------------------------- | |
1884 | ! Check to see if chip is in bypass mode. | |
1885 | ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a | |
1886 | ! CPU reset Otherwise, skip this step and keep going. | |
f901a83b WD |
1887 | ! Note: Running BIOS in bypass mode is not supported since PLB speed |
1888 | ! will not be fast enough for the SDRAM (min 66MHz) | |
8bde7f77 | 1889 | !----------------------------------------------------------------------- |
b867d705 | 1890 | */ |
f901a83b | 1891 | mfdcr r5, CPC0_PLLMR1 |
53677ef1 | 1892 | rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ |
f901a83b | 1893 | cmpi cr0,0,r4,0x1 |
b867d705 | 1894 | |
53677ef1 WD |
1895 | beq pll_done /* if SSCS =b'1' then PLL has */ |
1896 | /* already been set */ | |
1897 | /* and CPU has been reset */ | |
1898 | /* so skip to next section */ | |
b867d705 | 1899 | |
c157d8e2 | 1900 | #ifdef CONFIG_BUBINGA |
b867d705 | 1901 | /* |
8bde7f77 WD |
1902 | !----------------------------------------------------------------------- |
1903 | ! Read NVRAM to get value to write in PLLMR. | |
1904 | ! If value has not been correctly saved, write default value | |
1905 | ! Default config values (assuming on-board 33MHz SYS_CLK) are above. | |
1906 | ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. | |
1907 | ! | |
1908 | ! WARNING: This code assumes the first three words in the nvram_t | |
f901a83b WD |
1909 | ! structure in openbios.h. Changing the beginning of |
1910 | ! the structure will break this code. | |
8bde7f77 WD |
1911 | ! |
1912 | !----------------------------------------------------------------------- | |
b867d705 | 1913 | */ |
f901a83b WD |
1914 | addis r3,0,NVRAM_BASE@h |
1915 | addi r3,r3,NVRAM_BASE@l | |
1916 | ||
1917 | lwz r4, 0(r3) | |
1918 | addis r5,0,NVRVFY1@h | |
1919 | addi r5,r5,NVRVFY1@l | |
53677ef1 | 1920 | cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ |
f901a83b WD |
1921 | bne ..no_pllset |
1922 | addi r3,r3,4 | |
1923 | lwz r4, 0(r3) | |
1924 | addis r5,0,NVRVFY2@h | |
1925 | addi r5,r5,NVRVFY2@l | |
53677ef1 | 1926 | cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ |
f901a83b WD |
1927 | bne ..no_pllset |
1928 | addi r3,r3,8 /* Skip over conf_size */ | |
1929 | lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ | |
1930 | lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ | |
1931 | rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ | |
1932 | cmpi cr0,0,r5,1 /* See if PLL is locked */ | |
1933 | beq pll_write | |
b867d705 | 1934 | ..no_pllset: |
c157d8e2 | 1935 | #endif /* CONFIG_BUBINGA */ |
b867d705 | 1936 | |
d4024bb7 JO |
1937 | #ifdef CONFIG_TAIHU |
1938 | mfdcr r4, CPC0_BOOT | |
1939 | andi. r5, r4, CPC0_BOOT_SEP@l | |
1940 | bne strap_1 /* serial eeprom present */ | |
1941 | addis r5,0,CPLD_REG0_ADDR@h | |
1942 | ori r5,r5,CPLD_REG0_ADDR@l | |
1943 | andi. r5, r5, 0x10 | |
1944 | bne _pci_66mhz | |
1945 | #endif /* CONFIG_TAIHU */ | |
1946 | ||
779e9751 SR |
1947 | #if defined(CONFIG_ZEUS) |
1948 | mfdcr r4, CPC0_BOOT | |
1949 | andi. r5, r4, CPC0_BOOT_SEP@l | |
53677ef1 | 1950 | bne strap_1 /* serial eeprom present */ |
779e9751 SR |
1951 | lis r3,0x0000 |
1952 | addi r3,r3,0x3030 | |
1953 | lis r4,0x8042 | |
1954 | addi r4,r4,0x223e | |
1955 | b 1f | |
1956 | strap_1: | |
1957 | mfdcr r3, CPC0_PLLMR0 | |
1958 | mfdcr r4, CPC0_PLLMR1 | |
1959 | b 1f | |
1960 | #endif | |
1961 | ||
53677ef1 WD |
1962 | addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ |
1963 | ori r3,r3,PLLMR0_DEFAULT@l /* */ | |
1964 | addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ | |
1965 | ori r4,r4,PLLMR1_DEFAULT@l /* */ | |
b867d705 | 1966 | |
d4024bb7 JO |
1967 | #ifdef CONFIG_TAIHU |
1968 | b 1f | |
1969 | _pci_66mhz: | |
1970 | addis r3,0,PLLMR0_DEFAULT_PCI66@h | |
1971 | ori r3,r3,PLLMR0_DEFAULT_PCI66@l | |
1972 | addis r4,0,PLLMR1_DEFAULT_PCI66@h | |
1973 | ori r4,r4,PLLMR1_DEFAULT_PCI66@l | |
1974 | b 1f | |
1975 | strap_1: | |
1976 | mfdcr r3, CPC0_PLLMR0 | |
1977 | mfdcr r4, CPC0_PLLMR1 | |
d4024bb7 JO |
1978 | #endif /* CONFIG_TAIHU */ |
1979 | ||
779e9751 | 1980 | 1: |
53677ef1 | 1981 | b pll_write /* Write the CPC0_PLLMR with new value */ |
b867d705 SR |
1982 | |
1983 | pll_done: | |
8bde7f77 WD |
1984 | /* |
1985 | !----------------------------------------------------------------------- | |
1986 | ! Clear Soft Reset Register | |
1987 | ! This is needed to enable PCI if not booting from serial EPROM | |
1988 | !----------------------------------------------------------------------- | |
b867d705 | 1989 | */ |
f901a83b WD |
1990 | addi r3, 0, 0x0 |
1991 | mtdcr CPC0_SRR, r3 | |
b867d705 | 1992 | |
f901a83b WD |
1993 | addis r3,0,0x0010 |
1994 | mtctr r3 | |
b867d705 | 1995 | pci_wait: |
f901a83b | 1996 | bdnz pci_wait |
b867d705 | 1997 | |
53677ef1 | 1998 | blr /* return to main code */ |
b867d705 SR |
1999 | |
2000 | /* | |
2001 | !----------------------------------------------------------------------------- | |
f901a83b WD |
2002 | ! Function: pll_write |
2003 | ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation | |
2004 | ! That is: | |
2005 | ! 1. Pll is first disabled (de-activated by putting in bypass mode) | |
2006 | ! 2. PLL is reset | |
2007 | ! 3. Clock dividers are set while PLL is held in reset and bypassed | |
2008 | ! 4. PLL Reset is cleared | |
2009 | ! 5. Wait 100us for PLL to lock | |
2010 | ! 6. A core reset is performed | |
b867d705 SR |
2011 | ! Input: r3 = Value to write to CPC0_PLLMR0 |
2012 | ! Input: r4 = Value to write to CPC0_PLLMR1 | |
2013 | ! Output r3 = none | |
2014 | !----------------------------------------------------------------------------- | |
2015 | */ | |
0580e48f | 2016 | .globl pll_write |
b867d705 | 2017 | pll_write: |
8bde7f77 WD |
2018 | mfdcr r5, CPC0_UCR |
2019 | andis. r5,r5,0xFFFF | |
53677ef1 WD |
2020 | ori r5,r5,0x0101 /* Stop the UART clocks */ |
2021 | mtdcr CPC0_UCR,r5 /* Before changing PLL */ | |
8bde7f77 WD |
2022 | |
2023 | mfdcr r5, CPC0_PLLMR1 | |
53677ef1 | 2024 | rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ |
f901a83b | 2025 | mtdcr CPC0_PLLMR1,r5 |
53677ef1 | 2026 | oris r5,r5,0x4000 /* Set PLL Reset */ |
f901a83b WD |
2027 | mtdcr CPC0_PLLMR1,r5 |
2028 | ||
53677ef1 WD |
2029 | mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ |
2030 | rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ | |
2031 | oris r5,r5,0x4000 /* Set PLL Reset */ | |
2032 | mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ | |
2033 | rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ | |
f901a83b | 2034 | mtdcr CPC0_PLLMR1,r5 |
b867d705 SR |
2035 | |
2036 | /* | |
8bde7f77 WD |
2037 | ! Wait min of 100us for PLL to lock. |
2038 | ! See CMOS 27E databook for more info. | |
2039 | ! At 200MHz, that means waiting 20,000 instructions | |
b867d705 | 2040 | */ |
f901a83b WD |
2041 | addi r3,0,20000 /* 2000 = 0x4e20 */ |
2042 | mtctr r3 | |
b867d705 | 2043 | pll_wait: |
f901a83b | 2044 | bdnz pll_wait |
8bde7f77 | 2045 | |
f901a83b WD |
2046 | oris r5,r5,0x8000 /* Enable PLL */ |
2047 | mtdcr CPC0_PLLMR1,r5 /* Engage */ | |
8bde7f77 WD |
2048 | |
2049 | /* | |
2050 | * Reset CPU to guarantee timings are OK | |
2051 | * Not sure if this is needed... | |
2052 | */ | |
2053 | addis r3,0,0x1000 | |
58ea142f | 2054 | mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ |
53677ef1 WD |
2055 | /* execution will continue from the poweron */ |
2056 | /* vector of 0xfffffffc */ | |
b867d705 | 2057 | #endif /* CONFIG_405EP */ |
4745acaa SR |
2058 | |
2059 | #if defined(CONFIG_440) | |
4745acaa SR |
2060 | /*----------------------------------------------------------------------------+ |
2061 | | mttlb3. | |
2062 | +----------------------------------------------------------------------------*/ | |
2063 | function_prolog(mttlb3) | |
2064 | TLBWE(4,3,2) | |
2065 | blr | |
2066 | function_epilog(mttlb3) | |
2067 | ||
2068 | /*----------------------------------------------------------------------------+ | |
2069 | | mftlb3. | |
2070 | +----------------------------------------------------------------------------*/ | |
2071 | function_prolog(mftlb3) | |
74357114 | 2072 | TLBRE(3,3,2) |
4745acaa SR |
2073 | blr |
2074 | function_epilog(mftlb3) | |
2075 | ||
2076 | /*----------------------------------------------------------------------------+ | |
2077 | | mttlb2. | |
2078 | +----------------------------------------------------------------------------*/ | |
2079 | function_prolog(mttlb2) | |
2080 | TLBWE(4,3,1) | |
2081 | blr | |
2082 | function_epilog(mttlb2) | |
2083 | ||
2084 | /*----------------------------------------------------------------------------+ | |
2085 | | mftlb2. | |
2086 | +----------------------------------------------------------------------------*/ | |
2087 | function_prolog(mftlb2) | |
74357114 | 2088 | TLBRE(3,3,1) |
4745acaa SR |
2089 | blr |
2090 | function_epilog(mftlb2) | |
2091 | ||
2092 | /*----------------------------------------------------------------------------+ | |
2093 | | mttlb1. | |
2094 | +----------------------------------------------------------------------------*/ | |
2095 | function_prolog(mttlb1) | |
2096 | TLBWE(4,3,0) | |
2097 | blr | |
2098 | function_epilog(mttlb1) | |
2099 | ||
2100 | /*----------------------------------------------------------------------------+ | |
2101 | | mftlb1. | |
2102 | +----------------------------------------------------------------------------*/ | |
2103 | function_prolog(mftlb1) | |
74357114 | 2104 | TLBRE(3,3,0) |
4745acaa SR |
2105 | blr |
2106 | function_epilog(mftlb1) | |
2107 | #endif /* CONFIG_440 */ | |
64852d09 SR |
2108 | |
2109 | #if defined(CONFIG_NAND_SPL) | |
2110 | /* | |
2111 | * void nand_boot_relocate(dst, src, bytes) | |
2112 | * | |
2113 | * r3 = Destination address to copy code to (in SDRAM) | |
2114 | * r4 = Source address to copy code from | |
2115 | * r5 = size to copy in bytes | |
2116 | */ | |
2117 | nand_boot_relocate: | |
2118 | mr r6,r3 | |
2119 | mr r7,r4 | |
2120 | mflr r8 | |
2121 | ||
2122 | /* | |
2123 | * Copy SPL from icache into SDRAM | |
2124 | */ | |
2125 | subi r3,r3,4 | |
2126 | subi r4,r4,4 | |
2127 | srwi r5,r5,2 | |
2128 | mtctr r5 | |
2129 | ..spl_loop: | |
2130 | lwzu r0,4(r4) | |
2131 | stwu r0,4(r3) | |
2132 | bdnz ..spl_loop | |
2133 | ||
2134 | /* | |
2135 | * Calculate "corrected" link register, so that we "continue" | |
2136 | * in execution in destination range | |
2137 | */ | |
2138 | sub r3,r7,r6 /* r3 = src - dst */ | |
2139 | sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ | |
2140 | mtlr r8 | |
2141 | blr | |
2142 | ||
2143 | nand_boot_common: | |
2144 | /* | |
2145 | * First initialize SDRAM. It has to be available *before* calling | |
2146 | * nand_boot(). | |
2147 | */ | |
6d0f6bcf JCPV |
2148 | lis r3,CONFIG_SYS_SDRAM_BASE@h |
2149 | ori r3,r3,CONFIG_SYS_SDRAM_BASE@l | |
64852d09 SR |
2150 | bl initdram |
2151 | ||
2152 | /* | |
2153 | * Now copy the 4k SPL code into SDRAM and continue execution | |
2154 | * from there. | |
2155 | */ | |
6d0f6bcf JCPV |
2156 | lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h |
2157 | ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l | |
2158 | lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h | |
2159 | ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l | |
2160 | lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h | |
2161 | ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l | |
64852d09 SR |
2162 | bl nand_boot_relocate |
2163 | ||
2164 | /* | |
2165 | * We're running from SDRAM now!!! | |
2166 | * | |
2167 | * It is necessary for 4xx systems to relocate from running at | |
2168 | * the original location (0xfffffxxx) to somewhere else (SDRAM | |
2169 | * preferably). This is because CS0 needs to be reconfigured for | |
2170 | * NAND access. And we can't reconfigure this CS when currently | |
2171 | * "running" from it. | |
2172 | */ | |
2173 | ||
2174 | /* | |
2175 | * Finally call nand_boot() to load main NAND U-Boot image from | |
2176 | * NAND and jump to it. | |
2177 | */ | |
2178 | bl nand_boot /* will not return */ | |
2179 | #endif /* CONFIG_NAND_SPL */ |