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243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
243be8e2 KG |
5 | */ |
6 | ||
7 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
8 | #define _ASM_MPC85xx_CONFIG_H_ | |
9 | ||
10 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
11 | ||
e46fedfe TT |
12 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
13 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
14 | #endif | |
15 | ||
2a5fcb83 YS |
16 | /* |
17 | * This macro should be removed when we no longer care about backwards | |
18 | * compatibility with older operating systems. | |
19 | */ | |
20 | #define CONFIG_PPC_SPINTABLE_COMPATIBLE | |
21 | ||
34e026f9 YS |
22 | #include <fsl_ddrc_version.h> |
23 | #define CONFIG_SYS_FSL_DDR_BE | |
57495e4e | 24 | |
1b4175d6 PK |
25 | /* IP endianness */ |
26 | #define CONFIG_SYS_FSL_IFC_BE | |
028dbb8d | 27 | #define CONFIG_SYS_FSL_SEC_BE |
a2e225e6 | 28 | #define CONFIG_SYS_FSL_SFP_BE |
e04916a7 | 29 | #define CONFIG_SYS_FSL_SEC_MON_BE |
1b4175d6 | 30 | |
243be8e2 KG |
31 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
32 | #if defined(CONFIG_E500MC) | |
33 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
34 | #elif defined(CONFIG_E500) | |
35 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
36 | #endif | |
37 | ||
24ad75ae | 38 | #if defined(CONFIG_ARCH_MPC8536) |
243be8e2 KG |
39 | #define CONFIG_MAX_CPUS 1 |
40 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 41 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 |
243be8e2 | 42 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 43 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
9855b3be | 44 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 45 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 46 | |
7f825218 | 47 | #elif defined(CONFIG_ARCH_MPC8540) |
243be8e2 KG |
48 | #define CONFIG_MAX_CPUS 1 |
49 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 50 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 51 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 52 | |
3aff3082 | 53 | #elif defined(CONFIG_ARCH_MPC8541) |
243be8e2 KG |
54 | #define CONFIG_MAX_CPUS 1 |
55 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 56 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 57 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 58 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 59 | |
25cb74b3 | 60 | #elif defined(CONFIG_ARCH_MPC8544) |
243be8e2 KG |
61 | #define CONFIG_MAX_CPUS 1 |
62 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 63 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 64 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 65 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 66 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 67 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 68 | |
281ed4c7 | 69 | #elif defined(CONFIG_ARCH_MPC8548) |
243be8e2 KG |
70 | #define CONFIG_MAX_CPUS 1 |
71 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 72 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 73 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 74 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 75 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 76 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 77 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 78 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
79 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
80 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
81 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
82 | #define CONFIG_SYS_FSL_RMU | |
83 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 84 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
85 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
86 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 | |
243be8e2 | 87 | |
3c3d8ab5 | 88 | #elif defined(CONFIG_ARCH_MPC8555) |
243be8e2 KG |
89 | #define CONFIG_MAX_CPUS 1 |
90 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 91 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 92 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 93 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 94 | |
99d0a312 | 95 | #elif defined(CONFIG_ARCH_MPC8560) |
243be8e2 KG |
96 | #define CONFIG_MAX_CPUS 1 |
97 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 98 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 99 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
100 | |
101 | #elif defined(CONFIG_MPC8568) | |
102 | #define CONFIG_MAX_CPUS 1 | |
103 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 104 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
243be8e2 | 105 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
fdb4dad3 KG |
106 | #define QE_MURAM_SIZE 0x10000UL |
107 | #define MAX_QE_RISC 2 | |
108 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 109 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
110 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
111 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
112 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
113 | #define CONFIG_SYS_FSL_RMU | |
114 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
115 | |
116 | #elif defined(CONFIG_MPC8569) | |
117 | #define CONFIG_MAX_CPUS 1 | |
118 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
119 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
120 | #define QE_MURAM_SIZE 0x20000UL |
121 | #define MAX_QE_RISC 4 | |
122 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 123 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
124 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
125 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
126 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
127 | #define CONFIG_SYS_FSL_RMU | |
128 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 129 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 130 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
131 | |
132 | #elif defined(CONFIG_MPC8572) | |
133 | #define CONFIG_MAX_CPUS 2 | |
134 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 135 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 136 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 137 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 138 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 139 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
9855b3be | 140 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 141 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
142 | |
143 | #elif defined(CONFIG_P1010) | |
144 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 145 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 146 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 147 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
148 | #define CONFIG_TSECV2 |
149 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
150 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
151 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 152 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
362ee04b | 153 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
1fbf3483 | 154 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
8f29084a | 155 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 156 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 157 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 158 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
424bf942 | 159 | #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
bc6bbd6b | 160 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
954a1a47 | 161 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb | 162 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9855b3be | 163 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
11856919 | 164 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
15a6d496 | 165 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
9c641a87 | 166 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
0dc78ff8 | 167 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
9c3f77eb | 168 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 |
f28bea00 | 169 | #define CONFIG_ESDHC_HC_BLK_ADDR |
243be8e2 | 170 | |
093cffbe | 171 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
172 | #elif defined(CONFIG_P1011) |
173 | #define CONFIG_MAX_CPUS 1 | |
174 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 175 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 176 | #define CONFIG_TSECV2 |
b03a466d | 177 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 178 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 179 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 180 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
181 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
182 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 183 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 184 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 185 | |
093cffbe | 186 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
187 | #elif defined(CONFIG_P1012) |
188 | #define CONFIG_MAX_CPUS 1 | |
189 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 190 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 191 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 192 | #define CONFIG_TSECV2 |
b03a466d | 193 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 194 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 195 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
196 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
197 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
198 | #define QE_MURAM_SIZE 0x6000UL |
199 | #define MAX_QE_RISC 1 | |
200 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 201 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 202 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 203 | |
093cffbe | 204 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
205 | #elif defined(CONFIG_P1013) |
206 | #define CONFIG_MAX_CPUS 1 | |
207 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
703f5681 | 208 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ad75d442 | 209 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
210 | #define CONFIG_TSECV2 |
211 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 212 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
213 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
214 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
215 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
9855b3be | 216 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 217 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
218 | |
219 | #elif defined(CONFIG_P1014) | |
220 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 221 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 222 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 223 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
224 | #define CONFIG_TSECV2 |
225 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
226 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
227 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 228 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
1fbf3483 | 229 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
1b719e66 | 230 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 231 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 232 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 233 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
9855b3be | 234 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
243be8e2 | 235 | |
093cffbe | 236 | /* P1017 is single core version of P1023 */ |
67a719da RZ |
237 | #elif defined(CONFIG_P1017) |
238 | #define CONFIG_MAX_CPUS 1 | |
239 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
240 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
241 | #define CONFIG_SYS_NUM_FMAN 1 | |
242 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
243 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 244 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
245 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
246 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 247 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 248 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 249 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
9855b3be | 250 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 251 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
67a719da | 252 | |
243be8e2 KG |
253 | #elif defined(CONFIG_P1020) |
254 | #define CONFIG_MAX_CPUS 2 | |
255 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 256 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 257 | #define CONFIG_TSECV2 |
b03a466d | 258 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 259 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 260 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
261 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
262 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 263 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 264 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
80ba6a6f | 265 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT |
f1810d85 | 266 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
80ba6a6f | 267 | #endif |
243be8e2 KG |
268 | |
269 | #elif defined(CONFIG_P1021) | |
270 | #define CONFIG_MAX_CPUS 2 | |
271 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 272 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 273 | #define CONFIG_TSECV2 |
b03a466d | 274 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 275 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 276 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
277 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
278 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
279 | #define QE_MURAM_SIZE 0x6000UL |
280 | #define MAX_QE_RISC 1 | |
281 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 282 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 283 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 284 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
243be8e2 KG |
285 | |
286 | #elif defined(CONFIG_P1022) | |
287 | #define CONFIG_MAX_CPUS 2 | |
288 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 289 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
290 | #define CONFIG_TSECV2 |
291 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
703f5681 | 292 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
e46fedfe | 293 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
294 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
295 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
296 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
9855b3be | 297 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 298 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 299 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
243be8e2 | 300 | |
67a719da RZ |
301 | #elif defined(CONFIG_P1023) |
302 | #define CONFIG_MAX_CPUS 2 | |
303 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
304 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
305 | #define CONFIG_SYS_NUM_FMAN 1 | |
306 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
307 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 308 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
309 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
310 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 311 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 312 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 313 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
9855b3be | 314 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 315 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
316 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
317 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
67a719da | 318 | |
093cffbe KG |
319 | /* P1024 is lower end variant of P1020 */ |
320 | #elif defined(CONFIG_P1024) | |
321 | #define CONFIG_MAX_CPUS 2 | |
322 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 323 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
324 | #define CONFIG_TSECV2 |
325 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
326 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 327 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 328 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
329 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
330 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
9855b3be | 331 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 332 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
333 | |
334 | /* P1025 is lower end variant of P1021 */ | |
335 | #elif defined(CONFIG_P1025) | |
336 | #define CONFIG_MAX_CPUS 2 | |
337 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
1ff10a87 | 338 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ad75d442 | 339 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
340 | #define CONFIG_TSECV2 |
341 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
342 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 343 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
344 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
345 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
346 | #define QE_MURAM_SIZE 0x6000UL |
347 | #define MAX_QE_RISC 1 | |
348 | #define QE_NUM_OF_SNUM 28 | |
9855b3be | 349 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 350 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
351 | |
352 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
353 | #elif defined(CONFIG_P2010) |
354 | #define CONFIG_MAX_CPUS 1 | |
355 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 356 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 357 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 358 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
e46fedfe | 359 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 360 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 361 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
9855b3be | 362 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 363 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
364 | |
365 | #elif defined(CONFIG_P2020) | |
366 | #define CONFIG_MAX_CPUS 2 | |
367 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 368 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 369 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 370 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 371 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 372 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
7d67ed58 LG |
373 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
374 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
375 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
376 | #define CONFIG_SYS_FSL_RMU | |
377 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
9855b3be | 378 | #define CONFIG_SYS_FSL_ERRATUM_A004508 |
954a1a47 | 379 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 380 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
f1810d85 | 381 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
9855b3be | 382 | |
3e978f5d | 383 | #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ |
d1001e3f | 384 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 385 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
1f97987a KG |
386 | #define CONFIG_MAX_CPUS 4 |
387 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
388 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
389 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
390 | #define CONFIG_SYS_NUM_FMAN 1 | |
391 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
392 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
393 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 394 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
1f97987a KG |
395 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
396 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
397 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 398 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
399 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
400 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 401 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 402 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5e23ab0a | 403 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 404 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 405 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 406 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 407 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
408 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
409 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
410 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
411 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
412 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
413 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
414 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 415 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 416 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
9c3f77eb | 417 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 418 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 419 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 |
1f97987a | 420 | |
243be8e2 | 421 | #elif defined(CONFIG_PPC_P3041) |
d1001e3f | 422 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 423 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 424 | #define CONFIG_MAX_CPUS 4 |
b5c8753f | 425 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
426 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
427 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
428 | #define CONFIG_SYS_NUM_FMAN 1 |
429 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
430 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
431 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 432 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 |
c657d898 | 433 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 434 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 435 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 436 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
437 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
438 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 439 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
f1810d85 | 440 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
30009766 | 441 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
57125f22 | 442 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 443 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 444 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 445 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 446 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
447 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
448 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
449 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
450 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
451 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
452 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
453 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 454 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 455 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d217a9ad | 456 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 457 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 458 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 459 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 460 | |
3e978f5d | 461 | #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ |
d1001e3f | 462 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 463 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 464 | #define CONFIG_MAX_CPUS 8 |
b5c8753f | 465 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
466 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
467 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
468 | #define CONFIG_SYS_NUM_FMAN 2 | |
469 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
470 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
471 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
472 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
473 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 474 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 475 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 476 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 477 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 478 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 479 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
480 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
481 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 482 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
483 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
484 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
485 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
4e0be34a | 486 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
243be8e2 | 487 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 488 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 489 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 490 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 491 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 492 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 493 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 494 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
495 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
496 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
497 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
498 | #define CONFIG_SYS_FSL_RMU | |
499 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
500 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
501 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
502 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 503 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 504 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d607b968 | 505 | #define CONFIG_SYS_FSL_ERRATUM_A004580 |
c0a4e6b8 | 506 | #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 |
d217a9ad | 507 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 508 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
11856919 | 509 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
9c3f77eb | 510 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 511 | |
3e978f5d | 512 | #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ |
ffd06e02 | 513 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
d1001e3f | 514 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 515 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 516 | #define CONFIG_MAX_CPUS 2 |
b5c8753f | 517 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
518 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
519 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
520 | #define CONFIG_SYS_NUM_FMAN 1 |
521 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
522 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
523 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 524 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 525 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 526 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 527 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 528 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 529 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
530 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
531 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 532 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 533 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
99d7b0a4 | 534 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
e22be77a | 535 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 536 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
537 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
538 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
539 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
540 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
541 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
542 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 543 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
9c3f77eb | 544 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 545 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 546 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 547 | |
4905443f | 548 | #elif defined(CONFIG_PPC_P5040) |
1956e431 | 549 | #define CONFIG_SYS_PPC64 |
4905443f | 550 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 551 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
4905443f TT |
552 | #define CONFIG_MAX_CPUS 4 |
553 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 | |
554 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
555 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
556 | #define CONFIG_SYS_NUM_FMAN 2 | |
557 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
558 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
559 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
560 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
561 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 562 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 563 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
4905443f TT |
564 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
565 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
566 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
567 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
568 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
569 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
570 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
571 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
99d7b0a4 | 572 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
4905443f TT |
573 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
574 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
575 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
4905443f TT |
576 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
577 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
9c641a87 | 578 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
4905443f | 579 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 |
d217a9ad | 580 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
4905443f | 581 | |
115d60c0 | 582 | #elif defined(CONFIG_ARCH_BSC9131) |
19a8dbdc PK |
583 | #define CONFIG_MAX_CPUS 1 |
584 | #define CONFIG_FSL_SDHC_V2_3 | |
585 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
586 | #define CONFIG_TSECV2 | |
587 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
588 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 589 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 |
f1810d85 | 590 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
765b0bdb PJ |
591 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 |
592 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
362ee04b | 593 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
19a8dbdc PK |
594 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
595 | #define CONFIG_NAND_FSL_IFC | |
19a8dbdc | 596 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
954a1a47 | 597 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
0dc78ff8 | 598 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
f28bea00 | 599 | #define CONFIG_ESDHC_HC_BLK_ADDR |
19a8dbdc | 600 | |
115d60c0 | 601 | #elif defined(CONFIG_ARCH_BSC9132) |
35fe948e PK |
602 | #define CONFIG_MAX_CPUS 2 |
603 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
604 | #define CONFIG_FSL_SDHC_V2_3 | |
605 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
606 | #define CONFIG_TSECV2 | |
607 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
608 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
34e026f9 | 609 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
f1810d85 | 610 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
64501c66 PJ |
611 | #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 |
612 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 | |
613 | #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 | |
614 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
061ffeda | 615 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
35fe948e PK |
616 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
617 | #define CONFIG_NAND_FSL_IFC | |
35fe948e PK |
618 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
619 | #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK | |
620 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
954a1a47 | 621 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1a96ec1 | 622 | #define CONFIG_SYS_FSL_ERRATUM_A005434 |
0dc78ff8 | 623 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
9c3f77eb CL |
624 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
625 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
f28bea00 | 626 | #define CONFIG_ESDHC_HC_BLK_ADDR |
35fe948e | 627 | |
5122dfae SL |
628 | #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ |
629 | defined(CONFIG_PPC_T4080) | |
3d2972fe | 630 | #define CONFIG_E6500 |
ffd06e02 | 631 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
9e758758 YS |
632 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
633 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 634 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
9e758758 | 635 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
3d2972fe | 636 | #ifdef CONFIG_PPC_T4240 |
9e758758 | 637 | #define CONFIG_MAX_CPUS 12 |
ce746fe0 | 638 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } |
9e758758 YS |
639 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
640 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
641 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
642 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
643 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
f413d1ca | 644 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
3d2972fe | 645 | #else |
5122dfae | 646 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
3d2972fe | 647 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
5122dfae | 648 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 |
3d2972fe YS |
649 | #define CONFIG_SYS_NUM_FM2_10GEC 1 |
650 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
5122dfae SL |
651 | #if defined(CONFIG_PPC_T4160) |
652 | #define CONFIG_MAX_CPUS 8 | |
653 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } | |
654 | #elif defined(CONFIG_PPC_T4080) | |
655 | #define CONFIG_MAX_CPUS 4 | |
656 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } | |
657 | #endif | |
3d2972fe | 658 | #endif |
b6240846 YS |
659 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 |
660 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
a4c955bc PK |
661 | #define CONFIG_SYS_FSL_SRDS_1 |
662 | #define CONFIG_SYS_FSL_SRDS_2 | |
b6240846 YS |
663 | #define CONFIG_SYS_FSL_SRDS_3 |
664 | #define CONFIG_SYS_FSL_SRDS_4 | |
665 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
666 | #define CONFIG_SYS_NUM_FMAN 2 | |
f1810d85 | 667 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 | 668 | #define CONFIG_SYS_PME_CLK 0 |
b6240846 | 669 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 670 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
b6240846 | 671 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
672 | #define CONFIG_SYS_FM1_CLK 3 |
673 | #define CONFIG_SYS_FM2_CLK 3 | |
b6240846 YS |
674 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
675 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
676 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
677 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
678 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
679 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
08047937 | 680 | #define CONFIG_SYS_FSL_SRIO_LIODN |
b6240846 YS |
681 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
682 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
683 | #define CONFIG_SYS_FSL_ERRATUM_A004468 | |
684 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
685 | #define CONFIG_SYS_FSL_ERRATUM_A005871 | |
133fbfa9 | 686 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 687 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 688 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
f3dff695 | 689 | #define CONFIG_SYS_FSL_ERRATUM_A007798 |
b6240846 | 690 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
b6808cd8 | 691 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
b6240846 YS |
692 | #define CONFIG_SYS_FSL_PCI_VER_3_X |
693 | ||
8fa0102b PA |
694 | #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) |
695 | #define CONFIG_E6500 | |
e1dbdd81 PA |
696 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
697 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
698 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
699 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
b8bf0adc SL |
700 | #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ |
701 | #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ | |
702 | #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ | |
e1dbdd81 | 703 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
a4c955bc PK |
704 | #define CONFIG_SYS_FSL_SRDS_1 |
705 | #define CONFIG_SYS_FSL_SRDS_2 | |
b8bf0adc SL |
706 | #define CONFIG_SYS_MAPLE |
707 | #define CONFIG_SYS_CPRI | |
708 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 | |
e1dbdd81 PA |
709 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
710 | #define CONFIG_SYS_NUM_FMAN 1 | |
f1810d85 | 711 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ce746fe0 | 712 | #define CONFIG_SYS_FM1_CLK 0 |
b8bf0adc SL |
713 | #define CONFIG_SYS_CPRI_CLK 3 |
714 | #define CONFIG_SYS_ULB_CLK 4 | |
715 | #define CONFIG_SYS_ETVPE_CLK 1 | |
e1dbdd81 | 716 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 717 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
e1dbdd81 PA |
718 | #define CONFIG_SYS_FMAN_V3 |
719 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
720 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
721 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
722 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
723 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
04feb57f | 724 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 725 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
b6808cd8 | 726 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
82125192 | 727 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
11856919 | 728 | #define CONFIG_SYS_FSL_ERRATUM_A007075 |
7af9a074 SL |
729 | #define CONFIG_SYS_FSL_ERRATUM_A006475 |
730 | #define CONFIG_SYS_FSL_ERRATUM_A006384 | |
c3678b09 | 731 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
0dc78ff8 | 732 | #define CONFIG_SYS_FSL_ERRATUM_A004477 |
e1dbdd81 | 733 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
b6808cd8 | 734 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
e1dbdd81 | 735 | |
8fa0102b | 736 | #ifdef CONFIG_PPC_B4860 |
f6981439 | 737 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
d2404141 | 738 | #define CONFIG_MAX_CPUS 4 |
b8bf0adc SL |
739 | #define CONFIG_MAX_DSP_CPUS 12 |
740 | #define CONFIG_NUM_DSP_CPUS 6 | |
6df82e3c | 741 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 |
ce746fe0 | 742 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } |
d2404141 YS |
743 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
744 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
e394ceb1 | 745 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
f1810d85 | 746 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
d2404141 YS |
747 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
748 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
749 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
32f38ee3 | 750 | #define CONFIG_SYS_FSL_SRIO_LIODN |
8fa0102b PA |
751 | #else |
752 | #define CONFIG_MAX_CPUS 2 | |
b8bf0adc | 753 | #define CONFIG_MAX_DSP_CPUS 2 |
6df82e3c | 754 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 |
8fa0102b | 755 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 |
ce746fe0 | 756 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } |
8fa0102b PA |
757 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
758 | #define CONFIG_SYS_NUM_FM1_10GEC 0 | |
759 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
760 | #endif | |
d2404141 | 761 | |
2967af68 PJ |
762 | #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ |
763 | defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) | |
5f208d11 YS |
764 | #define CONFIG_E5500 |
765 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
766 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 767 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 |
5f208d11 | 768 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
34e026f9 YS |
769 | #ifdef CONFIG_SYS_FSL_DDR4 |
770 | #define CONFIG_SYS_FSL_DDRC_GEN4 | |
771 | #endif | |
1d384eca | 772 | #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) |
5f208d11 | 773 | #define CONFIG_MAX_CPUS 4 |
1d384eca PK |
774 | #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) |
775 | #define CONFIG_MAX_CPUS 2 | |
776 | #endif | |
777 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
ce746fe0 | 778 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } |
5f208d11 | 779 | #define CONFIG_SYS_FSL_NUM_LAWS 16 |
1d384eca PK |
780 | #define CONFIG_SYS_FSL_SRDS_1 |
781 | #define CONFIG_SYS_FSL_SEC_COMPAT 5 | |
5f208d11 YS |
782 | #define CONFIG_SYS_NUM_FMAN 1 |
783 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
784 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 785 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 PK |
786 | #define CONFIG_PME_PLAT_CLK_DIV 2 |
787 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
1d384eca PK |
788 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
789 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
9f074e67 | 790 | #define CONFIG_SYS_FSL_ERRATUM_A008044 |
5f208d11 | 791 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
792 | #define CONFIG_FM_PLAT_CLK_DIV 1 |
793 | #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV | |
2d9ca2c7 YL |
794 | #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 |
795 | per rcw field value */ | |
796 | #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ | |
1d384eca | 797 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 |
b135991a | 798 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
e03c76c3 | 799 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
5f208d11 | 800 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" |
a4f7cba6 | 801 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
5f208d11 YS |
802 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
803 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
1336e2d3 HZ |
804 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
805 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE | |
2a44efeb ZQ |
806 | #define QE_MURAM_SIZE 0x6000UL |
807 | #define MAX_QE_RISC 1 | |
808 | #define QE_NUM_OF_SNUM 28 | |
e622d9ed | 809 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
a46b1852 | 810 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
a994b3de | 811 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
5f208d11 | 812 | |
f6050790 SL |
813 | #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ |
814 | defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) | |
815 | #define CONFIG_E5500 | |
816 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
817 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
818 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 | |
819 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
820 | #define CONFIG_SYS_FMAN_V3 | |
821 | #ifdef CONFIG_SYS_FSL_DDR4 | |
822 | #define CONFIG_SYS_FSL_DDRC_GEN4 | |
823 | #endif | |
824 | #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) | |
825 | #define CONFIG_MAX_CPUS 2 | |
826 | #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) | |
827 | #define CONFIG_MAX_CPUS 1 | |
828 | #endif | |
829 | #define CONFIG_SYS_FSL_NUM_CC_PLL 2 | |
830 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } | |
f6050790 SL |
831 | #define CONFIG_SYS_FSL_NUM_LAWS 16 |
832 | #define CONFIG_SYS_FSL_SRDS_1 | |
833 | #define CONFIG_SYS_FSL_SEC_COMPAT 5 | |
834 | #define CONFIG_SYS_NUM_FMAN 1 | |
835 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
836 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
cc19c25e | 837 | #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION |
f6050790 SL |
838 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
839 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
840 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 | |
841 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
842 | #define CONFIG_SYS_FM1_CLK 0 | |
2d9ca2c7 YL |
843 | #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 |
844 | per rcw field value */ | |
f6050790 SL |
845 | #define CONFIG_QBMAN_CLK_DIV 1 |
846 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 | |
847 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK | |
848 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
849 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
850 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
851 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
852 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
853 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
854 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE | |
855 | #define QE_MURAM_SIZE 0x6000UL | |
856 | #define MAX_QE_RISC 1 | |
857 | #define QE_NUM_OF_SNUM 28 | |
858 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
a46b1852 | 859 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
a994b3de | 860 | #define CONFIG_SYS_FSL_ERRATUM_A009663 |
f6050790 | 861 | |
629d6b32 SL |
862 | #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) |
863 | #define CONFIG_E6500 | |
864 | #define CONFIG_SYS_PPC64 /* 64-bit core */ | |
865 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
866 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
867 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 | |
868 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
869 | #define CONFIG_SYS_FSL_QMAN_V3 | |
870 | #define CONFIG_MAX_CPUS 4 | |
871 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
872 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
873 | #define CONFIG_SYS_NUM_FMAN 1 | |
874 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } | |
875 | #define CONFIG_SYS_FSL_SRDS_1 | |
876 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
877 | #if defined(CONFIG_PPC_T2080) | |
878 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
879 | #define CONFIG_SYS_NUM_FM1_10GEC 4 | |
880 | #define CONFIG_SYS_FSL_SRDS_2 | |
881 | #define CONFIG_SYS_FSL_SRIO_LIODN | |
882 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
883 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
884 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
885 | #elif defined(CONFIG_PPC_T2081) | |
886 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 | |
887 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
888 | #endif | |
2ffa96d8 | 889 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
629d6b32 SL |
890 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
891 | #define CONFIG_PME_PLAT_CLK_DIV 1 | |
892 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
893 | #define CONFIG_SYS_FM1_CLK 0 | |
2d9ca2c7 YL |
894 | #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 |
895 | per rcw field value */ | |
896 | #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ | |
629d6b32 SL |
897 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
898 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
899 | #define CONFIG_SYS_FMAN_V3 | |
900 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
901 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
902 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
903 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
904 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
c3678b09 | 905 | #define CONFIG_SYS_FSL_ERRATUM_A007212 |
629d6b32 SL |
906 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
907 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
908 | #define CONFIG_SYS_FSL_ISBC_VER 2 | |
1336e2d3 | 909 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
c665c473 | 910 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
b6808cd8 | 911 | #define CONFIG_SYS_FSL_ERRATUM_A007186 |
c665c473 | 912 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
1336e2d3 | 913 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
b6808cd8 | 914 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
1336e2d3 | 915 | |
629d6b32 | 916 | |
4fd64746 | 917 | #elif defined(CONFIG_ARCH_C29X) |
3b75e982 MH |
918 | #define CONFIG_MAX_CPUS 1 |
919 | #define CONFIG_FSL_SDHC_V2_3 | |
920 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
921 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
922 | #define CONFIG_TSECV2_1 | |
923 | #define CONFIG_SYS_FSL_SEC_COMPAT 6 | |
924 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
925 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
34e026f9 | 926 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 |
3b75e982 MH |
927 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
928 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
954a1a47 | 929 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
404bf454 AP |
930 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 |
931 | #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 | |
3b75e982 | 932 | |
fa08d395 AG |
933 | #elif defined(CONFIG_QEMU_E500) |
934 | #define CONFIG_MAX_CPUS 1 | |
935 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 | |
936 | ||
243be8e2 KG |
937 | #else |
938 | #error Processor type not defined for this platform | |
939 | #endif | |
940 | ||
e46fedfe TT |
941 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
942 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
943 | #endif | |
944 | ||
f6981439 YS |
945 | #ifdef CONFIG_E6500 |
946 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 | |
947 | #else | |
948 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 | |
949 | #endif | |
950 | ||
5614e71b YS |
951 | #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ |
952 | !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ | |
34e026f9 YS |
953 | !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ |
954 | !defined(CONFIG_SYS_FSL_DDRC_GEN4) | |
5614e71b YS |
955 | #define CONFIG_SYS_FSL_DDRC_GEN3 |
956 | #endif | |
957 | ||
4fd64746 | 958 | #if !defined(CONFIG_ARCH_C29X) |
404bf454 AP |
959 | #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |
960 | #endif | |
961 | ||
243be8e2 | 962 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |