[people/ms/u-boot.git] / arch / powerpc / include / asm / gpio.h

/*
 * (C) Copyright 2007-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H

#include <asm/types.h>

/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) ||					\
	defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	\
	defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
	defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define GPIO_GROUP_MAX	2
#else
#define GPIO_GROUP_MAX	1
#endif

/* GPIO controller */
struct ppc4xx_gpio {
	u32 or;		/* Output Control */
	u32 tcr;	/* Tri-State Control */
	u32 osl;	/* Output Select 16..31 */
	u32 osh;	/* Output Select 0..15 */
	u32 tsl;	/* Tri-State Select 16..31 */
	u32 tsh;	/* Tri-State Select 0..15 */
	u32 odr;	/* Open Drain */
	u32 ir;		/* Input */
	u32 rr1;	/* Receive Register 1 */
	u32 rr2;	/* Receive Register 2 */
	u32 rr3;	/* Receive Register 3 */
	u32 reserved;
	u32 is1l;	/* Input Select 1 16..31 */
	u32 is1h;	/* Input Select 1 0..15 */
	u32 is2l;	/* Input Select 2 16..31 */
	u32 is2h;	/* Input Select 2 0..15 */
	u32 is3l;	/* Input Select 3 16..31 */
	u32 is3h;	/* Input Select 3 0..15 */
};

/* Offsets */
#define GPIOx_OR	0x00		/* GPIO Output Register */
#define GPIOx_TCR	0x04		/* GPIO Three-State Control Register */
#define GPIOx_OSL	0x08		/* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH	0x0C		/* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL	0x10		/* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH	0x14		/* GPIO Three-State Select Register  (Bits 32-63) */
#define GPIOx_ODR	0x18		/* GPIO Open drain Register */
#define GPIOx_IR	0x1C		/* GPIO Input Register */
#define GPIOx_RR1	0x20		/* GPIO Receive Register 1 */
#define GPIOx_RR2	0x24		/* GPIO Receive Register 2 */
#define GPIOx_RR3	0x28		/* GPIO Receive Register 3 */
#define GPIOx_IS1L	0x30		/* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H	0x34		/* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L	0x38		/* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H	0x3C		/* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L	0x40		/* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H	0x44		/* GPIO Input Select Register 3 (Bits 32-63) */

#define GPIO_OR(x)	(x+GPIOx_OR)	/* GPIO Output Register */
#define GPIO_TCR(x)	(x+GPIOx_TCR)	/* GPIO Three-State Control Register */
#define GPIO_OS(x)	(x+GPIOx_OSL)	/* GPIO Output Select Register High or Low */
#define GPIO_TS(x)	(x+GPIOx_TSL)	/* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x)	(x+GPIOx_IS1L)	/* GPIO Input register1 High or Low */
#define GPIO_IS2(x)	(x+GPIOx_IS2L)	/* GPIO Input register2 High or Low */
#define GPIO_IS3(x)	(x+GPIOx_IS3L)	/* GPIO Input register3 High or Low */

#define GPIO0		0
#define GPIO1		1

#define GPIO_MAX	32
#define GPIO_ALT1_SEL	0x40000000
#define GPIO_ALT2_SEL	0x80000000
#define GPIO_ALT3_SEL	0xc0000000
#define GPIO_IN_SEL	0x40000000
#define GPIO_MASK	0xc0000000

#define GPIO_VAL(gpio)	(0x80000000 >> (gpio))

#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out	 { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;

typedef struct {
	unsigned long	add;	/* gpio core base address	*/
	gpio_driver_t	in_out;	/* Driver Setting		*/
	gpio_select_t	alt_nb;	/* Selected Alternate		*/
	gpio_out_t	out_val;/* Default Output Value		*/
} gpio_param_s;
#endif

void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
int gpio_read_in_bit(int pin);
void gpio_set_chip_configuration(void);

#endif /* __ASM_PPC_GPIO_H */
Commit	Line	Data
0d974d52	1	/*
c813f1f8	2	* (C) Copyright 2007-2008
0d974d52 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
aee747f1 SR	24	#ifndef __ASM_PPC_GPIO_H
	25	#define __ASM_PPC_GPIO_H
	26
da799f66 MF	27	#include <asm/types.h>
da799f66 MF	28
0d974d52 SR	29	/* 4xx PPC's have 2 GPIO controllers */
	30	#if defined(CONFIG_405EZ) \|\| \
	31	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
c813f1f8 SR	32	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
c813f1f8 SR	33	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
0d974d52 SR	34	#define GPIO_GROUP_MAX 2
	35	#else
	36	#define GPIO_GROUP_MAX 1
	37	#endif
	38
da799f66 MF	39	/* GPIO controller */
	40	struct ppc4xx_gpio {
	41	u32 or; /* Output Control */
	42	u32 tcr; /* Tri-State Control */
	43	u32 osl; /* Output Select 16..31 */
	44	u32 osh; /* Output Select 0..15 */
	45	u32 tsl; /* Tri-State Select 16..31 */
	46	u32 tsh; /* Tri-State Select 0..15 */
	47	u32 odr; /* Open Drain */
	48	u32 ir; /* Input */
	49	u32 rr1; /* Receive Register 1 */
	50	u32 rr2; /* Receive Register 2 */
	51	u32 rr3; /* Receive Register 3 */
	52	u32 reserved;
	53	u32 is1l; /* Input Select 1 16..31 */
	54	u32 is1h; /* Input Select 1 0..15 */
	55	u32 is2l; /* Input Select 2 16..31 */
	56	u32 is2h; /* Input Select 2 0..15 */
	57	u32 is3l; /* Input Select 3 16..31 */
	58	u32 is3h; /* Input Select 3 0..15 */
	59	};
	60
aee747f1 SR	61	/* Offsets */
	62	#define GPIOx_OR 0x00 /* GPIO Output Register */
	63	#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
	64	#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
	65	#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
	66	#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
	67	#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
	68	#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
	69	#define GPIOx_IR 0x1C /* GPIO Input Register */
	70	#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
	71	#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
	72	#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
	73	#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
	74	#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
	75	#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
	76	#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
	77	#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
	78	#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
	79
	80	#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
	81	#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
	82	#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
	83	#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
	84	#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
	85	#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
	86	#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
	87
	88	#define GPIO0 0
	89	#define GPIO1 1
	90
0d974d52 SR	91	#define GPIO_MAX 32
	92	#define GPIO_ALT1_SEL 0x40000000
	93	#define GPIO_ALT2_SEL 0x80000000
	94	#define GPIO_ALT3_SEL 0xc0000000
	95	#define GPIO_IN_SEL 0x40000000
	96	#define GPIO_MASK 0xc0000000
	97
	98	#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
	99
	100	#ifndef __ASSEMBLY__
	101	typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
	102	typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
	103	typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
	104
	105	typedef struct {
85f73737 SR	106	unsigned long add; /* gpio core base address */
	107	gpio_driver_t in_out; /* Driver Setting */
	108	gpio_select_t alt_nb; /* Selected Alternate */
	109	gpio_out_t out_val;/* Default Output Value */
0d974d52 SR	110	} gpio_param_s;
	111	#endif
	112
	113	void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
	114	void gpio_write_bit(int pin, int val);
85f73737	115	int gpio_read_out_bit(int pin);
5ab884b2	116	int gpio_read_in_bit(int pin);
0d974d52	117	void gpio_set_chip_configuration(void);
aee747f1 SR	118
aee747f1 SR	119	#endif /* __ASM_PPC_GPIO_H */