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Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h
CommitLineData
42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
19a8dbdc 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
837f1ba0 5 *
42d1f039
WD		 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 10 */
11
12#ifndef __IMMAP_85xx__
13#define __IMMAP_85xx__
14
3dfa9cfd 15#include <asm/types.h>
b1f12650 16#include <asm/fsl_dma.h>
3dfa9cfd 17#include <asm/fsl_i2c.h>
0b66513b 18#include <fsl_ifc.h>
4e190b03 19#include <asm/fsl_lbc.h>
ebd7cb0b 20#include <asm/fsl_fman.h>
9a17eb5b 21#include <fsl_immap.h>
3dfa9cfd 22
01df5212 23typedef struct ccsr_local {
8280912e
KG		 24 u32 ccsrbarh; /* CCSR Base Addr High */
25 u32 ccsrbarl; /* CCSR Base Addr Low */
26 u32 ccsrar; /* CCSR Attr */
01df5212
KG		 27#define CCSRAR_C 0x80000000 /* Commit */
28 u8 res1[4];
8280912e
KG		 29 u32 altcbarh; /* Alternate Configuration Base Addr High */
30 u32 altcbarl; /* Alternate Configuration Base Addr Low */
31 u32 altcar; /* Alternate Configuration Attr */
01df5212 32 u8 res2[4];
8280912e
KG		 33 u32 bstrh; /* Boot space translation high */
34 u32 bstrl; /* Boot space translation Low */
35 u32 bstrar; /* Boot space translation attributes */
01df5212
KG		 36 u8 res3[0xbd4];
37 struct {
8280912e
KG		 38 u32 lawbarh; /* LAWn base addr high */
39 u32 lawbarl; /* LAWn base addr low */
40 u32 lawar; /* LAWn attributes */
01df5212
KG		 41 u8 res4[4];
42 } law[32];
43 u8 res35[0x204];
44} ccsr_local_t;
45
8280912e 46/* Local-Access Registers & ECM Registers */
42d1f039 47typedef struct ccsr_local_ecm {
8280912e
KG		 48 u32 ccsrbar; /* CCSR Base Addr */
49 u8 res1[4];
50 u32 altcbar; /* Alternate Configuration Base Addr */
51 u8 res2[4];
52 u32 altcar; /* Alternate Configuration Attr */
53 u8 res3[12];
54 u32 bptr; /* Boot Page Translation */
55 u8 res4[3044];
56 u32 lawbar0; /* Local Access Window 0 Base Addr */
57 u8 res5[4];
58 u32 lawar0; /* Local Access Window 0 Attrs */
59 u8 res6[20];
60 u32 lawbar1; /* Local Access Window 1 Base Addr */
61 u8 res7[4];
62 u32 lawar1; /* Local Access Window 1 Attrs */
63 u8 res8[20];
64 u32 lawbar2; /* Local Access Window 2 Base Addr */
65 u8 res9[4];
66 u32 lawar2; /* Local Access Window 2 Attrs */
67 u8 res10[20];
68 u32 lawbar3; /* Local Access Window 3 Base Addr */
69 u8 res11[4];
70 u32 lawar3; /* Local Access Window 3 Attrs */
71 u8 res12[20];
72 u32 lawbar4; /* Local Access Window 4 Base Addr */
73 u8 res13[4];
74 u32 lawar4; /* Local Access Window 4 Attrs */
75 u8 res14[20];
76 u32 lawbar5; /* Local Access Window 5 Base Addr */
77 u8 res15[4];
78 u32 lawar5; /* Local Access Window 5 Attrs */
79 u8 res16[20];
80 u32 lawbar6; /* Local Access Window 6 Base Addr */
81 u8 res17[4];
82 u32 lawar6; /* Local Access Window 6 Attrs */
83 u8 res18[20];
84 u32 lawbar7; /* Local Access Window 7 Base Addr */
85 u8 res19[4];
86 u32 lawar7; /* Local Access Window 7 Attrs */
87 u8 res19_8a[20];
88 u32 lawbar8; /* Local Access Window 8 Base Addr */
89 u8 res19_8b[4];
90 u32 lawar8; /* Local Access Window 8 Attrs */
91 u8 res19_9a[20];
92 u32 lawbar9; /* Local Access Window 9 Base Addr */
93 u8 res19_9b[4];
94 u32 lawar9; /* Local Access Window 9 Attrs */
95 u8 res19_10a[20];
96 u32 lawbar10; /* Local Access Window 10 Base Addr */
97 u8 res19_10b[4];
98 u32 lawar10; /* Local Access Window 10 Attrs */
99 u8 res19_11a[20];
100 u32 lawbar11; /* Local Access Window 11 Base Addr */
101 u8 res19_11b[4];
102 u32 lawar11; /* Local Access Window 11 Attrs */
103 u8 res20[652];
104 u32 eebacr; /* ECM CCB Addr Configuration */
105 u8 res21[12];
106 u32 eebpcr; /* ECM CCB Port Configuration */
107 u8 res22[3564];
108 u32 eedr; /* ECM Error Detect */
109 u8 res23[4];
110 u32 eeer; /* ECM Error Enable */
111 u32 eeatr; /* ECM Error Attrs Capture */
112 u32 eeadr; /* ECM Error Addr Capture */
113 u8 res24[492];
42d1f039
WD		 114} ccsr_local_ecm_t;
115
9ab87d04
KG		 116#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
117#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
118
8280912e 119/* I2C Registers */
42d1f039 120typedef struct ccsr_i2c {
3dfa9cfd
JL		 121 struct fsl_i2c i2c[1];
122 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
42d1f039
WD		 123} ccsr_i2c_t;
124
03f5c550
WD		 125#if defined(CONFIG_MPC8540) \
126 || defined(CONFIG_MPC8541) \
d9b94f28 127 || defined(CONFIG_MPC8548) \
03f5c550 128 || defined(CONFIG_MPC8555)
8280912e 129/* DUART Registers */
42d1f039 130typedef struct ccsr_duart {
8280912e
KG		 131 u8 res1[1280];
132/* URBR1, UTHR1, UDLB1 with the same addr */
133 u8 urbr1_uthr1_udlb1;
134/* UIER1, UDMB1 with the same addr01 */
135 u8 uier1_udmb1;
136/* UIIR1, UFCR1, UAFR1 with the same addr */
137 u8 uiir1_ufcr1_uafr1;
138 u8 ulcr1; /* UART1 Line Control */
139 u8 umcr1; /* UART1 Modem Control */
140 u8 ulsr1; /* UART1 Line Status */
141 u8 umsr1; /* UART1 Modem Status */
142 u8 uscr1; /* UART1 Scratch */
143 u8 res2[8];
144 u8 udsr1; /* UART1 DMA Status */
145 u8 res3[239];
146/* URBR2, UTHR2, UDLB2 with the same addr */
147 u8 urbr2_uthr2_udlb2;
148/* UIER2, UDMB2 with the same addr */
149 u8 uier2_udmb2;
150/* UIIR2, UFCR2, UAFR2 with the same addr */
151 u8 uiir2_ufcr2_uafr2;
152 u8 ulcr2; /* UART2 Line Control */
153 u8 umcr2; /* UART2 Modem Control */
154 u8 ulsr2; /* UART2 Line Status */
155 u8 umsr2; /* UART2 Modem Status */
156 u8 uscr2; /* UART2 Scratch */
157 u8 res4[8];
158 u8 udsr2; /* UART2 DMA Status */
159 u8 res5[2543];
42d1f039
WD		 160} ccsr_duart_t;
161#else /* MPC8560 uses UART on its CPM */
162typedef struct ccsr_duart {
8280912e 163 u8 res[4096];
42d1f039
WD		 164} ccsr_duart_t;
165#endif
166
8280912e 167/* eSPI Registers */
7fa96a9a 168typedef struct ccsr_espi {
8280912e
KG		 169 u32 mode; /* eSPI mode */
170 u32 event; /* eSPI event */
171 u32 mask; /* eSPI mask */
172 u32 com; /* eSPI command */
173 u32 tx; /* eSPI transmit FIFO access */
174 u32 rx; /* eSPI receive FIFO access */
175 u8 res1[8]; /* reserved */
176 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
177 u8 res2[4048]; /* fill up to 0x1000 */
7fa96a9a
MH		 178} ccsr_espi_t;
179
8280912e 180/* PCI Registers */
42d1f039 181typedef struct ccsr_pcix {
8280912e
KG		 182 u32 cfg_addr; /* PCIX Configuration Addr */
183 u32 cfg_data; /* PCIX Configuration Data */
184 u32 int_ack; /* PCIX IRQ Acknowledge */
e389a377
LT		 185 u8 res000c[52];
186 u32 liodn_base; /* PCIX LIODN base register */
8f9fe660
LT		 187 u8 res0044[2996];
188 u32 ipver1; /* PCIX IP block revision register 1 */
189 u32 ipver2; /* PCIX IP block revision register 2 */
8280912e
KG		 190 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
191 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
192 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
193 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
194 u32 powar0; /* PCIX Outbound Window Attrs 0 */
195 u8 res2[12];
196 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
197 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
198 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
199 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
200 u32 powar1; /* PCIX Outbound Window Attrs 1 */
201 u8 res3[12];
202 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
203 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
204 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
205 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
206 u32 powar2; /* PCIX Outbound Window Attrs 2 */
207 u8 res4[12];
208 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
209 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
210 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
211 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
212 u32 powar3; /* PCIX Outbound Window Attrs 3 */
213 u8 res5[12];
214 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
215 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
216 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
217 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
218 u32 powar4; /* PCIX Outbound Window Attrs 4 */
219 u8 res6[268];
220 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
221 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
222 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
223 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
224 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
225 u8 res7[12];
226 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
227 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
228 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
229 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
230 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
231 u8 res8[12];
232 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
233 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
234 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
235 u8 res9[4];
236 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
237 u8 res10[12];
238 u32 pedr; /* PCIX Error Detect */
239 u32 pecdr; /* PCIX Error Capture Disable */
240 u32 peer; /* PCIX Error Enable */
241 u32 peattrcr; /* PCIX Error Attrs Capture */
242 u32 peaddrcr; /* PCIX Error Addr Capture */
243 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
244 u32 pedlcr; /* PCIX Error Data Low Capture */
245 u32 pedhcr; /* PCIX Error Error Data High Capture */
246 u32 gas_timr; /* PCIX Gasket Timer */
247 u8 res11[476];
42d1f039
WD		 248} ccsr_pcix_t;
249
97074ed9
MM		 250#define PCIX_COMMAND 0x62
251#define POWAR_EN 0x80000000
252#define POWAR_IO_READ 0x00080000
253#define POWAR_MEM_READ 0x00040000
254#define POWAR_IO_WRITE 0x00008000
255#define POWAR_MEM_WRITE 0x00004000
256#define POWAR_MEM_512M 0x0000001c
257#define POWAR_IO_1M 0x00000013
258
259#define PIWAR_EN 0x80000000
260#define PIWAR_PF 0x20000000
261#define PIWAR_LOCAL 0x00f00000
262#define PIWAR_READ_SNOOP 0x00050000
263#define PIWAR_WRITE_SNOOP 0x00005000
264#define PIWAR_MEM_2G 0x0000001e
265
8280912e
KG		 266typedef struct ccsr_gpio {
267 u32 gpdir;
268 u32 gpodr;
269 u32 gpdat;
270 u32 gpier;
271 u32 gpimr;
272 u32 gpicr;
273} ccsr_gpio_t;
97074ed9 274
8280912e 275/* L2 Cache Registers */
42d1f039 276typedef struct ccsr_l2cache {
8280912e
KG		 277 u32 l2ctl; /* L2 configuration 0 */
278 u8 res1[12];
279 u32 l2cewar0; /* L2 cache external write addr 0 */
280 u8 res2[4];
281 u32 l2cewcr0; /* L2 cache external write control 0 */
282 u8 res3[4];
283 u32 l2cewar1; /* L2 cache external write addr 1 */
284 u8 res4[4];
285 u32 l2cewcr1; /* L2 cache external write control 1 */
286 u8 res5[4];
287 u32 l2cewar2; /* L2 cache external write addr 2 */
288 u8 res6[4];
289 u32 l2cewcr2; /* L2 cache external write control 2 */
290 u8 res7[4];
291 u32 l2cewar3; /* L2 cache external write addr 3 */
292 u8 res8[4];
293 u32 l2cewcr3; /* L2 cache external write control 3 */
294 u8 res9[180];
295 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
296 u8 res10[4];
297 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
298 u8 res11[3316];
299 u32 l2errinjhi; /* L2 error injection mask high */
300 u32 l2errinjlo; /* L2 error injection mask low */
301 u32 l2errinjctl; /* L2 error injection tag/ECC control */
302 u8 res12[20];
303 u32 l2captdatahi; /* L2 error data high capture */
304 u32 l2captdatalo; /* L2 error data low capture */
305 u32 l2captecc; /* L2 error ECC capture */
306 u8 res13[20];
307 u32 l2errdet; /* L2 error detect */
308 u32 l2errdis; /* L2 error disable */
309 u32 l2errinten; /* L2 error interrupt enable */
310 u32 l2errattr; /* L2 error attributes capture */
311 u32 l2erraddr; /* L2 error addr capture */
312 u8 res14[4];
313 u32 l2errctl; /* L2 error control */
314 u8 res15[420];
42d1f039
WD		 315} ccsr_l2cache_t;
316
76b474e2
MH		 317#define MPC85xx_L2CTL_L2E 0x80000000
318#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
319#define MPC85xx_L2ERRDIS_MBECC 0x00000008
320#define MPC85xx_L2ERRDIS_SBECC 0x00000004
321
8280912e 322/* DMA Registers */
42d1f039 323typedef struct ccsr_dma {
8280912e 324 u8 res1[256];
b1f12650 325 struct fsl_dma dma[4];
8280912e
KG		 326 u32 dgsr; /* DMA General Status */
327 u8 res2[11516];
42d1f039
WD		 328} ccsr_dma_t;
329
8280912e 330/* tsec */
42d1f039 331typedef struct ccsr_tsec {
8280912e
KG		 332 u8 res1[16];
333 u32 ievent; /* IRQ Event */
334 u32 imask; /* IRQ Mask */
335 u32 edis; /* Error Disabled */
336 u8 res2[4];
337 u32 ecntrl; /* Ethernet Control */
338 u32 minflr; /* Minimum Frame Len */
339 u32 ptv; /* Pause Time Value */
340 u32 dmactrl; /* DMA Control */
341 u32 tbipa; /* TBI PHY Addr */
342 u8 res3[88];
343 u32 fifo_tx_thr; /* FIFO transmit threshold */
344 u8 res4[8];
345 u32 fifo_tx_starve; /* FIFO transmit starve */
346 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
347 u8 res5[96];
348 u32 tctrl; /* TX Control */
349 u32 tstat; /* TX Status */
350 u8 res6[4];
351 u32 tbdlen; /* TX Buffer Desc Data Len */
352 u8 res7[16];
353 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
354 u32 ctbptr; /* Current TX Buffer Desc Ptr */
355 u8 res8[88];
356 u32 tbptrh; /* TX Buffer Desc Ptr High */
357 u32 tbptr; /* TX Buffer Desc Ptr Low */
358 u8 res9[120];
359 u32 tbaseh; /* TX Desc Base Addr High */
360 u32 tbase; /* TX Desc Base Addr */
361 u8 res10[168];
362 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
363 u32 ostbdp; /* OOS TX Data Buffer Ptr */
364 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
365 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
366 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
367 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
368 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
369 u8 res11[52];
370 u32 rctrl; /* RX Control */
371 u32 rstat; /* RX Status */
372 u8 res12[4];
373 u32 rbdlen; /* RxBD Data Len */
374 u8 res13[16];
375 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
376 u32 crbptr; /* Current RX Buffer Desc Ptr */
377 u8 res14[24];
378 u32 mrblr; /* Maximum RX Buffer Len */
379 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
380 u8 res15[56];
381 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
382 u32 rbptr; /* RX Buffer Desc Ptr */
383 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
384 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
385 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
386 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
387 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
388 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
389 u8 res16[96];
390 u32 rbaseh; /* RX Desc Base Addr High 0 */
391 u32 rbase; /* RX Desc Base Addr */
392 u32 rbaseh1; /* RX Desc Base Addr High 1 */
393 u32 rbasel1; /* RX Desc Base Addr Low 1 */
394 u32 rbaseh2; /* RX Desc Base Addr High 2 */
395 u32 rbasel2; /* RX Desc Base Addr Low 2 */
396 u32 rbaseh3; /* RX Desc Base Addr High 3 */
397 u32 rbasel3; /* RX Desc Base Addr Low 3 */
398 u8 res17[224];
399 u32 maccfg1; /* MAC Configuration 1 */
400 u32 maccfg2; /* MAC Configuration 2 */
401 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
402 u32 hafdup; /* Half Duplex */
403 u32 maxfrm; /* Maximum Frame Len */
404 u8 res18[12];
405 u32 miimcfg; /* MII Management Configuration */
406 u32 miimcom; /* MII Management Cmd */
407 u32 miimadd; /* MII Management Addr */
408 u32 miimcon; /* MII Management Control */
409 u32 miimstat; /* MII Management Status */
410 u32 miimind; /* MII Management Indicator */
411 u8 res19[4];
412 u32 ifstat; /* Interface Status */
413 u32 macstnaddr1; /* Station Addr Part 1 */
414 u32 macstnaddr2; /* Station Addr Part 2 */
415 u8 res20[312];
416 u32 tr64; /* TX & RX 64-byte Frame Counter */
417 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
418 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
419 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
420 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
421 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
422 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
423 u32 rbyt; /* RX Byte Counter */
424 u32 rpkt; /* RX Packet Counter */
425 u32 rfcs; /* RX FCS Error Counter */
426 u32 rmca; /* RX Multicast Packet Counter */
427 u32 rbca; /* RX Broadcast Packet Counter */
428 u32 rxcf; /* RX Control Frame Packet Counter */
429 u32 rxpf; /* RX Pause Frame Packet Counter */
430 u32 rxuo; /* RX Unknown OP Code Counter */
431 u32 raln; /* RX Alignment Error Counter */
432 u32 rflr; /* RX Frame Len Error Counter */
433 u32 rcde; /* RX Code Error Counter */
434 u32 rcse; /* RX Carrier Sense Error Counter */
435 u32 rund; /* RX Undersize Packet Counter */
436 u32 rovr; /* RX Oversize Packet Counter */
437 u32 rfrg; /* RX Fragments Counter */
438 u32 rjbr; /* RX Jabber Counter */
439 u32 rdrp; /* RX Drop Counter */
440 u32 tbyt; /* TX Byte Counter Counter */
441 u32 tpkt; /* TX Packet Counter */
442 u32 tmca; /* TX Multicast Packet Counter */
443 u32 tbca; /* TX Broadcast Packet Counter */
444 u32 txpf; /* TX Pause Control Frame Counter */
445 u32 tdfr; /* TX Deferral Packet Counter */
446 u32 tedf; /* TX Excessive Deferral Packet Counter */
447 u32 tscl; /* TX Single Collision Packet Counter */
448 u32 tmcl; /* TX Multiple Collision Packet Counter */
449 u32 tlcl; /* TX Late Collision Packet Counter */
450 u32 txcl; /* TX Excessive Collision Packet Counter */
451 u32 tncl; /* TX Total Collision Counter */
452 u8 res21[4];
453 u32 tdrp; /* TX Drop Frame Counter */
454 u32 tjbr; /* TX Jabber Frame Counter */
455 u32 tfcs; /* TX FCS Error Counter */
456 u32 txcf; /* TX Control Frame Counter */
457 u32 tovr; /* TX Oversize Frame Counter */
458 u32 tund; /* TX Undersize Frame Counter */
459 u32 tfrg; /* TX Fragments Frame Counter */
460 u32 car1; /* Carry One */
461 u32 car2; /* Carry Two */
462 u32 cam1; /* Carry Mask One */
463 u32 cam2; /* Carry Mask Two */
464 u8 res22[192];
465 u32 iaddr0; /* Indivdual addr 0 */
466 u32 iaddr1; /* Indivdual addr 1 */
467 u32 iaddr2; /* Indivdual addr 2 */
468 u32 iaddr3; /* Indivdual addr 3 */
469 u32 iaddr4; /* Indivdual addr 4 */
470 u32 iaddr5; /* Indivdual addr 5 */
471 u32 iaddr6; /* Indivdual addr 6 */
472 u32 iaddr7; /* Indivdual addr 7 */
473 u8 res23[96];
474 u32 gaddr0; /* Global addr 0 */
475 u32 gaddr1; /* Global addr 1 */
476 u32 gaddr2; /* Global addr 2 */
477 u32 gaddr3; /* Global addr 3 */
478 u32 gaddr4; /* Global addr 4 */
479 u32 gaddr5; /* Global addr 5 */
480 u32 gaddr6; /* Global addr 6 */
481 u32 gaddr7; /* Global addr 7 */
482 u8 res24[96];
483 u32 pmd0; /* Pattern Match Data */
484 u8 res25[4];
485 u32 pmask0; /* Pattern Mask */
486 u8 res26[4];
487 u32 pcntrl0; /* Pattern Match Control */
488 u8 res27[4];
489 u32 pattrb0; /* Pattern Match Attrs */
490 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
491 u32 pmd1; /* Pattern Match Data */
492 u8 res28[4];
493 u32 pmask1; /* Pattern Mask */
494 u8 res29[4];
495 u32 pcntrl1; /* Pattern Match Control */
496 u8 res30[4];
497 u32 pattrb1; /* Pattern Match Attrs */
498 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
499 u32 pmd2; /* Pattern Match Data */
500 u8 res31[4];
501 u32 pmask2; /* Pattern Mask */
502 u8 res32[4];
503 u32 pcntrl2; /* Pattern Match Control */
504 u8 res33[4];
505 u32 pattrb2; /* Pattern Match Attrs */
506 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
507 u32 pmd3; /* Pattern Match Data */
508 u8 res34[4];
509 u32 pmask3; /* Pattern Mask */
510 u8 res35[4];
511 u32 pcntrl3; /* Pattern Match Control */
512 u8 res36[4];
513 u32 pattrb3; /* Pattern Match Attrs */
514 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
515 u32 pmd4; /* Pattern Match Data */
516 u8 res37[4];
517 u32 pmask4; /* Pattern Mask */
518 u8 res38[4];
519 u32 pcntrl4; /* Pattern Match Control */
520 u8 res39[4];
521 u32 pattrb4; /* Pattern Match Attrs */
522 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
523 u32 pmd5; /* Pattern Match Data */
524 u8 res40[4];
525 u32 pmask5; /* Pattern Mask */
526 u8 res41[4];
527 u32 pcntrl5; /* Pattern Match Control */
528 u8 res42[4];
529 u32 pattrb5; /* Pattern Match Attrs */
530 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
531 u32 pmd6; /* Pattern Match Data */
532 u8 res43[4];
533 u32 pmask6; /* Pattern Mask */
534 u8 res44[4];
535 u32 pcntrl6; /* Pattern Match Control */
536 u8 res45[4];
537 u32 pattrb6; /* Pattern Match Attrs */
538 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
539 u32 pmd7; /* Pattern Match Data */
540 u8 res46[4];
541 u32 pmask7; /* Pattern Mask */
542 u8 res47[4];
543 u32 pcntrl7; /* Pattern Match Control */
544 u8 res48[4];
545 u32 pattrb7; /* Pattern Match Attrs */
546 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
547 u32 pmd8; /* Pattern Match Data */
548 u8 res49[4];
549 u32 pmask8; /* Pattern Mask */
550 u8 res50[4];
551 u32 pcntrl8; /* Pattern Match Control */
552 u8 res51[4];
553 u32 pattrb8; /* Pattern Match Attrs */
554 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
555 u32 pmd9; /* Pattern Match Data */
556 u8 res52[4];
557 u32 pmask9; /* Pattern Mask */
558 u8 res53[4];
559 u32 pcntrl9; /* Pattern Match Control */
560 u8 res54[4];
561 u32 pattrb9; /* Pattern Match Attrs */
562 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
563 u32 pmd10; /* Pattern Match Data */
564 u8 res55[4];
565 u32 pmask10; /* Pattern Mask */
566 u8 res56[4];
567 u32 pcntrl10; /* Pattern Match Control */
568 u8 res57[4];
569 u32 pattrb10; /* Pattern Match Attrs */
570 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
571 u32 pmd11; /* Pattern Match Data */
572 u8 res58[4];
573 u32 pmask11; /* Pattern Mask */
574 u8 res59[4];
575 u32 pcntrl11; /* Pattern Match Control */
576 u8 res60[4];
577 u32 pattrb11; /* Pattern Match Attrs */
578 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
579 u32 pmd12; /* Pattern Match Data */
580 u8 res61[4];
581 u32 pmask12; /* Pattern Mask */
582 u8 res62[4];
583 u32 pcntrl12; /* Pattern Match Control */
584 u8 res63[4];
585 u32 pattrb12; /* Pattern Match Attrs */
586 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
587 u32 pmd13; /* Pattern Match Data */
588 u8 res64[4];
589 u32 pmask13; /* Pattern Mask */
590 u8 res65[4];
591 u32 pcntrl13; /* Pattern Match Control */
592 u8 res66[4];
593 u32 pattrb13; /* Pattern Match Attrs */
594 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
595 u32 pmd14; /* Pattern Match Data */
596 u8 res67[4];
597 u32 pmask14; /* Pattern Mask */
598 u8 res68[4];
599 u32 pcntrl14; /* Pattern Match Control */
600 u8 res69[4];
601 u32 pattrb14; /* Pattern Match Attrs */
602 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
603 u32 pmd15; /* Pattern Match Data */
604 u8 res70[4];
605 u32 pmask15; /* Pattern Mask */
606 u8 res71[4];
607 u32 pcntrl15; /* Pattern Match Control */
608 u8 res72[4];
609 u32 pattrb15; /* Pattern Match Attrs */
610 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
611 u8 res73[248];
612 u32 attr; /* Attrs */
613 u32 attreli; /* Attrs Extract Len & Idx */
614 u8 res74[1024];
42d1f039
WD		 615} ccsr_tsec_t;
616
8280912e 617/* PIC Registers */
42d1f039 618typedef struct ccsr_pic {
8280912e
KG		 619 u8 res1[64];
620 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
621 u8 res2[12];
622 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
623 u8 res3[12];
624 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
625 u8 res4[12];
626 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
627 u8 res5[12];
628 u32 ctpr; /* Current Task Priority */
629 u8 res6[12];
630 u32 whoami; /* Who Am I */
631 u8 res7[12];
632 u32 iack; /* IRQ Acknowledge */
633 u8 res8[12];
634 u32 eoi; /* End Of IRQ */
635 u8 res9[3916];
636 u32 frr; /* Feature Reporting */
637 u8 res10[28];
638 u32 gcr; /* Global Configuration */
639#define MPC85xx_PICGCR_RST 0x80000000
640#define MPC85xx_PICGCR_M 0x20000000
641 u8 res11[92];
642 u32 vir; /* Vendor Identification */
643 u8 res12[12];
644 u32 pir; /* Processor Initialization */
645 u8 res13[12];
646 u32 ipivpr0; /* IPI Vector/Priority 0 */
647 u8 res14[12];
648 u32 ipivpr1; /* IPI Vector/Priority 1 */
649 u8 res15[12];
650 u32 ipivpr2; /* IPI Vector/Priority 2 */
651 u8 res16[12];
652 u32 ipivpr3; /* IPI Vector/Priority 3 */
653 u8 res17[12];
654 u32 svr; /* Spurious Vector */
655 u8 res18[12];
656 u32 tfrr; /* Timer Frequency Reporting */
657 u8 res19[12];
658 u32 gtccr0; /* Global Timer Current Count 0 */
659 u8 res20[12];
660 u32 gtbcr0; /* Global Timer Base Count 0 */
661 u8 res21[12];
662 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
663 u8 res22[12];
664 u32 gtdr0; /* Global Timer Destination 0 */
665 u8 res23[12];
666 u32 gtccr1; /* Global Timer Current Count 1 */
667 u8 res24[12];
668 u32 gtbcr1; /* Global Timer Base Count 1 */
669 u8 res25[12];
670 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
671 u8 res26[12];
672 u32 gtdr1; /* Global Timer Destination 1 */
673 u8 res27[12];
674 u32 gtccr2; /* Global Timer Current Count 2 */
675 u8 res28[12];
676 u32 gtbcr2; /* Global Timer Base Count 2 */
677 u8 res29[12];
678 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
679 u8 res30[12];
680 u32 gtdr2; /* Global Timer Destination 2 */
681 u8 res31[12];
682 u32 gtccr3; /* Global Timer Current Count 3 */
683 u8 res32[12];
684 u32 gtbcr3; /* Global Timer Base Count 3 */
685 u8 res33[12];
686 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
687 u8 res34[12];
688 u32 gtdr3; /* Global Timer Destination 3 */
689 u8 res35[268];
690 u32 tcr; /* Timer Control */
691 u8 res36[12];
692 u32 irqsr0; /* IRQ_OUT Summary 0 */
693 u8 res37[12];
694 u32 irqsr1; /* IRQ_OUT Summary 1 */
695 u8 res38[12];
696 u32 cisr0; /* Critical IRQ Summary 0 */
697 u8 res39[12];
698 u32 cisr1; /* Critical IRQ Summary 1 */
699 u8 res40[188];
700 u32 msgr0; /* Message 0 */
701 u8 res41[12];
702 u32 msgr1; /* Message 1 */
703 u8 res42[12];
704 u32 msgr2; /* Message 2 */
705 u8 res43[12];
706 u32 msgr3; /* Message 3 */
707 u8 res44[204];
708 u32 mer; /* Message Enable */
709 u8 res45[12];
710 u32 msr; /* Message Status */
711 u8 res46[60140];
712 u32 eivpr0; /* External IRQ Vector/Priority 0 */
713 u8 res47[12];
714 u32 eidr0; /* External IRQ Destination 0 */
715 u8 res48[12];
716 u32 eivpr1; /* External IRQ Vector/Priority 1 */
717 u8 res49[12];
718 u32 eidr1; /* External IRQ Destination 1 */
719 u8 res50[12];
720 u32 eivpr2; /* External IRQ Vector/Priority 2 */
721 u8 res51[12];
722 u32 eidr2; /* External IRQ Destination 2 */
723 u8 res52[12];
724 u32 eivpr3; /* External IRQ Vector/Priority 3 */
725 u8 res53[12];
726 u32 eidr3; /* External IRQ Destination 3 */
727 u8 res54[12];
728 u32 eivpr4; /* External IRQ Vector/Priority 4 */
729 u8 res55[12];
730 u32 eidr4; /* External IRQ Destination 4 */
731 u8 res56[12];
732 u32 eivpr5; /* External IRQ Vector/Priority 5 */
733 u8 res57[12];
734 u32 eidr5; /* External IRQ Destination 5 */
735 u8 res58[12];
736 u32 eivpr6; /* External IRQ Vector/Priority 6 */
737 u8 res59[12];
738 u32 eidr6; /* External IRQ Destination 6 */
739 u8 res60[12];
740 u32 eivpr7; /* External IRQ Vector/Priority 7 */
741 u8 res61[12];
742 u32 eidr7; /* External IRQ Destination 7 */
743 u8 res62[12];
744 u32 eivpr8; /* External IRQ Vector/Priority 8 */
745 u8 res63[12];
746 u32 eidr8; /* External IRQ Destination 8 */
747 u8 res64[12];
748 u32 eivpr9; /* External IRQ Vector/Priority 9 */
749 u8 res65[12];
750 u32 eidr9; /* External IRQ Destination 9 */
751 u8 res66[12];
752 u32 eivpr10; /* External IRQ Vector/Priority 10 */
753 u8 res67[12];
754 u32 eidr10; /* External IRQ Destination 10 */
755 u8 res68[12];
756 u32 eivpr11; /* External IRQ Vector/Priority 11 */
757 u8 res69[12];
758 u32 eidr11; /* External IRQ Destination 11 */
759 u8 res70[140];
760 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
761 u8 res71[12];
762 u32 iidr0; /* Internal IRQ Destination 0 */
763 u8 res72[12];
764 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
765 u8 res73[12];
766 u32 iidr1; /* Internal IRQ Destination 1 */
767 u8 res74[12];
768 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
769 u8 res75[12];
770 u32 iidr2; /* Internal IRQ Destination 2 */
771 u8 res76[12];
772 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
773 u8 res77[12];
774 u32 iidr3; /* Internal IRQ Destination 3 */
775 u8 res78[12];
776 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
777 u8 res79[12];
778 u32 iidr4; /* Internal IRQ Destination 4 */
779 u8 res80[12];
780 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
781 u8 res81[12];
782 u32 iidr5; /* Internal IRQ Destination 5 */
783 u8 res82[12];
784 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
785 u8 res83[12];
786 u32 iidr6; /* Internal IRQ Destination 6 */
787 u8 res84[12];
788 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
789 u8 res85[12];
790 u32 iidr7; /* Internal IRQ Destination 7 */
791 u8 res86[12];
792 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
793 u8 res87[12];
794 u32 iidr8; /* Internal IRQ Destination 8 */
795 u8 res88[12];
796 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
797 u8 res89[12];
798 u32 iidr9; /* Internal IRQ Destination 9 */
799 u8 res90[12];
800 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
801 u8 res91[12];
802 u32 iidr10; /* Internal IRQ Destination 10 */
803 u8 res92[12];
804 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
805 u8 res93[12];
806 u32 iidr11; /* Internal IRQ Destination 11 */
807 u8 res94[12];
808 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
809 u8 res95[12];
810 u32 iidr12; /* Internal IRQ Destination 12 */
811 u8 res96[12];
812 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
813 u8 res97[12];
814 u32 iidr13; /* Internal IRQ Destination 13 */
815 u8 res98[12];
816 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
817 u8 res99[12];
818 u32 iidr14; /* Internal IRQ Destination 14 */
819 u8 res100[12];
820 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
821 u8 res101[12];
822 u32 iidr15; /* Internal IRQ Destination 15 */
823 u8 res102[12];
824 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
825 u8 res103[12];
826 u32 iidr16; /* Internal IRQ Destination 16 */
827 u8 res104[12];
828 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
829 u8 res105[12];
830 u32 iidr17; /* Internal IRQ Destination 17 */
831 u8 res106[12];
832 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
833 u8 res107[12];
834 u32 iidr18; /* Internal IRQ Destination 18 */
835 u8 res108[12];
836 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
837 u8 res109[12];
838 u32 iidr19; /* Internal IRQ Destination 19 */
839 u8 res110[12];
840 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
841 u8 res111[12];
842 u32 iidr20; /* Internal IRQ Destination 20 */
843 u8 res112[12];
844 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
845 u8 res113[12];
846 u32 iidr21; /* Internal IRQ Destination 21 */
847 u8 res114[12];
848 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
849 u8 res115[12];
850 u32 iidr22; /* Internal IRQ Destination 22 */
851 u8 res116[12];
852 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
853 u8 res117[12];
854 u32 iidr23; /* Internal IRQ Destination 23 */
855 u8 res118[12];
856 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
857 u8 res119[12];
858 u32 iidr24; /* Internal IRQ Destination 24 */
859 u8 res120[12];
860 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
861 u8 res121[12];
862 u32 iidr25; /* Internal IRQ Destination 25 */
863 u8 res122[12];
864 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
865 u8 res123[12];
866 u32 iidr26; /* Internal IRQ Destination 26 */
867 u8 res124[12];
868 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
869 u8 res125[12];
870 u32 iidr27; /* Internal IRQ Destination 27 */
871 u8 res126[12];
872 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
873 u8 res127[12];
874 u32 iidr28; /* Internal IRQ Destination 28 */
875 u8 res128[12];
876 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
877 u8 res129[12];
878 u32 iidr29; /* Internal IRQ Destination 29 */
879 u8 res130[12];
880 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
881 u8 res131[12];
882 u32 iidr30; /* Internal IRQ Destination 30 */
883 u8 res132[12];
884 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
885 u8 res133[12];
886 u32 iidr31; /* Internal IRQ Destination 31 */
887 u8 res134[4108];
888 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
889 u8 res135[12];
890 u32 midr0; /* Messaging IRQ Destination 0 */
891 u8 res136[12];
892 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
893 u8 res137[12];
894 u32 midr1; /* Messaging IRQ Destination 1 */
895 u8 res138[12];
896 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
897 u8 res139[12];
898 u32 midr2; /* Messaging IRQ Destination 2 */
899 u8 res140[12];
900 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
901 u8 res141[12];
902 u32 midr3; /* Messaging IRQ Destination 3 */
903 u8 res142[59852];
904 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
905 u8 res143[12];
906 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
907 u8 res144[12];
908 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
909 u8 res145[12];
910 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
911 u8 res146[12];
912 u32 ctpr0; /* Current Task Priority for Processor 0 */
913 u8 res147[12];
914 u32 whoami0; /* Who Am I for Processor 0 */
915 u8 res148[12];
916 u32 iack0; /* IRQ Acknowledge for Processor 0 */
917 u8 res149[12];
918 u32 eoi0; /* End Of IRQ for Processor 0 */
919 u8 res150[130892];
42d1f039
WD		 920} ccsr_pic_t;
921
8280912e 922/* CPM Block */
9c4c5ae3 923#ifndef CONFIG_CPM2
42d1f039 924typedef struct ccsr_cpm {
8280912e 925 u8 res[262144];
42d1f039
WD		 926} ccsr_cpm_t;
927#else
de1d0a69 928/*
8280912e
KG		 929 * DPARM
930 * General SIU
de1d0a69 931 */
42d1f039 932typedef struct ccsr_cpm_siu {
8280912e
KG		 933 u8 res1[80];
934 u32 smaer;
935 u32 smser;
936 u32 smevr;
937 u8 res2[4];
938 u32 lmaer;
939 u32 lmser;
940 u32 lmevr;
941 u8 res3[2964];
42d1f039
WD		 942} ccsr_cpm_siu_t;
943
8280912e 944/* IRQ Controller */
42d1f039 945typedef struct ccsr_cpm_intctl {
8280912e
KG		 946 u16 sicr;
947 u8 res1[2];
948 u32 sivec;
949 u32 sipnrh;
950 u32 sipnrl;
951 u32 siprr;
952 u32 scprrh;
953 u32 scprrl;
954 u32 simrh;
955 u32 simrl;
956 u32 siexr;
957 u8 res2[88];
958 u32 sccr;
959 u8 res3[124];
42d1f039
WD		 960} ccsr_cpm_intctl_t;
961
8280912e 962/* input/output port */
42d1f039 963typedef struct ccsr_cpm_iop {
8280912e
KG		 964 u32 pdira;
965 u32 ppara;
966 u32 psora;
967 u32 podra;
968 u32 pdata;
969 u8 res1[12];
970 u32 pdirb;
971 u32 pparb;
972 u32 psorb;
973 u32 podrb;
974 u32 pdatb;
975 u8 res2[12];
976 u32 pdirc;
977 u32 pparc;
978 u32 psorc;
979 u32 podrc;
980 u32 pdatc;
981 u8 res3[12];
982 u32 pdird;
983 u32 ppard;
984 u32 psord;
985 u32 podrd;
986 u32 pdatd;
987 u8 res4[12];
42d1f039
WD		 988} ccsr_cpm_iop_t;
989
8280912e 990/* CPM timers */
42d1f039 991typedef struct ccsr_cpm_timer {
8280912e
KG		 992 u8 tgcr1;
993 u8 res1[3];
994 u8 tgcr2;
995 u8 res2[11];
996 u16 tmr1;
997 u16 tmr2;
998 u16 trr1;
999 u16 trr2;
1000 u16 tcr1;
1001 u16 tcr2;
1002 u16 tcn1;
1003 u16 tcn2;
1004 u16 tmr3;
1005 u16 tmr4;
1006 u16 trr3;
1007 u16 trr4;
1008 u16 tcr3;
1009 u16 tcr4;
1010 u16 tcn3;
1011 u16 tcn4;
1012 u16 ter1;
1013 u16 ter2;
1014 u16 ter3;
1015 u16 ter4;
1016 u8 res3[608];
42d1f039
WD		 1017} ccsr_cpm_timer_t;
1018
8280912e 1019/* SDMA */
42d1f039 1020typedef struct ccsr_cpm_sdma {
8280912e
KG		 1021 u8 sdsr;
1022 u8 res1[3];
1023 u8 sdmr;
1024 u8 res2[739];
42d1f039
WD		 1025} ccsr_cpm_sdma_t;
1026
8280912e 1027/* FCC1 */
42d1f039 1028typedef struct ccsr_cpm_fcc1 {
8280912e
KG		 1029 u32 gfmr;
1030 u32 fpsmr;
1031 u16 ftodr;
1032 u8 res1[2];
1033 u16 fdsr;
1034 u8 res2[2];
1035 u16 fcce;
1036 u8 res3[2];
1037 u16 fccm;
1038 u8 res4[2];
1039 u8 fccs;
1040 u8 res5[3];
1041 u8 ftirr_phy[4];
42d1f039
WD		 1042} ccsr_cpm_fcc1_t;
1043
8280912e 1044/* FCC2 */
42d1f039 1045typedef struct ccsr_cpm_fcc2 {
8280912e
KG		 1046 u32 gfmr;
1047 u32 fpsmr;
1048 u16 ftodr;
1049 u8 res1[2];
1050 u16 fdsr;
1051 u8 res2[2];
1052 u16 fcce;
1053 u8 res3[2];
1054 u16 fccm;
1055 u8 res4[2];
1056 u8 fccs;
1057 u8 res5[3];
1058 u8 ftirr_phy[4];
42d1f039
WD		 1059} ccsr_cpm_fcc2_t;
1060
8280912e 1061/* FCC3 */
42d1f039 1062typedef struct ccsr_cpm_fcc3 {
8280912e
KG		 1063 u32 gfmr;
1064 u32 fpsmr;
1065 u16 ftodr;
1066 u8 res1[2];
1067 u16 fdsr;
1068 u8 res2[2];
1069 u16 fcce;
1070 u8 res3[2];
1071 u16 fccm;
1072 u8 res4[2];
1073 u8 fccs;
1074 u8 res5[3];
1075 u8 res[36];
42d1f039
WD		 1076} ccsr_cpm_fcc3_t;
1077
8280912e 1078/* FCC1 extended */
42d1f039 1079typedef struct ccsr_cpm_fcc1_ext {
8280912e
KG		 1080 u32 firper;
1081 u32 firer;
1082 u32 firsr_h;
1083 u32 firsr_l;
1084 u8 gfemr;
1085 u8 res[15];
42d1f039
WD		 1086
1087} ccsr_cpm_fcc1_ext_t;
1088
8280912e 1089/* FCC2 extended */
42d1f039 1090typedef struct ccsr_cpm_fcc2_ext {
8280912e
KG		 1091 u32 firper;
1092 u32 firer;
1093 u32 firsr_h;
1094 u32 firsr_l;
1095 u8 gfemr;
1096 u8 res[31];
42d1f039
WD		 1097} ccsr_cpm_fcc2_ext_t;
1098
8280912e 1099/* FCC3 extended */
42d1f039 1100typedef struct ccsr_cpm_fcc3_ext {
8280912e
KG		 1101 u8 gfemr;
1102 u8 res[47];
42d1f039
WD		 1103} ccsr_cpm_fcc3_ext_t;
1104
8280912e 1105/* TC layers */
42d1f039 1106typedef struct ccsr_cpm_tmp1 {
8280912e 1107 u8 res[496];
42d1f039
WD		 1108} ccsr_cpm_tmp1_t;
1109
8280912e 1110/* BRGs:5,6,7,8 */
42d1f039 1111typedef struct ccsr_cpm_brg2 {
8280912e
KG		 1112 u32 brgc5;
1113 u32 brgc6;
1114 u32 brgc7;
1115 u32 brgc8;
1116 u8 res[608];
42d1f039
WD		 1117} ccsr_cpm_brg2_t;
1118
8280912e 1119/* I2C */
42d1f039 1120typedef struct ccsr_cpm_i2c {
8280912e
KG		 1121 u8 i2mod;
1122 u8 res1[3];
1123 u8 i2add;
1124 u8 res2[3];
1125 u8 i2brg;
1126 u8 res3[3];
1127 u8 i2com;
1128 u8 res4[3];
1129 u8 i2cer;
1130 u8 res5[3];
1131 u8 i2cmr;
1132 u8 res6[331];
42d1f039
WD		 1133} ccsr_cpm_i2c_t;
1134
8280912e 1135/* CPM core */
42d1f039 1136typedef struct ccsr_cpm_cp {
8280912e
KG		 1137 u32 cpcr;
1138 u32 rccr;
1139 u8 res1[14];
1140 u16 rter;
1141 u8 res2[2];
1142 u16 rtmr;
1143 u16 rtscr;
1144 u8 res3[2];
1145 u32 rtsr;
1146 u8 res4[12];
42d1f039
WD		 1147} ccsr_cpm_cp_t;
1148
8280912e 1149/* BRGs:1,2,3,4 */
42d1f039 1150typedef struct ccsr_cpm_brg1 {
8280912e
KG		 1151 u32 brgc1;
1152 u32 brgc2;
1153 u32 brgc3;
1154 u32 brgc4;
42d1f039
WD		 1155} ccsr_cpm_brg1_t;
1156
8280912e 1157/* SCC1-SCC4 */
42d1f039 1158typedef struct ccsr_cpm_scc {
8280912e
KG		 1159 u32 gsmrl;
1160 u32 gsmrh;
1161 u16 psmr;
1162 u8 res1[2];
1163 u16 todr;
1164 u16 dsr;
1165 u16 scce;
1166 u8 res2[2];
1167 u16 sccm;
1168 u8 res3;
1169 u8 sccs;
1170 u8 res4[8];
42d1f039
WD		 1171} ccsr_cpm_scc_t;
1172
42d1f039 1173typedef struct ccsr_cpm_tmp2 {
8280912e 1174 u8 res[32];
42d1f039
WD		 1175} ccsr_cpm_tmp2_t;
1176
8280912e 1177/* SPI */
42d1f039 1178typedef struct ccsr_cpm_spi {
8280912e
KG		 1179 u16 spmode;
1180 u8 res1[4];
1181 u8 spie;
1182 u8 res2[3];
1183 u8 spim;
1184 u8 res3[2];
1185 u8 spcom;
1186 u8 res4[82];
42d1f039
WD		 1187} ccsr_cpm_spi_t;
1188
8280912e 1189/* CPM MUX */
42d1f039 1190typedef struct ccsr_cpm_mux {
8280912e
KG		 1191 u8 cmxsi1cr;
1192 u8 res1;
1193 u8 cmxsi2cr;
1194 u8 res2;
1195 u32 cmxfcr;
1196 u32 cmxscr;
1197 u8 res3[2];
1198 u16 cmxuar;
1199 u8 res4[16];
42d1f039
WD		 1200} ccsr_cpm_mux_t;
1201
8280912e 1202/* SI,MCC,etc */
42d1f039 1203typedef struct ccsr_cpm_tmp3 {
8280912e 1204 u8 res[58592];
42d1f039
WD		 1205} ccsr_cpm_tmp3_t;
1206
1207typedef struct ccsr_cpm_iram {
8280912e
KG		 1208 u32 iram[8192];
1209 u8 res[98304];
42d1f039
WD		 1210} ccsr_cpm_iram_t;
1211
1212typedef struct ccsr_cpm {
8280912e 1213 /* Some references are into the unique & known dpram spaces,
42d1f039
WD		 1214 * others are from the generic base.
1215 */
53677ef1 1216#define im_dprambase im_dpram1
8280912e
KG		 1217 u8 im_dpram1[16*1024];
1218 u8 res1[16*1024];
1219 u8 im_dpram2[16*1024];
1220 u8 res2[16*1024];
1221 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1222 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1223 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1224 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1225 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
42d1f039
WD		 1226 ccsr_cpm_fcc1_t im_cpm_fcc1;
1227 ccsr_cpm_fcc2_t im_cpm_fcc2;
1228 ccsr_cpm_fcc3_t im_cpm_fcc3;
1229 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1230 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1231 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1232 ccsr_cpm_tmp1_t im_cpm_tmp1;
1233 ccsr_cpm_brg2_t im_cpm_brg2;
1234 ccsr_cpm_i2c_t im_cpm_i2c;
1235 ccsr_cpm_cp_t im_cpm_cp;
1236 ccsr_cpm_brg1_t im_cpm_brg1;
1237 ccsr_cpm_scc_t im_cpm_scc[4];
1238 ccsr_cpm_tmp2_t im_cpm_tmp2;
1239 ccsr_cpm_spi_t im_cpm_spi;
1240 ccsr_cpm_mux_t im_cpm_mux;
1241 ccsr_cpm_tmp3_t im_cpm_tmp3;
1242 ccsr_cpm_iram_t im_cpm_iram;
1243} ccsr_cpm_t;
1244#endif
42d1f039 1245
7d67ed58
LG		 1246#ifdef CONFIG_SYS_SRIO
1247/* Architectural regsiters */
1248struct rio_arch {
1249 u32 didcar; /* Device Identity CAR */
1250 u32 dicar; /* Device Information CAR */
1251 u32 aidcar; /* Assembly Identity CAR */
1252 u32 aicar; /* Assembly Information CAR */
1253 u32 pefcar; /* Processing Element Features CAR */
1254 u8 res0[4];
1255 u32 socar; /* Source Operations CAR */
1256 u32 docar; /* Destination Operations CAR */
8280912e 1257 u8 res1[32];
7d67ed58
LG		 1258 u32 mcsr; /* Mailbox CSR */
1259 u32 pwdcsr; /* Port-Write and Doorbell CSR */
8280912e
KG		 1260 u8 res2[4];
1261 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1262 u8 res3[12];
7d67ed58
LG		 1263 u32 lcsbacsr; /* Local Configuration Space BACSR */
1264 u32 bdidcsr; /* Base Device ID CSR */
8280912e 1265 u8 res4[4];
7d67ed58
LG		 1266 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1267 u32 ctcsr; /* Component Tag CSR */
1268};
1269
1270/* Extended Features Space: 1x/4x LP-Serial Port registers */
1271struct rio_lp_serial_port {
1272 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1273 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1274 u32 plascsr; /* Port Local Ackid Status CSR */
1275 u8 res0[12];
1276 u32 pescsr; /* Port Error and Status CSR */
1277 u32 pccsr; /* Port Control CSR */
1278};
1279
1280/* Extended Features Space: 1x/4x LP-Serial registers */
1281struct rio_lp_serial {
1282 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1283 u8 res0[28];
1284 u32 pltoccsr; /* Port Link Time-out CCSR */
1285 u32 prtoccsr; /* Port Response Time-out CCSR */
1286 u8 res1[20];
1287 u32 pgccsr; /* Port General CSR */
1288 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1289};
1290
1291/* Logical error reporting registers */
1292struct rio_logical_err {
1293 u32 erbh; /* Error Reporting Block Header Register */
1294 u8 res0[4];
1295 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1296 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1297 u8 res1[4];
1298 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1299 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1300 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1301};
1302
1303/* Physical error reporting port registers */
1304struct rio_phys_err_port {
1305 u32 edcsr; /* Port error detect CSR */
1306 u32 erecsr; /* Port error rate enable CSR */
1307 u32 ecacsr; /* Port error capture attributes CSR */
1308 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1309 u32 peccsr[3]; /* Port error capture CSR */
1310 u8 res0[12];
1311 u32 ercsr; /* Port error rate CSR */
1312 u32 ertcsr; /* Port error rate threshold CSR */
1313 u8 res1[16];
1314};
1315
1316/* Physical error reporting registers */
1317struct rio_phys_err {
1318 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1319};
1320
1321/* Implementation Space: General Port-Common */
1322struct rio_impl_common {
1323 u8 res0[4];
1324 u32 llcr; /* Logical Layer Configuration Register */
1325 u8 res1[8];
1326 u32 epwisr; /* Error / Port-Write Interrupt SR */
1327 u8 res2[12];
1328 u32 lretcr; /* Logical Retry Error Threshold CR */
1329 u8 res3[92];
1330 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1331 u8 res4[124];
1332};
1333
1334/* Implementation Space: Port Specific */
1335struct rio_impl_port_spec {
1336 u32 adidcsr; /* Port Alt. Device ID CSR */
1337 u8 res0[28];
1338 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1339 u32 lopttlcr;
1340 u8 res1[8];
1341 u32 iecsr; /* Port Implementation Error CSR */
1342 u8 res2[12];
1343 u32 pcr; /* Port Phsyical Configuration Register */
1344 u8 res3[20];
1345 u32 slcsr; /* Port Serial Link CSR */
1346 u8 res4[4];
1347 u32 sleicr; /* Port Serial Link Error Injection */
1348 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1349 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1350 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1351 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1352 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1353};
1354
1355/* Implementation Space: register */
1356struct rio_implement {
1357 struct rio_impl_common com;
1358 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1359};
1360
1361/* Revision Control Register */
1362struct rio_rev_ctrl {
1363 u32 ipbrr[2]; /* IP Block Revision Register */
1364};
1365
1366struct rio_atmu_row {
1367 u32 rowtar; /* RapidIO Outbound Window TAR */
1368 u32 rowtear; /* RapidIO Outbound Window TEAR */
1369 u32 rowbar;
1370 u8 res0[4];
1371 u32 rowar; /* RapidIO Outbound Attributes Register */
1372 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1373};
1374
1375struct rio_atmu_riw {
1376 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1377 u8 res0[4];
1378 u32 riwbar; /* RapidIO Inbound Window Base AR */
1379 u8 res1[4];
1380 u32 riwar; /* RapidIO Inbound Attributes Register */
1381 u8 res2[12];
1382};
1383
1384/* ATMU window registers */
1385struct rio_atmu_win {
1386 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1387 u8 res0[64];
1388 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1389};
1390
1391struct rio_atmu {
1392 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1393};
1394
1395#ifdef CONFIG_SYS_FSL_RMU
1396struct rio_msg {
1397 u32 omr; /* Outbound Mode Register */
1398 u32 osr; /* Outbound Status Register */
1399 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1400 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1401 u32 eosar; /* Extended Outbound Unit Source AR */
1402 u32 osar; /* Outbound Unit Source AR */
1403 u32 odpr; /* Outbound Destination Port Register */
1404 u32 odatr; /* Outbound Destination Attributes Register */
1405 u32 odcr; /* Outbound Doubleword Count Register */
1406 u32 eodqepar; /* Extended Outbound DQ EPAR */
1407 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1408 u32 oretr; /* Outbound Retry Error Threshold Register */
1409 u32 omgr; /* Outbound Multicast Group Register */
1410 u32 omlr; /* Outbound Multicast List Register */
1411 u8 res0[40];
1412 u32 imr; /* Outbound Mode Register */
1413 u32 isr; /* Inbound Status Register */
1414 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1415 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1416 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1417 u32 ifqepar; /* Inbound Frame Queue EPAR */
1418 u32 imirir; /* Inbound Maximum Interrutp RIR */
1419 u8 res1[4];
1420 u32 eihqepar; /* Extended inbound message header queue EPAR */
1421 u32 ihqepar; /* Inbound message header queue EPAR */
1422 u8 res2[120];
1423};
1424
1425struct rio_dbell {
1426 u32 odmr; /* Outbound Doorbell Mode Register */
1427 u32 odsr; /* Outbound Doorbell Status Register */
1428 u8 res0[16];
1429 u32 oddpr; /* Outbound Doorbell Destination Port */
1430 u32 oddatr; /* Outbound Doorbell Destination AR */
1431 u8 res1[12];
1432 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1433 u8 res2[48];
1434 u32 idmr; /* Inbound Doorbell Mode Register */
1435 u32 idsr; /* Inbound Doorbell Status Register */
1436 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1437 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1438 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1439 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1440 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1441};
1442
1443struct rio_pw {
1444 u32 pwmr; /* Port-Write Mode Register */
1445 u32 pwsr; /* Port-Write Status Register */
1446 u32 epwqbar; /* Extended Port-Write Queue BAR */
1447 u32 pwqbar; /* Port-Write Queue Base Address Register */
1448};
1449#endif
1450
b3831020
LG		 1451#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1452struct rio_liodn {
1453 u32 plbr;
1454 u8 res0[28];
1455 u32 plaor;
1456 u8 res1[12];
1457 u32 pludr;
1458 u32 plldr;
1459 u8 res2[456];
1460};
1461#endif
1462
7d67ed58
LG		 1463/* RapidIO Registers */
1464struct ccsr_rio {
1465 struct rio_arch arch;
1466 u8 res0[144];
1467 struct rio_lp_serial lp_serial;
1468 u8 res1[1152];
1469 struct rio_logical_err logical_err;
1470 u8 res2[32];
1471 struct rio_phys_err phys_err;
1472 u8 res3[63808];
1473 struct rio_implement impl;
1474 u8 res4[2552];
1475 struct rio_rev_ctrl rev;
1476 struct rio_atmu atmu;
1477#ifdef CONFIG_SYS_FSL_RMU
1478 u8 res5[8192];
1479 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1480 u8 res6[512];
1481 struct rio_dbell dbell;
1482 u8 res7[100];
1483 struct rio_pw pw;
1484#endif
b3831020
LG		 1485#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1486 u8 res5[8192];
1487 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1488#endif
7d67ed58
LG		 1489};
1490#endif
42d1f039 1491
8280912e 1492/* Quick Engine Block Pin Muxing Registers */
c59e4091 1493typedef struct par_io {
8280912e
KG		 1494 u32 cpodr;
1495 u32 cpdat;
1496 u32 cpdir1;
1497 u32 cpdir2;
1498 u32 cppar1;
1499 u32 cppar2;
1500 u8 res[8];
1501} par_io_t;
c59e4091 1502
8b0ab304
BB		 1503#ifdef CONFIG_SYS_FSL_CPC
1504/*
1505 * Define a single offset that is the start of all the CPC register
1506 * blocks - if there is more than one CPC, we expect these to be
1507 * contiguous 4k regions
1508 */
1509
1510typedef struct cpc_corenet {
1511 u32 cpccsr0; /* Config/status reg */
1512 u32 res1;
1513 u32 cpccfg0; /* Configuration register */
1514 u32 res2;
1515 u32 cpcewcr0; /* External Write reg 0 */
1516 u32 cpcewabr0; /* External write base reg 0 */
1517 u32 res3[2];
1518 u32 cpcewcr1; /* External Write reg 1 */
1519 u32 cpcewabr1; /* External write base reg 1 */
1520 u32 res4[54];
1521 u32 cpcsrcr1; /* SRAM control reg 1 */
1522 u32 cpcsrcr0; /* SRAM control reg 0 */
1523 u32 res5[62];
1524 struct {
1525 u32 id; /* partition ID */
1526 u32 res;
1527 u32 alloc; /* partition allocation */
1528 u32 way; /* partition way */
1529 } partition_regs[16];
1530 u32 res6[704];
1531 u32 cpcerrinjhi; /* Error injection high */
1532 u32 cpcerrinjlo; /* Error injection lo */
1533 u32 cpcerrinjctl; /* Error injection control */
1534 u32 res7[5];
1535 u32 cpccaptdatahi; /* capture data high */
1536 u32 cpccaptdatalo; /* capture data low */
1537 u32 cpcaptecc; /* capture ECC */
1538 u32 res8[5];
1539 u32 cpcerrdet; /* error detect */
1540 u32 cpcerrdis; /* error disable */
1541 u32 cpcerrinten; /* errir interrupt enable */
1542 u32 cpcerrattr; /* error attribute */
1543 u32 cpcerreaddr; /* error extended address */
1544 u32 cpcerraddr; /* error address */
1545 u32 cpcerrctl; /* error control */
3c6a22b9
KG		 1546 u32 res9[41]; /* pad out to 4k */
1547 u32 cpchdbcr0; /* hardware debug control register 0 */
1548 u32 res10[63]; /* pad out to 4k */
8b0ab304
BB		 1549} cpc_corenet_t;
1550
1551#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1552#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1553#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1554#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1555#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1556#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1557#define CPC_CFG0_SZ_MASK 0x00003fff
1558#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1559#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1560#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1561#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1562#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1563 & CPC_SRCR1_SRBARU_MASK)
1564#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1565#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1566#define CPC_SRCR0_INTLVEN 0x00000100
1567#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1568#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1569#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1570#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1571#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1572#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1573#define CPC_SRCR0_SRAMEN 0x00000001
1574#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
3c6a22b9 1575#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1d2c2a62 1576#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
868da593 1577#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
133fbfa9 1578#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
8b0ab304
BB		 1579#endif /* CONFIG_SYS_FSL_CPC */
1580
8280912e 1581/* Global Utilities Block */
01df5212
KG		 1582#ifdef CONFIG_FSL_CORENET
1583typedef struct ccsr_gur {
45c18853
YS		 1584 u32 porsr1; /* POR status 1 */
1585 u32 porsr2; /* POR status 2 */
0c12a159 1586#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1587#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1588#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1589#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1590#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1591#endif
45c18853 1592 u8 res_008[0x20-0x8];
8280912e 1593 u32 gpporcr1; /* General-purpose POR configuration */
45c18853
YS		 1594 u32 gpporcr2; /* General-purpose POR configuration 2 */
1595 u32 dcfg_fusesr; /* Fuse status register */
1596#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1597#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1598#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1599#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1600 u8 res_02c[0x70-0x2c];
8280912e 1601 u32 devdisr; /* Device disable control */
9e758758
YS		 1602 u32 devdisr2; /* Device disable control 2 */
1603 u32 devdisr3; /* Device disable control 3 */
1604 u32 devdisr4; /* Device disable control 4 */
1605#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1606 u32 devdisr5; /* Device disable control 5 */
1607#define FSL_CORENET_DEVDISR_PBL 0x80000000
1608#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1609#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1610#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1611#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1612#define FSL_CORENET_DEVDISR_USB1 0x00080000
1613#define FSL_CORENET_DEVDISR_USB2 0x00040000
1614#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1615#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1616#define FSL_CORENET_DEVDISR_PME 0x00000800
1617#define FSL_CORENET_DEVDISR_SEC 0x00000200
1618#define FSL_CORENET_DEVDISR_RMU 0x00000080
1619#define FSL_CORENET_DEVDISR_DCE 0x00000040
1620#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1621#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1622#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1623#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1624#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1625#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1626#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1627#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1628#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1629#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
82a55c1e
SL		 1630#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1631#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
9e758758
YS		 1632#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1633#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1634#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1635#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1636#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1637#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1638#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1639#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1640#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1641#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1642#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1643#define FSL_CORENET_DEVDISR2_FM2 0x00000040
d2404141 1644#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
9e758758
YS		 1645#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1646#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1647#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1648#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1649#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1650#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1651#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1652#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1653#define FSL_CORENET_DEVDISR3_LA1 0x00008000
d2404141
YS		 1654#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1655#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1656#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
9e758758
YS		 1657#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1658#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1659#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1660#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1661#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1662#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1663#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1664#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1665#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1666#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1667#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1668#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1669#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1670#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1671#define FSL_CORENET_DEVDISR5_NAL 0x00100000
d2404141 1672#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
9e758758
YS		 1673#define FSL_CORENET_NUM_DEVDISR 5
1674#else
01df5212
KG		 1675#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1676#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1677#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
9ab87d04 1678#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
01df5212
KG		 1679#define FSL_CORENET_DEVDISR_RMU 0x08000000
1680#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1681#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1682#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1683#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1684#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1685#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1686#define FSL_CORENET_DEVDISR_DBG 0x00010000
1687#define FSL_CORENET_DEVDISR_NAL 0x00008000
9ab87d04
KG		 1688#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1689#define FSL_CORENET_DEVDISR_SATA2 0x00002000
01df5212
KG		 1690#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1691#define FSL_CORENET_DEVDISR_USB1 0x00000800
1692#define FSL_CORENET_DEVDISR_USB2 0x00000400
1693#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1694#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1695#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1696#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1697#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1698#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1699#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1231c498
KG		 1700#define FSL_CORENET_DEVDISR2_PME 0x80000000
1701#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1702#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1703#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1704#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1705#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1706#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1707#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1708#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
9ab87d04 1709#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1231c498
KG		 1710#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1711#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1712#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1713#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1714#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1715#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
99abf7de 1716#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
9ab87d04 1717#define FSL_CORENET_NUM_DEVDISR 2
8280912e 1718 u32 powmgtcsr; /* Power management status & control */
9e758758 1719#endif
01df5212 1720 u8 res8[12];
8280912e
KG		 1721 u32 coredisru; /* uppper portion for support of 64 cores */
1722 u32 coredisrl; /* lower portion for support of 64 cores */
01df5212 1723 u8 res9[8];
8280912e
KG		 1724 u32 pvr; /* Processor version */
1725 u32 svr; /* System version */
01df5212 1726 u8 res10[8];
8280912e
KG		 1727 u32 rstcr; /* Reset control */
1728 u32 rstrqpblsr; /* Reset request preboot loader status */
01df5212 1729 u8 res11[8];
8280912e 1730 u32 rstrqmr1; /* Reset request mask */
fb07c0a1
SL		 1731#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1732#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1733#endif
8280912e
KG		 1734 u8 res12[4];
1735 u32 rstrqsr1; /* Reset request status */
1736 u8 res13[4];
1737 u8 res14[4];
1738 u32 rstrqwdtmrl; /* Reset request WDT mask */
1739 u8 res15[4];
1740 u32 rstrqwdtsrl; /* Reset request WDT status */
1741 u8 res16[4];
1742 u32 brrl; /* Boot release */
01df5212 1743 u8 res17[24];
8280912e 1744 u32 rcwsr[16]; /* Reset control word status */
fd3cebd0
YS		 1745
1746#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
f77329cf 1747#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
c3678b09
YS		 1748/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
1749#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
f77329cf 1750#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
5122dfae
SL		 1751#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
1752 defined(CONFIG_PPC_T4080)
fd3cebd0
YS		 1753#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1754#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1755#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1756#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1757#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1758#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1759#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1760#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
69fdf900 1761#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
e1dbdd81 1762#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
d2404141
YS		 1763#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1764#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1765#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1766#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
5870fe44 1767#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
2967af68
PJ		 1768#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
1769defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
5f208d11
YS		 1770#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1771#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1772#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1773#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
5b7672fc
PK		 1774#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1775#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1776#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1777#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1778#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
1779#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1780#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1781#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
1782#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1783#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1784#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
bf4699db
PJ		 1785#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1786#define PXCKEN_MASK 0x80000000
1787#define PXCK_MASK 0x00FF0000
1788#define PXCK_BITS_START 16
629d6b32
SL		 1789#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1790#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1791#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1792#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1793#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1794#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
9e758758 1795#endif
fd3cebd0
YS		 1796#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1797#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1798#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1799#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1800#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1801#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1802#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1803#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
b135991a
PJ		 1804#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1805#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1806#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
fd3cebd0
YS		 1807
1808#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1809#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1810#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
01df5212 1811#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
ab48ca1a
SS		 1812#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1813#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1231c498 1814#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
4905443f 1815#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
81fa73ba 1816#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
9ab87d04
KG		 1817#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1818#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
fd3cebd0
YS		 1819#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1820
01df5212
KG		 1821#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1822#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1823#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
9ab87d04 1824#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
055ce080 1825#ifdef CONFIG_PPC_P4080
c916d7c9
KG		 1826#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1827#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
9ab87d04 1828#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
c916d7c9
KG		 1829#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1830#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1831#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1832#endif
3e978f5d 1833#if defined(CONFIG_PPC_P2041) \
c916d7c9
KG		 1834 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1835#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1836#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1837#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1838#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1839#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1840#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1841#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
4905443f
TT		 1842#endif
1843#if defined(CONFIG_PPC_P5040)
1844#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1845#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1846#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1847#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1848#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1849#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1850#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
9e758758 1851#endif
5122dfae
SL		 1852#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
1853 defined(CONFIG_PPC_T4080)
9e758758
YS		 1854#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1855#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1856#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1857#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1858#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1859#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1860#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
629d6b32
SL		 1861#endif
1862#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1863#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1864#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1865#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1866#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1867#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1868#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1869#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
c916d7c9 1870#endif
8280912e
KG		 1871 u8 res18[192];
1872 u32 scratchrw[4]; /* Scratch Read/Write */
1873 u8 res19[240];
1874 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1875 u8 res20[240];
1876 u32 scrtsr[8]; /* Core reset status */
1877 u8 res21[224];
1878 u32 pex1liodnr; /* PCI Express 1 LIODN */
1879 u32 pex2liodnr; /* PCI Express 2 LIODN */
1880 u32 pex3liodnr; /* PCI Express 3 LIODN */
1881 u32 pex4liodnr; /* PCI Express 4 LIODN */
1882 u32 rio1liodnr; /* RIO 1 LIODN */
1883 u32 rio2liodnr; /* RIO 2 LIODN */
1884 u32 rio3liodnr; /* RIO 3 LIODN */
1885 u32 rio4liodnr; /* RIO 4 LIODN */
1886 u32 usb1liodnr; /* USB 1 LIODN */
1887 u32 usb2liodnr; /* USB 2 LIODN */
1888 u32 usb3liodnr; /* USB 3 LIODN */
1889 u32 usb4liodnr; /* USB 4 LIODN */
1890 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1891 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1892 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1893 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
9ab87d04
KG		 1894 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1895 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1896 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1897 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1898 u32 sata1liodnr; /* SATA 1 LIODN */
1899 u32 sata2liodnr; /* SATA 2 LIODN */
1900 u32 sata3liodnr; /* SATA 3 LIODN */
1901 u32 sata4liodnr; /* SATA 4 LIODN */
377ffcfa
SS		 1902 u8 res22[20];
1903 u32 tdmliodnr; /* TDM LIODN */
2a44efeb
ZQ		 1904 u32 qeliodnr; /* QE LIODN */
1905 u8 res_57c[4];
8280912e
KG		 1906 u32 dma1liodnr; /* DMA 1 LIODN */
1907 u32 dma2liodnr; /* DMA 2 LIODN */
1908 u32 dma3liodnr; /* DMA 3 LIODN */
1909 u32 dma4liodnr; /* DMA 4 LIODN */
1910 u8 res23[48];
1911 u8 res24[64];
1912 u32 pblsr; /* Preboot loader status */
1913 u32 pamubypenr; /* PAMU bypass enable */
1914 u32 dmacr1; /* DMA control */
1915 u8 res25[4];
1916 u32 gensr1; /* General status */
1917 u8 res26[12];
1918 u32 gencr1; /* General control */
1919 u8 res27[12];
1920 u8 res28[4];
1921 u32 cgensrl; /* Core general status */
1922 u8 res29[8];
1923 u8 res30[4];
1924 u32 cgencrl; /* Core general control */
1925 u8 res31[184];
1926 u32 sriopstecr; /* SRIO prescaler timer enable control */
f110fe94 1927 u32 dcsrcr; /* DCSR Control register */
1ca8690d
YS		 1928 u8 res31a[56];
1929 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1930 struct {
1931 u32 upper;
1932 u32 lower;
1933 } tp_cluster[16]; /* Core Cluster n Topology Register */
1934 u8 res32[1344];
17d90f31
DL		 1935 u32 pmuxcr; /* Pin multiplexing control */
1936 u8 res33[60];
1937 u32 iovselsr; /* I/O voltage selection status */
1938 u8 res34[28];
1939 u32 ddrclkdr; /* DDR clock disable */
1940 u8 res35;
1941 u32 elbcclkdr; /* eLBC clock disable */
1942 u8 res36[20];
1943 u32 sdhcpcr; /* eSDHC polarity configuration */
1944 u8 res37[380];
01df5212
KG		 1945} ccsr_gur_t;
1946
1ca8690d
YS		 1947#define TP_ITYP_AV 0x00000001 /* Initiator available */
1948#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1949#define TP_ITYP_TYPE_OTHER 0x0
1950#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1951#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1952#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1953#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1954#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1955
1956#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1957#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
f6981439 1958#define TP_INIT_PER_CLUSTER 4
1ca8690d 1959
f110fe94
SG		 1960#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1961#define FSL_CORENET_DCSR_SZ_4M 0x0
1962#define FSL_CORENET_DCSR_SZ_1G 0x3
1963
9ab87d04
KG		 1964/*
1965 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1966 * everything after has RMan thus msg unit LIODN is used for maintenance
1967 */
1968#define rmuliodnr rio1maintliodnr
1969
01df5212 1970typedef struct ccsr_clk {
f6981439
YS		 1971 struct {
1972 u32 clkcncsr; /* core cluster n clock control status */
1973 u8 res_004[0x0c];
1974 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
1975 u8 res_014[0x0c];
ce746fe0
PK		 1976 } clkcsr[12];
1977 u8 res_100[0x680]; /* 0x100 */
1978 struct {
1979 u32 pllcngsr;
1980 u8 res10[0x1c];
1981 } pllcgsr[12];
1982 u8 res21[0x280];
9a653a98
YS		 1983 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
1984 u8 res16[0x1c];
1985 u32 plldgsr; /* 0xc20 DDR PLL General Status */
1986 u8 res17[0x3dc];
01df5212
KG		 1987} ccsr_clk_t;
1988
1ca8690d
YS		 1989#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1990typedef struct ccsr_rcpm {
1991 u8 res_00[12];
1992 u32 tph10sr0; /* Thread PH10 Status Register */
1993 u8 res_10[12];
1994 u32 tph10setr0; /* Thread PH10 Set Control Register */
1995 u8 res_20[12];
1996 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
1997 u8 res_30[12];
1998 u32 tph10psr0; /* Thread PH10 Previous Status Register */
1999 u8 res_40[12];
2000 u32 twaitsr0; /* Thread Wait Status Register */
2001 u8 res_50[96];
2002 u32 pcph15sr; /* Physical Core PH15 Status Register */
2003 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
2004 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
2005 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
2006 u8 res_c0[16];
2007 u32 pcph20sr; /* Physical Core PH20 Status Register */
2008 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
2009 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
2010 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
2011 u32 pcpw20sr; /* Physical Core PW20 Status Register */
2012 u8 res_e0[12];
2013 u32 pcph30sr; /* Physical Core PH30 Status Register */
2014 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
2015 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
2016 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
2017 u8 res_100[32];
2018 u32 ippwrgatecr; /* IP Power Gating Control Register */
2019 u8 res_124[12];
2020 u32 powmgtcsr; /* Power Management Control & Status Reg */
2021 u8 res_134[12];
2022 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
2023 u8 res_150[12];
2024 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
2025 u8 res_160[12];
2026 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
2027 u8 res_170[12];
2028 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
2029 u8 res_180[12];
2030 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
2031 u8 res_190[12];
2032 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
2033 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2034 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2035 u32 tbclkdivr; /* Time Base Clock Divider Register */
2036 u8 res_1ac[4];
2037 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2038 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2039 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2040 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2041 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2042 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2043 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2044 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2045 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2046 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2047 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2048 u8 res_1e8[8];
2049 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2050 u8 res_300[3568];
2051} ccsr_rcpm_t;
2052
2053#define ctbenrl pctbenr
2054
2055#else
01df5212 2056typedef struct ccsr_rcpm {
8280912e
KG		 2057 u8 res1[4];
2058 u32 cdozsrl; /* Core Doze Status */
2059 u8 res2[4];
2060 u32 cdozcrl; /* Core Doze Control */
2061 u8 res3[4];
2062 u32 cnapsrl; /* Core Nap Status */
2063 u8 res4[4];
2064 u32 cnapcrl; /* Core Nap Control */
2065 u8 res5[4];
2066 u32 cdozpsrl; /* Core Doze Previous Status */
2067 u8 res6[4];
2068 u32 cdozpcrl; /* Core Doze Previous Control */
2069 u8 res7[4];
2070 u32 cwaitsrl; /* Core Wait Status */
2071 u8 res8[8];
2072 u32 powmgtcsr; /* Power Mangement Control & Status */
2073 u8 res9[12];
2074 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2075 u8 res10[12];
2076 u8 res11[4];
2077 u32 cpmimrl; /* Core PM IRQ Masking */
2078 u8 res12[4];
2079 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2080 u8 res13[4];
2081 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2082 u8 res14[4];
2083 u32 cpmnmimrl; /* Core PM NMI Masking */
2084 u8 res15[4];
2085 u32 ctbenrl; /* Core Time Base Enable */
2086 u8 res16[4];
2087 u32 ctbclkselrl; /* Core Time Base Clock Select */
2088 u8 res17[4];
2089 u32 ctbhltcrl; /* Core Time Base Halt Control */
01df5212
KG		 2090 u8 res18[0xf68];
2091} ccsr_rcpm_t;
1ca8690d 2092#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
01df5212
KG		 2093
2094#else
42d1f039 2095typedef struct ccsr_gur {
8280912e 2096 u32 porpllsr; /* POR PLL ratio status */
c0391111
JJ		 2097#ifdef CONFIG_MPC8536
2098#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2099#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
3b75e982
MH		 2100#elif defined(CONFIG_PPC_C29X)
2101#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2102#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2103 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2104 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
c0391111 2105#else
35fe948e 2106#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
19a8dbdc
PK		 2107#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2108#else
c0391111 2109#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
19a8dbdc 2110#endif
c0391111
JJ		 2111#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2112#endif
b3d7f20f
HW		 2113#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2114#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
266139b8 2115#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
8280912e
KG		 2116#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2117 u32 porbmsr; /* POR boot mode status */
53677ef1 2118#define MPC85xx_PORBMSR_HA 0x00070000
6442b71b 2119#define MPC85xx_PORBMSR_HA_SHIFT 16
8bd00c94 2120#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
35fe948e
PK		 2121#define PORBMSR_ROMLOC_SPI 0x6
2122#define PORBMSR_ROMLOC_SDHC 0x7
2123#define PORBMSR_ROMLOC_NAND_2K 0x9
2124#define PORBMSR_ROMLOC_NOR 0xf
8280912e
KG		 2125 u32 porimpscr; /* POR I/O impedance status & control */
2126 u32 pordevsr; /* POR I/O device status regsiter */
67a719da
RZ		 2127#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2128#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2129#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
c916d7c9 2130#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
67a719da 2131#else
837f1ba0
ES		 2132#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2133#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
67a719da 2134#endif
837f1ba0
ES		 2135#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2136#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
8280912e 2137#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
9427ccde 2138#define MPC85xx_PORDEVSR_PCI1 0x00800000
0c955daf
DL		 2139#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2140#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2141#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
67a719da
RZ		 2142#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2143#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2144#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
0c955daf 2145#else
28747f9b
PK		 2146#if defined(CONFIG_P1010)
2147#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2148#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
35fe948e
PK		 2149#elif defined(CONFIG_BSC9132)
2150#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2151#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
3b75e982
MH		 2152#elif defined(CONFIG_PPC_C29X)
2153#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2154#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
28747f9b 2155#else
4442f45b 2156#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
6442b71b 2157#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
28747f9b 2158#endif /* if defined(CONFIG_P1010) */
0c955daf 2159#endif
53677ef1
WD		 2160#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2161#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2162#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2163#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2164#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
837f1ba0 2165#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
53677ef1 2166#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
837f1ba0 2167#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
8280912e
KG		 2168 u32 pordbgmsr; /* POR debug mode status */
2169 u32 pordevsr2; /* POR I/O device status 2 */
3b75e982
MH		 2170#if defined(CONFIG_PPC_C29X)
2171#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2172#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2173#endif
681c02d0 2174/* The 8544 RM says this is bit 26, but it's really bit 24 */
f7d190b1 2175#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
8280912e
KG		 2176 u8 res1[8];
2177 u32 gpporcr; /* General-purpose POR configuration */
2178 u8 res2[12];
ae2044d8
XX		 2179#if defined(CONFIG_MPC8536)
2180 u32 gencfgr; /* General Configuration Register */
2181#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2182#else
8280912e 2183 u32 gpiocr; /* GPIO control */
ae2044d8 2184#endif
8280912e 2185 u8 res3[12];
22b6dbc1 2186#if defined(CONFIG_MPC8569)
8280912e
KG		 2187 u32 plppar1; /* Platform port pin assignment 1 */
2188 u32 plppar2; /* Platform port pin assignment 2 */
2189 u32 plpdir1; /* Platform port pin direction 1 */
2190 u32 plpdir2; /* Platform port pin direction 2 */
22b6dbc1 2191#else
8280912e
KG		 2192 u32 gpoutdr; /* General-purpose output data */
2193 u8 res4[12];
22b6dbc1 2194#endif
8280912e
KG		 2195 u32 gpindr; /* General-purpose input data */
2196 u8 res5[12];
2197 u32 pmuxcr; /* Alt. function signal multiplex control */
4b77047c
DD		 2198#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2199#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2200#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2201#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2202#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2203#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2204#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2205#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2206#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2207#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2208#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2209#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2210#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2211#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2212#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2213#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2214#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2215#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2216#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2217#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2218#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2219#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2220#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2221#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2222#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2223#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2224#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2225#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2226#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2227#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2228#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2229#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2230#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2231#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2232#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2233#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2234#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2235#define MPC85xx_PMUXCR_SPI_RES 0x00000030
2236#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2237#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2238#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2239#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2240#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2241#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2242#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2243#endif
fe1a1da0
RZ		 2244#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2245#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2246#else
80522dc8
AF		 2247#define MPC85xx_PMUXCR_SD_DATA 0x80000000
2248#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2249#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2bad42a0 2250#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
4aa8405c 2251#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
a52d2f81
HW		 2252#define MPC85xx_PMUXCR_QE0 0x00008000
2253#define MPC85xx_PMUXCR_QE1 0x00004000
2254#define MPC85xx_PMUXCR_QE2 0x00002000
2255#define MPC85xx_PMUXCR_QE3 0x00001000
2256#define MPC85xx_PMUXCR_QE4 0x00000800
2257#define MPC85xx_PMUXCR_QE5 0x00000400
2258#define MPC85xx_PMUXCR_QE6 0x00000200
2259#define MPC85xx_PMUXCR_QE7 0x00000100
2260#define MPC85xx_PMUXCR_QE8 0x00000080
2261#define MPC85xx_PMUXCR_QE9 0x00000040
2262#define MPC85xx_PMUXCR_QE10 0x00000020
2263#define MPC85xx_PMUXCR_QE11 0x00000010
2264#define MPC85xx_PMUXCR_QE12 0x00000008
fe1a1da0 2265#endif
b93f81a4
JY		 2266#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2267#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2268#define MPC85xx_PMUXCR_TDM 0x00014800
2269#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2270#define MPC85xx_PMUXCR_SPI 0x00000000
19a8dbdc
PK		 2271#endif
2272#if defined(CONFIG_BSC9131)
2273#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2274#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2275#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2276#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2277#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2278#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2279#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2280#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2281#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2282#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2283#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2284#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2285#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2286#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2287#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2288#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2289#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2290#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2291#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2292#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2293#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2294#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2295#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2296#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2297#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2298#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2299#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2300#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2301#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2302#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2303#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2304#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2305#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2306#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2307#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2308#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2309#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2310#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2311#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2312#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2313#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2314#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
35fe948e
PK		 2315#endif
2316#ifdef CONFIG_BSC9132
2317#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2318#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
3b75e982
MH		 2319#endif
2320#if defined(CONFIG_PPC_C29X)
2321#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2322#define MPC85xx_PMUXCR_SPI 0x00000000
2323#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
b93f81a4 2324#endif
6e37a044 2325 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
4b77047c
DD		 2326#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2327#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2328#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2329#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2330#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2331#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2332#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2333#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2334#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2335#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2336#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2337#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2338#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2339#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2340#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2341#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2342#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2343#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2344#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2345#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2346#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2347#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2348#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2349#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2350#endif
b93f81a4 2351#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
aeb6716a 2352#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
b93f81a4
JY		 2353#define MPC85xx_PMUXCR2_USB 0x00150000
2354#endif
35fe948e 2355#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
19a8dbdc
PK		 2356#if defined(CONFIG_BSC9131)
2357#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2358#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2359#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2360#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2361#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2362#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2363#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2364#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2365#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2366#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2367#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2368#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2369#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2370#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2371#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2372#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2373#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2374#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2375#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2376#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2377#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2378#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2379#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2380#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2381#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2382#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2383#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2384#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2385#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2386#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2387#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2388#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2389#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2390#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2391#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2392#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2393#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2394#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2395#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2396#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2397#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2398#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
35fe948e 2399#endif
19a8dbdc 2400 u32 pmuxcr3;
35fe948e 2401#if defined(CONFIG_BSC9131)
19a8dbdc
PK		 2402#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2403#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2404#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2405#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2406#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2407#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2408#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2409#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2410#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2411#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2412#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2413#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2414#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2415#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
35fe948e
PK		 2416#endif
2417#ifdef CONFIG_BSC9132
2418#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2419#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2420#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2421#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2422#endif
19a8dbdc
PK		 2423 u32 pmuxcr4;
2424#else
6e37a044 2425 u8 res6[8];
19a8dbdc 2426#endif
8280912e 2427 u32 devdisr; /* Device disable control */
837f1ba0
ES		 2428#define MPC85xx_DEVDISR_PCI1 0x80000000
2429#define MPC85xx_DEVDISR_PCI2 0x40000000
2430#define MPC85xx_DEVDISR_PCIE 0x20000000
2431#define MPC85xx_DEVDISR_LBC 0x08000000
2432#define MPC85xx_DEVDISR_PCIE2 0x04000000
2433#define MPC85xx_DEVDISR_PCIE3 0x02000000
2434#define MPC85xx_DEVDISR_SEC 0x01000000
2435#define MPC85xx_DEVDISR_SRIO 0x00080000
2436#define MPC85xx_DEVDISR_RMSG 0x00040000
53677ef1
WD		 2437#define MPC85xx_DEVDISR_DDR 0x00010000
2438#define MPC85xx_DEVDISR_CPU 0x00008000
2439#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2440#define MPC85xx_DEVDISR_TB 0x00004000
2441#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2442#define MPC85xx_DEVDISR_CPU1 0x00002000
2443#define MPC85xx_DEVDISR_TB1 0x00001000
837f1ba0
ES		 2444#define MPC85xx_DEVDISR_DMA 0x00000400
2445#define MPC85xx_DEVDISR_TSEC1 0x00000080
2446#define MPC85xx_DEVDISR_TSEC2 0x00000040
2447#define MPC85xx_DEVDISR_TSEC3 0x00000020
2448#define MPC85xx_DEVDISR_TSEC4 0x00000010
2449#define MPC85xx_DEVDISR_I2C 0x00000004
2450#define MPC85xx_DEVDISR_DUART 0x00000002
8280912e
KG		 2451 u8 res7[12];
2452 u32 powmgtcsr; /* Power management status & control */
2453 u8 res8[12];
2454 u32 mcpsumr; /* Machine check summary */
2455 u8 res9[12];
2456 u32 pvr; /* Processor version */
2457 u32 svr; /* System version */
a52d2f81 2458 u8 res10[8];
8280912e 2459 u32 rstcr; /* Reset control */
22b6dbc1 2460#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
a52d2f81 2461 u8 res11a[76];
8280912e 2462 par_io_t qe_par_io[7];
a52d2f81 2463 u8 res11b[1600];
be7bebea 2464#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
a52d2f81
HW		 2465 u8 res11a[12];
2466 u32 iovselsr;
2467 u8 res11b[60];
2468 par_io_t qe_par_io[3];
2469 u8 res11c[1496];
c59e4091 2470#else
a52d2f81 2471 u8 res11a[1868];
c59e4091 2472#endif
6e37a044 2473 u32 clkdvdr; /* Clock Divide register */
a52d2f81 2474 u8 res12[1532];
8280912e 2475 u32 clkocr; /* Clock out select */
a52d2f81 2476 u8 res13[12];
8280912e 2477 u32 ddrdllcr; /* DDR DLL control */
a52d2f81 2478 u8 res14[12];
8280912e 2479 u32 lbcdllcr; /* LBC DLL control */
19a8dbdc
PK		 2480#if defined(CONFIG_BSC9131)
2481 u8 res15[12];
2482 u32 halt_req_mask;
2483#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2484 u8 res18[232];
2485#else
a52d2f81 2486 u8 res15[248];
19a8dbdc 2487#endif
8280912e
KG		 2488 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2489 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2490 u32 ddrioovcr; /* DDR IO Override Control */
2491 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2492 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
4aa8405c
ZC		 2493 u8 res16[52];
2494 u32 sdhcdcr; /* SDHC debug control register */
2495 u8 res17[61592];
42d1f039 2496} ccsr_gur_t;
01df5212
KG		 2497#endif
2498
4aa8405c
ZC		 2499#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2500
fd3cebd0
YS		 2501#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2502#define MAX_SERDES 4
d1001e3f
YS		 2503#define SRDS_MAX_LANES 8
2504#define SRDS_MAX_BANK 2
fd3cebd0
YS		 2505typedef struct serdes_corenet {
2506 struct {
2507 u32 rstctl; /* Reset Control Register */
2508#define SRDS_RSTCTL_RST 0x80000000
2509#define SRDS_RSTCTL_RSTDONE 0x40000000
2510#define SRDS_RSTCTL_RSTERR 0x20000000
2511#define SRDS_RSTCTL_SWRST 0x10000000
6fbe9889
SL		 2512#define SRDS_RSTCTL_SDEN 0x00000020
2513#define SRDS_RSTCTL_SDRST_B 0x00000040
2514#define SRDS_RSTCTL_PLLRST_B 0x00000080
7af9a074 2515#define SRDS_RSTCTL_RSTERR_SHIFT 29
fd3cebd0
YS		 2516 u32 pllcr0; /* PLL Control Register 0 */
2517#define SRDS_PLLCR0_POFF 0x80000000
2518#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2519#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2520#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2521#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2522#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2523#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2524#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
b6808cd8 2525#define SRDS_PLLCR0_PLL_LCK 0x00800000
7af9a074 2526#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
fd3cebd0
YS		 2527#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2528#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
b6808cd8 2529#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
fd3cebd0
YS		 2530#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2531#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2532#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
b6808cd8
SL		 2533#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2534#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2535#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
7af9a074
SL		 2536#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2537#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
fd3cebd0 2538 u32 pllcr1; /* PLL Control Register 1 */
7af9a074
SL		 2539#define SRDS_PLLCR1_BCAP_EN 0x20000000
2540#define SRDS_PLLCR1_BCAP_OVD 0x10000000
2541#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2542#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2543#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2544#define SRDS_PLLCR1_BYP_CAL 0x02000000
2545 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
2546#define SRDS_PLLSR2_BCAP_EN 0x00800000
2547#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2548#define SRDS_PLLSR2_FCAP 0x003F0000
2549#define SRDS_PLLSR2_FCAP_SHIFT 16
2550#define SRDS_PLLSR2_DCBIAS 0x000F0000
2551#define SRDS_PLLSR2_DCBIAS_SHIFT 16
fd3cebd0
YS		 2552 u32 pllcr3;
2553 u32 pllcr4;
2554 u8 res_18[0x20-0x18];
2555 } bank[2];
2556 u8 res_40[0x90-0x40];
2557 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2558 u8 res_94[0xa0-0x94];
2559 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2560 u8 res_a4[0xb0-0xa4];
2561 u32 srdsgr0; /* 0xb0 General Register 0 */
2562 u8 res_b4[0xe0-0xb4];
2563 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2564 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2565 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2566 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2567 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2568 u8 res_f4[0x100-0xf4];
2569 struct {
2570 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2571 u8 res_104[0x120-0x104];
2572 } srdslnpssr[8];
2573 u8 res_200[0x800-0x200];
2574 struct {
2575 u32 gcr0; /* 0x800 General Control Register 0 */
2576 u32 gcr1; /* 0x804 General Control Register 1 */
2577 u32 gcr2; /* 0x808 General Control Register 2 */
2578 u32 res_80c;
2579 u32 recr0; /* 0x810 Receive Equalization Control */
2580 u32 res_814;
2581 u32 tecr0; /* 0x818 Transmit Equalization Control */
2582 u32 res_81c;
2583 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2584 u8 res_824[0x840-0x824];
2585 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2586 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2587} serdes_corenet_t;
2588
2589#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2590
d1001e3f
YS		 2591#define SRDS_MAX_LANES 18
2592#define SRDS_MAX_BANK 3
11588b5d
KG		 2593typedef struct serdes_corenet {
2594 struct {
2595 u32 rstctl; /* Reset Control Register */
2596#define SRDS_RSTCTL_RST 0x80000000
2597#define SRDS_RSTCTL_RSTDONE 0x40000000
2598#define SRDS_RSTCTL_RSTERR 0x20000000
1231c498 2599#define SRDS_RSTCTL_SDPD 0x00000020
11588b5d 2600 u32 pllcr0; /* PLL Control Register 0 */
f8f85b04 2601#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
4905443f 2602#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
1231c498
KG		 2603#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2604#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2605#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
e02aea61 2606#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
f8f85b04 2607#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
1231c498
KG		 2608#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2609#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2610#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
11588b5d
KG		 2611 u32 pllcr1; /* PLL Control Register 1 */
2612#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2613 u32 res[5];
2614 } bank[3];
2615 u32 res1[12];
2616 u32 srdstcalcr; /* TX Calibration Control */
2617 u32 res2[3];
2618 u32 srdsrcalcr; /* RX Calibration Control */
2619 u32 res3[3];
2620 u32 srdsgr0; /* General Register 0 */
2621 u32 res4[11];
2622 u32 srdspccr0; /* Protocol Converter Config 0 */
2623 u32 srdspccr1; /* Protocol Converter Config 1 */
2624 u32 srdspccr2; /* Protocol Converter Config 2 */
2625#define SRDS_PCCR2_RST_XGMII1 0x00800000
2626#define SRDS_PCCR2_RST_XGMII2 0x00400000
2627 u32 res5[197];
d607b968 2628 struct serdes_lane {
11588b5d
KG		 2629 u32 gcr0; /* General Control Register 0 */
2630#define SRDS_GCR0_RRST 0x00400000
2631#define SRDS_GCR0_1STLANE 0x00010000
4905443f 2632#define SRDS_GCR0_UOTHL 0x00100000
11588b5d
KG		 2633 u32 gcr1; /* General Control Register 1 */
2634#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2635#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2636#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2637#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2638#define SRDS_GCR1_OPAD_CTL 0x04000000
2639 u32 res1[4];
2640 u32 tecr0; /* TX Equalization Control Reg 0 */
2641#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2642#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2643 u32 res3;
2644 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
df8af0b4 2645#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
b25f6de7
TT		 2646#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2647#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
f68d3063 2648#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
df8af0b4 2649#define SRDS_TTLCR0_PM_DIS 0x00004000
b25f6de7 2650#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
11588b5d
KG		 2651 u32 res4[7];
2652 } lane[24];
2653 u32 res6[384];
2654} serdes_corenet_t;
fd3cebd0 2655#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
11588b5d
KG		 2656
2657enum {
2658 FSL_SRDS_B1_LANE_A = 0,
2659 FSL_SRDS_B1_LANE_B = 1,
2660 FSL_SRDS_B1_LANE_C = 2,
2661 FSL_SRDS_B1_LANE_D = 3,
2662 FSL_SRDS_B1_LANE_E = 4,
2663 FSL_SRDS_B1_LANE_F = 5,
2664 FSL_SRDS_B1_LANE_G = 6,
2665 FSL_SRDS_B1_LANE_H = 7,
2666 FSL_SRDS_B1_LANE_I = 8,
2667 FSL_SRDS_B1_LANE_J = 9,
2668 FSL_SRDS_B2_LANE_A = 16,
2669 FSL_SRDS_B2_LANE_B = 17,
2670 FSL_SRDS_B2_LANE_C = 18,
2671 FSL_SRDS_B2_LANE_D = 19,
2672 FSL_SRDS_B3_LANE_A = 20,
2673 FSL_SRDS_B3_LANE_B = 21,
2674 FSL_SRDS_B3_LANE_C = 22,
2675 FSL_SRDS_B3_LANE_D = 23,
2676};
2677
22f292c7
KP		 2678/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2679#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2680typedef struct ccsr_sec {
9ab87d04
KG		 2681 u32 res0;
2682 u32 mcfgr; /* Master CFG Register */
2683 u8 res1[0x8];
2684 struct {
2685 u32 ms; /* Job Ring LIODN Register, MS */
2686 u32 ls; /* Job Ring LIODN Register, LS */
ed062e0f 2687 } jrliodnr[4];
9ab87d04
KG		 2688 u8 res2[0x30];
2689 struct {
2690 u32 ms; /* RTIC LIODN Register, MS */
2691 u32 ls; /* RTIC LIODN Register, LS */
2692 } rticliodnr[4];
2693 u8 res3[0x1c];
2694 u32 decorr; /* DECO Request Register */
2695 struct {
2696 u32 ms; /* DECO LIODN Register, MS */
2697 u32 ls; /* DECO LIODN Register, LS */
f311838d
AF		 2698 } decoliodnr[8];
2699 u8 res4[0x40];
9ab87d04
KG		 2700 u32 dar; /* DECO Avail Register */
2701 u32 drr; /* DECO Reset Register */
2702 u8 res5[0xe78];
22f292c7
KP		 2703 u32 crnr_ms; /* CHA Revision Number Register, MS */
2704 u32 crnr_ls; /* CHA Revision Number Register, LS */
2705 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
22f292c7 2706 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
9ab87d04 2707 u8 res6[0x10];
22f292c7
KP		 2708 u32 far_ms; /* Fault Address Register, MS */
2709 u32 far_ls; /* Fault Address Register, LS */
2710 u32 falr; /* Fault Address LIODN Register */
2711 u32 fadr; /* Fault Address Detail Register */
9ab87d04 2712 u8 res7[0x4];
22f292c7 2713 u32 csta; /* CAAM Status Register */
9ab87d04 2714 u8 res8[0x8];
22f292c7 2715 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
22f292c7
KP		 2716 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2717 u32 chavid_ms; /* CHA Version ID Register, MS */
2718 u32 chavid_ls; /* CHA Version ID Register, LS */
2719 u32 chanum_ms; /* CHA Number Register, MS */
9ab87d04
KG		 2720 u32 chanum_ls; /* CHA Number Register, LS */
2721 u32 secvid_ms; /* SEC Version ID Register, MS */
2722 u32 secvid_ls; /* SEC Version ID Register, LS */
2723 u8 res9[0x6020];
2724 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2725 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2726 u8 res10[0x8fd8];
2727} ccsr_sec_t;
2728
2729#define SEC_CTPR_MS_AXI_LIODN 0x08000000
2730#define SEC_CTPR_MS_QI 0x02000000
2731#define SEC_RVID_MA 0x0f000000
ed062e0f
KG		 2732#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2733#define SEC_CHANUM_MS_JRNUM_SHIFT 28
22f292c7
KP		 2734#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2735#define SEC_CHANUM_MS_DECONUM_SHIFT 24
5e95e2d8
VG		 2736#define SEC_SECVID_MS_IPID_MASK 0xffff0000
2737#define SEC_SECVID_MS_IPID_SHIFT 16
2738#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2739#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2740#define SEC_CCBVID_ERA_MASK 0xff000000
2741#define SEC_CCBVID_ERA_SHIFT 24
22f292c7
KP		 2742#endif
2743
9ab87d04 2744typedef struct ccsr_qman {
92230d49
YS		 2745#ifdef CONFIG_SYS_FSL_QMAN_V3
2746 u8 res0[0x200];
2747#else
9ab87d04
KG		 2748 struct {
2749 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2750 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2751 u32 res;
2752 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2753 } qcsp[32];
92230d49 2754#endif
9ab87d04
KG		 2755 /* Not actually reserved, but irrelevant to u-boot */
2756 u8 res[0xbf8 - 0x200];
2757 u32 ip_rev_1;
2758 u32 ip_rev_2;
2759 u32 fqd_bare; /* FQD Extended Base Addr Register */
2760 u32 fqd_bar; /* FQD Base Addr Register */
2761 u8 res1[0x8];
2762 u32 fqd_ar; /* FQD Attributes Register */
2763 u8 res2[0xc];
2764 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2765 u32 pfdr_bar; /* PFDR Base Addr Register */
2766 u8 res3[0x8];
2767 u32 pfdr_ar; /* PFDR Attributes Register */
2768 u8 res4[0x4c];
2769 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2770 u32 qcsp_bar; /* QCSP Base Addr Register */
2771 u8 res5[0x78];
2772 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2773 u32 srcidr; /* Source ID Register */
2774 u32 liodnr; /* LIODN Register */
2775 u8 res6[4];
2776 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2777 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2778 u8 res7[0x2e8];
92230d49
YS		 2779#ifdef CONFIG_SYS_FSL_QMAN_V3
2780 struct {
2781 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2782 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2783 u32 res;
2784 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2785 } qcsp[50];
2786#endif
9ab87d04
KG		 2787} ccsr_qman_t;
2788
2789typedef struct ccsr_bman {
2790 /* Not actually reserved, but irrelevant to u-boot */
2791 u8 res[0xbf8];
2792 u32 ip_rev_1;
2793 u32 ip_rev_2;
2794 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2795 u32 fbpr_bar; /* FBPR Base Addr Register */
2796 u8 res1[0x8];
2797 u32 fbpr_ar; /* FBPR Attributes Register */
2798 u8 res2[0xf0];
2799 u32 srcidr; /* Source ID Register */
2800 u32 liodnr; /* LIODN Register */
2801 u8 res7[0x2f4];
2802} ccsr_bman_t;
2803
2804typedef struct ccsr_pme {
2805 u8 res0[0x804];
2806 u32 liodnbr; /* LIODN Base Register */
2807 u8 res1[0x1f8];
2808 u32 srcidr; /* Source ID Register */
2809 u8 res2[8];
2810 u32 liodnr; /* LIODN Register */
2811 u8 res3[0x1e8];
2812 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2813 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2814 u8 res4[0x400];
2815} ccsr_pme_t;
2816
6b3a8d00
KG		 2817#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2818struct ccsr_raide {
2819 u8 res0[0x543];
2820 u32 liodnbr; /* LIODN Base Register */
2821 u8 res1[0xab8];
2822 struct {
2823 struct {
2824 u32 cfg0; /* cfg register 0 */
2825 u32 cfg1; /* cfg register 1 */
2826 u8 res1[0x3f8];
2827 } ring[2];
2828 u8 res[0x800];
2829 } jq[2];
2830};
2831#endif
2832
4d28db8a
KG		 2833#ifdef CONFIG_SYS_DPAA_RMAN
2834struct ccsr_rman {
2835 u8 res0[0xf64];
2836 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2837 u32 mmitar; /* RMAN Inbound Translation Address Register */
2838 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2839 u8 res4[0x1f090];
2840};
2841#endif
2842
f311838d
AF		 2843#ifdef CONFIG_SYS_PMAN
2844struct ccsr_pman {
2845 u8 res_00[0x40];
2846 u32 poes1; /* PMAN Operation Error Status Register 1 */
2847 u32 poes2; /* PMAN Operation Error Status Register 2 */
2848 u32 poeah; /* PMAN Operation Error Address High */
2849 u32 poeal; /* PMAN Operation Error Address Low */
2850 u8 res_50[0x50];
2851 u32 pr1; /* PMAN Revision Register 1 */
2852 u32 pr2; /* PMAN Revision Register 2 */
2853 u8 res_a8[0x8];
2854 u32 pcap; /* PMAN Capabilities Register */
2855 u8 res_b4[0xc];
2856 u32 pc1; /* PMAN Control Register 1 */
2857 u32 pc2; /* PMAN Control Register 2 */
2858 u32 pc3; /* PMAN Control Register 3 */
2859 u32 pc4; /* PMAN Control Register 4 */
2860 u32 pc5; /* PMAN Control Register 5 */
2861 u32 pc6; /* PMAN Control Register 6 */
2862 u8 res_d8[0x8];
2863 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2864 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2865 u8 res_e8[0x8];
2866 u32 pics; /* PMAN Interrupt Control and Status */
2867 u8 res_f4[0xf0c];
2868};
2869#endif
b6808cd8
SL		 2870#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2871struct ccsr_sfp_regs {
2872 u32 ospr; /* 0x200 */
2873 u32 reserved0[14];
2874 u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
2875 u32 oem_uid; /* 0x9c OEM Unique ID */
2876 u8 reserved2[0x04];
2877 u32 ovpr; /* 0xA4 Intent To Secure */
2878 u8 reserved4[0x08];
2879 u32 fsl_uid; /* 0xB0 FSL Unique ID */
2880 u8 reserved5[0x04];
2881 u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
2882 u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
2883};
2884#endif
f311838d 2885
01df5212
KG		 2886#ifdef CONFIG_FSL_CORENET
2887#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
f311838d
AF		 2888#ifdef CONFIG_SYS_PMAN
2889#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2890#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2891#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2892#endif
e76cd5d4
AF		 2893#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2894#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2895#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
01df5212
KG		 2896#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2897#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
b6808cd8
SL		 2898#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2899/* In SFPv3, OSPR register is now at offset 0x200.
2900 * * So directly mapping sfp register map to this address */
2901#define CONFIG_SYS_OSPR_OFFSET 0x200
2902#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2903#else
2904#define CONFIG_SYS_SFP_OFFSET 0xE8000
2905#endif
11588b5d 2906#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
4905443f 2907#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
8b0ab304 2908#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
bf4699db 2909#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
9ab87d04
KG		 2910#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2911#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
629d6b32 2912#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
9ab87d04 2913#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
01df5212
KG		 2914#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2915#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2916#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
50d96e95 2917#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
01df5212 2918#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
377ffcfa 2919#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2a44efeb 2920#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
4d28db8a 2921#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
ada961e2
LG		 2922#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2923 && !defined(CONFIG_PPC_B4420)
9e758758
YS		 2924#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2925#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2926#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2927#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2928#else
9ab87d04
KG		 2929#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2930#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2931#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2932#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
9e758758 2933#endif
9ab87d04
KG		 2934#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2935#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
86221f09
RZ		 2936#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2937#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
9ab87d04
KG		 2938#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2939#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
22f292c7 2940#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
9ab87d04 2941#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
24995d82
HW		 2942#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2943#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
6b3a8d00 2944#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
9ab87d04
KG		 2945#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2946#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2947#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2948#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2949#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2950#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
f311838d 2951#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
9ab87d04 2952#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
f311838d 2953#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
9ab87d04
KG		 2954#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2955#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2956#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2957#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2958#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2959#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2960#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
f311838d 2961#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
9ab87d04 2962#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
f311838d 2963#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
6d2b9da1 2964#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
01df5212
KG		 2965#else
2966#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
e76cd5d4 2967#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
01df5212 2968#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
e76cd5d4 2969#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
01df5212 2970#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
99d9c07e 2971#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
01df5212 2972#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
99d9c07e 2973#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
01df5212 2974#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
99d9c07e
KG		 2975#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2976#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2977#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2978#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2979#else
2980#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2981#endif
01df5212
KG		 2982#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2983#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2984#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
d789b5f5 2985#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
01df5212
KG		 2986#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2987#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
77354e9d 2988#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
9839709e 2989#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
3ad89c4e
KG		 2990#ifdef CONFIG_TSECV2
2991#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
3b75e982
MH		 2992#elif defined(CONFIG_TSECV2_1)
2993#define CONFIG_SYS_TSEC1_OFFSET 0x10000
3ad89c4e 2994#else
b9e186fc 2995#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e
KG		 2996#endif
2997#define CONFIG_SYS_MDIO1_OFFSET 0x24000
01df5212 2998#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
3b75e982
MH		 2999#if defined(CONFIG_PPC_C29X)
3000#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
3001#else
5e95e2d8 3002#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
3b75e982 3003#endif
01df5212
KG		 3004#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
3005#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
7065b7d4
RG		 3006#define CONFIG_SYS_SNVS_OFFSET 0xE6000
3007#define CONFIG_SYS_SFP_OFFSET 0xE7000
01df5212 3008#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
67a719da
RZ		 3009#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
3010#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
3011#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
3012#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
3013#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
3014#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
01df5212
KG		 3015#endif
3016
3017#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
3018#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
5ffa88ec 3019#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
42d1f039 3020
f9d379a7
PJ		 3021#if defined(CONFIG_BSC9132)
3022#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
3023#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
3024 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
3025#endif
3026
8b0ab304
BB		 3027#define CONFIG_SYS_FSL_CPC_ADDR \
3028 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
bf4699db
PJ		 3029#define CONFIG_SYS_FSL_SCFG_ADDR \
3030 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
3031#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
3032 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
24995d82
HW		 3033#define CONFIG_SYS_FSL_QMAN_ADDR \
3034 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3035#define CONFIG_SYS_FSL_BMAN_ADDR \
3036 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
9ab87d04
KG		 3037#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3038 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
6b3a8d00
KG		 3039#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3040 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
4d28db8a
KG		 3041#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3042 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
8280912e
KG		 3043#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3044 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3045#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3046 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3047#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3048 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3049#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3050 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3051#define CONFIG_SYS_MPC85xx_ECM_ADDR \
3052 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
5614e71b 3053#define CONFIG_SYS_FSL_DDR_ADDR \
e76cd5d4 3054 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
5614e71b 3055#define CONFIG_SYS_FSL_DDR2_ADDR \
e76cd5d4 3056 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
5614e71b 3057#define CONFIG_SYS_FSL_DDR3_ADDR \
e76cd5d4 3058 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
f51cdaf1 3059#define CONFIG_SYS_LBC_ADDR \
8280912e 3060 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
d789b5f5
DD		 3061#define CONFIG_SYS_IFC_ADDR \
3062 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
8280912e
KG		 3063#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3064 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3065#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3066 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3067#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3068 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3069#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3070 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3071#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3072 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3073#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3074 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3075#define CONFIG_SYS_MPC85xx_L2_ADDR \
3076 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3077#define CONFIG_SYS_MPC85xx_DMA_ADDR \
3078 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3079#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3080 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
680c613a 3081#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
8280912e
KG		 3082 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3083#define CONFIG_SYS_MPC85xx_CPM_ADDR \
3084 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3085#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
17028be2 3086 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
8280912e
KG		 3087#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3088 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
11588b5d
KG		 3089#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3090 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
4905443f
TT		 3091#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3092 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
77354e9d 3093#define CONFIG_SYS_MPC85xx_USB1_ADDR \
3094 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3095#define CONFIG_SYS_MPC85xx_USB2_ADDR \
3096 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
86221f09
RZ		 3097#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3098 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3099#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3100 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
22f292c7
KP		 3101#define CONFIG_SYS_FSL_SEC_ADDR \
3102 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
9ab87d04
KG		 3103#define CONFIG_SYS_FSL_FM1_ADDR \
3104 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3105#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3106 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3107#define CONFIG_SYS_FSL_FM2_ADDR \
3108 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
5ffa88ec
LG		 3109#define CONFIG_SYS_FSL_SRIO_ADDR \
3110 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
aafeefbd 3111
99d9c07e
KG		 3112#define CONFIG_SYS_PCI1_ADDR \
3113 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3114#define CONFIG_SYS_PCI2_ADDR \
3115 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3116#define CONFIG_SYS_PCIE1_ADDR \
3117 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3118#define CONFIG_SYS_PCIE2_ADDR \
3119 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3120#define CONFIG_SYS_PCIE3_ADDR \
3121 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
9ab87d04
KG		 3122#define CONFIG_SYS_PCIE4_ADDR \
3123 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
99d9c07e 3124
b6808cd8
SL		 3125#define CONFIG_SYS_SFP_ADDR \
3126 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
3127
b9e186fc
SG		 3128#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3129#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3130
6d2b9da1
YS		 3131#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3132struct ccsr_cluster_l2 {
3133 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3134 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3135 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3136 u8 res_0c[500];/* 0x00c - 0x1ff */
3137 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3138 u8 res_204[4];
3139 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3140 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3141 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3142 u8 res_214[4];
3143 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3144 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3145 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3146 u8 res_224[4];
3147 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3148 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3149 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3150 u8 res_234[4];
3151 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3152 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3153 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3154 u8 res244[4];
3155 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3156 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3157 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3158 u8 res_254[4];
3159 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3160 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3161 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3162 u8 res_264[4];
3163 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3164 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3165 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3166 u8 res274[4];
3167 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3168 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3169 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3170 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3171 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3172 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3173 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3174 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3175 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3176 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3177 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3178 u32 l2errdet; /* 0xe40 L2 cache error detect */
3179 u32 l2errdis; /* 0xe44 L2 cache error disable */
3180 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3181 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3182 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3183 u32 l2erraddr; /* 0xe54 L2 cache error address */
3184 u32 l2errctl; /* 0xe58 L2 cache error control */
3185};
3186#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3187 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3188#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
99d7b0a4
X		 3189
3190#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3191struct dcsr_dcfg_regs {
3192 u8 res_0[0x520];
3193 u32 ecccr1;
3194#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3195#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3196 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3197};
5aef4c86
TY		 3198
3199#define CONFIG_SYS_MPC85xx_SCFG \
3200 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
3201#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3202/* The supplement configuration unit register */
3203struct ccsr_scfg {
3204 u32 dpslpcr; /* 0x000 Deep Sleep Control register */
3205 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
3206 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
3207 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
3208 u32 res1[4];
3209 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
3210 u32 res2;
3211 u32 pixclkcr; /* 0x028 Pixel Clock Control register */
3212 u32 res3[245];
3213 u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
3214 u32 emiiocr; /* 0x404 EMI MDIO Control Register */
3215 u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
3216 u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
3217 u32 res4[60];
3218 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
3219};
42d1f039 3220#endif /*__IMMAP_85xx__*/
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