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powerpc/85xx: Enable support for ATI graphics cards on P1022DS
[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h
CommitLineData
42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
1d2c2a62 4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
837f1ba0 5 *
42d1f039
WD		 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
11588b5d
KG		 9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
42d1f039
WD		 26 */
27
28#ifndef __IMMAP_85xx__
29#define __IMMAP_85xx__
30
3dfa9cfd 31#include <asm/types.h>
b1f12650 32#include <asm/fsl_dma.h>
3dfa9cfd 33#include <asm/fsl_i2c.h>
d789b5f5 34#include <asm/fsl_ifc.h>
4e190b03 35#include <asm/fsl_lbc.h>
ebd7cb0b 36#include <asm/fsl_fman.h>
3dfa9cfd 37
01df5212 38typedef struct ccsr_local {
8280912e
KG		 39 u32 ccsrbarh; /* CCSR Base Addr High */
40 u32 ccsrbarl; /* CCSR Base Addr Low */
41 u32 ccsrar; /* CCSR Attr */
01df5212
KG		 42#define CCSRAR_C 0x80000000 /* Commit */
43 u8 res1[4];
8280912e
KG		 44 u32 altcbarh; /* Alternate Configuration Base Addr High */
45 u32 altcbarl; /* Alternate Configuration Base Addr Low */
46 u32 altcar; /* Alternate Configuration Attr */
01df5212 47 u8 res2[4];
8280912e
KG		 48 u32 bstrh; /* Boot space translation high */
49 u32 bstrl; /* Boot space translation Low */
50 u32 bstrar; /* Boot space translation attributes */
01df5212
KG		 51 u8 res3[0xbd4];
52 struct {
8280912e
KG		 53 u32 lawbarh; /* LAWn base addr high */
54 u32 lawbarl; /* LAWn base addr low */
55 u32 lawar; /* LAWn attributes */
01df5212
KG		 56 u8 res4[4];
57 } law[32];
58 u8 res35[0x204];
59} ccsr_local_t;
60
8280912e 61/* Local-Access Registers & ECM Registers */
42d1f039 62typedef struct ccsr_local_ecm {
8280912e
KG		 63 u32 ccsrbar; /* CCSR Base Addr */
64 u8 res1[4];
65 u32 altcbar; /* Alternate Configuration Base Addr */
66 u8 res2[4];
67 u32 altcar; /* Alternate Configuration Attr */
68 u8 res3[12];
69 u32 bptr; /* Boot Page Translation */
70 u8 res4[3044];
71 u32 lawbar0; /* Local Access Window 0 Base Addr */
72 u8 res5[4];
73 u32 lawar0; /* Local Access Window 0 Attrs */
74 u8 res6[20];
75 u32 lawbar1; /* Local Access Window 1 Base Addr */
76 u8 res7[4];
77 u32 lawar1; /* Local Access Window 1 Attrs */
78 u8 res8[20];
79 u32 lawbar2; /* Local Access Window 2 Base Addr */
80 u8 res9[4];
81 u32 lawar2; /* Local Access Window 2 Attrs */
82 u8 res10[20];
83 u32 lawbar3; /* Local Access Window 3 Base Addr */
84 u8 res11[4];
85 u32 lawar3; /* Local Access Window 3 Attrs */
86 u8 res12[20];
87 u32 lawbar4; /* Local Access Window 4 Base Addr */
88 u8 res13[4];
89 u32 lawar4; /* Local Access Window 4 Attrs */
90 u8 res14[20];
91 u32 lawbar5; /* Local Access Window 5 Base Addr */
92 u8 res15[4];
93 u32 lawar5; /* Local Access Window 5 Attrs */
94 u8 res16[20];
95 u32 lawbar6; /* Local Access Window 6 Base Addr */
96 u8 res17[4];
97 u32 lawar6; /* Local Access Window 6 Attrs */
98 u8 res18[20];
99 u32 lawbar7; /* Local Access Window 7 Base Addr */
100 u8 res19[4];
101 u32 lawar7; /* Local Access Window 7 Attrs */
102 u8 res19_8a[20];
103 u32 lawbar8; /* Local Access Window 8 Base Addr */
104 u8 res19_8b[4];
105 u32 lawar8; /* Local Access Window 8 Attrs */
106 u8 res19_9a[20];
107 u32 lawbar9; /* Local Access Window 9 Base Addr */
108 u8 res19_9b[4];
109 u32 lawar9; /* Local Access Window 9 Attrs */
110 u8 res19_10a[20];
111 u32 lawbar10; /* Local Access Window 10 Base Addr */
112 u8 res19_10b[4];
113 u32 lawar10; /* Local Access Window 10 Attrs */
114 u8 res19_11a[20];
115 u32 lawbar11; /* Local Access Window 11 Base Addr */
116 u8 res19_11b[4];
117 u32 lawar11; /* Local Access Window 11 Attrs */
118 u8 res20[652];
119 u32 eebacr; /* ECM CCB Addr Configuration */
120 u8 res21[12];
121 u32 eebpcr; /* ECM CCB Port Configuration */
122 u8 res22[3564];
123 u32 eedr; /* ECM Error Detect */
124 u8 res23[4];
125 u32 eeer; /* ECM Error Enable */
126 u32 eeatr; /* ECM Error Attrs Capture */
127 u32 eeadr; /* ECM Error Addr Capture */
128 u8 res24[492];
42d1f039
WD		 129} ccsr_local_ecm_t;
130
8280912e 131/* DDR memory controller registers */
42d1f039 132typedef struct ccsr_ddr {
8280912e
KG		 133 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
134 u8 res1[4];
135 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
136 u8 res2[4];
137 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
138 u8 res3[4];
139 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
140 u8 res4[100];
141 u32 cs0_config; /* Chip Select Configuration */
142 u32 cs1_config; /* Chip Select Configuration */
143 u32 cs2_config; /* Chip Select Configuration */
144 u32 cs3_config; /* Chip Select Configuration */
145 u8 res4a[48];
146 u32 cs0_config_2; /* Chip Select Configuration 2 */
147 u32 cs1_config_2; /* Chip Select Configuration 2 */
148 u32 cs2_config_2; /* Chip Select Configuration 2 */
149 u32 cs3_config_2; /* Chip Select Configuration 2 */
150 u8 res5[48];
151 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
152 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
153 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
154 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
155 u32 sdram_cfg; /* SDRAM Control Configuration */
156 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
157 u32 sdram_mode; /* SDRAM Mode Configuration */
158 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
159 u32 sdram_md_cntl; /* SDRAM Mode Control */
160 u32 sdram_interval; /* SDRAM Interval Configuration */
161 u32 sdram_data_init; /* SDRAM Data initialization */
162 u8 res6[4];
163 u32 sdram_clk_cntl; /* SDRAM Clock Control */
164 u8 res7[20];
165 u32 init_addr; /* training init addr */
166 u32 init_ext_addr; /* training init extended addr */
167 u8 res8_1[16];
168 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
169 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
170 u8 reg8_1a[8];
171 u32 ddr_zq_cntl; /* ZQ calibration control*/
172 u32 ddr_wrlvl_cntl; /* write leveling control*/
173 u8 reg8_1aa[4];
174 u32 ddr_sr_cntr; /* self refresh counter */
175 u32 ddr_sdram_rcw_1; /* Control Words 1 */
176 u32 ddr_sdram_rcw_2; /* Control Words 2 */
9ab87d04
KG		 177 u8 reg_1ab[8];
178 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
179 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
180 u8 res8_1b[104];
181 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
182 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
183 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
184 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
185 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
186 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
187 u8 res8_1ba[0x908];
8280912e
KG		 188 u32 ddr_dsr1; /* Debug Status 1 */
189 u32 ddr_dsr2; /* Debug Status 2 */
190 u32 ddr_cdr1; /* Control Driver 1 */
191 u32 ddr_cdr2; /* Control Driver 2 */
192 u8 res8_1c[200];
193 u32 ip_rev1; /* IP Block Revision 1 */
194 u32 ip_rev2; /* IP Block Revision 2 */
9ab87d04
KG		 195 u32 eor; /* Enhanced Optimization Register */
196 u8 res8_2[252];
197 u32 mtcr; /* Memory Test Control Register */
198 u8 res8_3[28];
199 u32 mtp1; /* Memory Test Pattern 1 */
200 u32 mtp2; /* Memory Test Pattern 2 */
201 u32 mtp3; /* Memory Test Pattern 3 */
202 u32 mtp4; /* Memory Test Pattern 4 */
203 u32 mtp5; /* Memory Test Pattern 5 */
204 u32 mtp6; /* Memory Test Pattern 6 */
205 u32 mtp7; /* Memory Test Pattern 7 */
206 u32 mtp8; /* Memory Test Pattern 8 */
207 u32 mtp9; /* Memory Test Pattern 9 */
208 u32 mtp10; /* Memory Test Pattern 10 */
209 u8 res8_4[184];
8280912e
KG		 210 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
211 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
212 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
213 u8 res9[20];
214 u32 capture_data_hi; /* Data Path Read Capture High */
215 u32 capture_data_lo; /* Data Path Read Capture Low */
216 u32 capture_ecc; /* Data Path Read Capture ECC */
217 u8 res10[20];
218 u32 err_detect; /* Error Detect */
219 u32 err_disable; /* Error Disable */
220 u32 err_int_en;
221 u32 capture_attributes; /* Error Attrs Capture */
222 u32 capture_address; /* Error Addr Capture */
223 u32 capture_ext_address; /* Error Extended Addr Capture */
224 u32 err_sbe; /* Single-Bit ECC Error Management */
225 u8 res11[164];
d2a9568c
YS		 226 u32 debug[32]; /* debug_1 to debug_32 */
227 u8 res12[128];
42d1f039
WD		 228} ccsr_ddr_t;
229
9ab87d04
KG		 230#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
231#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
232
8280912e 233/* I2C Registers */
42d1f039 234typedef struct ccsr_i2c {
3dfa9cfd
JL		 235 struct fsl_i2c i2c[1];
236 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
42d1f039
WD		 237} ccsr_i2c_t;
238
03f5c550
WD		 239#if defined(CONFIG_MPC8540) \
240 || defined(CONFIG_MPC8541) \
d9b94f28 241 || defined(CONFIG_MPC8548) \
03f5c550 242 || defined(CONFIG_MPC8555)
8280912e 243/* DUART Registers */
42d1f039 244typedef struct ccsr_duart {
8280912e
KG		 245 u8 res1[1280];
246/* URBR1, UTHR1, UDLB1 with the same addr */
247 u8 urbr1_uthr1_udlb1;
248/* UIER1, UDMB1 with the same addr01 */
249 u8 uier1_udmb1;
250/* UIIR1, UFCR1, UAFR1 with the same addr */
251 u8 uiir1_ufcr1_uafr1;
252 u8 ulcr1; /* UART1 Line Control */
253 u8 umcr1; /* UART1 Modem Control */
254 u8 ulsr1; /* UART1 Line Status */
255 u8 umsr1; /* UART1 Modem Status */
256 u8 uscr1; /* UART1 Scratch */
257 u8 res2[8];
258 u8 udsr1; /* UART1 DMA Status */
259 u8 res3[239];
260/* URBR2, UTHR2, UDLB2 with the same addr */
261 u8 urbr2_uthr2_udlb2;
262/* UIER2, UDMB2 with the same addr */
263 u8 uier2_udmb2;
264/* UIIR2, UFCR2, UAFR2 with the same addr */
265 u8 uiir2_ufcr2_uafr2;
266 u8 ulcr2; /* UART2 Line Control */
267 u8 umcr2; /* UART2 Modem Control */
268 u8 ulsr2; /* UART2 Line Status */
269 u8 umsr2; /* UART2 Modem Status */
270 u8 uscr2; /* UART2 Scratch */
271 u8 res4[8];
272 u8 udsr2; /* UART2 DMA Status */
273 u8 res5[2543];
42d1f039
WD		 274} ccsr_duart_t;
275#else /* MPC8560 uses UART on its CPM */
276typedef struct ccsr_duart {
8280912e 277 u8 res[4096];
42d1f039
WD		 278} ccsr_duart_t;
279#endif
280
8280912e 281/* eSPI Registers */
7fa96a9a 282typedef struct ccsr_espi {
8280912e
KG		 283 u32 mode; /* eSPI mode */
284 u32 event; /* eSPI event */
285 u32 mask; /* eSPI mask */
286 u32 com; /* eSPI command */
287 u32 tx; /* eSPI transmit FIFO access */
288 u32 rx; /* eSPI receive FIFO access */
289 u8 res1[8]; /* reserved */
290 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
291 u8 res2[4048]; /* fill up to 0x1000 */
7fa96a9a
MH		 292} ccsr_espi_t;
293
8280912e 294/* PCI Registers */
42d1f039 295typedef struct ccsr_pcix {
8280912e
KG		 296 u32 cfg_addr; /* PCIX Configuration Addr */
297 u32 cfg_data; /* PCIX Configuration Data */
298 u32 int_ack; /* PCIX IRQ Acknowledge */
299 u8 res1[3060];
300 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
301 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
302 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
303 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
304 u32 powar0; /* PCIX Outbound Window Attrs 0 */
305 u8 res2[12];
306 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
307 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
308 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
309 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
310 u32 powar1; /* PCIX Outbound Window Attrs 1 */
311 u8 res3[12];
312 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
313 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
314 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
315 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
316 u32 powar2; /* PCIX Outbound Window Attrs 2 */
317 u8 res4[12];
318 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
319 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
320 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
321 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
322 u32 powar3; /* PCIX Outbound Window Attrs 3 */
323 u8 res5[12];
324 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
325 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
326 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
327 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
328 u32 powar4; /* PCIX Outbound Window Attrs 4 */
329 u8 res6[268];
330 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
331 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
332 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
333 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
334 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
335 u8 res7[12];
336 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
337 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
338 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
339 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
340 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
341 u8 res8[12];
342 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
343 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
344 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
345 u8 res9[4];
346 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
347 u8 res10[12];
348 u32 pedr; /* PCIX Error Detect */
349 u32 pecdr; /* PCIX Error Capture Disable */
350 u32 peer; /* PCIX Error Enable */
351 u32 peattrcr; /* PCIX Error Attrs Capture */
352 u32 peaddrcr; /* PCIX Error Addr Capture */
353 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
354 u32 pedlcr; /* PCIX Error Data Low Capture */
355 u32 pedhcr; /* PCIX Error Error Data High Capture */
356 u32 gas_timr; /* PCIX Gasket Timer */
357 u8 res11[476];
42d1f039
WD		 358} ccsr_pcix_t;
359
97074ed9
MM		 360#define PCIX_COMMAND 0x62
361#define POWAR_EN 0x80000000
362#define POWAR_IO_READ 0x00080000
363#define POWAR_MEM_READ 0x00040000
364#define POWAR_IO_WRITE 0x00008000
365#define POWAR_MEM_WRITE 0x00004000
366#define POWAR_MEM_512M 0x0000001c
367#define POWAR_IO_1M 0x00000013
368
369#define PIWAR_EN 0x80000000
370#define PIWAR_PF 0x20000000
371#define PIWAR_LOCAL 0x00f00000
372#define PIWAR_READ_SNOOP 0x00050000
373#define PIWAR_WRITE_SNOOP 0x00005000
374#define PIWAR_MEM_2G 0x0000001e
375
8280912e
KG		 376typedef struct ccsr_gpio {
377 u32 gpdir;
378 u32 gpodr;
379 u32 gpdat;
380 u32 gpier;
381 u32 gpimr;
382 u32 gpicr;
383} ccsr_gpio_t;
97074ed9 384
8280912e 385/* L2 Cache Registers */
42d1f039 386typedef struct ccsr_l2cache {
8280912e
KG		 387 u32 l2ctl; /* L2 configuration 0 */
388 u8 res1[12];
389 u32 l2cewar0; /* L2 cache external write addr 0 */
390 u8 res2[4];
391 u32 l2cewcr0; /* L2 cache external write control 0 */
392 u8 res3[4];
393 u32 l2cewar1; /* L2 cache external write addr 1 */
394 u8 res4[4];
395 u32 l2cewcr1; /* L2 cache external write control 1 */
396 u8 res5[4];
397 u32 l2cewar2; /* L2 cache external write addr 2 */
398 u8 res6[4];
399 u32 l2cewcr2; /* L2 cache external write control 2 */
400 u8 res7[4];
401 u32 l2cewar3; /* L2 cache external write addr 3 */
402 u8 res8[4];
403 u32 l2cewcr3; /* L2 cache external write control 3 */
404 u8 res9[180];
405 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
406 u8 res10[4];
407 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
408 u8 res11[3316];
409 u32 l2errinjhi; /* L2 error injection mask high */
410 u32 l2errinjlo; /* L2 error injection mask low */
411 u32 l2errinjctl; /* L2 error injection tag/ECC control */
412 u8 res12[20];
413 u32 l2captdatahi; /* L2 error data high capture */
414 u32 l2captdatalo; /* L2 error data low capture */
415 u32 l2captecc; /* L2 error ECC capture */
416 u8 res13[20];
417 u32 l2errdet; /* L2 error detect */
418 u32 l2errdis; /* L2 error disable */
419 u32 l2errinten; /* L2 error interrupt enable */
420 u32 l2errattr; /* L2 error attributes capture */
421 u32 l2erraddr; /* L2 error addr capture */
422 u8 res14[4];
423 u32 l2errctl; /* L2 error control */
424 u8 res15[420];
42d1f039
WD		 425} ccsr_l2cache_t;
426
76b474e2
MH		 427#define MPC85xx_L2CTL_L2E 0x80000000
428#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
429#define MPC85xx_L2ERRDIS_MBECC 0x00000008
430#define MPC85xx_L2ERRDIS_SBECC 0x00000004
431
8280912e 432/* DMA Registers */
42d1f039 433typedef struct ccsr_dma {
8280912e 434 u8 res1[256];
b1f12650 435 struct fsl_dma dma[4];
8280912e
KG		 436 u32 dgsr; /* DMA General Status */
437 u8 res2[11516];
42d1f039
WD		 438} ccsr_dma_t;
439
8280912e 440/* tsec */
42d1f039 441typedef struct ccsr_tsec {
8280912e
KG		 442 u8 res1[16];
443 u32 ievent; /* IRQ Event */
444 u32 imask; /* IRQ Mask */
445 u32 edis; /* Error Disabled */
446 u8 res2[4];
447 u32 ecntrl; /* Ethernet Control */
448 u32 minflr; /* Minimum Frame Len */
449 u32 ptv; /* Pause Time Value */
450 u32 dmactrl; /* DMA Control */
451 u32 tbipa; /* TBI PHY Addr */
452 u8 res3[88];
453 u32 fifo_tx_thr; /* FIFO transmit threshold */
454 u8 res4[8];
455 u32 fifo_tx_starve; /* FIFO transmit starve */
456 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
457 u8 res5[96];
458 u32 tctrl; /* TX Control */
459 u32 tstat; /* TX Status */
460 u8 res6[4];
461 u32 tbdlen; /* TX Buffer Desc Data Len */
462 u8 res7[16];
463 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
464 u32 ctbptr; /* Current TX Buffer Desc Ptr */
465 u8 res8[88];
466 u32 tbptrh; /* TX Buffer Desc Ptr High */
467 u32 tbptr; /* TX Buffer Desc Ptr Low */
468 u8 res9[120];
469 u32 tbaseh; /* TX Desc Base Addr High */
470 u32 tbase; /* TX Desc Base Addr */
471 u8 res10[168];
472 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
473 u32 ostbdp; /* OOS TX Data Buffer Ptr */
474 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
475 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
476 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
477 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
478 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
479 u8 res11[52];
480 u32 rctrl; /* RX Control */
481 u32 rstat; /* RX Status */
482 u8 res12[4];
483 u32 rbdlen; /* RxBD Data Len */
484 u8 res13[16];
485 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
486 u32 crbptr; /* Current RX Buffer Desc Ptr */
487 u8 res14[24];
488 u32 mrblr; /* Maximum RX Buffer Len */
489 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
490 u8 res15[56];
491 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
492 u32 rbptr; /* RX Buffer Desc Ptr */
493 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
494 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
495 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
496 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
497 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
498 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
499 u8 res16[96];
500 u32 rbaseh; /* RX Desc Base Addr High 0 */
501 u32 rbase; /* RX Desc Base Addr */
502 u32 rbaseh1; /* RX Desc Base Addr High 1 */
503 u32 rbasel1; /* RX Desc Base Addr Low 1 */
504 u32 rbaseh2; /* RX Desc Base Addr High 2 */
505 u32 rbasel2; /* RX Desc Base Addr Low 2 */
506 u32 rbaseh3; /* RX Desc Base Addr High 3 */
507 u32 rbasel3; /* RX Desc Base Addr Low 3 */
508 u8 res17[224];
509 u32 maccfg1; /* MAC Configuration 1 */
510 u32 maccfg2; /* MAC Configuration 2 */
511 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
512 u32 hafdup; /* Half Duplex */
513 u32 maxfrm; /* Maximum Frame Len */
514 u8 res18[12];
515 u32 miimcfg; /* MII Management Configuration */
516 u32 miimcom; /* MII Management Cmd */
517 u32 miimadd; /* MII Management Addr */
518 u32 miimcon; /* MII Management Control */
519 u32 miimstat; /* MII Management Status */
520 u32 miimind; /* MII Management Indicator */
521 u8 res19[4];
522 u32 ifstat; /* Interface Status */
523 u32 macstnaddr1; /* Station Addr Part 1 */
524 u32 macstnaddr2; /* Station Addr Part 2 */
525 u8 res20[312];
526 u32 tr64; /* TX & RX 64-byte Frame Counter */
527 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
528 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
529 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
530 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
531 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
532 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
533 u32 rbyt; /* RX Byte Counter */
534 u32 rpkt; /* RX Packet Counter */
535 u32 rfcs; /* RX FCS Error Counter */
536 u32 rmca; /* RX Multicast Packet Counter */
537 u32 rbca; /* RX Broadcast Packet Counter */
538 u32 rxcf; /* RX Control Frame Packet Counter */
539 u32 rxpf; /* RX Pause Frame Packet Counter */
540 u32 rxuo; /* RX Unknown OP Code Counter */
541 u32 raln; /* RX Alignment Error Counter */
542 u32 rflr; /* RX Frame Len Error Counter */
543 u32 rcde; /* RX Code Error Counter */
544 u32 rcse; /* RX Carrier Sense Error Counter */
545 u32 rund; /* RX Undersize Packet Counter */
546 u32 rovr; /* RX Oversize Packet Counter */
547 u32 rfrg; /* RX Fragments Counter */
548 u32 rjbr; /* RX Jabber Counter */
549 u32 rdrp; /* RX Drop Counter */
550 u32 tbyt; /* TX Byte Counter Counter */
551 u32 tpkt; /* TX Packet Counter */
552 u32 tmca; /* TX Multicast Packet Counter */
553 u32 tbca; /* TX Broadcast Packet Counter */
554 u32 txpf; /* TX Pause Control Frame Counter */
555 u32 tdfr; /* TX Deferral Packet Counter */
556 u32 tedf; /* TX Excessive Deferral Packet Counter */
557 u32 tscl; /* TX Single Collision Packet Counter */
558 u32 tmcl; /* TX Multiple Collision Packet Counter */
559 u32 tlcl; /* TX Late Collision Packet Counter */
560 u32 txcl; /* TX Excessive Collision Packet Counter */
561 u32 tncl; /* TX Total Collision Counter */
562 u8 res21[4];
563 u32 tdrp; /* TX Drop Frame Counter */
564 u32 tjbr; /* TX Jabber Frame Counter */
565 u32 tfcs; /* TX FCS Error Counter */
566 u32 txcf; /* TX Control Frame Counter */
567 u32 tovr; /* TX Oversize Frame Counter */
568 u32 tund; /* TX Undersize Frame Counter */
569 u32 tfrg; /* TX Fragments Frame Counter */
570 u32 car1; /* Carry One */
571 u32 car2; /* Carry Two */
572 u32 cam1; /* Carry Mask One */
573 u32 cam2; /* Carry Mask Two */
574 u8 res22[192];
575 u32 iaddr0; /* Indivdual addr 0 */
576 u32 iaddr1; /* Indivdual addr 1 */
577 u32 iaddr2; /* Indivdual addr 2 */
578 u32 iaddr3; /* Indivdual addr 3 */
579 u32 iaddr4; /* Indivdual addr 4 */
580 u32 iaddr5; /* Indivdual addr 5 */
581 u32 iaddr6; /* Indivdual addr 6 */
582 u32 iaddr7; /* Indivdual addr 7 */
583 u8 res23[96];
584 u32 gaddr0; /* Global addr 0 */
585 u32 gaddr1; /* Global addr 1 */
586 u32 gaddr2; /* Global addr 2 */
587 u32 gaddr3; /* Global addr 3 */
588 u32 gaddr4; /* Global addr 4 */
589 u32 gaddr5; /* Global addr 5 */
590 u32 gaddr6; /* Global addr 6 */
591 u32 gaddr7; /* Global addr 7 */
592 u8 res24[96];
593 u32 pmd0; /* Pattern Match Data */
594 u8 res25[4];
595 u32 pmask0; /* Pattern Mask */
596 u8 res26[4];
597 u32 pcntrl0; /* Pattern Match Control */
598 u8 res27[4];
599 u32 pattrb0; /* Pattern Match Attrs */
600 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
601 u32 pmd1; /* Pattern Match Data */
602 u8 res28[4];
603 u32 pmask1; /* Pattern Mask */
604 u8 res29[4];
605 u32 pcntrl1; /* Pattern Match Control */
606 u8 res30[4];
607 u32 pattrb1; /* Pattern Match Attrs */
608 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
609 u32 pmd2; /* Pattern Match Data */
610 u8 res31[4];
611 u32 pmask2; /* Pattern Mask */
612 u8 res32[4];
613 u32 pcntrl2; /* Pattern Match Control */
614 u8 res33[4];
615 u32 pattrb2; /* Pattern Match Attrs */
616 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
617 u32 pmd3; /* Pattern Match Data */
618 u8 res34[4];
619 u32 pmask3; /* Pattern Mask */
620 u8 res35[4];
621 u32 pcntrl3; /* Pattern Match Control */
622 u8 res36[4];
623 u32 pattrb3; /* Pattern Match Attrs */
624 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
625 u32 pmd4; /* Pattern Match Data */
626 u8 res37[4];
627 u32 pmask4; /* Pattern Mask */
628 u8 res38[4];
629 u32 pcntrl4; /* Pattern Match Control */
630 u8 res39[4];
631 u32 pattrb4; /* Pattern Match Attrs */
632 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
633 u32 pmd5; /* Pattern Match Data */
634 u8 res40[4];
635 u32 pmask5; /* Pattern Mask */
636 u8 res41[4];
637 u32 pcntrl5; /* Pattern Match Control */
638 u8 res42[4];
639 u32 pattrb5; /* Pattern Match Attrs */
640 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
641 u32 pmd6; /* Pattern Match Data */
642 u8 res43[4];
643 u32 pmask6; /* Pattern Mask */
644 u8 res44[4];
645 u32 pcntrl6; /* Pattern Match Control */
646 u8 res45[4];
647 u32 pattrb6; /* Pattern Match Attrs */
648 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
649 u32 pmd7; /* Pattern Match Data */
650 u8 res46[4];
651 u32 pmask7; /* Pattern Mask */
652 u8 res47[4];
653 u32 pcntrl7; /* Pattern Match Control */
654 u8 res48[4];
655 u32 pattrb7; /* Pattern Match Attrs */
656 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
657 u32 pmd8; /* Pattern Match Data */
658 u8 res49[4];
659 u32 pmask8; /* Pattern Mask */
660 u8 res50[4];
661 u32 pcntrl8; /* Pattern Match Control */
662 u8 res51[4];
663 u32 pattrb8; /* Pattern Match Attrs */
664 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
665 u32 pmd9; /* Pattern Match Data */
666 u8 res52[4];
667 u32 pmask9; /* Pattern Mask */
668 u8 res53[4];
669 u32 pcntrl9; /* Pattern Match Control */
670 u8 res54[4];
671 u32 pattrb9; /* Pattern Match Attrs */
672 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
673 u32 pmd10; /* Pattern Match Data */
674 u8 res55[4];
675 u32 pmask10; /* Pattern Mask */
676 u8 res56[4];
677 u32 pcntrl10; /* Pattern Match Control */
678 u8 res57[4];
679 u32 pattrb10; /* Pattern Match Attrs */
680 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
681 u32 pmd11; /* Pattern Match Data */
682 u8 res58[4];
683 u32 pmask11; /* Pattern Mask */
684 u8 res59[4];
685 u32 pcntrl11; /* Pattern Match Control */
686 u8 res60[4];
687 u32 pattrb11; /* Pattern Match Attrs */
688 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
689 u32 pmd12; /* Pattern Match Data */
690 u8 res61[4];
691 u32 pmask12; /* Pattern Mask */
692 u8 res62[4];
693 u32 pcntrl12; /* Pattern Match Control */
694 u8 res63[4];
695 u32 pattrb12; /* Pattern Match Attrs */
696 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
697 u32 pmd13; /* Pattern Match Data */
698 u8 res64[4];
699 u32 pmask13; /* Pattern Mask */
700 u8 res65[4];
701 u32 pcntrl13; /* Pattern Match Control */
702 u8 res66[4];
703 u32 pattrb13; /* Pattern Match Attrs */
704 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
705 u32 pmd14; /* Pattern Match Data */
706 u8 res67[4];
707 u32 pmask14; /* Pattern Mask */
708 u8 res68[4];
709 u32 pcntrl14; /* Pattern Match Control */
710 u8 res69[4];
711 u32 pattrb14; /* Pattern Match Attrs */
712 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
713 u32 pmd15; /* Pattern Match Data */
714 u8 res70[4];
715 u32 pmask15; /* Pattern Mask */
716 u8 res71[4];
717 u32 pcntrl15; /* Pattern Match Control */
718 u8 res72[4];
719 u32 pattrb15; /* Pattern Match Attrs */
720 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
721 u8 res73[248];
722 u32 attr; /* Attrs */
723 u32 attreli; /* Attrs Extract Len & Idx */
724 u8 res74[1024];
42d1f039
WD		 725} ccsr_tsec_t;
726
8280912e 727/* PIC Registers */
42d1f039 728typedef struct ccsr_pic {
8280912e
KG		 729 u8 res1[64];
730 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
731 u8 res2[12];
732 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
733 u8 res3[12];
734 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
735 u8 res4[12];
736 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
737 u8 res5[12];
738 u32 ctpr; /* Current Task Priority */
739 u8 res6[12];
740 u32 whoami; /* Who Am I */
741 u8 res7[12];
742 u32 iack; /* IRQ Acknowledge */
743 u8 res8[12];
744 u32 eoi; /* End Of IRQ */
745 u8 res9[3916];
746 u32 frr; /* Feature Reporting */
747 u8 res10[28];
748 u32 gcr; /* Global Configuration */
749#define MPC85xx_PICGCR_RST 0x80000000
750#define MPC85xx_PICGCR_M 0x20000000
751 u8 res11[92];
752 u32 vir; /* Vendor Identification */
753 u8 res12[12];
754 u32 pir; /* Processor Initialization */
755 u8 res13[12];
756 u32 ipivpr0; /* IPI Vector/Priority 0 */
757 u8 res14[12];
758 u32 ipivpr1; /* IPI Vector/Priority 1 */
759 u8 res15[12];
760 u32 ipivpr2; /* IPI Vector/Priority 2 */
761 u8 res16[12];
762 u32 ipivpr3; /* IPI Vector/Priority 3 */
763 u8 res17[12];
764 u32 svr; /* Spurious Vector */
765 u8 res18[12];
766 u32 tfrr; /* Timer Frequency Reporting */
767 u8 res19[12];
768 u32 gtccr0; /* Global Timer Current Count 0 */
769 u8 res20[12];
770 u32 gtbcr0; /* Global Timer Base Count 0 */
771 u8 res21[12];
772 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
773 u8 res22[12];
774 u32 gtdr0; /* Global Timer Destination 0 */
775 u8 res23[12];
776 u32 gtccr1; /* Global Timer Current Count 1 */
777 u8 res24[12];
778 u32 gtbcr1; /* Global Timer Base Count 1 */
779 u8 res25[12];
780 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
781 u8 res26[12];
782 u32 gtdr1; /* Global Timer Destination 1 */
783 u8 res27[12];
784 u32 gtccr2; /* Global Timer Current Count 2 */
785 u8 res28[12];
786 u32 gtbcr2; /* Global Timer Base Count 2 */
787 u8 res29[12];
788 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
789 u8 res30[12];
790 u32 gtdr2; /* Global Timer Destination 2 */
791 u8 res31[12];
792 u32 gtccr3; /* Global Timer Current Count 3 */
793 u8 res32[12];
794 u32 gtbcr3; /* Global Timer Base Count 3 */
795 u8 res33[12];
796 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
797 u8 res34[12];
798 u32 gtdr3; /* Global Timer Destination 3 */
799 u8 res35[268];
800 u32 tcr; /* Timer Control */
801 u8 res36[12];
802 u32 irqsr0; /* IRQ_OUT Summary 0 */
803 u8 res37[12];
804 u32 irqsr1; /* IRQ_OUT Summary 1 */
805 u8 res38[12];
806 u32 cisr0; /* Critical IRQ Summary 0 */
807 u8 res39[12];
808 u32 cisr1; /* Critical IRQ Summary 1 */
809 u8 res40[188];
810 u32 msgr0; /* Message 0 */
811 u8 res41[12];
812 u32 msgr1; /* Message 1 */
813 u8 res42[12];
814 u32 msgr2; /* Message 2 */
815 u8 res43[12];
816 u32 msgr3; /* Message 3 */
817 u8 res44[204];
818 u32 mer; /* Message Enable */
819 u8 res45[12];
820 u32 msr; /* Message Status */
821 u8 res46[60140];
822 u32 eivpr0; /* External IRQ Vector/Priority 0 */
823 u8 res47[12];
824 u32 eidr0; /* External IRQ Destination 0 */
825 u8 res48[12];
826 u32 eivpr1; /* External IRQ Vector/Priority 1 */
827 u8 res49[12];
828 u32 eidr1; /* External IRQ Destination 1 */
829 u8 res50[12];
830 u32 eivpr2; /* External IRQ Vector/Priority 2 */
831 u8 res51[12];
832 u32 eidr2; /* External IRQ Destination 2 */
833 u8 res52[12];
834 u32 eivpr3; /* External IRQ Vector/Priority 3 */
835 u8 res53[12];
836 u32 eidr3; /* External IRQ Destination 3 */
837 u8 res54[12];
838 u32 eivpr4; /* External IRQ Vector/Priority 4 */
839 u8 res55[12];
840 u32 eidr4; /* External IRQ Destination 4 */
841 u8 res56[12];
842 u32 eivpr5; /* External IRQ Vector/Priority 5 */
843 u8 res57[12];
844 u32 eidr5; /* External IRQ Destination 5 */
845 u8 res58[12];
846 u32 eivpr6; /* External IRQ Vector/Priority 6 */
847 u8 res59[12];
848 u32 eidr6; /* External IRQ Destination 6 */
849 u8 res60[12];
850 u32 eivpr7; /* External IRQ Vector/Priority 7 */
851 u8 res61[12];
852 u32 eidr7; /* External IRQ Destination 7 */
853 u8 res62[12];
854 u32 eivpr8; /* External IRQ Vector/Priority 8 */
855 u8 res63[12];
856 u32 eidr8; /* External IRQ Destination 8 */
857 u8 res64[12];
858 u32 eivpr9; /* External IRQ Vector/Priority 9 */
859 u8 res65[12];
860 u32 eidr9; /* External IRQ Destination 9 */
861 u8 res66[12];
862 u32 eivpr10; /* External IRQ Vector/Priority 10 */
863 u8 res67[12];
864 u32 eidr10; /* External IRQ Destination 10 */
865 u8 res68[12];
866 u32 eivpr11; /* External IRQ Vector/Priority 11 */
867 u8 res69[12];
868 u32 eidr11; /* External IRQ Destination 11 */
869 u8 res70[140];
870 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
871 u8 res71[12];
872 u32 iidr0; /* Internal IRQ Destination 0 */
873 u8 res72[12];
874 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
875 u8 res73[12];
876 u32 iidr1; /* Internal IRQ Destination 1 */
877 u8 res74[12];
878 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
879 u8 res75[12];
880 u32 iidr2; /* Internal IRQ Destination 2 */
881 u8 res76[12];
882 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
883 u8 res77[12];
884 u32 iidr3; /* Internal IRQ Destination 3 */
885 u8 res78[12];
886 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
887 u8 res79[12];
888 u32 iidr4; /* Internal IRQ Destination 4 */
889 u8 res80[12];
890 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
891 u8 res81[12];
892 u32 iidr5; /* Internal IRQ Destination 5 */
893 u8 res82[12];
894 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
895 u8 res83[12];
896 u32 iidr6; /* Internal IRQ Destination 6 */
897 u8 res84[12];
898 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
899 u8 res85[12];
900 u32 iidr7; /* Internal IRQ Destination 7 */
901 u8 res86[12];
902 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
903 u8 res87[12];
904 u32 iidr8; /* Internal IRQ Destination 8 */
905 u8 res88[12];
906 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
907 u8 res89[12];
908 u32 iidr9; /* Internal IRQ Destination 9 */
909 u8 res90[12];
910 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
911 u8 res91[12];
912 u32 iidr10; /* Internal IRQ Destination 10 */
913 u8 res92[12];
914 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
915 u8 res93[12];
916 u32 iidr11; /* Internal IRQ Destination 11 */
917 u8 res94[12];
918 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
919 u8 res95[12];
920 u32 iidr12; /* Internal IRQ Destination 12 */
921 u8 res96[12];
922 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
923 u8 res97[12];
924 u32 iidr13; /* Internal IRQ Destination 13 */
925 u8 res98[12];
926 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
927 u8 res99[12];
928 u32 iidr14; /* Internal IRQ Destination 14 */
929 u8 res100[12];
930 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
931 u8 res101[12];
932 u32 iidr15; /* Internal IRQ Destination 15 */
933 u8 res102[12];
934 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
935 u8 res103[12];
936 u32 iidr16; /* Internal IRQ Destination 16 */
937 u8 res104[12];
938 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
939 u8 res105[12];
940 u32 iidr17; /* Internal IRQ Destination 17 */
941 u8 res106[12];
942 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
943 u8 res107[12];
944 u32 iidr18; /* Internal IRQ Destination 18 */
945 u8 res108[12];
946 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
947 u8 res109[12];
948 u32 iidr19; /* Internal IRQ Destination 19 */
949 u8 res110[12];
950 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
951 u8 res111[12];
952 u32 iidr20; /* Internal IRQ Destination 20 */
953 u8 res112[12];
954 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
955 u8 res113[12];
956 u32 iidr21; /* Internal IRQ Destination 21 */
957 u8 res114[12];
958 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
959 u8 res115[12];
960 u32 iidr22; /* Internal IRQ Destination 22 */
961 u8 res116[12];
962 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
963 u8 res117[12];
964 u32 iidr23; /* Internal IRQ Destination 23 */
965 u8 res118[12];
966 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
967 u8 res119[12];
968 u32 iidr24; /* Internal IRQ Destination 24 */
969 u8 res120[12];
970 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
971 u8 res121[12];
972 u32 iidr25; /* Internal IRQ Destination 25 */
973 u8 res122[12];
974 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
975 u8 res123[12];
976 u32 iidr26; /* Internal IRQ Destination 26 */
977 u8 res124[12];
978 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
979 u8 res125[12];
980 u32 iidr27; /* Internal IRQ Destination 27 */
981 u8 res126[12];
982 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
983 u8 res127[12];
984 u32 iidr28; /* Internal IRQ Destination 28 */
985 u8 res128[12];
986 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
987 u8 res129[12];
988 u32 iidr29; /* Internal IRQ Destination 29 */
989 u8 res130[12];
990 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
991 u8 res131[12];
992 u32 iidr30; /* Internal IRQ Destination 30 */
993 u8 res132[12];
994 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
995 u8 res133[12];
996 u32 iidr31; /* Internal IRQ Destination 31 */
997 u8 res134[4108];
998 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
999 u8 res135[12];
1000 u32 midr0; /* Messaging IRQ Destination 0 */
1001 u8 res136[12];
1002 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
1003 u8 res137[12];
1004 u32 midr1; /* Messaging IRQ Destination 1 */
1005 u8 res138[12];
1006 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
1007 u8 res139[12];
1008 u32 midr2; /* Messaging IRQ Destination 2 */
1009 u8 res140[12];
1010 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
1011 u8 res141[12];
1012 u32 midr3; /* Messaging IRQ Destination 3 */
1013 u8 res142[59852];
1014 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1015 u8 res143[12];
1016 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1017 u8 res144[12];
1018 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1019 u8 res145[12];
1020 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1021 u8 res146[12];
1022 u32 ctpr0; /* Current Task Priority for Processor 0 */
1023 u8 res147[12];
1024 u32 whoami0; /* Who Am I for Processor 0 */
1025 u8 res148[12];
1026 u32 iack0; /* IRQ Acknowledge for Processor 0 */
1027 u8 res149[12];
1028 u32 eoi0; /* End Of IRQ for Processor 0 */
1029 u8 res150[130892];
42d1f039
WD		 1030} ccsr_pic_t;
1031
8280912e 1032/* CPM Block */
9c4c5ae3 1033#ifndef CONFIG_CPM2
42d1f039 1034typedef struct ccsr_cpm {
8280912e 1035 u8 res[262144];
42d1f039
WD		 1036} ccsr_cpm_t;
1037#else
de1d0a69 1038/*
8280912e
KG		 1039 * DPARM
1040 * General SIU
de1d0a69 1041 */
42d1f039 1042typedef struct ccsr_cpm_siu {
8280912e
KG		 1043 u8 res1[80];
1044 u32 smaer;
1045 u32 smser;
1046 u32 smevr;
1047 u8 res2[4];
1048 u32 lmaer;
1049 u32 lmser;
1050 u32 lmevr;
1051 u8 res3[2964];
42d1f039
WD		 1052} ccsr_cpm_siu_t;
1053
8280912e 1054/* IRQ Controller */
42d1f039 1055typedef struct ccsr_cpm_intctl {
8280912e
KG		 1056 u16 sicr;
1057 u8 res1[2];
1058 u32 sivec;
1059 u32 sipnrh;
1060 u32 sipnrl;
1061 u32 siprr;
1062 u32 scprrh;
1063 u32 scprrl;
1064 u32 simrh;
1065 u32 simrl;
1066 u32 siexr;
1067 u8 res2[88];
1068 u32 sccr;
1069 u8 res3[124];
42d1f039
WD		 1070} ccsr_cpm_intctl_t;
1071
8280912e 1072/* input/output port */
42d1f039 1073typedef struct ccsr_cpm_iop {
8280912e
KG		 1074 u32 pdira;
1075 u32 ppara;
1076 u32 psora;
1077 u32 podra;
1078 u32 pdata;
1079 u8 res1[12];
1080 u32 pdirb;
1081 u32 pparb;
1082 u32 psorb;
1083 u32 podrb;
1084 u32 pdatb;
1085 u8 res2[12];
1086 u32 pdirc;
1087 u32 pparc;
1088 u32 psorc;
1089 u32 podrc;
1090 u32 pdatc;
1091 u8 res3[12];
1092 u32 pdird;
1093 u32 ppard;
1094 u32 psord;
1095 u32 podrd;
1096 u32 pdatd;
1097 u8 res4[12];
42d1f039
WD		 1098} ccsr_cpm_iop_t;
1099
8280912e 1100/* CPM timers */
42d1f039 1101typedef struct ccsr_cpm_timer {
8280912e
KG		 1102 u8 tgcr1;
1103 u8 res1[3];
1104 u8 tgcr2;
1105 u8 res2[11];
1106 u16 tmr1;
1107 u16 tmr2;
1108 u16 trr1;
1109 u16 trr2;
1110 u16 tcr1;
1111 u16 tcr2;
1112 u16 tcn1;
1113 u16 tcn2;
1114 u16 tmr3;
1115 u16 tmr4;
1116 u16 trr3;
1117 u16 trr4;
1118 u16 tcr3;
1119 u16 tcr4;
1120 u16 tcn3;
1121 u16 tcn4;
1122 u16 ter1;
1123 u16 ter2;
1124 u16 ter3;
1125 u16 ter4;
1126 u8 res3[608];
42d1f039
WD		 1127} ccsr_cpm_timer_t;
1128
8280912e 1129/* SDMA */
42d1f039 1130typedef struct ccsr_cpm_sdma {
8280912e
KG		 1131 u8 sdsr;
1132 u8 res1[3];
1133 u8 sdmr;
1134 u8 res2[739];
42d1f039
WD		 1135} ccsr_cpm_sdma_t;
1136
8280912e 1137/* FCC1 */
42d1f039 1138typedef struct ccsr_cpm_fcc1 {
8280912e
KG		 1139 u32 gfmr;
1140 u32 fpsmr;
1141 u16 ftodr;
1142 u8 res1[2];
1143 u16 fdsr;
1144 u8 res2[2];
1145 u16 fcce;
1146 u8 res3[2];
1147 u16 fccm;
1148 u8 res4[2];
1149 u8 fccs;
1150 u8 res5[3];
1151 u8 ftirr_phy[4];
42d1f039
WD		 1152} ccsr_cpm_fcc1_t;
1153
8280912e 1154/* FCC2 */
42d1f039 1155typedef struct ccsr_cpm_fcc2 {
8280912e
KG		 1156 u32 gfmr;
1157 u32 fpsmr;
1158 u16 ftodr;
1159 u8 res1[2];
1160 u16 fdsr;
1161 u8 res2[2];
1162 u16 fcce;
1163 u8 res3[2];
1164 u16 fccm;
1165 u8 res4[2];
1166 u8 fccs;
1167 u8 res5[3];
1168 u8 ftirr_phy[4];
42d1f039
WD		 1169} ccsr_cpm_fcc2_t;
1170
8280912e 1171/* FCC3 */
42d1f039 1172typedef struct ccsr_cpm_fcc3 {
8280912e
KG		 1173 u32 gfmr;
1174 u32 fpsmr;
1175 u16 ftodr;
1176 u8 res1[2];
1177 u16 fdsr;
1178 u8 res2[2];
1179 u16 fcce;
1180 u8 res3[2];
1181 u16 fccm;
1182 u8 res4[2];
1183 u8 fccs;
1184 u8 res5[3];
1185 u8 res[36];
42d1f039
WD		 1186} ccsr_cpm_fcc3_t;
1187
8280912e 1188/* FCC1 extended */
42d1f039 1189typedef struct ccsr_cpm_fcc1_ext {
8280912e
KG		 1190 u32 firper;
1191 u32 firer;
1192 u32 firsr_h;
1193 u32 firsr_l;
1194 u8 gfemr;
1195 u8 res[15];
42d1f039
WD		 1196
1197} ccsr_cpm_fcc1_ext_t;
1198
8280912e 1199/* FCC2 extended */
42d1f039 1200typedef struct ccsr_cpm_fcc2_ext {
8280912e
KG		 1201 u32 firper;
1202 u32 firer;
1203 u32 firsr_h;
1204 u32 firsr_l;
1205 u8 gfemr;
1206 u8 res[31];
42d1f039
WD		 1207} ccsr_cpm_fcc2_ext_t;
1208
8280912e 1209/* FCC3 extended */
42d1f039 1210typedef struct ccsr_cpm_fcc3_ext {
8280912e
KG		 1211 u8 gfemr;
1212 u8 res[47];
42d1f039
WD		 1213} ccsr_cpm_fcc3_ext_t;
1214
8280912e 1215/* TC layers */
42d1f039 1216typedef struct ccsr_cpm_tmp1 {
8280912e 1217 u8 res[496];
42d1f039
WD		 1218} ccsr_cpm_tmp1_t;
1219
8280912e 1220/* BRGs:5,6,7,8 */
42d1f039 1221typedef struct ccsr_cpm_brg2 {
8280912e
KG		 1222 u32 brgc5;
1223 u32 brgc6;
1224 u32 brgc7;
1225 u32 brgc8;
1226 u8 res[608];
42d1f039
WD		 1227} ccsr_cpm_brg2_t;
1228
8280912e 1229/* I2C */
42d1f039 1230typedef struct ccsr_cpm_i2c {
8280912e
KG		 1231 u8 i2mod;
1232 u8 res1[3];
1233 u8 i2add;
1234 u8 res2[3];
1235 u8 i2brg;
1236 u8 res3[3];
1237 u8 i2com;
1238 u8 res4[3];
1239 u8 i2cer;
1240 u8 res5[3];
1241 u8 i2cmr;
1242 u8 res6[331];
42d1f039
WD		 1243} ccsr_cpm_i2c_t;
1244
8280912e 1245/* CPM core */
42d1f039 1246typedef struct ccsr_cpm_cp {
8280912e
KG		 1247 u32 cpcr;
1248 u32 rccr;
1249 u8 res1[14];
1250 u16 rter;
1251 u8 res2[2];
1252 u16 rtmr;
1253 u16 rtscr;
1254 u8 res3[2];
1255 u32 rtsr;
1256 u8 res4[12];
42d1f039
WD		 1257} ccsr_cpm_cp_t;
1258
8280912e 1259/* BRGs:1,2,3,4 */
42d1f039 1260typedef struct ccsr_cpm_brg1 {
8280912e
KG		 1261 u32 brgc1;
1262 u32 brgc2;
1263 u32 brgc3;
1264 u32 brgc4;
42d1f039
WD		 1265} ccsr_cpm_brg1_t;
1266
8280912e 1267/* SCC1-SCC4 */
42d1f039 1268typedef struct ccsr_cpm_scc {
8280912e
KG		 1269 u32 gsmrl;
1270 u32 gsmrh;
1271 u16 psmr;
1272 u8 res1[2];
1273 u16 todr;
1274 u16 dsr;
1275 u16 scce;
1276 u8 res2[2];
1277 u16 sccm;
1278 u8 res3;
1279 u8 sccs;
1280 u8 res4[8];
42d1f039
WD		 1281} ccsr_cpm_scc_t;
1282
42d1f039 1283typedef struct ccsr_cpm_tmp2 {
8280912e 1284 u8 res[32];
42d1f039
WD		 1285} ccsr_cpm_tmp2_t;
1286
8280912e 1287/* SPI */
42d1f039 1288typedef struct ccsr_cpm_spi {
8280912e
KG		 1289 u16 spmode;
1290 u8 res1[4];
1291 u8 spie;
1292 u8 res2[3];
1293 u8 spim;
1294 u8 res3[2];
1295 u8 spcom;
1296 u8 res4[82];
42d1f039
WD		 1297} ccsr_cpm_spi_t;
1298
8280912e 1299/* CPM MUX */
42d1f039 1300typedef struct ccsr_cpm_mux {
8280912e
KG		 1301 u8 cmxsi1cr;
1302 u8 res1;
1303 u8 cmxsi2cr;
1304 u8 res2;
1305 u32 cmxfcr;
1306 u32 cmxscr;
1307 u8 res3[2];
1308 u16 cmxuar;
1309 u8 res4[16];
42d1f039
WD		 1310} ccsr_cpm_mux_t;
1311
8280912e 1312/* SI,MCC,etc */
42d1f039 1313typedef struct ccsr_cpm_tmp3 {
8280912e 1314 u8 res[58592];
42d1f039
WD		 1315} ccsr_cpm_tmp3_t;
1316
1317typedef struct ccsr_cpm_iram {
8280912e
KG		 1318 u32 iram[8192];
1319 u8 res[98304];
42d1f039
WD		 1320} ccsr_cpm_iram_t;
1321
1322typedef struct ccsr_cpm {
8280912e 1323 /* Some references are into the unique & known dpram spaces,
42d1f039
WD		 1324 * others are from the generic base.
1325 */
53677ef1 1326#define im_dprambase im_dpram1
8280912e
KG		 1327 u8 im_dpram1[16*1024];
1328 u8 res1[16*1024];
1329 u8 im_dpram2[16*1024];
1330 u8 res2[16*1024];
1331 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1332 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1333 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1334 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1335 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
42d1f039
WD		 1336 ccsr_cpm_fcc1_t im_cpm_fcc1;
1337 ccsr_cpm_fcc2_t im_cpm_fcc2;
1338 ccsr_cpm_fcc3_t im_cpm_fcc3;
1339 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1340 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1341 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1342 ccsr_cpm_tmp1_t im_cpm_tmp1;
1343 ccsr_cpm_brg2_t im_cpm_brg2;
1344 ccsr_cpm_i2c_t im_cpm_i2c;
1345 ccsr_cpm_cp_t im_cpm_cp;
1346 ccsr_cpm_brg1_t im_cpm_brg1;
1347 ccsr_cpm_scc_t im_cpm_scc[4];
1348 ccsr_cpm_tmp2_t im_cpm_tmp2;
1349 ccsr_cpm_spi_t im_cpm_spi;
1350 ccsr_cpm_mux_t im_cpm_mux;
1351 ccsr_cpm_tmp3_t im_cpm_tmp3;
1352 ccsr_cpm_iram_t im_cpm_iram;
1353} ccsr_cpm_t;
1354#endif
42d1f039 1355
8280912e 1356/* RapidIO Registers */
42d1f039 1357typedef struct ccsr_rio {
8280912e
KG		 1358 u32 didcar; /* Device Identity Capability */
1359 u32 dicar; /* Device Information Capability */
1360 u32 aidcar; /* Assembly Identity Capability */
1361 u32 aicar; /* Assembly Information Capability */
1362 u32 pefcar; /* Processing Element Features Capability */
1363 u32 spicar; /* Switch Port Information Capability */
1364 u32 socar; /* Source Operations Capability */
1365 u32 docar; /* Destination Operations Capability */
1366 u8 res1[32];
1367 u32 msr; /* Mailbox Cmd And Status */
1368 u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */
1369 u8 res2[4];
1370 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1371 u8 res3[12];
1372 u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */
1373 u32 bdidcsr; /* Base Device ID Cmd & Status */
1374 u8 res4[4];
1375 u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */
1376 u32 ctcsr; /* Component Tag Cmd & Status */
1377 u8 res5[144];
1378 u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */
1379 u8 res6[28];
1380 u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */
1381 u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */
1382 u8 res7[20];
1383 u32 pgccsr; /* Port General Cmd & Status */
1384 u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */
1385 u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */
1386 u32 plascsr; /* Port Local Ackid Status Cmd & Status */
1387 u8 res8[12];
1388 u32 pescsr; /* Port Error & Status Cmd & Status */
1389 u32 pccsr; /* Port Control Cmd & Status */
1390 u8 res9[65184];
1391 u32 cr; /* Port Control Cmd & Status */
1392 u8 res10[12];
1393 u32 pcr; /* Port Configuration */
1394 u32 peir; /* Port Error Injection */
1395 u8 res11[3048];
1396 u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */
1397 u8 res12[12];
1398 u32 rowar0; /* RIO Outbound Attrs 0 */
1399 u8 res13[12];
1400 u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */
1401 u8 res14[4];
1402 u32 rowbar1; /* RIO Outbound Window Base Addr 1 */
1403 u8 res15[4];
1404 u32 rowar1; /* RIO Outbound Attrs 1 */
1405 u8 res16[12];
1406 u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */
1407 u8 res17[4];
1408 u32 rowbar2; /* RIO Outbound Window Base Addr 2 */
1409 u8 res18[4];
1410 u32 rowar2; /* RIO Outbound Attrs 2 */
1411 u8 res19[12];
1412 u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */
1413 u8 res20[4];
1414 u32 rowbar3; /* RIO Outbound Window Base Addr 3 */
1415 u8 res21[4];
1416 u32 rowar3; /* RIO Outbound Attrs 3 */
1417 u8 res22[12];
1418 u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */
1419 u8 res23[4];
1420 u32 rowbar4; /* RIO Outbound Window Base Addr 4 */
1421 u8 res24[4];
1422 u32 rowar4; /* RIO Outbound Attrs 4 */
1423 u8 res25[12];
1424 u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */
1425 u8 res26[4];
1426 u32 rowbar5; /* RIO Outbound Window Base Addr 5 */
1427 u8 res27[4];
1428 u32 rowar5; /* RIO Outbound Attrs 5 */
1429 u8 res28[12];
1430 u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */
1431 u8 res29[4];
1432 u32 rowbar6; /* RIO Outbound Window Base Addr 6 */
1433 u8 res30[4];
1434 u32 rowar6; /* RIO Outbound Attrs 6 */
1435 u8 res31[12];
1436 u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */
1437 u8 res32[4];
1438 u32 rowbar7; /* RIO Outbound Window Base Addr 7 */
1439 u8 res33[4];
1440 u32 rowar7; /* RIO Outbound Attrs 7 */
1441 u8 res34[12];
1442 u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */
1443 u8 res35[4];
1444 u32 rowbar8; /* RIO Outbound Window Base Addr 8 */
1445 u8 res36[4];
1446 u32 rowar8; /* RIO Outbound Attrs 8 */
1447 u8 res37[76];
1448 u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */
1449 u8 res38[4];
1450 u32 riwbar4; /* RIO Inbound Window Base Addr 4 */
1451 u8 res39[4];
1452 u32 riwar4; /* RIO Inbound Attrs 4 */
1453 u8 res40[12];
1454 u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */
1455 u8 res41[4];
1456 u32 riwbar3; /* RIO Inbound Window Base Addr 3 */
1457 u8 res42[4];
1458 u32 riwar3; /* RIO Inbound Attrs 3 */
1459 u8 res43[12];
1460 u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */
1461 u8 res44[4];
1462 u32 riwbar2; /* RIO Inbound Window Base Addr 2 */
1463 u8 res45[4];
1464 u32 riwar2; /* RIO Inbound Attrs 2 */
1465 u8 res46[12];
1466 u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */
1467 u8 res47[4];
1468 u32 riwbar1; /* RIO Inbound Window Base Addr 1 */
1469 u8 res48[4];
1470 u32 riwar1; /* RIO Inbound Attrs 1 */
1471 u8 res49[12];
1472 u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */
1473 u8 res50[12];
1474 u32 riwar0; /* RIO Inbound Attrs 0 */
1475 u8 res51[12];
1476 u32 pnfedr; /* Port Notification/Fatal Error Detect */
1477 u32 pnfedir; /* Port Notification/Fatal Error Detect */
1478 u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */
1479 u32 pecr; /* Port Error Control */
1480 u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */
1481 u32 pepr1; /* Port Error Packet 1 */
1482 u32 pepr2; /* Port Error Packet 2 */
1483 u8 res52[4];
1484 u32 predr; /* Port Recoverable Error Detect */
1485 u8 res53[4];
1486 u32 pertr; /* Port Error Recovery Threshold */
1487 u32 prtr; /* Port Retry Threshold */
1488 u8 res54[464];
1489 u32 omr; /* Outbound Mode */
1490 u32 osr; /* Outbound Status */
1491 u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */
1492 u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */
1493 u32 eosar; /* Extended Outbound Unit Source Addr */
1494 u32 osar; /* Outbound Unit Source Addr */
1495 u32 odpr; /* Outbound Destination Port */
1496 u32 odatr; /* Outbound Destination Attrs */
1497 u32 odcr; /* Outbound Doubleword Count */
1498 u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */
1499 u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */
1500 u8 res55[52];
1501 u32 imr; /* Outbound Mode */
1502 u32 isr; /* Inbound Status */
1503 u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */
1504 u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */
1505 u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */
1506 u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */
1507 u8 res56[1000];
1508 u32 dmr; /* Doorbell Mode */
1509 u32 dsr; /* Doorbell Status */
1510 u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */
1511 u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */
1512 u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */
1513 u32 dqhpar; /* Doorbell Queue Head Ptr Addr */
1514 u8 res57[104];
1515 u32 pwmr; /* Port-Write Mode */
1516 u32 pwsr; /* Port-Write Status */
1517 u32 epwqbar; /* Extended Port-Write Queue Base Addr */
1518 u32 pwqbar; /* Port-Write Queue Base Addr */
1519 u8 res58[60176];
42d1f039
WD		 1520} ccsr_rio_t;
1521
8280912e 1522/* Quick Engine Block Pin Muxing Registers */
c59e4091 1523typedef struct par_io {
8280912e
KG		 1524 u32 cpodr;
1525 u32 cpdat;
1526 u32 cpdir1;
1527 u32 cpdir2;
1528 u32 cppar1;
1529 u32 cppar2;
1530 u8 res[8];
1531} par_io_t;
c59e4091 1532
8b0ab304
BB		 1533#ifdef CONFIG_SYS_FSL_CPC
1534/*
1535 * Define a single offset that is the start of all the CPC register
1536 * blocks - if there is more than one CPC, we expect these to be
1537 * contiguous 4k regions
1538 */
1539
1540typedef struct cpc_corenet {
1541 u32 cpccsr0; /* Config/status reg */
1542 u32 res1;
1543 u32 cpccfg0; /* Configuration register */
1544 u32 res2;
1545 u32 cpcewcr0; /* External Write reg 0 */
1546 u32 cpcewabr0; /* External write base reg 0 */
1547 u32 res3[2];
1548 u32 cpcewcr1; /* External Write reg 1 */
1549 u32 cpcewabr1; /* External write base reg 1 */
1550 u32 res4[54];
1551 u32 cpcsrcr1; /* SRAM control reg 1 */
1552 u32 cpcsrcr0; /* SRAM control reg 0 */
1553 u32 res5[62];
1554 struct {
1555 u32 id; /* partition ID */
1556 u32 res;
1557 u32 alloc; /* partition allocation */
1558 u32 way; /* partition way */
1559 } partition_regs[16];
1560 u32 res6[704];
1561 u32 cpcerrinjhi; /* Error injection high */
1562 u32 cpcerrinjlo; /* Error injection lo */
1563 u32 cpcerrinjctl; /* Error injection control */
1564 u32 res7[5];
1565 u32 cpccaptdatahi; /* capture data high */
1566 u32 cpccaptdatalo; /* capture data low */
1567 u32 cpcaptecc; /* capture ECC */
1568 u32 res8[5];
1569 u32 cpcerrdet; /* error detect */
1570 u32 cpcerrdis; /* error disable */
1571 u32 cpcerrinten; /* errir interrupt enable */
1572 u32 cpcerrattr; /* error attribute */
1573 u32 cpcerreaddr; /* error extended address */
1574 u32 cpcerraddr; /* error address */
1575 u32 cpcerrctl; /* error control */
3c6a22b9
KG		 1576 u32 res9[41]; /* pad out to 4k */
1577 u32 cpchdbcr0; /* hardware debug control register 0 */
1578 u32 res10[63]; /* pad out to 4k */
8b0ab304
BB		 1579} cpc_corenet_t;
1580
1581#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1582#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1583#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1584#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1585#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1586#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1587#define CPC_CFG0_SZ_MASK 0x00003fff
1588#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1589#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1590#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1591#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1592#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1593 & CPC_SRCR1_SRBARU_MASK)
1594#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1595#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1596#define CPC_SRCR0_INTLVEN 0x00000100
1597#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1598#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1599#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1600#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1601#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1602#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1603#define CPC_SRCR0_SRAMEN 0x00000001
1604#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
3c6a22b9 1605#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1d2c2a62 1606#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
868da593 1607#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
8b0ab304
BB		 1608#endif /* CONFIG_SYS_FSL_CPC */
1609
8280912e 1610/* Global Utilities Block */
01df5212
KG		 1611#ifdef CONFIG_FSL_CORENET
1612typedef struct ccsr_gur {
8280912e
KG		 1613 u32 porsr1; /* POR status */
1614 u8 res1[28];
1615 u32 gpporcr1; /* General-purpose POR configuration */
01df5212 1616 u8 res2[12];
8280912e 1617 u32 gpiocr; /* GPIO control */
01df5212 1618 u8 res3[12];
8280912e 1619 u32 gpoutdr; /* General-purpose output data */
01df5212 1620 u8 res4[12];
8280912e 1621 u32 gpindr; /* General-purpose input data */
01df5212 1622 u8 res5[12];
17d90f31 1623 u32 alt_pmuxcr; /* Alt function signal multiplex control */
01df5212 1624 u8 res6[12];
8280912e 1625 u32 devdisr; /* Device disable control */
01df5212
KG		 1626#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1627#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1628#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
9ab87d04 1629#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
01df5212
KG		 1630#define FSL_CORENET_DEVDISR_RMU 0x08000000
1631#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1632#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1633#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1634#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1635#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1636#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1637#define FSL_CORENET_DEVDISR_DBG 0x00010000
1638#define FSL_CORENET_DEVDISR_NAL 0x00008000
9ab87d04
KG		 1639#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1640#define FSL_CORENET_DEVDISR_SATA2 0x00002000
01df5212
KG		 1641#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1642#define FSL_CORENET_DEVDISR_USB1 0x00000800
1643#define FSL_CORENET_DEVDISR_USB2 0x00000400
1644#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1645#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1646#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1647#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1648#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1649#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1650#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1231c498
KG		 1651 u32 devdisr2; /* Device disable control 2 */
1652#define FSL_CORENET_DEVDISR2_PME 0x80000000
1653#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1654#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1655#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1656#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1657#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1658#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1659#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1660#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
9ab87d04 1661#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1231c498
KG		 1662#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1663#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1664#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1665#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1666#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1667#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
9ab87d04 1668#define FSL_CORENET_NUM_DEVDISR 2
1231c498 1669 u8 res7[8];
8280912e 1670 u32 powmgtcsr; /* Power management status & control */
01df5212 1671 u8 res8[12];
8280912e
KG		 1672 u32 coredisru; /* uppper portion for support of 64 cores */
1673 u32 coredisrl; /* lower portion for support of 64 cores */
01df5212 1674 u8 res9[8];
8280912e
KG		 1675 u32 pvr; /* Processor version */
1676 u32 svr; /* System version */
01df5212 1677 u8 res10[8];
8280912e
KG		 1678 u32 rstcr; /* Reset control */
1679 u32 rstrqpblsr; /* Reset request preboot loader status */
01df5212 1680 u8 res11[8];
8280912e
KG		 1681 u32 rstrqmr1; /* Reset request mask */
1682 u8 res12[4];
1683 u32 rstrqsr1; /* Reset request status */
1684 u8 res13[4];
1685 u8 res14[4];
1686 u32 rstrqwdtmrl; /* Reset request WDT mask */
1687 u8 res15[4];
1688 u32 rstrqwdtsrl; /* Reset request WDT status */
1689 u8 res16[4];
1690 u32 brrl; /* Boot release */
01df5212 1691 u8 res17[24];
8280912e 1692 u32 rcwsr[16]; /* Reset control word status */
01df5212 1693#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
ab48ca1a
SS		 1694#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1695#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1231c498 1696#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
9ab87d04
KG		 1697#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1698#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
01df5212
KG		 1699#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1700#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1701#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
9ab87d04
KG		 1702#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1703#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1704#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1705#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1706#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1707#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1708#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
8280912e
KG		 1709 u8 res18[192];
1710 u32 scratchrw[4]; /* Scratch Read/Write */
1711 u8 res19[240];
1712 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1713 u8 res20[240];
1714 u32 scrtsr[8]; /* Core reset status */
1715 u8 res21[224];
1716 u32 pex1liodnr; /* PCI Express 1 LIODN */
1717 u32 pex2liodnr; /* PCI Express 2 LIODN */
1718 u32 pex3liodnr; /* PCI Express 3 LIODN */
1719 u32 pex4liodnr; /* PCI Express 4 LIODN */
1720 u32 rio1liodnr; /* RIO 1 LIODN */
1721 u32 rio2liodnr; /* RIO 2 LIODN */
1722 u32 rio3liodnr; /* RIO 3 LIODN */
1723 u32 rio4liodnr; /* RIO 4 LIODN */
1724 u32 usb1liodnr; /* USB 1 LIODN */
1725 u32 usb2liodnr; /* USB 2 LIODN */
1726 u32 usb3liodnr; /* USB 3 LIODN */
1727 u32 usb4liodnr; /* USB 4 LIODN */
1728 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1729 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1730 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1731 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
9ab87d04
KG		 1732 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1733 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1734 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1735 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1736 u32 sata1liodnr; /* SATA 1 LIODN */
1737 u32 sata2liodnr; /* SATA 2 LIODN */
1738 u32 sata3liodnr; /* SATA 3 LIODN */
1739 u32 sata4liodnr; /* SATA 4 LIODN */
1740 u8 res22[32];
8280912e
KG		 1741 u32 dma1liodnr; /* DMA 1 LIODN */
1742 u32 dma2liodnr; /* DMA 2 LIODN */
1743 u32 dma3liodnr; /* DMA 3 LIODN */
1744 u32 dma4liodnr; /* DMA 4 LIODN */
1745 u8 res23[48];
1746 u8 res24[64];
1747 u32 pblsr; /* Preboot loader status */
1748 u32 pamubypenr; /* PAMU bypass enable */
1749 u32 dmacr1; /* DMA control */
1750 u8 res25[4];
1751 u32 gensr1; /* General status */
1752 u8 res26[12];
1753 u32 gencr1; /* General control */
1754 u8 res27[12];
1755 u8 res28[4];
1756 u32 cgensrl; /* Core general status */
1757 u8 res29[8];
1758 u8 res30[4];
1759 u32 cgencrl; /* Core general control */
1760 u8 res31[184];
1761 u32 sriopstecr; /* SRIO prescaler timer enable control */
17d90f31
DL		 1762 u8 res32[1788];
1763 u32 pmuxcr; /* Pin multiplexing control */
1764 u8 res33[60];
1765 u32 iovselsr; /* I/O voltage selection status */
1766 u8 res34[28];
1767 u32 ddrclkdr; /* DDR clock disable */
1768 u8 res35;
1769 u32 elbcclkdr; /* eLBC clock disable */
1770 u8 res36[20];
1771 u32 sdhcpcr; /* eSDHC polarity configuration */
1772 u8 res37[380];
01df5212
KG		 1773} ccsr_gur_t;
1774
9ab87d04
KG		 1775/*
1776 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1777 * everything after has RMan thus msg unit LIODN is used for maintenance
1778 */
1779#define rmuliodnr rio1maintliodnr
1780
01df5212 1781typedef struct ccsr_clk {
8280912e
KG		 1782 u32 clkc0csr; /* Core 0 Clock control/status */
1783 u8 res1[0x1c];
1784 u32 clkc1csr; /* Core 1 Clock control/status */
1785 u8 res2[0x1c];
1786 u32 clkc2csr; /* Core 2 Clock control/status */
1787 u8 res3[0x1c];
1788 u32 clkc3csr; /* Core 3 Clock control/status */
1789 u8 res4[0x1c];
1790 u32 clkc4csr; /* Core 4 Clock control/status */
1791 u8 res5[0x1c];
1792 u32 clkc5csr; /* Core 5 Clock control/status */
1793 u8 res6[0x1c];
1794 u32 clkc6csr; /* Core 6 Clock control/status */
1795 u8 res7[0x1c];
1796 u32 clkc7csr; /* Core 7 Clock control/status */
1797 u8 res8[0x71c];
1798 u32 pllc1gsr; /* Cluster PLL 1 General Status */
1799 u8 res10[0x1c];
1800 u32 pllc2gsr; /* Cluster PLL 2 General Status */
1801 u8 res11[0x1c];
1802 u32 pllc3gsr; /* Cluster PLL 3 General Status */
1803 u8 res12[0x1c];
1804 u32 pllc4gsr; /* Cluster PLL 4 General Status */
1805 u8 res13[0x39c];
1806 u32 pllpgsr; /* Platform PLL General Status */
1807 u8 res14[0x1c];
1808 u32 plldgsr; /* DDR PLL General Status */
1809 u8 res15[0x3dc];
01df5212
KG		 1810} ccsr_clk_t;
1811
1812typedef struct ccsr_rcpm {
8280912e
KG		 1813 u8 res1[4];
1814 u32 cdozsrl; /* Core Doze Status */
1815 u8 res2[4];
1816 u32 cdozcrl; /* Core Doze Control */
1817 u8 res3[4];
1818 u32 cnapsrl; /* Core Nap Status */
1819 u8 res4[4];
1820 u32 cnapcrl; /* Core Nap Control */
1821 u8 res5[4];
1822 u32 cdozpsrl; /* Core Doze Previous Status */
1823 u8 res6[4];
1824 u32 cdozpcrl; /* Core Doze Previous Control */
1825 u8 res7[4];
1826 u32 cwaitsrl; /* Core Wait Status */
1827 u8 res8[8];
1828 u32 powmgtcsr; /* Power Mangement Control & Status */
1829 u8 res9[12];
1830 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
1831 u8 res10[12];
1832 u8 res11[4];
1833 u32 cpmimrl; /* Core PM IRQ Masking */
1834 u8 res12[4];
1835 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
1836 u8 res13[4];
1837 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
1838 u8 res14[4];
1839 u32 cpmnmimrl; /* Core PM NMI Masking */
1840 u8 res15[4];
1841 u32 ctbenrl; /* Core Time Base Enable */
1842 u8 res16[4];
1843 u32 ctbclkselrl; /* Core Time Base Clock Select */
1844 u8 res17[4];
1845 u32 ctbhltcrl; /* Core Time Base Halt Control */
01df5212
KG		 1846 u8 res18[0xf68];
1847} ccsr_rcpm_t;
1848
1849#else
42d1f039 1850typedef struct ccsr_gur {
8280912e 1851 u32 porpllsr; /* POR PLL ratio status */
c0391111
JJ		 1852#ifdef CONFIG_MPC8536
1853#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1854#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1855#else
1856#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1857#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1858#endif
b3d7f20f
HW		 1859#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1860#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
266139b8 1861#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
8280912e
KG		 1862#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
1863 u32 porbmsr; /* POR boot mode status */
53677ef1 1864#define MPC85xx_PORBMSR_HA 0x00070000
6442b71b 1865#define MPC85xx_PORBMSR_HA_SHIFT 16
8280912e
KG		 1866 u32 porimpscr; /* POR I/O impedance status & control */
1867 u32 pordevsr; /* POR I/O device status regsiter */
67a719da
RZ		 1868#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
1869#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
1870#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
1871#else
837f1ba0
ES		 1872#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1873#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
67a719da 1874#endif
837f1ba0
ES		 1875#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1876#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
8280912e 1877#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
9427ccde 1878#define MPC85xx_PORDEVSR_PCI1 0x00800000
0c955daf
DL		 1879#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
1880#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
1881#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
67a719da
RZ		 1882#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
1883#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1884#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
0c955daf 1885#else
28747f9b
PK		 1886#if defined(CONFIG_P1010)
1887#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1888#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
1889#else
4442f45b 1890#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
6442b71b 1891#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
28747f9b 1892#endif /* if defined(CONFIG_P1010) */
0c955daf 1893#endif
53677ef1
WD		 1894#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1895#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1896#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1897#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1898#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
837f1ba0 1899#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
53677ef1 1900#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
837f1ba0 1901#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
8280912e
KG		 1902 u32 pordbgmsr; /* POR debug mode status */
1903 u32 pordevsr2; /* POR I/O device status 2 */
681c02d0 1904/* The 8544 RM says this is bit 26, but it's really bit 24 */
f7d190b1 1905#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
8280912e
KG		 1906 u8 res1[8];
1907 u32 gpporcr; /* General-purpose POR configuration */
1908 u8 res2[12];
1909 u32 gpiocr; /* GPIO control */
1910 u8 res3[12];
22b6dbc1 1911#if defined(CONFIG_MPC8569)
8280912e
KG		 1912 u32 plppar1; /* Platform port pin assignment 1 */
1913 u32 plppar2; /* Platform port pin assignment 2 */
1914 u32 plpdir1; /* Platform port pin direction 1 */
1915 u32 plpdir2; /* Platform port pin direction 2 */
22b6dbc1 1916#else
8280912e
KG		 1917 u32 gpoutdr; /* General-purpose output data */
1918 u8 res4[12];
22b6dbc1 1919#endif
8280912e
KG		 1920 u32 gpindr; /* General-purpose input data */
1921 u8 res5[12];
1922 u32 pmuxcr; /* Alt. function signal multiplex control */
80522dc8
AF		 1923#define MPC85xx_PMUXCR_SD_DATA 0x80000000
1924#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1925#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
4aa8405c 1926#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
a52d2f81
HW		 1927#define MPC85xx_PMUXCR_QE0 0x00008000
1928#define MPC85xx_PMUXCR_QE1 0x00004000
1929#define MPC85xx_PMUXCR_QE2 0x00002000
1930#define MPC85xx_PMUXCR_QE3 0x00001000
1931#define MPC85xx_PMUXCR_QE4 0x00000800
1932#define MPC85xx_PMUXCR_QE5 0x00000400
1933#define MPC85xx_PMUXCR_QE6 0x00000200
1934#define MPC85xx_PMUXCR_QE7 0x00000100
1935#define MPC85xx_PMUXCR_QE8 0x00000080
1936#define MPC85xx_PMUXCR_QE9 0x00000040
1937#define MPC85xx_PMUXCR_QE10 0x00000020
1938#define MPC85xx_PMUXCR_QE11 0x00000010
1939#define MPC85xx_PMUXCR_QE12 0x00000008
6e37a044
TT		 1940 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
1941 u8 res6[8];
8280912e 1942 u32 devdisr; /* Device disable control */
837f1ba0
ES		 1943#define MPC85xx_DEVDISR_PCI1 0x80000000
1944#define MPC85xx_DEVDISR_PCI2 0x40000000
1945#define MPC85xx_DEVDISR_PCIE 0x20000000
1946#define MPC85xx_DEVDISR_LBC 0x08000000
1947#define MPC85xx_DEVDISR_PCIE2 0x04000000
1948#define MPC85xx_DEVDISR_PCIE3 0x02000000
1949#define MPC85xx_DEVDISR_SEC 0x01000000
1950#define MPC85xx_DEVDISR_SRIO 0x00080000
1951#define MPC85xx_DEVDISR_RMSG 0x00040000
53677ef1
WD		 1952#define MPC85xx_DEVDISR_DDR 0x00010000
1953#define MPC85xx_DEVDISR_CPU 0x00008000
1954#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1955#define MPC85xx_DEVDISR_TB 0x00004000
1956#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1957#define MPC85xx_DEVDISR_CPU1 0x00002000
1958#define MPC85xx_DEVDISR_TB1 0x00001000
837f1ba0
ES		 1959#define MPC85xx_DEVDISR_DMA 0x00000400
1960#define MPC85xx_DEVDISR_TSEC1 0x00000080
1961#define MPC85xx_DEVDISR_TSEC2 0x00000040
1962#define MPC85xx_DEVDISR_TSEC3 0x00000020
1963#define MPC85xx_DEVDISR_TSEC4 0x00000010
1964#define MPC85xx_DEVDISR_I2C 0x00000004
1965#define MPC85xx_DEVDISR_DUART 0x00000002
8280912e
KG		 1966 u8 res7[12];
1967 u32 powmgtcsr; /* Power management status & control */
1968 u8 res8[12];
1969 u32 mcpsumr; /* Machine check summary */
1970 u8 res9[12];
1971 u32 pvr; /* Processor version */
1972 u32 svr; /* System version */
a52d2f81 1973 u8 res10[8];
8280912e 1974 u32 rstcr; /* Reset control */
22b6dbc1 1975#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
a52d2f81 1976 u8 res11a[76];
8280912e 1977 par_io_t qe_par_io[7];
a52d2f81
HW		 1978 u8 res11b[1600];
1979#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1980 defined(CONFIG_P1021) || defined(CONFIG_P1025)
1981 u8 res11a[12];
1982 u32 iovselsr;
1983 u8 res11b[60];
1984 par_io_t qe_par_io[3];
1985 u8 res11c[1496];
c59e4091 1986#else
a52d2f81 1987 u8 res11a[1868];
c59e4091 1988#endif
6e37a044 1989 u32 clkdvdr; /* Clock Divide register */
a52d2f81 1990 u8 res12[1532];
8280912e 1991 u32 clkocr; /* Clock out select */
a52d2f81 1992 u8 res13[12];
8280912e 1993 u32 ddrdllcr; /* DDR DLL control */
a52d2f81 1994 u8 res14[12];
8280912e 1995 u32 lbcdllcr; /* LBC DLL control */
a52d2f81 1996 u8 res15[248];
8280912e
KG		 1997 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
1998 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
1999 u32 ddrioovcr; /* DDR IO Override Control */
2000 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2001 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
4aa8405c
ZC		 2002 u8 res16[52];
2003 u32 sdhcdcr; /* SDHC debug control register */
2004 u8 res17[61592];
42d1f039 2005} ccsr_gur_t;
01df5212
KG		 2006#endif
2007
4aa8405c
ZC		 2008#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2009
11588b5d
KG		 2010typedef struct serdes_corenet {
2011 struct {
2012 u32 rstctl; /* Reset Control Register */
2013#define SRDS_RSTCTL_RST 0x80000000
2014#define SRDS_RSTCTL_RSTDONE 0x40000000
2015#define SRDS_RSTCTL_RSTERR 0x20000000
1231c498 2016#define SRDS_RSTCTL_SDPD 0x00000020
11588b5d 2017 u32 pllcr0; /* PLL Control Register 0 */
1231c498
KG		 2018#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
2019#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2020#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2021#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2022#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2023#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2024#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
11588b5d
KG		 2025 u32 pllcr1; /* PLL Control Register 1 */
2026#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2027 u32 res[5];
2028 } bank[3];
2029 u32 res1[12];
2030 u32 srdstcalcr; /* TX Calibration Control */
2031 u32 res2[3];
2032 u32 srdsrcalcr; /* RX Calibration Control */
2033 u32 res3[3];
2034 u32 srdsgr0; /* General Register 0 */
2035 u32 res4[11];
2036 u32 srdspccr0; /* Protocol Converter Config 0 */
2037 u32 srdspccr1; /* Protocol Converter Config 1 */
2038 u32 srdspccr2; /* Protocol Converter Config 2 */
2039#define SRDS_PCCR2_RST_XGMII1 0x00800000
2040#define SRDS_PCCR2_RST_XGMII2 0x00400000
2041 u32 res5[197];
2042 struct {
2043 u32 gcr0; /* General Control Register 0 */
2044#define SRDS_GCR0_RRST 0x00400000
2045#define SRDS_GCR0_1STLANE 0x00010000
2046 u32 gcr1; /* General Control Register 1 */
2047#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2048#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2049#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2050#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2051#define SRDS_GCR1_OPAD_CTL 0x04000000
2052 u32 res1[4];
2053 u32 tecr0; /* TX Equalization Control Reg 0 */
2054#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2055#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2056 u32 res3;
2057 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2058 u32 res4[7];
2059 } lane[24];
2060 u32 res6[384];
2061} serdes_corenet_t;
2062
2063enum {
2064 FSL_SRDS_B1_LANE_A = 0,
2065 FSL_SRDS_B1_LANE_B = 1,
2066 FSL_SRDS_B1_LANE_C = 2,
2067 FSL_SRDS_B1_LANE_D = 3,
2068 FSL_SRDS_B1_LANE_E = 4,
2069 FSL_SRDS_B1_LANE_F = 5,
2070 FSL_SRDS_B1_LANE_G = 6,
2071 FSL_SRDS_B1_LANE_H = 7,
2072 FSL_SRDS_B1_LANE_I = 8,
2073 FSL_SRDS_B1_LANE_J = 9,
2074 FSL_SRDS_B2_LANE_A = 16,
2075 FSL_SRDS_B2_LANE_B = 17,
2076 FSL_SRDS_B2_LANE_C = 18,
2077 FSL_SRDS_B2_LANE_D = 19,
2078 FSL_SRDS_B3_LANE_A = 20,
2079 FSL_SRDS_B3_LANE_B = 21,
2080 FSL_SRDS_B3_LANE_C = 22,
2081 FSL_SRDS_B3_LANE_D = 23,
2082};
2083
22f292c7
KP		 2084/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2085#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2086typedef struct ccsr_sec {
9ab87d04
KG		 2087 u32 res0;
2088 u32 mcfgr; /* Master CFG Register */
2089 u8 res1[0x8];
2090 struct {
2091 u32 ms; /* Job Ring LIODN Register, MS */
2092 u32 ls; /* Job Ring LIODN Register, LS */
ed062e0f 2093 } jrliodnr[4];
9ab87d04
KG		 2094 u8 res2[0x30];
2095 struct {
2096 u32 ms; /* RTIC LIODN Register, MS */
2097 u32 ls; /* RTIC LIODN Register, LS */
2098 } rticliodnr[4];
2099 u8 res3[0x1c];
2100 u32 decorr; /* DECO Request Register */
2101 struct {
2102 u32 ms; /* DECO LIODN Register, MS */
2103 u32 ls; /* DECO LIODN Register, LS */
2104 } decoliodnr[5];
2105 u8 res4[0x58];
2106 u32 dar; /* DECO Avail Register */
2107 u32 drr; /* DECO Reset Register */
2108 u8 res5[0xe78];
22f292c7
KP		 2109 u32 crnr_ms; /* CHA Revision Number Register, MS */
2110 u32 crnr_ls; /* CHA Revision Number Register, LS */
2111 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
22f292c7 2112 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
9ab87d04 2113 u8 res6[0x10];
22f292c7
KP		 2114 u32 far_ms; /* Fault Address Register, MS */
2115 u32 far_ls; /* Fault Address Register, LS */
2116 u32 falr; /* Fault Address LIODN Register */
2117 u32 fadr; /* Fault Address Detail Register */
9ab87d04 2118 u8 res7[0x4];
22f292c7 2119 u32 csta; /* CAAM Status Register */
9ab87d04 2120 u8 res8[0x8];
22f292c7 2121 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
22f292c7
KP		 2122 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2123 u32 chavid_ms; /* CHA Version ID Register, MS */
2124 u32 chavid_ls; /* CHA Version ID Register, LS */
2125 u32 chanum_ms; /* CHA Number Register, MS */
9ab87d04
KG		 2126 u32 chanum_ls; /* CHA Number Register, LS */
2127 u32 secvid_ms; /* SEC Version ID Register, MS */
2128 u32 secvid_ls; /* SEC Version ID Register, LS */
2129 u8 res9[0x6020];
2130 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2131 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2132 u8 res10[0x8fd8];
2133} ccsr_sec_t;
2134
2135#define SEC_CTPR_MS_AXI_LIODN 0x08000000
2136#define SEC_CTPR_MS_QI 0x02000000
2137#define SEC_RVID_MA 0x0f000000
ed062e0f
KG		 2138#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2139#define SEC_CHANUM_MS_JRNUM_SHIFT 28
22f292c7
KP		 2140#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2141#define SEC_CHANUM_MS_DECONUM_SHIFT 24
22f292c7
KP		 2142#endif
2143
9ab87d04
KG		 2144typedef struct ccsr_qman {
2145 struct {
2146 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2147 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2148 u32 res;
2149 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2150 } qcsp[32];
2151
2152 /* Not actually reserved, but irrelevant to u-boot */
2153 u8 res[0xbf8 - 0x200];
2154 u32 ip_rev_1;
2155 u32 ip_rev_2;
2156 u32 fqd_bare; /* FQD Extended Base Addr Register */
2157 u32 fqd_bar; /* FQD Base Addr Register */
2158 u8 res1[0x8];
2159 u32 fqd_ar; /* FQD Attributes Register */
2160 u8 res2[0xc];
2161 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2162 u32 pfdr_bar; /* PFDR Base Addr Register */
2163 u8 res3[0x8];
2164 u32 pfdr_ar; /* PFDR Attributes Register */
2165 u8 res4[0x4c];
2166 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2167 u32 qcsp_bar; /* QCSP Base Addr Register */
2168 u8 res5[0x78];
2169 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2170 u32 srcidr; /* Source ID Register */
2171 u32 liodnr; /* LIODN Register */
2172 u8 res6[4];
2173 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2174 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2175 u8 res7[0x2e8];
2176} ccsr_qman_t;
2177
2178typedef struct ccsr_bman {
2179 /* Not actually reserved, but irrelevant to u-boot */
2180 u8 res[0xbf8];
2181 u32 ip_rev_1;
2182 u32 ip_rev_2;
2183 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2184 u32 fbpr_bar; /* FBPR Base Addr Register */
2185 u8 res1[0x8];
2186 u32 fbpr_ar; /* FBPR Attributes Register */
2187 u8 res2[0xf0];
2188 u32 srcidr; /* Source ID Register */
2189 u32 liodnr; /* LIODN Register */
2190 u8 res7[0x2f4];
2191} ccsr_bman_t;
2192
2193typedef struct ccsr_pme {
2194 u8 res0[0x804];
2195 u32 liodnbr; /* LIODN Base Register */
2196 u8 res1[0x1f8];
2197 u32 srcidr; /* Source ID Register */
2198 u8 res2[8];
2199 u32 liodnr; /* LIODN Register */
2200 u8 res3[0x1e8];
2201 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2202 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2203 u8 res4[0x400];
2204} ccsr_pme_t;
2205
01df5212
KG		 2206#ifdef CONFIG_FSL_CORENET
2207#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2208#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
2209#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
2210#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2211#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
11588b5d 2212#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
8b0ab304 2213#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
9ab87d04
KG		 2214#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2215#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2216#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
01df5212
KG		 2217#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2218#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2219#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2220#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
9ab87d04
KG		 2221#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2222#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2223#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2224#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2225#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2226#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2227#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
2228#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2229#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
22f292c7 2230#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
9ab87d04 2231#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
24995d82
HW		 2232#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2233#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
9ab87d04
KG		 2234#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2235#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2236#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2237#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2238#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2239#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2240#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2241#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2242#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2243#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2244#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2245#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2246#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2247#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2248#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
01df5212
KG		 2249#else
2250#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2251#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
2252#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2253#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
2254#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
99d9c07e 2255#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
01df5212 2256#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
99d9c07e 2257#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
01df5212 2258#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
99d9c07e
KG		 2259#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2260#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2261#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2262#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2263#else
2264#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2265#endif
01df5212
KG		 2266#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2267#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2268#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
d789b5f5 2269#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
01df5212
KG		 2270#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2271#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
8280912e 2272#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
3ad89c4e
KG		 2273#ifdef CONFIG_TSECV2
2274#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2275#else
b9e186fc 2276#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e
KG		 2277#endif
2278#define CONFIG_SYS_MDIO1_OFFSET 0x24000
01df5212
KG		 2279#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2280#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2281#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2282#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
67a719da
RZ		 2283#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2284#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2285#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2286#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2287#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2288#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
01df5212
KG		 2289#endif
2290
2291#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2292#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
42d1f039 2293
8b0ab304
BB		 2294#define CONFIG_SYS_FSL_CPC_ADDR \
2295 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
24995d82
HW		 2296#define CONFIG_SYS_FSL_QMAN_ADDR \
2297 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2298#define CONFIG_SYS_FSL_BMAN_ADDR \
2299 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
9ab87d04
KG		 2300#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2301 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
8280912e
KG		 2302#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2303 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2304#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2305 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2306#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2307 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2308#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2309 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2310#define CONFIG_SYS_MPC85xx_ECM_ADDR \
2311 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2312#define CONFIG_SYS_MPC85xx_DDR_ADDR \
2313 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
2314#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
2315 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
f51cdaf1 2316#define CONFIG_SYS_LBC_ADDR \
8280912e 2317 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
d789b5f5
DD		 2318#define CONFIG_SYS_IFC_ADDR \
2319 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
8280912e
KG		 2320#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2321 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2322#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2323 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2324#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2325 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2326#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2327 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2328#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2329 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2330#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2331 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2332#define CONFIG_SYS_MPC85xx_L2_ADDR \
2333 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2334#define CONFIG_SYS_MPC85xx_DMA_ADDR \
2335 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2336#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2337 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
680c613a 2338#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
8280912e
KG		 2339 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
2340#define CONFIG_SYS_MPC85xx_CPM_ADDR \
2341 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
2342#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
17028be2 2343 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
8280912e
KG		 2344#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2345 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
11588b5d
KG		 2346#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
2347 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
a07bf180 2348#define CONFIG_SYS_MPC85xx_USB_ADDR \
8280912e 2349 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
22f292c7
KP		 2350#define CONFIG_SYS_FSL_SEC_ADDR \
2351 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
9ab87d04
KG		 2352#define CONFIG_SYS_FSL_FM1_ADDR \
2353 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
2354#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
2355 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
2356#define CONFIG_SYS_FSL_FM2_ADDR \
2357 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
aafeefbd 2358
99d9c07e
KG		 2359#define CONFIG_SYS_PCI1_ADDR \
2360 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
2361#define CONFIG_SYS_PCI2_ADDR \
2362 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
2363#define CONFIG_SYS_PCIE1_ADDR \
2364 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
2365#define CONFIG_SYS_PCIE2_ADDR \
2366 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
2367#define CONFIG_SYS_PCIE3_ADDR \
2368 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
9ab87d04
KG		 2369#define CONFIG_SYS_PCIE4_ADDR \
2370 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
99d9c07e 2371
b9e186fc
SG		 2372#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
2373#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
2374
42d1f039 2375#endif /*__IMMAP_85xx__*/
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