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fe8c2806 1/*
82826d54 2 * (C) Copyright 2000-2010
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
52cb4d4f 28#include <stdio_dev.h>
fe8c2806
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
WD
36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
fe8c2806
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
fe8c2806
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
272cc70b
AF
51#ifdef CONFIG_GENERIC_MMC
52#include <mmc.h>
53#endif
281e00a3 54#include <serial.h>
6d0f6bcf 55#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
fe8c2806
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
56f94be3
WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
9c67352f 71#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
42d1f039
WD
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
ecf5b98c
KG
78#ifdef CONFIG_ADDR_MAP
79#include <asm/mmu.h>
80#endif
81
fc39c2fd
KG
82#ifdef CONFIG_MP
83#include <asm/mp.h>
84#endif
85
310cecb8
LCM
86#ifdef CONFIG_BITBANGMII
87#include <miiphy.h>
88#endif
89
6d0f6bcf 90#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
fa230445
HS
91extern int update_flash_size (int flash_size);
92#endif
93
9045f33c 94#if defined(CONFIG_SC3)
ca43ba18
HS
95extern void sc3_read_eeprom(void);
96#endif
97
7def6b34 98#if defined(CONFIG_CMD_DOC)
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99void doc_init (void);
100#endif
101#if defined(CONFIG_HARD_I2C) || \
102 defined(CONFIG_SOFT_I2C)
103#include <i2c.h>
104#endif
04a9e118 105#include <spi.h>
d6ac2ed8 106#include <nand.h>
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107
108static char *failed = "*** failed ***\n";
109
544d97e9 110#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
fe8c2806 111extern flash_info_t flash_info[];
17d704eb 112#endif
fe8c2806 113
ca43ba18
HS
114#if defined(CONFIG_START_IDE)
115extern int board_start_ide(void);
116#endif
fe8c2806 117#include <environment.h>
d87080b7 118
bce84c4d 119DECLARE_GLOBAL_DATA_PTR;
fe8c2806 120
6d0f6bcf
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121#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
122#define CONFIG_SYS_MEM_TOP_HIDE 0
6fb4b640
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123#endif
124
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125extern ulong __init_end;
126extern ulong _end;
3b57fe0a
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127ulong monitor_flash_len;
128
7def6b34 129#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
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130#include <bedbug/type.h>
131#endif
132
fe8c2806
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133/************************************************************************
134 * Utilities *
135 ************************************************************************
136 */
137
fe8c2806
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138/*
139 * All attempts to come up with a "common" initialization sequence
140 * that works for all boards and architectures failed: some of the
141 * requirements are just _too_ different. To get rid of the resulting
142 * mess of board dependend #ifdef'ed code we now make the whole
143 * initialization sequence configurable to the user.
144 *
145 * The requirements for any new initalization function is simple: it
146 * receives a pointer to the "global data" structure as it's only
147 * argument, and returns an integer return code, where 0 means
148 * "continue" and != 0 means "fatal error, hang the system".
149 */
150typedef int (init_fnc_t) (void);
151
152/************************************************************************
153 * Init Utilities *
154 ************************************************************************
155 * Some of this code should be moved into the core functions,
156 * but let's get it working (again) first...
157 */
158
159static int init_baudrate (void)
160{
77ddac94 161 char tmp[64]; /* long enough for environment variables */
cdb74977 162 int i = getenv_f("baudrate", tmp, sizeof (tmp));
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163
164 gd->baudrate = (i > 0)
165 ? (int) simple_strtoul (tmp, NULL, 10)
166 : CONFIG_BAUDRATE;
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167 return (0);
168}
169
170/***********************************************************************/
171
79f240f7
KP
172void __board_add_ram_info(int use_default)
173{
174 /* please define platform specific board_add_ram_info() */
175}
176void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
177
c62491d2
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178int __board_flash_wp_on(void)
179{
180 /*
181 * Most flashes can't be detected when write protection is enabled,
182 * so provide a way to let U-Boot gracefully ignore write protected
183 * devices.
184 */
185 return 0;
186}
187int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on")));
d96f41e0 188
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189static int init_func_ram (void)
190{
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191#ifdef CONFIG_BOARD_TYPES
192 int board_type = gd->board_type;
193#else
194 int board_type = 0; /* use dummy arg */
195#endif
196 puts ("DRAM: ");
197
198 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 199 print_size (gd->ram_size, "");
d96f41e0 200 board_add_ram_info(0);
d96f41e0 201 putc('\n');
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202 return (0);
203 }
204 puts (failed);
205 return (1);
206}
207
208/***********************************************************************/
209
210#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
211static int init_func_i2c (void)
212{
213 puts ("I2C: ");
6d0f6bcf 214 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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215 puts ("ready\n");
216 return (0);
217}
218#endif
219
04a9e118
BW
220#if defined(CONFIG_HARD_SPI)
221static int init_func_spi (void)
222{
223 puts ("SPI: ");
224 spi_init ();
225 puts ("ready\n");
226 return (0);
227}
228#endif
229
fe8c2806
WD
230/***********************************************************************/
231
232#if defined(CONFIG_WATCHDOG)
233static int init_func_watchdog_init (void)
234{
235 puts (" Watchdog enabled\n");
236 WATCHDOG_RESET ();
237 return (0);
238}
239# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
240
241static int init_func_watchdog_reset (void)
242{
243 WATCHDOG_RESET ();
244 return (0);
245}
246# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
247#else
248# define INIT_FUNC_WATCHDOG_INIT /* undef */
249# define INIT_FUNC_WATCHDOG_RESET /* undef */
250#endif /* CONFIG_WATCHDOG */
251
252/************************************************************************
253 * Initialization sequence *
254 ************************************************************************
255 */
256
257init_fnc_t *init_sequence[] = {
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258#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
259 probecpu,
260#endif
91525c67
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261#if defined(CONFIG_BOARD_EARLY_INIT_F)
262 board_early_init_f,
263#endif
66ca92a5 264#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 265 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
266#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
267 && !defined(CONFIG_TQM885D)
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WD
268 adjust_sdram_tbs_8xx,
269#endif
fe8c2806 270 init_timebase,
c178d3da 271#endif
6d0f6bcf 272#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 273#if !defined(CONFIG_CPM2)
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274 dpram_init,
275#endif
7aa78614 276#endif
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277#if defined(CONFIG_BOARD_POSTCLK_INIT)
278 board_postclk_init,
279#endif
280 env_init,
66ca92a5 281#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
c178d3da
WD
282 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
283 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
284 init_timebase,
285#endif
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286 init_baudrate,
287 serial_init,
288 console_init_f,
289 display_options,
290#if defined(CONFIG_8260)
291 prt_8260_rsr,
292 prt_8260_clks,
293#endif /* CONFIG_8260 */
0f898604 294#if defined(CONFIG_MPC83xx)
9be39a67
DL
295 prt_83xx_rsr,
296#endif
fe8c2806 297 checkcpu,
cbd8a35c 298#if defined(CONFIG_MPC5xxx)
945af8d7 299 prt_mpc5xxx_clks,
cbd8a35c 300#endif /* CONFIG_MPC5xxx */
983fda83
WD
301#if defined(CONFIG_MPC8220)
302 prt_mpc8220_clks,
303#endif
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304 checkboard,
305 INIT_FUNC_WATCHDOG_INIT
c837dcb1 306#if defined(CONFIG_MISC_INIT_F)
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307 misc_init_f,
308#endif
309 INIT_FUNC_WATCHDOG_RESET
310#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
311 init_func_i2c,
312#endif
04a9e118
BW
313#if defined(CONFIG_HARD_SPI)
314 init_func_spi,
315#endif
4532cb69
WD
316#ifdef CONFIG_POST
317 post_init_f,
fe8c2806
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318#endif
319 INIT_FUNC_WATCHDOG_RESET
320 init_func_ram,
6d0f6bcf 321#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 322 testdram,
6d0f6bcf 323#endif /* CONFIG_SYS_DRAM_TEST */
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WD
324 INIT_FUNC_WATCHDOG_RESET
325
326 NULL, /* Terminate this list */
327};
328
81d93e5c
KG
329ulong get_effective_memsize(void)
330{
331#ifndef CONFIG_VERY_BIG_RAM
332 return gd->ram_size;
333#else
334 /* limit stack to what we can reasonable map */
335 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
336 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
337#endif
338}
339
fe8c2806
WD
340/************************************************************************
341 *
342 * This is the first part of the initialization sequence that is
343 * implemented in C, but still running from ROM.
344 *
345 * The main purpose is to provide a (serial) console interface as
346 * soon as possible (so we can see any error messages), and to
347 * initialize the RAM so that we can relocate the monitor code to
348 * RAM.
349 *
350 * Be aware of the restrictions: global data is read-only, BSS is not
351 * initialized, and stack space is limited to a few kB.
352 *
353 ************************************************************************
354 */
355
95d449ad
MB
356#ifdef CONFIG_LOGBUFFER
357unsigned long logbuffer_base(void)
358{
6d0f6bcf 359 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
MB
360}
361#endif
362
fe8c2806
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363void board_init_f (ulong bootflag)
364{
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WD
365 bd_t *bd;
366 ulong len, addr, addr_sp;
7bc5ee07 367 ulong *s;
fe8c2806
WD
368 gd_t *id;
369 init_fnc_t **init_fnc_ptr;
370#ifdef CONFIG_PRAM
371 int i;
372 ulong reg;
373 uchar tmp[64]; /* long enough for environment variables */
374#endif
375
376 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 377 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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WD
378 /* compiler optimization barrier needed for GCC >= 3.4 */
379 __asm__ __volatile__("": : :"memory");
fe8c2806 380
82826d54
DZ
381#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
382 !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
383 !defined(CONFIG_MPC86xx)
fe8c2806
WD
384 /* Clear initial global data */
385 memset ((void *) gd, 0, sizeof (gd_t));
386#endif
387
388 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
389 if ((*init_fnc_ptr) () != 0) {
390 hang ();
391 }
392 }
393
394 /*
395 * Now that we have DRAM mapped and working, we can
396 * relocate the code and continue running from DRAM.
397 *
398 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 399 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 400 * - kernel log buffer
fe8c2806
WD
401 * - protected RAM
402 * - LCD framebuffer
403 * - monitor code
404 * - board info struct
405 */
6d0f6bcf 406 len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
fe8c2806 407
14f73ca6
SR
408 /*
409 * Subtract specified amount of memory to hide so that it won't
410 * get "touched" at all by U-Boot. By fixing up gd->ram_size
411 * the Linux kernel should now get passed the now "corrected"
412 * memory size and won't touch it either. This should work
413 * for arch/ppc and arch/powerpc. Only Linux board ports in
414 * arch/powerpc with bootwrapper support, that recalculate the
415 * memory size from the SDRAM controller setup will have to
416 * get fixed.
417 */
6d0f6bcf 418 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 419
6d0f6bcf 420 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 421
fc39c2fd
KG
422#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
423 /*
424 * We need to make sure the location we intend to put secondary core
425 * boot code is reserved and not used by any part of u-boot
c0a14aed 426 */
fc39c2fd
KG
427 if (addr > determine_mp_bootpg()) {
428 addr = determine_mp_bootpg();
429 debug ("Reserving MP boot page to %08lx\n", addr);
430 }
431#endif
432
228f29ac 433#ifdef CONFIG_LOGBUFFER
3d610186 434#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
435 /* reserve kernel log buffer */
436 addr -= (LOGBUFF_RESERVE);
9d2b18a0 437 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 438#endif
3d610186 439#endif
228f29ac 440
fe8c2806
WD
441#ifdef CONFIG_PRAM
442 /*
443 * reserve protected RAM
444 */
cdb74977 445 i = getenv_f("pram", (char *)tmp, sizeof (tmp));
77ddac94 446 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 447 addr -= (reg << 10); /* size is in kB */
9d2b18a0 448 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
449#endif /* CONFIG_PRAM */
450
451 /* round down to next 4 kB limit */
452 addr &= ~(4096 - 1);
9d2b18a0 453 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
fe8c2806
WD
454
455#ifdef CONFIG_LCD
456 /* reserve memory for LCD display (always full pages) */
457 addr = lcd_setmem (addr);
458 gd->fb_base = addr;
459#endif /* CONFIG_LCD */
460
461#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
462 /* reserve memory for video display (always full pages) */
463 addr = video_setmem (addr);
464 gd->fb_base = addr;
465#endif /* CONFIG_VIDEO */
466
467 /*
468 * reserve memory for U-Boot code, data & bss
682011ff 469 * round down to next 4 kB limit
fe8c2806
WD
470 */
471 addr -= len;
682011ff 472 addr &= ~(4096 - 1);
7d314992
WD
473#ifdef CONFIG_E500
474 /* round down to next 64 kB limit so that IVPR stays aligned */
475 addr &= ~(65536 - 1);
476#endif
fe8c2806 477
9d2b18a0 478 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806
WD
479
480 /*
481 * reserve memory for malloc() arena
482 */
483 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 484 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 485 TOTAL_MALLOC_LEN >> 10, addr_sp);
fe8c2806
WD
486
487 /*
488 * (permanently) allocate a Board Info struct
489 * and a permanent copy of the "global" data
490 */
491 addr_sp -= sizeof (bd_t);
492 bd = (bd_t *) addr_sp;
a1c4864a 493 memset(bd, 0, sizeof(bd_t));
fe8c2806 494 gd->bd = bd;
b64f190b 495 debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
fe8c2806 496 sizeof (bd_t), addr_sp);
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WD
497 addr_sp -= sizeof (gd_t);
498 id = (gd_t *) addr_sp;
b64f190b 499 debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
fe8c2806 500 sizeof (gd_t), addr_sp);
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WD
501
502 /*
503 * Finally, we set up a new (bigger) stack.
504 *
505 * Leave some safety gap for SP, force alignment on 16 byte boundary
506 * Clear initial stack frame
507 */
508 addr_sp -= 16;
509 addr_sp &= ~0xF;
7bc5ee07
WD
510 s = (ulong *)addr_sp;
511 *s-- = 0;
512 *s-- = 0;
513 addr_sp = (ulong)s;
9d2b18a0 514 debug ("Stack Pointer at: %08lx\n", addr_sp);
fe8c2806
WD
515
516 /*
517 * Save local variables to board info struct
518 */
519
6d0f6bcf 520 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
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WD
521 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
522
36116650 523#ifdef CONFIG_SYS_SRAM_BASE
6d0f6bcf
JCPV
524 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
525 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
fe8c2806
WD
526#endif
527
42d1f039 528#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 529 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 530 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 531#endif
cbd8a35c 532#if defined(CONFIG_MPC5xxx)
6d0f6bcf 533 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 534#endif
0f898604 535#if defined(CONFIG_MPC83xx)
6d0f6bcf 536 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 537#endif
983fda83 538#if defined(CONFIG_MPC8220)
6d0f6bcf 539 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
983fda83
WD
540 bd->bi_inpfreq = gd->inp_clk;
541 bd->bi_pcifreq = gd->pci_clk;
542 bd->bi_vcofreq = gd->vco_clk;
543 bd->bi_pevfreq = gd->pev_clk;
544 bd->bi_flbfreq = gd->flb_clk;
545
dd520bf3
WD
546 /* store bootparam to sram (backward compatible), here? */
547 {
6d0f6bcf 548 u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
dd520bf3
WD
549 *sram++ = gd->ram_size;
550 *sram++ = gd->bus_clk;
551 *sram++ = gd->inp_clk;
552 *sram++ = gd->cpu_clk;
553 *sram++ = gd->vco_clk;
554 *sram++ = gd->flb_clk;
555 *sram++ = 0xb8c3ba11; /* boot signature */
556 }
983fda83 557#endif
fe8c2806 558
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WD
559 WATCHDOG_RESET ();
560 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
561 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 562#if defined(CONFIG_CPM2)
fe8c2806
WD
563 bd->bi_cpmfreq = gd->cpm_clk;
564 bd->bi_brgfreq = gd->brg_clk;
565 bd->bi_sccfreq = gd->scc_clk;
566 bd->bi_vco = gd->vco_out;
9c4c5ae3 567#endif /* CONFIG_CPM2 */
281ff9a4 568#if defined(CONFIG_MPC512X)
5d49e0e1 569 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 570#endif /* CONFIG_MPC512X */
cbd8a35c 571#if defined(CONFIG_MPC5xxx)
945af8d7
WD
572 bd->bi_ipbfreq = gd->ipb_clk;
573 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 574#endif /* CONFIG_MPC5xxx */
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WD
575 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
576
6d0f6bcf 577#ifdef CONFIG_SYS_EXTBDINFO
77ddac94
WD
578 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
579 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
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WD
580
581 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
582 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
583#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
584 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
585 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 586 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 587 bd->bi_opbfreq = get_OPB_freq ();
9fea65a6 588#elif defined(CONFIG_XILINX_405)
028ab6b5 589 bd->bi_pci_busfreq = get_PCI_freq ();
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WD
590#endif
591#endif
592
9d2b18a0 593 debug ("New Stack Pointer is: %08lx\n", addr_sp);
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WD
594
595 WATCHDOG_RESET ();
596
597#ifdef CONFIG_POST
598 post_bootmode_init();
6dff5529 599 post_run (NULL, POST_ROM | post_bootmode_get(0));
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WD
600#endif
601
602 WATCHDOG_RESET();
603
4b99327a
RR
604 gd->relocaddr = addr; /* Record relocation address, useful for debug */
605
27b207fd 606 memcpy (id, (void *)gd, sizeof (gd_t));
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WD
607
608 relocate_code (addr_sp, id, addr);
609
610 /* NOTREACHED - relocate_code() does not return */
611}
612
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WD
613/************************************************************************
614 *
615 * This is the next part if the initialization sequence: we are now
616 * running from RAM and have a "normal" C environment, i. e. global
617 * data can be written, BSS has been cleared, the stack size in not
618 * that critical any more, etc.
619 *
620 ************************************************************************
621 */
fe8c2806
WD
622void board_init_r (gd_t *id, ulong dest_addr)
623{
ff7dc067 624 char *s;
fe8c2806 625 bd_t *bd;
a483a167 626 ulong malloc_start;
fe8c2806 627
6d0f6bcf 628#ifndef CONFIG_SYS_NO_FLASH
fe8c2806
WD
629 ulong flash_size;
630#endif
631
632 gd = id; /* initialize RAM version of global data */
633 bd = gd->bd;
634
635 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63 636
d4e8ada0 637 /* The Malloc area is immediately below the monitor copy in DRAM */
a483a167 638 malloc_start = dest_addr - TOTAL_MALLOC_LEN;
13d46ab2 639
f9476902
PT
640#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
641 /*
642 * The gd->cpu pointer is set to an address in flash before relocation.
643 * We need to update it to point to the same CPU entry in RAM.
644 */
645 gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
a55bb834
KG
646#endif
647
648#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
649 /*
650 * Some systems need to relocate the env_addr pointer early because the
651 * location it points to will get invalidated before env_relocate is
652 * called. One example is on systems that might use a L2 or L3 cache
653 * in SRAM mode and initialize that cache from SRAM mode back to being
654 * a cache in cpu_init_r.
655 */
656 gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
f9476902
PT
657#endif
658
bb105f24
MB
659#ifdef CONFIG_SERIAL_MULTI
660 serial_initialize();
661#endif
fe8c2806 662
9d2b18a0 663 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
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WD
664
665 WATCHDOG_RESET ();
666
d025aa4b
BB
667 /*
668 * Setup trap handlers
669 */
670 trap_init (dest_addr);
671
c9315e6b 672#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
673 init_addr_map();
674#endif
675
c837dcb1
WD
676#if defined(CONFIG_BOARD_EARLY_INIT_R)
677 board_early_init_r ();
678#endif
679
3b57fe0a 680 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806 681
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WD
682 WATCHDOG_RESET ();
683
56f94be3 684#ifdef CONFIG_LOGBUFFER
228f29ac 685 logbuff_init_ptrs ();
56f94be3 686#endif
fe8c2806 687#ifdef CONFIG_POST
228f29ac 688 post_output_backlog ();
fe8c2806
WD
689#endif
690
691 WATCHDOG_RESET();
692
1a2e203b 693#if defined(CONFIG_SYS_DELAYED_ICACHE)
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WD
694 icache_enable (); /* it's time to enable the instruction cache */
695#endif
696
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WD
697#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
698 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
699#endif
700
76221a6c 701#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
fe8c2806 702 /*
76221a6c
AS
703 * Do early PCI configuration _before_ the flash gets initialised,
704 * because PCU ressources are crucial for flash access on some boards.
fe8c2806
WD
705 */
706 pci_init ();
3bac3513 707#endif
57d6c589 708#if defined(CONFIG_WINBOND_83C553)
fe8c2806
WD
709 /*
710 * Initialise the ISA bridge
711 */
712 initialise_w83c553f ();
713#endif
714
715 asm ("sync ; isync");
716
a483a167 717 mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
c790b04d 718
6d0f6bcf 719#if !defined(CONFIG_SYS_NO_FLASH)
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WD
720 puts ("FLASH: ");
721
c62491d2
JS
722 if (board_flash_wp_on()) {
723 printf("Uninitialized - Write Protect On\n");
724 /* Since WP is on, we can't find real size. Set to 0 */
725 flash_size = 0;
726 } else if ((flash_size = flash_init ()) > 0) {
6d0f6bcf 727# ifdef CONFIG_SYS_FLASH_CHECKSUM
fe8c2806
WD
728 print_size (flash_size, "");
729 /*
730 * Compute and print flash CRC if flashchecksum is set to 'y'
731 *
732 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
733 */
734 s = getenv ("flashchecksum");
735 if (s && (*s == 'y')) {
06c53bea 736 printf (" CRC: %08X",
6d0f6bcf 737 crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
7e780369 738 );
fe8c2806
WD
739 }
740 putc ('\n');
6d0f6bcf 741# else /* !CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 742 print_size (flash_size, "\n");
6d0f6bcf 743# endif /* CONFIG_SYS_FLASH_CHECKSUM */
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WD
744 } else {
745 puts (failed);
746 hang ();
747 }
748
6d0f6bcf 749 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
fe8c2806 750 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445 751
6d0f6bcf 752#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445
HS
753 /* Make a update of the Memctrl. */
754 update_flash_size (flash_size);
755#endif
756
757
544d97e9 758# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
7e780369 759 /* flash mapped at end of memory map */
14d0a02a 760 bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
6d0f6bcf 761# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
3b57fe0a 762 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 763# endif
6d0f6bcf 764#endif /* !CONFIG_SYS_NO_FLASH */
fe8c2806
WD
765
766 WATCHDOG_RESET ();
767
768 /* initialize higher level parts of CPU like time base and timers */
769 cpu_init_r ();
770
771 WATCHDOG_RESET ();
772
fe8c2806 773#ifdef CONFIG_SPI
bb1f8b4f 774# if !defined(CONFIG_ENV_IS_IN_EEPROM)
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WD
775 spi_init_f ();
776# endif
777 spi_init_r ();
778#endif
779
7def6b34 780#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
781 WATCHDOG_RESET ();
782 puts ("NAND: ");
783 nand_init(); /* go init the NAND */
784#endif
785
a8060359
TL
786#ifdef CONFIG_GENERIC_MMC
787/*
788 * MMC initialization is called before relocating env.
789 * Thus It is required that operations like pin multiplexer
790 * be put in board_init.
791 */
792 WATCHDOG_RESET ();
793 puts ("MMC: ");
794 mmc_initialize (bd);
795#endif
796
fe8c2806
WD
797 /* relocate environment function pointers etc. */
798 env_relocate ();
799
800 /*
801 * Fill in missing fields of bd_info.
8bde7f77
WD
802 * We do this here, where we have "normal" access to the
803 * environment; we used to do this still running from ROM,
cdb74977 804 * where had to use getenv_f(), which can be pretty slow when
8bde7f77 805 * the environment is in EEPROM.
fe8c2806 806 */
7abf0c58 807
6d0f6bcf 808#if defined(CONFIG_SYS_EXTBDINFO)
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WD
809#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
810#if defined(CONFIG_I2CFAST)
811 /*
812 * set bi_iic_fast for linux taking environment variable
813 * "i2cfast" into account
814 */
815 {
816 char *s = getenv ("i2cfast");
817 if (s && ((*s == 'y') || (*s == 'Y'))) {
818 bd->bi_iic_fast[0] = 1;
819 bd->bi_iic_fast[1] = 1;
7abf0c58
WD
820 }
821 }
7abf0c58
WD
822#endif /* CONFIG_I2CFAST */
823#endif /* CONFIG_405GP, CONFIG_405EP */
6d0f6bcf 824#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 825
9045f33c 826#if defined(CONFIG_SC3)
ca43ba18
HS
827 sc3_read_eeprom();
828#endif
d59feffb 829
6d0f6bcf 830#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
831 mac_read_from_eeprom();
832#endif
833
fe8c2806
WD
834#ifdef CONFIG_HERMES
835 if ((gd->board_type >> 16) == 2)
836 bd->bi_ethspeed = gd->board_type & 0xFFFF;
837 else
838 bd->bi_ethspeed = 0xFFFF;
839#endif
840
02a301cd 841#ifdef CONFIG_CMD_NET
eb85aa59
MF
842 /* kept around for legacy kernels only ... ignore the next section */
843 eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
e2ffd59b 844#ifdef CONFIG_HAS_ETH1
eb85aa59 845 eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
fe8c2806 846#endif
e2ffd59b 847#ifdef CONFIG_HAS_ETH2
eb85aa59 848 eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
fe8c2806 849#endif
e2ffd59b 850#ifdef CONFIG_HAS_ETH3
eb85aa59 851 eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
ba56f625 852#endif
c68a05fe 853#ifdef CONFIG_HAS_ETH4
eb85aa59 854 eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
c68a05fe 855#endif
c68a05fe 856#ifdef CONFIG_HAS_ETH5
eb85aa59 857 eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
c68a05fe 858#endif
02a301cd 859#endif /* CONFIG_CMD_NET */
c68a05fe 860
fe8c2806
WD
861 /* IP Address */
862 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
863
864 WATCHDOG_RESET ();
865
76221a6c 866#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
fe8c2806
WD
867 /*
868 * Do pci configuration
869 */
870 pci_init ();
871#endif
872
873/** leave this here (after malloc(), environment and PCI are working) **/
52cb4d4f
JCPV
874 /* Initialize stdio devices */
875 stdio_init ();
fe8c2806 876
27b207fd
WD
877 /* Initialize the jump table for applications */
878 jumptable_init ();
fe8c2806 879
500856eb
RJ
880#if defined(CONFIG_API)
881 /* Initialize API */
882 api_init ();
883#endif
884
fe8c2806
WD
885 /* Initialize the console (after the relocation and devices init) */
886 console_init_r ();
fe8c2806 887
3a8f28d0 888#if defined(CONFIG_MISC_INIT_R)
fe8c2806
WD
889 /* miscellaneous platform dependent initialisations */
890 misc_init_r ();
891#endif
892
893#ifdef CONFIG_HERMES
894 if (bd->bi_ethspeed != 0xFFFF)
895 hermes_start_lxt980 ((int) bd->bi_ethspeed);
896#endif
897
7def6b34 898#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
899 WATCHDOG_RESET ();
900 puts ("KGDB: ");
901 kgdb_init ();
902#endif
903
9d2b18a0 904 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
905
906 /*
907 * Enable Interrupts
908 */
909 interrupt_init ();
910
566a494f 911#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
912 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
913#endif
914
915 udelay (20);
916
917 set_timer (0);
918
fe8c2806
WD
919 /* Initialize from environment */
920 if ((s = getenv ("loadaddr")) != NULL) {
921 load_addr = simple_strtoul (s, NULL, 16);
922 }
7def6b34 923#if defined(CONFIG_CMD_NET)
fe8c2806
WD
924 if ((s = getenv ("bootfile")) != NULL) {
925 copy_filename (BootFile, s, sizeof (BootFile));
926 }
b3aff0cb 927#endif
fe8c2806
WD
928
929 WATCHDOG_RESET ();
930
9c2d63ec
HS
931#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
932 dtt_init ();
933#endif
7def6b34 934#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
935 WATCHDOG_RESET ();
936 puts ("SCSI: ");
937 scsi_init ();
938#endif
939
7def6b34 940#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
941 WATCHDOG_RESET ();
942 puts ("DOC: ");
943 doc_init ();
944#endif
945
310cecb8
LCM
946#ifdef CONFIG_BITBANGMII
947 bb_miiphy_init();
948#endif
7def6b34 949#if defined(CONFIG_CMD_NET)
63ff004c 950#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
951 WATCHDOG_RESET ();
952 puts ("Net: ");
63ff004c 953#endif
fe8c2806
WD
954 eth_initialize (bd);
955#endif
956
004eca0c 957#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
63ff004c
MB
958 WATCHDOG_RESET ();
959 debug ("Reset Ethernet PHY\n");
960 reset_phy ();
961#endif
962
fe8c2806 963#ifdef CONFIG_POST
6dff5529 964 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
965#endif
966
7def6b34
JL
967#if defined(CONFIG_CMD_PCMCIA) \
968 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
969 WATCHDOG_RESET ();
970 puts ("PCMCIA:");
971 pcmcia_init ();
972#endif
973
7def6b34 974#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
975 WATCHDOG_RESET ();
976# ifdef CONFIG_IDE_8xx_PCCARD
977 puts ("PCMCIA:");
978# else
979 puts ("IDE: ");
980#endif
ca43ba18
HS
981#if defined(CONFIG_START_IDE)
982 if (board_start_ide())
983 ide_init ();
984#else
fe8c2806 985 ide_init ();
ca43ba18 986#endif
b3aff0cb 987#endif
fe8c2806
WD
988
989#ifdef CONFIG_LAST_STAGE_INIT
990 WATCHDOG_RESET ();
991 /*
992 * Some parts can be only initialized if all others (like
993 * Interrupts) are up and running (i.e. the PC-style ISA
994 * keyboard).
995 */
996 last_stage_init ();
997#endif
998
7def6b34 999#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1000 WATCHDOG_RESET ();
1001 bedbug_init ();
1002#endif
1003
228f29ac 1004#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1005 /*
1006 * Export available size of memory for Linux,
1007 * taking into account the protected RAM at top of memory
1008 */
1009 {
1010 ulong pram;
fe8c2806 1011 uchar memsz[32];
228f29ac
WD
1012#ifdef CONFIG_PRAM
1013 char *s;
fe8c2806
WD
1014
1015 if ((s = getenv ("pram")) != NULL) {
1016 pram = simple_strtoul (s, NULL, 10);
1017 } else {
1018 pram = CONFIG_PRAM;
1019 }
228f29ac
WD
1020#else
1021 pram=0;
1022#endif
1023#ifdef CONFIG_LOGBUFFER
3d610186 1024#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1025 /* Also take the logbuffer into account (pram is in kB) */
1026 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1027#endif
228f29ac 1028#endif
77ddac94
WD
1029 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1030 setenv ("mem", (char *)memsz);
fe8c2806
WD
1031 }
1032#endif
1033
1c43771b
WD
1034#ifdef CONFIG_PS2KBD
1035 puts ("PS/2: ");
1036 kbd_init();
1037#endif
1038
4532cb69
WD
1039#ifdef CONFIG_MODEM_SUPPORT
1040 {
1041 extern int do_mdm_init;
1042 do_mdm_init = gd->do_mdm_init;
1043 }
1044#endif
1045
fe8c2806
WD
1046 /* Initialization complete - start the monitor */
1047
1048 /* main_loop() can return to retry autoboot, if so just run it again. */
1049 for (;;) {
1050 WATCHDOG_RESET ();
1051 main_loop ();
1052 }
1053
1054 /* NOTREACHED - no way out of command loop except booting */
1055}
1056
1057void hang (void)
1058{
1059 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1060 show_boot_progress(-30);
fe8c2806
WD
1061 for (;;);
1062}
1063
4532cb69 1064
fe8c2806
WD
1065#if 0 /* We could use plain global data, but the resulting code is bigger */
1066/*
1067 * Pointer to initial global data area
1068 *
1069 * Here we initialize it.
1070 */
1071#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1072#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
6d0f6bcf 1073DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
fe8c2806
WD
1074#endif /* 0 */
1075
1076/************************************************************************/