[people/ms/u-boot.git] / arch / ppc / cpu / mpc8xxx / ddr / options.c

/*
 * Copyright 2008, 2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */

#include <common.h>
#include <asm/fsl_ddr_sdram.h>

#include "ddr.h"

/* Board-specific functions defined in each board's ddr.c */
extern void fsl_ddr_board_options(memctl_options_t *popts,
		dimm_params_t *pdimm,
		unsigned int ctrl_num);

unsigned int populate_memctl_options(int all_DIMMs_registered,
			memctl_options_t *popts,
			dimm_params_t *pdimm,
			unsigned int ctrl_num)
{
	unsigned int i;
	const char *p;

	/* Chip select options. */

	/* Pick chip-select local options. */
	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
		/* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */

		/* only for single CS? */
		popts->cs_local_opts[i].odt_rd_cfg = 0;

		popts->cs_local_opts[i].odt_wr_cfg = 1;
		popts->cs_local_opts[i].auto_precharge = 0;
	}

	/* Pick interleaving mode. */

	/*
	 * 0 = no interleaving
	 * 1 = interleaving between 2 controllers
	 */
	popts->memctl_interleaving = 0;

	/*
	 * 0 = cacheline
	 * 1 = page
	 * 2 = (logical) bank
	 * 3 = superbank (only if CS interleaving is enabled)
	 */
	popts->memctl_interleaving_mode = 0;

	/*
	 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
	 * 1: page:      bit to the left of the column bits selects the memctl
	 * 2: bank:      bit to the left of the bank bits selects the memctl
	 * 3: superbank: bit to the left of the chip select selects the memctl
	 *
	 * NOTE: ba_intlv (rank interleaving) is independent of memory
	 * controller interleaving; it is only within a memory controller.
	 * Must use superbank interleaving if rank interleaving is used and
	 * memory controller interleaving is enabled.
	 */

	/*
	 * 0 = no
	 * 0x40 = CS0,CS1
	 * 0x20 = CS2,CS3
	 * 0x60 = CS0,CS1 + CS2,CS3
	 * 0x04 = CS0,CS1,CS2,CS3
	 */
	popts->ba_intlv_ctl = 0;

	/* Memory Organization Parameters */
	popts->registered_dimm_en = all_DIMMs_registered;

	/* Operational Mode Paramters */

	/* Pick ECC modes */
#ifdef CONFIG_DDR_ECC
	popts->ECC_mode = 1;		  /* 0 = disabled, 1 = enabled */
#else
	popts->ECC_mode = 0;		  /* 0 = disabled, 1 = enabled */
#endif
	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */

	/*
	 * Choose DQS config
	 * 0 for DDR1
	 * 1 for DDR2
	 */
#if defined(CONFIG_FSL_DDR1)
	popts->DQS_config = 0;
#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
	popts->DQS_config = 1;
#endif

	/* Choose self-refresh during sleep. */
	popts->self_refresh_in_sleep = 1;

	/* Choose dynamic power management mode. */
	popts->dynamic_power = 0;

	/* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
	popts->data_bus_width = 0;

	/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)
	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
#else
	popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
	popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
#endif
#else
	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
#endif

	/* Choose ddr controller address mirror mode */
#if defined(CONFIG_FSL_DDR3)
	popts->mirrored_dimm = pdimm[0].mirrored_dimm;
#endif

	/* Global Timing Parameters. */
	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());

	/* Pick a caslat override. */
	popts->cas_latency_override = 0;
	popts->cas_latency_override_value = 3;
	if (popts->cas_latency_override) {
		debug("using caslat override value = %u\n",
		       popts->cas_latency_override_value);
	}

	/* Decide whether to use the computed derated latency */
	popts->use_derated_caslat = 0;

	/* Choose an additive latency. */
	popts->additive_latency_override = 0;
	popts->additive_latency_override_value = 3;
	if (popts->additive_latency_override) {
		debug("using additive latency override value = %u\n",
		       popts->additive_latency_override_value);
	}

	/*
	 * 2T_EN setting
	 *
	 * Factors to consider for 2T_EN:
	 *	- number of DIMMs installed
	 *	- number of components, number of active ranks
	 *	- how much time you want to spend playing around
	 */
	popts->twoT_en = 0;
	popts->threeT_en = 0;

	/*
	 * BSTTOPRE precharge interval
	 *
	 * Set this to 0 for global auto precharge
	 *
	 * FIXME: Should this be configured in picoseconds?
	 * Why it should be in ps:  better understanding of this
	 * relative to actual DRAM timing parameters such as tRAS.
	 * e.g. tRAS(min) = 40 ns
	 */
	popts->bstopre = 0x100;

	/* Minimum CKE pulse width -- tCKE(MIN) */
	popts->tCKE_clock_pulse_width_ps
		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);

	/*
	 * Window for four activates -- tFAW
	 *
	 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
	 * FIXME: varies depending upon number of column addresses or data
	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
	 */
#if defined(CONFIG_FSL_DDR1)
	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);

#elif defined(CONFIG_FSL_DDR2)
	/*
	 * x4/x8;  some datasheets have 35000
	 * x16 wide columns only?  Use 50000?
	 */
	popts->tFAW_window_four_activates_ps = 37500;

#elif defined(CONFIG_FSL_DDR3)
	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
#endif
	popts->zq_en = 0;
	popts->wrlvl_en = 0;
#if defined(CONFIG_FSL_DDR3)
	/*
	 * due to ddr3 dimm is fly-by topology
	 * we suggest to enable write leveling to
	 * meet the tQDSS under different loading.
	 */
	popts->wrlvl_en = 1;
	popts->wrlvl_override = 0;
#endif

	/*
	 * Check interleaving configuration from environment.
	 * Please refer to doc/README.fsl-ddr for the detail.
	 *
	 * If memory controller interleaving is enabled, then the data
	 * bus widths must be programmed identically for the 2 memory
	 * controllers.
	 *
	 * XXX: Attempt to set both controllers to the same chip select
	 * interleaving mode. It will do a best effort to get the
	 * requested ranks interleaved together such that the result
	 * should be a subset of the requested configuration.
	 */
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
	if ((p = getenv("memctl_intlv_ctl")) != NULL) {
		if (pdimm[0].n_ranks == 0) {
			printf("There is no rank on CS0. Because only rank on "
				"CS0 and ranks chip-select interleaved with CS0"
				" are controller interleaved, force non memory "
				"controller interleaving\n");
			popts->memctl_interleaving = 0;
		} else {
			popts->memctl_interleaving = 1;
			if (strcmp(p, "cacheline") == 0)
				popts->memctl_interleaving_mode =
					FSL_DDR_CACHE_LINE_INTERLEAVING;
			else if (strcmp(p, "page") == 0)
				popts->memctl_interleaving_mode =
					FSL_DDR_PAGE_INTERLEAVING;
			else if (strcmp(p, "bank") == 0)
				popts->memctl_interleaving_mode =
					FSL_DDR_BANK_INTERLEAVING;
			else if (strcmp(p, "superbank") == 0)
				popts->memctl_interleaving_mode =
					FSL_DDR_SUPERBANK_INTERLEAVING;
			else
				popts->memctl_interleaving_mode =
						simple_strtoul(p, NULL, 0);
		}
	}
#endif

	if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
		if (strcmp(p, "cs0_cs1") == 0)
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
		else if (strcmp(p, "cs2_cs3") == 0)
			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
		else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
		else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
		else
			popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);

		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
		case FSL_DDR_CS0_CS1_CS2_CS3:
		case FSL_DDR_CS0_CS1:
			if (pdimm[0].n_ranks != 2) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for "
					"CS0+CS1, force non-interleaving!\n");
			}
			break;
		case FSL_DDR_CS2_CS3:
			if (pdimm[1].n_ranks !=2){
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(CS) for CS2+CS3, "
					"force non-interleaving!\n");
			}
			break;
		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
			if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(CS) for CS0+CS1 or "
					"CS2+CS3, force non-interleaving!\n");
			}
			break;
		default:
			popts->ba_intlv_ctl = 0;
			break;
		}
	}

	fsl_ddr_board_options(popts, pdimm, ctrl_num);

	return 0;
}
Commit	Line	Data
58e5e9af	1	/*
22c9de06	2	* Copyright 2008, 2010 Freescale Semiconductor, Inc.
58e5e9af	3	*
22c9de06 DL	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
58e5e9af KG	8	*/
	9
	10	#include <common.h>
	11	#include <asm/fsl_ddr_sdram.h>
	12
	13	#include "ddr.h"
	14
	15	/* Board-specific functions defined in each board's ddr.c */
	16	extern void fsl_ddr_board_options(memctl_options_t *popts,
dfb49108	17	dimm_params_t *pdimm,
58e5e9af KG	18	unsigned int ctrl_num);
	19
	20	unsigned int populate_memctl_options(int all_DIMMs_registered,
	21	memctl_options_t *popts,
dfb49108	22	dimm_params_t *pdimm,
58e5e9af KG	23	unsigned int ctrl_num)
	24	{
	25	unsigned int i;
c9ffd839	26	const char *p;
58e5e9af KG	27
	28	/* Chip select options. */
	29
	30	/* Pick chip-select local options. */
	31	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
	32	/* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
	33
	34	/* only for single CS? */
	35	popts->cs_local_opts[i].odt_rd_cfg = 0;
	36
	37	popts->cs_local_opts[i].odt_wr_cfg = 1;
	38	popts->cs_local_opts[i].auto_precharge = 0;
	39	}
	40
	41	/* Pick interleaving mode. */
	42
	43	/*
	44	* 0 = no interleaving
	45	* 1 = interleaving between 2 controllers
	46	*/
	47	popts->memctl_interleaving = 0;
	48
	49	/*
	50	* 0 = cacheline
	51	* 1 = page
	52	* 2 = (logical) bank
	53	* 3 = superbank (only if CS interleaving is enabled)
	54	*/
	55	popts->memctl_interleaving_mode = 0;
	56
	57	/*
	58	* 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
	59	* 1: page: bit to the left of the column bits selects the memctl
	60	* 2: bank: bit to the left of the bank bits selects the memctl
	61	* 3: superbank: bit to the left of the chip select selects the memctl
	62	*
	63	* NOTE: ba_intlv (rank interleaving) is independent of memory
	64	* controller interleaving; it is only within a memory controller.
	65	* Must use superbank interleaving if rank interleaving is used and
	66	* memory controller interleaving is enabled.
	67	*/
	68
	69	/*
	70	* 0 = no
	71	* 0x40 = CS0,CS1
	72	* 0x20 = CS2,CS3
	73	* 0x60 = CS0,CS1 + CS2,CS3
	74	* 0x04 = CS0,CS1,CS2,CS3
	75	*/
	76	popts->ba_intlv_ctl = 0;
	77
	78	/* Memory Organization Parameters */
	79	popts->registered_dimm_en = all_DIMMs_registered;
	80
	81	/* Operational Mode Paramters */
	82
	83	/* Pick ECC modes */
	84	#ifdef CONFIG_DDR_ECC
	85	popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
	86	#else
	87	popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
	88	#endif
	89	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
	90
91	/*
92	* Choose DQS config
93	* 0 for DDR1
94	* 1 for DDR2
95	*/
96	#if defined(CONFIG_FSL_DDR1)
97	popts->DQS_config = 0;
c360ceac	98	#elif defined(CONFIG_FSL_DDR2) \|\| defined(CONFIG_FSL_DDR3)
58e5e9af	99	popts->DQS_config = 1;
58e5e9af KG	100	#endif
	101
	102	/* Choose self-refresh during sleep. */
	103	popts->self_refresh_in_sleep = 1;
	104
	105	/* Choose dynamic power management mode. */
	106	popts->dynamic_power = 0;
	107
	108	/* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
	109	popts->data_bus_width = 0;
	110
	111	/* Choose burst length. */
c360ceac	112	#if defined(CONFIG_FSL_DDR3)
22c9de06 DL	113	#if defined(CONFIG_E500MC)
	114	popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
	115	popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
	116	#else
c360ceac DL	117	popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
c360ceac DL	118	popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
22c9de06	119	#endif
c360ceac DL	120	#else
	121	popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
	122	#endif
	123
	124	/* Choose ddr controller address mirror mode */
	125	#if defined(CONFIG_FSL_DDR3)
	126	popts->mirrored_dimm = pdimm[0].mirrored_dimm;
	127	#endif
58e5e9af KG	128
	129	/* Global Timing Parameters. */
	130	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
	131
	132	/* Pick a caslat override. */
	133	popts->cas_latency_override = 0;
	134	popts->cas_latency_override_value = 3;
	135	if (popts->cas_latency_override) {
	136	debug("using caslat override value = %u\n",
	137	popts->cas_latency_override_value);
	138	}
	139
	140	/* Decide whether to use the computed derated latency */
	141	popts->use_derated_caslat = 0;
	142
	143	/* Choose an additive latency. */
	144	popts->additive_latency_override = 0;
	145	popts->additive_latency_override_value = 3;
	146	if (popts->additive_latency_override) {
	147	debug("using additive latency override value = %u\n",
	148	popts->additive_latency_override_value);
	149	}
	150
	151	/*
	152	* 2T_EN setting
	153	*
	154	* Factors to consider for 2T_EN:
	155	* - number of DIMMs installed
	156	* - number of components, number of active ranks
	157	* - how much time you want to spend playing around
	158	*/
b4983e16	159	popts->twoT_en = 0;
58e5e9af KG	160	popts->threeT_en = 0;
	161
	162	/*
	163	* BSTTOPRE precharge interval
	164	*
	165	* Set this to 0 for global auto precharge
	166	*
	167	* FIXME: Should this be configured in picoseconds?
	168	* Why it should be in ps: better understanding of this
	169	* relative to actual DRAM timing parameters such as tRAS.
	170	* e.g. tRAS(min) = 40 ns
	171	*/
	172	popts->bstopre = 0x100;
	173
	174	/* Minimum CKE pulse width -- tCKE(MIN) */
	175	popts->tCKE_clock_pulse_width_ps
	176	= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
	177
	178	/*
	179	* Window for four activates -- tFAW
	180	*
	181	* FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
	182	* FIXME: varies depending upon number of column addresses or data
	183	* FIXME: width, was considering looking at pdimm->primary_sdram_width
	184	*/
	185	#if defined(CONFIG_FSL_DDR1)
	186	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
	187
	188	#elif defined(CONFIG_FSL_DDR2)
	189	/*
	190	* x4/x8; some datasheets have 35000
	191	* x16 wide columns only? Use 50000?
	192	*/
	193	popts->tFAW_window_four_activates_ps = 37500;
	194
	195	#elif defined(CONFIG_FSL_DDR3)
c360ceac DL	196	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
	197	#endif
	198	popts->zq_en = 0;
	199	popts->wrlvl_en = 0;
	200	#if defined(CONFIG_FSL_DDR3)
	201	/*
	202	* due to ddr3 dimm is fly-by topology
	203	* we suggest to enable write leveling to
	204	* meet the tQDSS under different loading.
	205	*/
	206	popts->wrlvl_en = 1;
bdc9f7b5	207	popts->wrlvl_override = 0;
58e5e9af KG	208	#endif
58e5e9af KG	209
58e5e9af	210	/*
c9ffd839 HW	211	* Check interleaving configuration from environment.
c9ffd839 HW	212	* Please refer to doc/README.fsl-ddr for the detail.
58e5e9af KG	213	*
	214	* If memory controller interleaving is enabled, then the data
	215	* bus widths must be programmed identically for the 2 memory
	216	* controllers.
c9ffd839 HW	217	*
	218	* XXX: Attempt to set both controllers to the same chip select
	219	* interleaving mode. It will do a best effort to get the
	220	* requested ranks interleaved together such that the result
	221	* should be a subset of the requested configuration.
58e5e9af	222	*/
1542fbde	223	#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
c9ffd839 HW	224	if ((p = getenv("memctl_intlv_ctl")) != NULL) {
c9ffd839 HW	225	if (pdimm[0].n_ranks == 0) {
7008d26a ES	226	printf("There is no rank on CS0. Because only rank on "
	227	"CS0 and ranks chip-select interleaved with CS0"
	228	" are controller interleaved, force non memory "
	229	"controller interleaving\n");
c9ffd839 HW	230	popts->memctl_interleaving = 0;
	231	} else {
	232	popts->memctl_interleaving = 1;
	233	if (strcmp(p, "cacheline") == 0)
	234	popts->memctl_interleaving_mode =
	235	FSL_DDR_CACHE_LINE_INTERLEAVING;
	236	else if (strcmp(p, "page") == 0)
	237	popts->memctl_interleaving_mode =
	238	FSL_DDR_PAGE_INTERLEAVING;
	239	else if (strcmp(p, "bank") == 0)
	240	popts->memctl_interleaving_mode =
	241	FSL_DDR_BANK_INTERLEAVING;
	242	else if (strcmp(p, "superbank") == 0)
	243	popts->memctl_interleaving_mode =
	244	FSL_DDR_SUPERBANK_INTERLEAVING;
	245	else
	246	popts->memctl_interleaving_mode =
	247	simple_strtoul(p, NULL, 0);
	248	}
	249	}
3ad95deb	250	#endif
c9ffd839	251
3ad95deb DL	252	if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
3ad95deb DL	253	(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
c9ffd839 HW	254	if (strcmp(p, "cs0_cs1") == 0)
	255	popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
	256	else if (strcmp(p, "cs2_cs3") == 0)
	257	popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
	258	else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
	259	popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
	260	else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
	261	popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
	262	else
	263	popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
	264
	265	switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
	266	case FSL_DDR_CS0_CS1_CS2_CS3:
	267	case FSL_DDR_CS0_CS1:
	268	if (pdimm[0].n_ranks != 2) {
	269	popts->ba_intlv_ctl = 0;
7008d26a ES	270	printf("Not enough bank(chip-select) for "
7008d26a ES	271	"CS0+CS1, force non-interleaving!\n");
c9ffd839 HW	272	}
	273	break;
	274	case FSL_DDR_CS2_CS3:
	275	if (pdimm[1].n_ranks !=2){
	276	popts->ba_intlv_ctl = 0;
7008d26a ES	277	printf("Not enough bank(CS) for CS2+CS3, "
7008d26a ES	278	"force non-interleaving!\n");
c9ffd839 HW	279	}
	280	break;
	281	case FSL_DDR_CS0_CS1_AND_CS2_CS3:
	282	if ((pdimm[0].n_ranks != 2)\|\|(pdimm[1].n_ranks != 2)) {
	283	popts->ba_intlv_ctl = 0;
7008d26a ES	284	printf("Not enough bank(CS) for CS0+CS1 or "
7008d26a ES	285	"CS2+CS3, force non-interleaving!\n");
c9ffd839 HW	286	}
	287	break;
	288	default:
	289	popts->ba_intlv_ctl = 0;
	290	break;
	291	}
	292	}
58e5e9af	293
dfb49108	294	fsl_ddr_board_options(popts, pdimm, ctrl_num);
58e5e9af KG	295
	296	return 0;
	297	}