[thirdparty/u-boot.git] / arch / riscv / Kconfig

menu "RISC-V architecture"
	depends on RISCV

config SYS_ARCH
	default "riscv"

choice
	prompt "Target select"
	optional

config TARGET_ANDES_AE350
	bool "Support Andes ae350"

config TARGET_MICROCHIP_ICICLE
	bool "Support Microchip PolarFire-SoC Icicle Board"

config TARGET_MILKV_DUO
	bool "Support Milk-v Duo Board"

config TARGET_OPENPITON_RISCV64
	bool "Support RISC-V cores on OpenPiton SoC"

config TARGET_QEMU_VIRT
	bool "Support QEMU Virt Board"
	select BOARD_LATE_INIT

config TARGET_SIFIVE_UNLEASHED
	bool "Support SiFive Unleashed Board"

config TARGET_SIFIVE_UNMATCHED
	bool "Support SiFive Unmatched Board"
	select SYS_CACHE_SHIFT_6

config TARGET_SIPEED_MAIX
	bool "Support Sipeed Maix Board"
	select SYS_CACHE_SHIFT_6

config TARGET_STARFIVE_VISIONFIVE2
	bool "Support StarFive VisionFive2 Board"
	select BOARD_LATE_INIT

config TARGET_TH1520_LPI4A
	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
	select SYS_CACHE_SHIFT_6

config TARGET_XILINX_MBV
	bool "Support AMD/Xilinx MicroBlaze V"

endchoice

config SYS_ICACHE_OFF
	bool "Do not enable icache"
	help
	  Do not enable instruction cache in U-Boot.

config SPL_SYS_ICACHE_OFF
	bool "Do not enable icache in SPL"
	depends on SPL
	default SYS_ICACHE_OFF
	help
	  Do not enable instruction cache in SPL.

config SYS_DCACHE_OFF
	bool "Do not enable dcache"
	help
	  Do not enable data cache in U-Boot.

config SPL_SYS_DCACHE_OFF
	bool "Do not enable dcache in SPL"
	depends on SPL
	default SYS_DCACHE_OFF
	help
	  Do not enable data cache in SPL.

config SPL_ZERO_MEM_BEFORE_USE
	bool "Zero memory before use"
	depends on SPL
	help
	  Zero stack/GD/malloc area in SPL before using them, this is needed for
	  Sifive core devices that uses L2 cache to store SPL.

# board-specific options below
source "board/andestech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
source "board/sophgo/milkv_duo/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"

# platform-specific options below
source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"

# architecture-specific options below

choice
	prompt "Base ISA"
	default ARCH_RV32I

config ARCH_RV32I
	bool "RV32I"
	select 32BIT
	help
	  Choose this option to target the RV32I base integer instruction set.

config ARCH_RV64I
	bool "RV64I"
	select 64BIT
	select PHYS_64BIT
	help
	  Choose this option to target the RV64I base integer instruction set.

endchoice

config FRAMEPOINTER
	bool "Build with frame pointer for stack unwinding"
	help
	  Choose this option to use the frame pointer so the stack can be
	  unwound if needed. This is useful for tracing where faults came
	  from as the source may be several functions back

	  If you say Y here, then the code size will be increased due to
	  having to store the fp.

config SPL_FRAMEPOINTER
	bool "Build SPL with frame pointer for stack unwinding"
	help
	  Choose this option to use the frame pointer so the stack can be
	  unwound if needed. This is useful for tracing where faults came
	  from as the source may be several functions back

	  If you say Y here, then the code size will be increased due to
	  having to store the fp.

choice
	prompt "Code Model"
	default CMODEL_MEDLOW

config CMODEL_MEDLOW
	bool "medium low code model"
	help
	  U-Boot and its statically defined symbols must lie within a single 2 GiB
	  address range and must lie between absolute addresses -2 GiB and +2 GiB.

config CMODEL_MEDANY
	bool "medium any code model"
	help
	  U-Boot and its statically defined symbols must be within any single 2 GiB
	  address range.

endchoice

choice
	prompt "Run Mode"
	default RISCV_MMODE

config RISCV_MMODE
	bool "Machine"
	help
	  Choose this option to build U-Boot for RISC-V M-Mode.

config RISCV_SMODE
	bool "Supervisor"
	imply DEBUG_UART
	help
	  Choose this option to build U-Boot for RISC-V S-Mode.

endchoice

choice
	prompt "SPL Run Mode"
	default SPL_RISCV_MMODE
	depends on SPL

config SPL_RISCV_MMODE
	bool "Machine"
	help
	  Choose this option to build U-Boot SPL for RISC-V M-Mode.

config SPL_RISCV_SMODE
	bool "Supervisor"
	help
	  Choose this option to build U-Boot SPL for RISC-V S-Mode.

endchoice

config RISCV_ISA_C
	bool "Emit compressed instructions"
	default y
	help
	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
	  when building U-Boot, which results in compressed instructions in the
	  U-Boot binary.

config RISCV_ISA_F
	bool "Standard extension for Single-Precision Floating Point"
	default y
	help
	  Adds "F" to the ISA string passed to the compiler.

config RISCV_ISA_D
	bool "Standard extension for Double-Precision Floating Point"
	depends on RISCV_ISA_F
	default y
	help
	  Adds "D" to the ISA string passed to the compiler and changes the
	  riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
	  lp64d.

config RISCV_ISA_ZBB
	bool "Zbb extension support for bit manipulation instructions"
	help
	  Adds ZBB extension (basic bit manipulation) to the ISA subsets
	  that the toolchain is allowed to emit when building U-Boot.
	  The Zbb extension provides instructions to accelerate a number
	  of bit-specific operations (count bit population, sign extending,
	  bitrotation, etc) and enables optimized string routines.

menu "Use assembly optimized implementation of string routines"

config USE_ARCH_STRLEN
	bool "Use an assembly optimized implementation of strlen"
	default y
	depends on RISCV_ISA_ZBB
	help
	  Enable the generation of an optimized version of strlen using
	  Zbb extension.

config SPL_USE_ARCH_STRLEN
	bool "Use an assembly optimized implementation of strlen for SPL"
	default y if USE_ARCH_STRLEN
	depends on RISCV_ISA_ZBB
	depends on SPL
	help
	  Enable the generation of an optimized version of strlen using
	  Zbb extension.

config TPL_USE_ARCH_STRLEN
	bool "Use an assembly optimized implementation of strlen for TPL"
	default y if USE_ARCH_STRLEN
	depends on RISCV_ISA_ZBB
	depends on TPL
	help
	  Enable the generation of an optimized version of strlen using
	  Zbb extension.

config USE_ARCH_STRCMP
	bool "Use an assembly optimized implementation of strcmp"
	default y
	depends on RISCV_ISA_ZBB
	help
	  Enable the generation of an optimized version of strcmp using
	  Zbb extension.

config SPL_USE_ARCH_STRCMP
	bool "Use an assembly optimized implementation of strcmp for SPL"
	default y if USE_ARCH_STRCMP
	depends on RISCV_ISA_ZBB
	depends on SPL
	help
	  Enable the generation of an optimized version of strcmp using
	  Zbb extension.

config TPL_USE_ARCH_STRCMP
	bool "Use an assembly optimized implementation of strcmp for TPL"
	default y if USE_ARCH_STRCMP
	depends on RISCV_ISA_ZBB
	depends on TPL
	help
	  Enable the generation of an optimized version of strcmp using
	  Zbb extension.

config USE_ARCH_STRNCMP
	bool "Use an assembly optimized implementation of strncmp"
	default y
	depends on RISCV_ISA_ZBB
	help
	  Enable the generation of an optimized version of strncmp using
	  Zbb extension.

config SPL_USE_ARCH_STRNCMP
	bool "Use an assembly optimized implementation of strncmp for SPL"
	default y if USE_ARCH_STRNCMP
	depends on RISCV_ISA_ZBB
	depends on SPL
	help
	  Enable the generation of an optimized version of strncmp using
	  Zbb extension.

config TPL_USE_ARCH_STRNCMP
	bool "Use an assembly optimized implementation of strncmp for TPL"
	default y if USE_ARCH_STRNCMP
	depends on RISCV_ISA_ZBB
	depends on TPL
	help
	  Enable the generation of an optimized version of strncmp using
	  Zbb extension.

endmenu

config RISCV_ISA_A
	def_bool y

config DMA_ADDR_T_64BIT
	bool
	default y if 64BIT

config RISCV_ACLINT
	bool
	depends on RISCV_MMODE
	select REGMAP
	select SYSCON
	help
	  The RISC-V ACLINT block holds memory-mapped control and status registers
	  associated with software and timer interrupts.

config SPL_RISCV_ACLINT
	bool
	depends on SPL_RISCV_MMODE
	select SPL_REGMAP
	select SPL_SYSCON
	help
	  The RISC-V ACLINT block holds memory-mapped control and status registers
	  associated with software and timer interrupts.

config SIFIVE_CACHE
	bool
	help
	  This enables the operations to configure SiFive cache

config ANDES_PLICSW
	bool
	depends on RISCV_MMODE || SPL_RISCV_MMODE
	select REGMAP
	select SYSCON
	select SPL_REGMAP if SPL
	select SPL_SYSCON if SPL
	help
	  The Andes PLICSW block holds memory-mapped claim and pending
	  registers associated with software interrupt.

config SMP
	bool "Symmetric Multi-Processing"
	depends on SBI_V01 || !RISCV_SMODE
	help
	  This enables support for systems with more than one CPU. If
	  you say N here, U-Boot will run on single and multiprocessor
	  machines, but will use only one CPU of a multiprocessor
	  machine. If you say Y here, U-Boot will run on many, but not
	  all, single processor machines.

config SPL_SMP
	bool "Symmetric Multi-Processing in SPL"
	depends on SPL && SPL_RISCV_MMODE
	default y
	help
	  This enables support for systems with more than one CPU in SPL.
	  If you say N here, U-Boot SPL will run on single and multiprocessor
	  machines, but will use only one CPU of a multiprocessor
	  machine. If you say Y here, U-Boot SPL will run on many, but not
	  all, single processor machines.

config NR_CPUS
	int "Maximum number of CPUs (2-32)"
	range 2 32
	depends on SMP || SPL_SMP
	default 8
	help
	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
	  Stack memory is pre-allocated. U-Boot must therefore know the
	  maximum number of CPUs that may be present.

config SBI
	bool
	default y if RISCV_SMODE || SPL_RISCV_SMODE

choice
	prompt "SBI support"
	default SBI_V02

config SBI_V01
	bool "SBI v0.1 support"
	depends on SBI
	help
	  This config allows kernel to use SBI v0.1 APIs. This will be
	  deprecated in future once legacy M-mode software are no longer in use.

config SBI_V02
	bool "SBI v0.2 or later support"
	depends on SBI
	help
	  The SBI specification introduced the concept of extensions in version
	  v0.2. With this configuration option U-Boot can detect and use SBI
	  extensions. With the HSM extension introduced in SBI 0.2, only a
	  single hart needs to boot and enter the operating system. The booting
	  hart can bring up secondary harts one by one afterwards.

	  Choose this option if OpenSBI release v0.7 or above is used together
	  with U-Boot.

endchoice

config SBI_IPI
	bool
	depends on SBI
	default y if RISCV_SMODE || SPL_RISCV_SMODE
	depends on SMP

config XIP
	bool "XIP mode"
	help
	  XIP (eXecute In Place) is a method for executing code directly
	  from a NOR flash memory without copying the code to ram.
	  Say yes here if U-Boot boots from flash directly.

config SPL_XIP
	bool "Enable XIP mode for SPL"
	help
	  If SPL starts in read-only memory (XIP for example) then we shouldn't
	  rely on lock variables (for example hart_lottery and available_harts_lock),
	  this affects only SPL, other stages should proceed as non-XIP.

config AVAILABLE_HARTS
	bool "Send IPI by available harts"
	default y
	help
	  By default, IPI sending mechanism will depend on available_harts.
	  If disable this, it will send IPI by CPUs node numbers of device tree.

config SHOW_REGS
	bool "Show registers on unhandled exception"

config RISCV_PRIV_1_9
	bool "Use version 1.9 of the RISC-V priviledged specification"
	help
	  Older versions of the RISC-V priviledged specification had
	  separate counter enable CSRs for each privilege mode. Writing
	  to the unified mcounteren CSR on a processor implementing the
	  old specification will result in an illegal instruction
	  exception. In addition to counter CSR changes, the way virtual
	  memory is configured was also changed.

config STACK_SIZE_SHIFT
	int
	default 14

config OF_BOARD_FIXUP
	default y if OF_SEPARATE && RISCV_SMODE

menu "Use assembly optimized implementation of memory routines"

config USE_ARCH_MEMCPY
	bool "Use an assembly optimized implementation of memcpy"
	default y
	help
	  Enable the generation of an optimized version of memcpy.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config SPL_USE_ARCH_MEMCPY
	bool "Use an assembly optimized implementation of memcpy for SPL"
	default y if USE_ARCH_MEMCPY
	depends on SPL
	help
	  Enable the generation of an optimized version of memcpy.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config TPL_USE_ARCH_MEMCPY
	bool "Use an assembly optimized implementation of memcpy for TPL"
	default y if USE_ARCH_MEMCPY
	depends on TPL
	help
	  Enable the generation of an optimized version of memcpy.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config USE_ARCH_MEMMOVE
	bool "Use an assembly optimized implementation of memmove"
	default y
	help
	  Enable the generation of an optimized version of memmove.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config SPL_USE_ARCH_MEMMOVE
	bool "Use an assembly optimized implementation of memmove for SPL"
	default y if USE_ARCH_MEMCPY
	depends on SPL
	help
	  Enable the generation of an optimized version of memmove.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config TPL_USE_ARCH_MEMMOVE
	bool "Use an assembly optimized implementation of memmove for TPL"
	default y if USE_ARCH_MEMCPY
	depends on TPL
	help
	  Enable the generation of an optimized version of memmove.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config USE_ARCH_MEMSET
	bool "Use an assembly optimized implementation of memset"
	default y
	help
	  Enable the generation of an optimized version of memset.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config SPL_USE_ARCH_MEMSET
	bool "Use an assembly optimized implementation of memset for SPL"
	default y if USE_ARCH_MEMSET
	depends on SPL
	help
	  Enable the generation of an optimized version of memset.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

config TPL_USE_ARCH_MEMSET
	bool "Use an assembly optimized implementation of memset for TPL"
	default y if USE_ARCH_MEMSET
	depends on TPL
	help
	  Enable the generation of an optimized version of memset.
	  Such an implementation may be faster under some conditions
	  but may increase the binary size.

endmenu

config SPL_LOAD_FIT_OPENSBI_OS_BOOT
	bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
	depends on SPL_LOAD_FIT
	help
	  Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
	  This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
	  -> linux to u-boot SPL -> OpenSBI -> linux.

endmenu
Commit	Line	Data
117a433d	1	menu "RISC-V architecture"
f94c44e5 RC	2	depends on RISCV
	3
	4	config SYS_ARCH
	5	default "riscv"
	6
	7	choice
	8	prompt "Target select"
	9	optional
	10
b68bf22f R	11	config TARGET_ANDES_AE350
b68bf22f R	12	bool "Support Andes ae350"
f94c44e5	13
39494822 PB	14	config TARGET_MICROCHIP_ICICLE
	15	bool "Support Microchip PolarFire-SoC Icicle Board"
	16
0dc6ee6d KL	17	config TARGET_MILKV_DUO
	18	bool "Support Milk-v Duo Board"
	19
a6a77e47 SH	20	config TARGET_OPENPITON_RISCV64
	21	bool "Support RISC-V cores on OpenPiton SoC"
	22
510e379c BM	23	config TARGET_QEMU_VIRT
510e379c BM	24	bool "Support QEMU Virt Board"
c532ddde	25	select BOARD_LATE_INIT
510e379c	26
ae2d9506 BM	27	config TARGET_SIFIVE_UNLEASHED
ae2d9506 BM	28	bool "Support SiFive Unleashed Board"
3fda0262	29
70415e1e GW	30	config TARGET_SIFIVE_UNMATCHED
70415e1e GW	31	bool "Support SiFive Unmatched Board"
ab92b38a	32	select SYS_CACHE_SHIFT_6
70415e1e	33
a6a77e47 SH	34	config TARGET_SIPEED_MAIX
	35	bool "Support Sipeed Maix Board"
	36	select SYS_CACHE_SHIFT_6
	37
331ad93c YW	38	config TARGET_STARFIVE_VISIONFIVE2
331ad93c YW	39	bool "Support StarFive VisionFive2 Board"
16dbe3d9	40	select BOARD_LATE_INIT
331ad93c	41
5f3a7fdb YL	42	config TARGET_TH1520_LPI4A
	43	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
	44	select SYS_CACHE_SHIFT_6
	45
7576ab2f MS	46	config TARGET_XILINX_MBV
	47	bool "Support AMD/Xilinx MicroBlaze V"
	48
f94c44e5 RC	49	endchoice
f94c44e5 RC	50
a0aba8a2 TW	51	config SYS_ICACHE_OFF
a0aba8a2 TW	52	bool "Do not enable icache"
a0aba8a2 TW	53	help
	54	Do not enable instruction cache in U-Boot.
	55
10015025 TW	56	config SPL_SYS_ICACHE_OFF
	57	bool "Do not enable icache in SPL"
	58	depends on SPL
	59	default SYS_ICACHE_OFF
	60	help
	61	Do not enable instruction cache in SPL.
	62
a0aba8a2 TW	63	config SYS_DCACHE_OFF
a0aba8a2 TW	64	bool "Do not enable dcache"
a0aba8a2 TW	65	help
	66	Do not enable data cache in U-Boot.
	67
10015025 TW	68	config SPL_SYS_DCACHE_OFF
	69	bool "Do not enable dcache in SPL"
	70	depends on SPL
	71	default SYS_DCACHE_OFF
	72	help
	73	Do not enable data cache in SPL.
	74
d365f664 SQ	75	config SPL_ZERO_MEM_BEFORE_USE
	76	bool "Zero memory before use"
	77	depends on SPL
d365f664 SQ	78	help
	79	Zero stack/GD/malloc area in SPL before using them, this is needed for
	80	Sifive core devices that uses L2 cache to store SPL.
	81
52923c6d	82	# board-specific options below
2b8dc36b	83	source "board/andestech/ae350/Kconfig"
510e379c	84	source "board/emulation/qemu-riscv/Kconfig"
39494822	85	source "board/microchip/mpfs_icicle/Kconfig"
a6a77e47	86	source "board/openpiton/riscv64/Kconfig"
ae2d9506	87	source "board/sifive/unleashed/Kconfig"
70415e1e	88	source "board/sifive/unmatched/Kconfig"
a7c81fc8	89	source "board/sipeed/maix/Kconfig"
0dc6ee6d	90	source "board/sophgo/milkv_duo/Kconfig"
331ad93c	91	source "board/starfive/visionfive2/Kconfig"
a6a77e47	92	source "board/thead/th1520_lpi4a/Kconfig"
7576ab2f	93	source "board/xilinx/mbv/Kconfig"
f94c44e5	94
52923c6d	95	# platform-specific options below
2b8dc36b	96	source "arch/riscv/cpu/andes/Kconfig"
ae800aa7	97	source "arch/riscv/cpu/cv1800b/Kconfig"
7c45fc98	98	source "arch/riscv/cpu/fu540/Kconfig"
a74e9d89	99	source "arch/riscv/cpu/fu740/Kconfig"
fdff1f96	100	source "arch/riscv/cpu/generic/Kconfig"
331ad93c	101	source "arch/riscv/cpu/jh7110/Kconfig"
52923c6d RC	102
	103	# architecture-specific options below
	104
f94c44e5	105	choice
862e2e75 LA	106	prompt "Base ISA"
862e2e75 LA	107	default ARCH_RV32I
f94c44e5	108
862e2e75 LA	109	config ARCH_RV32I
862e2e75 LA	110	bool "RV32I"
f94c44e5 RC	111	select 32BIT
f94c44e5 RC	112	help
862e2e75	113	Choose this option to target the RV32I base integer instruction set.
f94c44e5	114
862e2e75 LA	115	config ARCH_RV64I
862e2e75 LA	116	bool "RV64I"
f94c44e5	117	select 64BIT
71158564	118	select PHYS_64BIT
f94c44e5	119	help
862e2e75	120	Choose this option to target the RV64I base integer instruction set.
f94c44e5 RC	121
	122	endchoice
	123
e4f69492 BD	124	config FRAMEPOINTER
	125	bool "Build with frame pointer for stack unwinding"
	126	help
	127	Choose this option to use the frame pointer so the stack can be
	128	unwound if needed. This is useful for tracing where faults came
	129	from as the source may be several functions back
	130
	131	If you say Y here, then the code size will be increased due to
	132	having to store the fp.
	133
	134	config SPL_FRAMEPOINTER
	135	bool "Build SPL with frame pointer for stack unwinding"
	136	help
	137	Choose this option to use the frame pointer so the stack can be
	138	unwound if needed. This is useful for tracing where faults came
	139	from as the source may be several functions back
	140
	141	If you say Y here, then the code size will be increased due to
	142	having to store the fp.
	143
8176ea4d LA	144	choice
	145	prompt "Code Model"
	146	default CMODEL_MEDLOW
	147
	148	config CMODEL_MEDLOW
	149	bool "medium low code model"
	150	help
	151	U-Boot and its statically defined symbols must lie within a single 2 GiB
	152	address range and must lie between absolute addresses -2 GiB and +2 GiB.
	153
	154	config CMODEL_MEDANY
	155	bool "medium any code model"
	156	help
	157	U-Boot and its statically defined symbols must be within any single 2 GiB
	158	address range.
	159
	160	endchoice
	161
3cfc8252 AP	162	choice
	163	prompt "Run Mode"
	164	default RISCV_MMODE
	165
	166	config RISCV_MMODE
	167	bool "Machine"
	168	help
	169	Choose this option to build U-Boot for RISC-V M-Mode.
	170
	171	config RISCV_SMODE
	172	bool "Supervisor"
e637e455	173	imply DEBUG_UART
3cfc8252 AP	174	help
	175	Choose this option to build U-Boot for RISC-V S-Mode.
	176
	177	endchoice
	178
fbfd92bf LA	179	choice
	180	prompt "SPL Run Mode"
	181	default SPL_RISCV_MMODE
	182	depends on SPL
	183
	184	config SPL_RISCV_MMODE
	185	bool "Machine"
	186	help
	187	Choose this option to build U-Boot SPL for RISC-V M-Mode.
	188
	189	config SPL_RISCV_SMODE
	190	bool "Supervisor"
	191	help
	192	Choose this option to build U-Boot SPL for RISC-V S-Mode.
	193
	194	endchoice
	195
d57ffa65 LA	196	config RISCV_ISA_C
	197	bool "Emit compressed instructions"
	198	default y
	199	help
	200	Adds "C" to the ISA subsets that the toolchain is allowed to emit
	201	when building U-Boot, which results in compressed instructions in the
	202	U-Boot binary.
	203
e67f34f7 HS	204	config RISCV_ISA_F
	205	bool "Standard extension for Single-Precision Floating Point"
	206	default y
	207	help
	208	Adds "F" to the ISA string passed to the compiler.
	209
	210	config RISCV_ISA_D
	211	bool "Standard extension for Double-Precision Floating Point"
	212	depends on RISCV_ISA_F
	213	default y
	214	help
	215	Adds "D" to the ISA string passed to the compiler and changes the
	216	riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
	217	lp64d.
	218
bc5a5045 YCPL	219	config RISCV_ISA_ZBB
	220	bool "Zbb extension support for bit manipulation instructions"
	221	help
	222	Adds ZBB extension (basic bit manipulation) to the ISA subsets
	223	that the toolchain is allowed to emit when building U-Boot.
	224	The Zbb extension provides instructions to accelerate a number
	225	of bit-specific operations (count bit population, sign extending,
	226	bitrotation, etc) and enables optimized string routines.
	227
	228	menu "Use assembly optimized implementation of string routines"
	229
	230	config USE_ARCH_STRLEN
	231	bool "Use an assembly optimized implementation of strlen"
	232	default y
	233	depends on RISCV_ISA_ZBB
	234	help
	235	Enable the generation of an optimized version of strlen using
	236	Zbb extension.
	237
	238	config SPL_USE_ARCH_STRLEN
	239	bool "Use an assembly optimized implementation of strlen for SPL"
	240	default y if USE_ARCH_STRLEN
	241	depends on RISCV_ISA_ZBB
	242	depends on SPL
	243	help
	244	Enable the generation of an optimized version of strlen using
	245	Zbb extension.
	246
	247	config TPL_USE_ARCH_STRLEN
	248	bool "Use an assembly optimized implementation of strlen for TPL"
	249	default y if USE_ARCH_STRLEN
	250	depends on RISCV_ISA_ZBB
	251	depends on TPL
	252	help
	253	Enable the generation of an optimized version of strlen using
	254	Zbb extension.
	255
	256	config USE_ARCH_STRCMP
	257	bool "Use an assembly optimized implementation of strcmp"
	258	default y
	259	depends on RISCV_ISA_ZBB
	260	help
	261	Enable the generation of an optimized version of strcmp using
	262	Zbb extension.
	263
	264	config SPL_USE_ARCH_STRCMP
	265	bool "Use an assembly optimized implementation of strcmp for SPL"
	266	default y if USE_ARCH_STRCMP
	267	depends on RISCV_ISA_ZBB
	268	depends on SPL
	269	help
	270	Enable the generation of an optimized version of strcmp using
	271	Zbb extension.
	272
	273	config TPL_USE_ARCH_STRCMP
	274	bool "Use an assembly optimized implementation of strcmp for TPL"
	275	default y if USE_ARCH_STRCMP
	276	depends on RISCV_ISA_ZBB
	277	depends on TPL
	278	help
	279	Enable the generation of an optimized version of strcmp using
	280	Zbb extension.
	281
	282	config USE_ARCH_STRNCMP
283	bool "Use an assembly optimized implementation of strncmp"
284	default y
285	depends on RISCV_ISA_ZBB
286	help
287	Enable the generation of an optimized version of strncmp using
288	Zbb extension.
289
290	config SPL_USE_ARCH_STRNCMP
291	bool "Use an assembly optimized implementation of strncmp for SPL"
292	default y if USE_ARCH_STRNCMP
293	depends on RISCV_ISA_ZBB
294	depends on SPL
295	help
296	Enable the generation of an optimized version of strncmp using
297	Zbb extension.
298
299	config TPL_USE_ARCH_STRNCMP
300	bool "Use an assembly optimized implementation of strncmp for TPL"
301	default y if USE_ARCH_STRNCMP
302	depends on RISCV_ISA_ZBB
303	depends on TPL
304	help
305	Enable the generation of an optimized version of strncmp using
306	Zbb extension.
307
308	endmenu
309
d57ffa65 LA	310	config RISCV_ISA_A
	311	def_bool y
	312
5af3574f PB	313	config DMA_ADDR_T_64BIT
	314	bool
	315	default y if 64BIT
	316
9675d920	317	config RISCV_ACLINT
644a3cd7	318	bool
a6d7e8c9	319	depends on RISCV_MMODE
7f1a30fd BM	320	select REGMAP
7f1a30fd BM	321	select SYSCON
a6d7e8c9	322	help
9675d920	323	The RISC-V ACLINT block holds memory-mapped control and status registers
a6d7e8c9 BM	324	associated with software and timer interrupts.
a6d7e8c9 BM	325
9675d920	326	config SPL_RISCV_ACLINT
a6d7e8c9 BM	327	bool
a6d7e8c9 BM	328	depends on SPL_RISCV_MMODE
7f1a30fd BM	329	select SPL_REGMAP
7f1a30fd BM	330	select SPL_SYSCON
644a3cd7	331	help
9675d920	332	The RISC-V ACLINT block holds memory-mapped control and status registers
644a3cd7 BM	333	associated with software and timer interrupts.
644a3cd7 BM	334
213ed175 ZL	335	config SIFIVE_CACHE
	336	bool
	337	help
	338	This enables the operations to configure SiFive cache
	339
a5dfa3b8	340	config ANDES_PLICSW
0d389468	341	bool
fbfd92bf	342	depends on RISCV_MMODE \|\| SPL_RISCV_MMODE
0d389468 RC	343	select REGMAP
0d389468 RC	344	select SYSCON
fbfd92bf LA	345	select SPL_REGMAP if SPL
fbfd92bf LA	346	select SPL_SYSCON if SPL
0d389468	347	help
a5dfa3b8 YCPL	348	The Andes PLICSW block holds memory-mapped claim and pending
a5dfa3b8 YCPL	349	registers associated with software interrupt.
0d389468	350
fa33f08f LA	351	config SMP
fa33f08f LA	352	bool "Symmetric Multi-Processing"
6fa022e8	353	depends on SBI_V01 \|\| !RISCV_SMODE
fa33f08f LA	354	help
	355	This enables support for systems with more than one CPU. If
	356	you say N here, U-Boot will run on single and multiprocessor
	357	machines, but will use only one CPU of a multiprocessor
	358	machine. If you say Y here, U-Boot will run on many, but not
	359	all, single processor machines.
	360
191636e4 BM	361	config SPL_SMP
	362	bool "Symmetric Multi-Processing in SPL"
	363	depends on SPL && SPL_RISCV_MMODE
	364	default y
	365	help
	366	This enables support for systems with more than one CPU in SPL.
	367	If you say N here, U-Boot SPL will run on single and multiprocessor
	368	machines, but will use only one CPU of a multiprocessor
	369	machine. If you say Y here, U-Boot SPL will run on many, but not
	370	all, single processor machines.
	371
fa33f08f LA	372	config NR_CPUS
	373	int "Maximum number of CPUs (2-32)"
	374	range 2 32
191636e4	375	depends on SMP \|\| SPL_SMP
fa33f08f LA	376	default 8
	377	help
	378	On multiprocessor machines, U-Boot sets up a stack for each CPU.
	379	Stack memory is pre-allocated. U-Boot must therefore know the
	380	maximum number of CPUs that may be present.
	381
f58fc34a BM	382	config SBI
	383	bool
	384	default y if RISCV_SMODE \|\| SPL_RISCV_SMODE
	385
ff0fa6c1 BM	386	choice
ff0fa6c1 BM	387	prompt "SBI support"
fa16ec23	388	default SBI_V02
ff0fa6c1	389
1b3c8d64 BM	390	config SBI_V01
1b3c8d64 BM	391	bool "SBI v0.1 support"
1b3c8d64 BM	392	depends on SBI
	393	help
	394	This config allows kernel to use SBI v0.1 APIs. This will be
	395	deprecated in future once legacy M-mode software are no longer in use.
	396
ff0fa6c1	397	config SBI_V02
5c894672	398	bool "SBI v0.2 or later support"
ff0fa6c1 BM	399	depends on SBI
ff0fa6c1 BM	400	help
5c894672 HS	401	The SBI specification introduced the concept of extensions in version
	402	v0.2. With this configuration option U-Boot can detect and use SBI
	403	extensions. With the HSM extension introduced in SBI 0.2, only a
	404	single hart needs to boot and enter the operating system. The booting
	405	hart can bring up secondary harts one by one afterwards.
ff0fa6c1	406
5c894672	407	Choose this option if OpenSBI release v0.7 or above is used together
ff0fa6c1 BM	408	with U-Boot.
	409
	410	endchoice
	411
f152febb LA	412	config SBI_IPI
f152febb LA	413	bool
f58fc34a	414	depends on SBI
fbfd92bf	415	default y if RISCV_SMODE \|\| SPL_RISCV_SMODE
f152febb LA	416	depends on SMP
f152febb LA	417
bdce3896 RC	418	config XIP
	419	bool "XIP mode"
	420	help
	421	XIP (eXecute In Place) is a method for executing code directly
	422	from a NOR flash memory without copying the code to ram.
	423	Say yes here if U-Boot boots from flash directly.
	424
c2bdf02c NS	425	config SPL_XIP
	426	bool "Enable XIP mode for SPL"
	427	help
	428	If SPL starts in read-only memory (XIP for example) then we shouldn't
	429	rely on lock variables (for example hart_lottery and available_harts_lock),
	430	this affects only SPL, other stages should proceed as non-XIP.
	431
e0465f80 RC	432	config AVAILABLE_HARTS
	433	bool "Send IPI by available harts"
	434	default y
	435	help
	436	By default, IPI sending mechanism will depend on available_harts.
	437	If disable this, it will send IPI by CPUs node numbers of device tree.
	438
fd1f6e9a SA	439	config SHOW_REGS
	440	bool "Show registers on unhandled exception"
	441
b8bc1209 SA	442	config RISCV_PRIV_1_9
	443	bool "Use version 1.9 of the RISC-V priviledged specification"
	444	help
	445	Older versions of the RISC-V priviledged specification had
	446	separate counter enable CSRs for each privilege mode. Writing
	447	to the unified mcounteren CSR on a processor implementing the
	448	old specification will result in an illegal instruction
	449	exception. In addition to counter CSR changes, the way virtual
	450	memory is configured was also changed.
	451
3dea63c8 LA	452	config STACK_SIZE_SHIFT
3dea63c8 LA	453	int
6b20dc16	454	default 14
3dea63c8	455
1c17e555	456	config OF_BOARD_FIXUP
32cef69d	457	default y if OF_SEPARATE && RISCV_SMODE
1c17e555	458
89419279 BM	459	menu "Use assembly optimized implementation of memory routines"
89419279 BM	460
8f0dc4cf HS	461	config USE_ARCH_MEMCPY
	462	bool "Use an assembly optimized implementation of memcpy"
	463	default y
	464	help
	465	Enable the generation of an optimized version of memcpy.
	466	Such an implementation may be faster under some conditions
	467	but may increase the binary size.
	468
	469	config SPL_USE_ARCH_MEMCPY
	470	bool "Use an assembly optimized implementation of memcpy for SPL"
	471	default y if USE_ARCH_MEMCPY
	472	depends on SPL
	473	help
	474	Enable the generation of an optimized version of memcpy.
	475	Such an implementation may be faster under some conditions
	476	but may increase the binary size.
	477
	478	config TPL_USE_ARCH_MEMCPY
	479	bool "Use an assembly optimized implementation of memcpy for TPL"
	480	default y if USE_ARCH_MEMCPY
	481	depends on TPL
	482	help
	483	Enable the generation of an optimized version of memcpy.
	484	Such an implementation may be faster under some conditions
	485	but may increase the binary size.
	486
	487	config USE_ARCH_MEMMOVE
	488	bool "Use an assembly optimized implementation of memmove"
	489	default y
	490	help
	491	Enable the generation of an optimized version of memmove.
	492	Such an implementation may be faster under some conditions
	493	but may increase the binary size.
	494
	495	config SPL_USE_ARCH_MEMMOVE
	496	bool "Use an assembly optimized implementation of memmove for SPL"
	497	default y if USE_ARCH_MEMCPY
	498	depends on SPL
	499	help
	500	Enable the generation of an optimized version of memmove.
	501	Such an implementation may be faster under some conditions
	502	but may increase the binary size.
	503
	504	config TPL_USE_ARCH_MEMMOVE
	505	bool "Use an assembly optimized implementation of memmove for TPL"
	506	default y if USE_ARCH_MEMCPY
	507	depends on TPL
	508	help
	509	Enable the generation of an optimized version of memmove.
	510	Such an implementation may be faster under some conditions
	511	but may increase the binary size.
	512
	513	config USE_ARCH_MEMSET
	514	bool "Use an assembly optimized implementation of memset"
	515	default y
	516	help
	517	Enable the generation of an optimized version of memset.
	518	Such an implementation may be faster under some conditions
	519	but may increase the binary size.
	520
	521	config SPL_USE_ARCH_MEMSET
	522	bool "Use an assembly optimized implementation of memset for SPL"
	523	default y if USE_ARCH_MEMSET
	524	depends on SPL
525	help
526	Enable the generation of an optimized version of memset.
527	Such an implementation may be faster under some conditions
528	but may increase the binary size.
529
530	config TPL_USE_ARCH_MEMSET
531	bool "Use an assembly optimized implementation of memset for TPL"
532	default y if USE_ARCH_MEMSET
533	depends on TPL
534	help
535	Enable the generation of an optimized version of memset.
536	Such an implementation may be faster under some conditions
537	but may increase the binary size.
538
f94c44e5	539	endmenu
89419279	540
e09a2287 R	541	config SPL_LOAD_FIT_OPENSBI_OS_BOOT
	542	bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
	543	depends on SPL_LOAD_FIT
	544	help
	545	Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
	546	This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
	547	-> linux to u-boot SPL -> OpenSBI -> linux.
	548
89419279	549	endmenu