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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e8e39597 | 2 | /* |
d8a146d1 | 3 | * Copyright (C) 2023 Andes Technology Corporation |
e8e39597 | 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
e8e39597 RC |
5 | */ |
6 | ||
7 | /* CPU specific code */ | |
9edefc27 | 8 | #include <cpu_func.h> |
1eb69ae4 | 9 | #include <irq_func.h> |
52923c6d | 10 | #include <asm/cache.h> |
1b2b52f2 | 11 | #include <asm/csr.h> |
d8a146d1 | 12 | #include <asm/arch-andes/csr.h> |
e8e39597 RC |
13 | |
14 | /* | |
15 | * cleanup_before_linux() is called just before we call linux | |
16 | * it prepares the processor for linux | |
17 | * | |
18 | * we disable interrupt and caches. | |
19 | */ | |
20 | int cleanup_before_linux(void) | |
21 | { | |
22 | disable_interrupts(); | |
23 | ||
52923c6d | 24 | cache_flush(); |
e8e39597 RC |
25 | |
26 | return 0; | |
27 | } | |
1b2b52f2 LYCL |
28 | |
29 | void harts_early_init(void) | |
30 | { | |
d8a146d1 | 31 | /* Enable I/D-cache in SPL */ |
1b2b52f2 | 32 | if (CONFIG_IS_ENABLED(RISCV_MMODE)) { |
d8a146d1 | 33 | unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); |
bf12bb99 | 34 | unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); |
d8a146d1 | 35 | |
bf12bb99 LYCL |
36 | mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ |
37 | MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ | |
61d5c543 LYCL |
38 | MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ |
39 | MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); | |
b0469041 LYCL |
40 | |
41 | if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) | |
42 | mcache_ctl_val |= MCACHE_CTL_IC_EN; | |
43 | ||
44 | if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) | |
45 | mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); | |
1b2b52f2 | 46 | |
1b2b52f2 LYCL |
47 | csr_write(CSR_MCACHE_CTL, mcache_ctl_val); |
48 | ||
b0469041 LYCL |
49 | if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { |
50 | /* | |
51 | * Check mcache_ctl.DC_COHEN, we assume this platform does | |
52 | * not support CM if the bit is hard-wired to 0. | |
53 | */ | |
54 | if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { | |
55 | /* Wait for DC_COHSTA bit to be set */ | |
56 | while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); | |
57 | } | |
1b2b52f2 | 58 | } |
bf12bb99 LYCL |
59 | |
60 | mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; | |
61 | ||
62 | csr_write(CSR_MMISC_CTL, mmisc_ctl_val); | |
1b2b52f2 LYCL |
63 | } |
64 | } |