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Commit | Line | Data |
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dd84058d MY |
1 | menu "x86 architecture" |
2 | depends on X86 | |
3 | ||
4 | config SYS_ARCH | |
dd84058d MY |
5 | default "x86" |
6 | ||
a66ad67f SG |
7 | choice |
8 | prompt "Run U-Boot in 32/64-bit mode" | |
9 | default X86_RUN_32BIT | |
10 | help | |
11 | U-Boot can be built as a 32-bit binary which runs in 32-bit mode | |
12 | even on 64-bit machines. In this case SPL is not used, and U-Boot | |
13 | runs directly from the reset vector (via 16-bit start-up). | |
14 | ||
15 | Alternatively it can be run as a 64-bit binary, thus requiring a | |
16 | 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit | |
17 | start-up) then jumps to U-Boot in 64-bit mode. | |
18 | ||
19 | For now, 32-bit mode is recommended, as 64-bit is still | |
20 | experimental and is missing a lot of features. | |
21 | ||
22 | config X86_RUN_32BIT | |
23 | bool "32-bit" | |
24 | help | |
25 | Build U-Boot as a 32-bit binary with no SPL. This is the currently | |
26 | supported normal setup. U-Boot will stay in 32-bit mode even on | |
27 | 64-bit machines. When booting a 64-bit kernel, U-Boot will switch | |
28 | to 64-bit just before starting the kernel. Only the bottom 4GB of | |
29 | memory can be accessed through normal means, although | |
30 | arch_phys_memset() can be used for basic access to other memory. | |
31 | ||
32 | config X86_RUN_64BIT | |
33 | bool "64-bit" | |
34 | select X86_64 | |
35 | select SUPPORT_SPL | |
36 | select SPL | |
37 | select SPL_SEPARATE_BSS | |
38 | help | |
39 | Build U-Boot as a 64-bit binary with a 32-bit SPL. This is | |
40 | experimental and many features are missing. U-Boot SPL starts up, | |
41 | runs through the 16-bit and 32-bit init, then switches to 64-bit | |
42 | mode and jumps to U-Boot proper. | |
43 | ||
44 | endchoice | |
45 | ||
46 | config X86_64 | |
47 | bool | |
48 | ||
49 | config SPL_X86_64 | |
50 | bool | |
51 | depends on SPL | |
52 | ||
dd84058d | 53 | choice |
65c4ac0a | 54 | prompt "Mainboard vendor" |
99a309f3 | 55 | default VENDOR_EMULATION |
dd84058d | 56 | |
215099a5 GM |
57 | config VENDOR_ADVANTECH |
58 | bool "advantech" | |
59 | ||
82ceba2c SR |
60 | config VENDOR_CONGATEC |
61 | bool "congatec" | |
62 | ||
65c4ac0a BM |
63 | config VENDOR_COREBOOT |
64 | bool "coreboot" | |
3a1a18ff | 65 | |
b1ad6c69 SR |
66 | config VENDOR_DFI |
67 | bool "dfi" | |
68 | ||
3dcdd17b BS |
69 | config VENDOR_EFI |
70 | bool "efi" | |
71 | ||
a65b25d1 BM |
72 | config VENDOR_EMULATION |
73 | bool "emulation" | |
74 | ||
65c4ac0a BM |
75 | config VENDOR_GOOGLE |
76 | bool "Google" | |
3a1a18ff | 77 | |
65c4ac0a BM |
78 | config VENDOR_INTEL |
79 | bool "Intel" | |
ef46bea0 | 80 | |
dd84058d MY |
81 | endchoice |
82 | ||
65c4ac0a | 83 | # board-specific options below |
215099a5 | 84 | source "board/advantech/Kconfig" |
82ceba2c | 85 | source "board/congatec/Kconfig" |
65c4ac0a | 86 | source "board/coreboot/Kconfig" |
b1ad6c69 | 87 | source "board/dfi/Kconfig" |
3e9aa320 | 88 | source "board/efi/Kconfig" |
a65b25d1 | 89 | source "board/emulation/Kconfig" |
65c4ac0a BM |
90 | source "board/google/Kconfig" |
91 | source "board/intel/Kconfig" | |
92 | ||
029194a3 BM |
93 | # platform-specific options below |
94 | source "arch/x86/cpu/baytrail/Kconfig" | |
2f3f477b | 95 | source "arch/x86/cpu/broadwell/Kconfig" |
029194a3 BM |
96 | source "arch/x86/cpu/coreboot/Kconfig" |
97 | source "arch/x86/cpu/ivybridge/Kconfig" | |
a65b25d1 | 98 | source "arch/x86/cpu/qemu/Kconfig" |
029194a3 BM |
99 | source "arch/x86/cpu/quark/Kconfig" |
100 | source "arch/x86/cpu/queensbay/Kconfig" | |
101 | ||
102 | # architecture-specific options below | |
103 | ||
a219639d SG |
104 | config AHCI |
105 | default y | |
106 | ||
b724bd7d SG |
107 | config SYS_MALLOC_F_LEN |
108 | default 0x800 | |
109 | ||
70a09c6c SG |
110 | config RAMBASE |
111 | hex | |
112 | default 0x100000 | |
113 | ||
70a09c6c SG |
114 | config XIP_ROM_SIZE |
115 | hex | |
7698d36a | 116 | depends on X86_RESET_VECTOR |
bbd43d65 | 117 | default ROM_SIZE |
70a09c6c SG |
118 | |
119 | config CPU_ADDR_BITS | |
120 | int | |
121 | default 36 | |
122 | ||
65dd74a6 SG |
123 | config HPET_ADDRESS |
124 | hex | |
125 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE | |
126 | ||
127 | config SMM_TSEG | |
128 | bool | |
129 | default n | |
130 | ||
131 | config SMM_TSEG_SIZE | |
132 | hex | |
133 | ||
8cb20ccc BM |
134 | config X86_RESET_VECTOR |
135 | bool | |
136 | default n | |
137 | ||
13f1dc64 SG |
138 | # The following options control where the 16-bit and 32-bit init lies |
139 | # If SPL is enabled then it normally holds this init code, and U-Boot proper | |
140 | # is normally a 64-bit build. | |
141 | # | |
142 | # The 16-bit init refers to the reset vector and the small amount of code to | |
143 | # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, | |
144 | # or missing altogether if U-Boot is started from EFI or coreboot. | |
145 | # | |
146 | # The 32-bit init refers to processor init, running binary blobs including | |
147 | # FSP, setting up interrupts and anything else that needs to be done in | |
148 | # 32-bit code. It is normally in the same place as 16-bit init if that is | |
149 | # enabled (i.e. they are both in SPL, or both in U-Boot proper). | |
150 | config X86_16BIT_INIT | |
151 | bool | |
152 | depends on X86_RESET_VECTOR | |
153 | default y if X86_RESET_VECTOR && !SPL | |
154 | help | |
155 | This is enabled when 16-bit init is in U-Boot proper | |
156 | ||
157 | config SPL_X86_16BIT_INIT | |
158 | bool | |
159 | depends on X86_RESET_VECTOR | |
160 | default y if X86_RESET_VECTOR && SPL | |
161 | help | |
162 | This is enabled when 16-bit init is in SPL | |
163 | ||
164 | config X86_32BIT_INIT | |
165 | bool | |
166 | depends on X86_RESET_VECTOR | |
167 | default y if X86_RESET_VECTOR && !SPL | |
168 | help | |
169 | This is enabled when 32-bit init is in U-Boot proper | |
170 | ||
171 | config SPL_X86_32BIT_INIT | |
172 | bool | |
173 | depends on X86_RESET_VECTOR | |
174 | default y if X86_RESET_VECTOR && SPL | |
175 | help | |
176 | This is enabled when 32-bit init is in SPL | |
177 | ||
343fb990 BM |
178 | config RESET_SEG_START |
179 | hex | |
180 | depends on X86_RESET_VECTOR | |
181 | default 0xffff0000 | |
182 | ||
183 | config RESET_SEG_SIZE | |
184 | hex | |
185 | depends on X86_RESET_VECTOR | |
186 | default 0x10000 | |
187 | ||
188 | config RESET_VEC_LOC | |
189 | hex | |
190 | depends on X86_RESET_VECTOR | |
191 | default 0xfffffff0 | |
192 | ||
8cb20ccc BM |
193 | config SYS_X86_START16 |
194 | hex | |
195 | depends on X86_RESET_VECTOR | |
196 | default 0xfffff800 | |
197 | ||
64542f46 BM |
198 | config BOARD_ROMSIZE_KB_512 |
199 | bool | |
200 | config BOARD_ROMSIZE_KB_1024 | |
201 | bool | |
202 | config BOARD_ROMSIZE_KB_2048 | |
203 | bool | |
204 | config BOARD_ROMSIZE_KB_4096 | |
205 | bool | |
206 | config BOARD_ROMSIZE_KB_8192 | |
207 | bool | |
208 | config BOARD_ROMSIZE_KB_16384 | |
209 | bool | |
210 | ||
211 | choice | |
212 | prompt "ROM chip size" | |
7698d36a | 213 | depends on X86_RESET_VECTOR |
64542f46 BM |
214 | default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 |
215 | default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 | |
216 | default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 | |
217 | default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 | |
218 | default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 | |
219 | default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 | |
220 | help | |
221 | Select the size of the ROM chip you intend to flash U-Boot on. | |
222 | ||
223 | The build system will take care of creating a u-boot.rom file | |
224 | of the matching size. | |
225 | ||
226 | config UBOOT_ROMSIZE_KB_512 | |
227 | bool "512 KB" | |
228 | help | |
229 | Choose this option if you have a 512 KB ROM chip. | |
230 | ||
231 | config UBOOT_ROMSIZE_KB_1024 | |
232 | bool "1024 KB (1 MB)" | |
233 | help | |
234 | Choose this option if you have a 1024 KB (1 MB) ROM chip. | |
235 | ||
236 | config UBOOT_ROMSIZE_KB_2048 | |
237 | bool "2048 KB (2 MB)" | |
238 | help | |
239 | Choose this option if you have a 2048 KB (2 MB) ROM chip. | |
240 | ||
241 | config UBOOT_ROMSIZE_KB_4096 | |
242 | bool "4096 KB (4 MB)" | |
243 | help | |
244 | Choose this option if you have a 4096 KB (4 MB) ROM chip. | |
245 | ||
246 | config UBOOT_ROMSIZE_KB_8192 | |
247 | bool "8192 KB (8 MB)" | |
248 | help | |
249 | Choose this option if you have a 8192 KB (8 MB) ROM chip. | |
250 | ||
251 | config UBOOT_ROMSIZE_KB_16384 | |
252 | bool "16384 KB (16 MB)" | |
253 | help | |
254 | Choose this option if you have a 16384 KB (16 MB) ROM chip. | |
255 | ||
256 | endchoice | |
257 | ||
258 | # Map the config names to an integer (KB). | |
259 | config UBOOT_ROMSIZE_KB | |
260 | int | |
261 | default 512 if UBOOT_ROMSIZE_KB_512 | |
262 | default 1024 if UBOOT_ROMSIZE_KB_1024 | |
263 | default 2048 if UBOOT_ROMSIZE_KB_2048 | |
264 | default 4096 if UBOOT_ROMSIZE_KB_4096 | |
265 | default 8192 if UBOOT_ROMSIZE_KB_8192 | |
266 | default 16384 if UBOOT_ROMSIZE_KB_16384 | |
267 | ||
268 | # Map the config names to a hex value (bytes). | |
fce7b276 SG |
269 | config ROM_SIZE |
270 | hex | |
64542f46 BM |
271 | default 0x80000 if UBOOT_ROMSIZE_KB_512 |
272 | default 0x100000 if UBOOT_ROMSIZE_KB_1024 | |
273 | default 0x200000 if UBOOT_ROMSIZE_KB_2048 | |
274 | default 0x400000 if UBOOT_ROMSIZE_KB_4096 | |
275 | default 0x800000 if UBOOT_ROMSIZE_KB_8192 | |
276 | default 0xc00000 if UBOOT_ROMSIZE_KB_12288 | |
277 | default 0x1000000 if UBOOT_ROMSIZE_KB_16384 | |
fce7b276 SG |
278 | |
279 | config HAVE_INTEL_ME | |
280 | bool "Platform requires Intel Management Engine" | |
281 | help | |
282 | Newer higher-end devices have an Intel Management Engine (ME) | |
283 | which is a very large binary blob (typically 1.5MB) which is | |
284 | required for the platform to work. This enforces a particular | |
285 | SPI flash format. You will need to supply the me.bin file in | |
286 | your board directory. | |
287 | ||
65dd74a6 SG |
288 | config X86_RAMTEST |
289 | bool "Perform a simple RAM test after SDRAM initialisation" | |
290 | help | |
291 | If there is something wrong with SDRAM then the platform will | |
292 | often crash within U-Boot or the kernel. This option enables a | |
293 | very simple RAM test that quickly checks whether the SDRAM seems | |
294 | to work correctly. It is not exhaustive but can save time by | |
295 | detecting obvious failures. | |
296 | ||
8ce24cd9 SG |
297 | config HAVE_FSP |
298 | bool "Add an Firmware Support Package binary" | |
e49cceac | 299 | depends on !EFI |
8ce24cd9 SG |
300 | help |
301 | Select this option to add an Firmware Support Package binary to | |
302 | the resulting U-Boot image. It is a binary blob which U-Boot uses | |
303 | to set up SDRAM and other chipset specific initialization. | |
304 | ||
305 | Note: Without this binary U-Boot will not be able to set up its | |
306 | SDRAM so will not boot. | |
307 | ||
308 | config FSP_FILE | |
309 | string "Firmware Support Package binary filename" | |
310 | depends on HAVE_FSP | |
311 | default "fsp.bin" | |
312 | help | |
313 | The filename of the file to use as Firmware Support Package binary | |
314 | in the board directory. | |
315 | ||
316 | config FSP_ADDR | |
317 | hex "Firmware Support Package binary location" | |
318 | depends on HAVE_FSP | |
319 | default 0xfffc0000 | |
320 | help | |
321 | FSP is not Position Independent Code (PIC) and the whole FSP has to | |
322 | be rebased if it is placed at a location which is different from the | |
323 | perferred base address specified during the FSP build. Use Intel's | |
324 | Binary Configuration Tool (BCT) to do the rebase. | |
325 | ||
326 | The default base address of 0xfffc0000 indicates that the binary must | |
327 | be located at offset 0xc0000 from the beginning of a 1MB flash device. | |
328 | ||
329 | config FSP_TEMP_RAM_ADDR | |
330 | hex | |
d04e30b8 | 331 | depends on HAVE_FSP |
8ce24cd9 SG |
332 | default 0x2000000 |
333 | help | |
48aa6c26 | 334 | Stack top address which is used in fsp_init() after DRAM is ready and |
8ce24cd9 SG |
335 | CAR is disabled. |
336 | ||
57b10f59 BM |
337 | config FSP_SYS_MALLOC_F_LEN |
338 | hex | |
339 | depends on HAVE_FSP | |
340 | default 0x100000 | |
341 | help | |
342 | Additional size of malloc() pool before relocation. | |
343 | ||
3340f2cc BM |
344 | config FSP_USE_UPD |
345 | bool | |
346 | depends on HAVE_FSP | |
347 | default y | |
348 | help | |
349 | Most FSPs use UPD data region for some FSP customization. But there | |
350 | are still some FSPs that might not even have UPD. For such FSPs, | |
351 | override this to n in their platform Kconfig files. | |
352 | ||
dc5be508 BM |
353 | config FSP_BROKEN_HOB |
354 | bool | |
355 | depends on HAVE_FSP | |
356 | help | |
357 | Indicate some buggy FSPs that does not report memory used by FSP | |
358 | itself as reserved in the resource descriptor HOB. Select this to | |
359 | tell U-Boot to do some additional work to ensure U-Boot relocation | |
360 | do not overwrite the important boot service data which is used by | |
361 | FSP, otherwise the subsequent call to fsp_notify() will fail. | |
362 | ||
e2d76e95 BM |
363 | config ENABLE_MRC_CACHE |
364 | bool "Enable MRC cache" | |
365 | depends on !EFI && !SYS_COREBOOT | |
366 | help | |
367 | Enable this feature to cause MRC data to be cached in NV storage | |
368 | to be used for speeding up boot time on future reboots and/or | |
369 | power cycles. | |
370 | ||
5c60a3ab BM |
371 | For platforms that use Intel FSP for the memory initialization, |
372 | please check FSP output HOB via U-Boot command 'fsp hob' to see | |
373 | if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). | |
374 | If such GUID does not exist, MRC cache is not avaiable on such | |
375 | platform (eg: Intel Queensbay), which means selecting this option | |
376 | here does not make any difference. | |
377 | ||
f7d35bc1 SG |
378 | config HAVE_MRC |
379 | bool "Add a System Agent binary" | |
380 | depends on !HAVE_FSP | |
381 | help | |
382 | Select this option to add a System Agent binary to | |
383 | the resulting U-Boot image. MRC stands for Memory Reference Code. | |
384 | It is a binary blob which U-Boot uses to set up SDRAM. | |
385 | ||
386 | Note: Without this binary U-Boot will not be able to set up its | |
387 | SDRAM so will not boot. | |
388 | ||
389 | config CACHE_MRC_BIN | |
390 | bool | |
391 | depends on HAVE_MRC | |
392 | default n | |
393 | help | |
394 | Enable caching for the memory reference code binary. This uses an | |
395 | MTRR (memory type range register) to turn on caching for the section | |
396 | of SPI flash that contains the memory reference code. This makes | |
397 | SDRAM init run faster. | |
398 | ||
399 | config CACHE_MRC_SIZE_KB | |
400 | int | |
401 | depends on HAVE_MRC | |
402 | default 512 | |
403 | help | |
404 | Sets the size of the cached area for the memory reference code. | |
405 | This ends at the end of SPI flash (address 0xffffffff) and is | |
406 | measured in KB. Typically this is set to 512, providing for 0.5MB | |
407 | of cached space. | |
408 | ||
409 | config DCACHE_RAM_BASE | |
410 | hex | |
411 | depends on HAVE_MRC | |
412 | help | |
413 | Sets the base of the data cache area in memory space. This is the | |
414 | start address of the cache-as-RAM (CAR) area and the address varies | |
415 | depending on the CPU. Once CAR is set up, read/write memory becomes | |
416 | available at this address and can be used temporarily until SDRAM | |
417 | is working. | |
418 | ||
419 | config DCACHE_RAM_SIZE | |
420 | hex | |
421 | depends on HAVE_MRC | |
422 | default 0x40000 | |
423 | help | |
424 | Sets the total size of the data cache area in memory space. This | |
425 | sets the size of the cache-as-RAM (CAR) area. Note that much of the | |
426 | CAR space is required by the MRC. The CAR space available to U-Boot | |
427 | is normally at the start and typically extends to 1/4 or 1/2 of the | |
428 | available size. | |
429 | ||
430 | config DCACHE_RAM_MRC_VAR_SIZE | |
431 | hex | |
432 | depends on HAVE_MRC | |
433 | help | |
434 | This is the amount of CAR (Cache as RAM) reserved for use by the | |
435 | memory reference code. This depends on the implementation of the | |
436 | memory reference code and must be set correctly or the board will | |
437 | not boot. | |
438 | ||
0adf8d35 SG |
439 | config HAVE_REFCODE |
440 | bool "Add a Reference Code binary" | |
441 | help | |
442 | Select this option to add a Reference Code binary to the resulting | |
443 | U-Boot image. This is an Intel binary blob that handles system | |
444 | initialisation, in this case the PCH and System Agent. | |
445 | ||
446 | Note: Without this binary (on platforms that need it such as | |
447 | broadwell) U-Boot will be missing some critical setup steps. | |
448 | Various peripherals may fail to work. | |
449 | ||
45b5a378 SG |
450 | config SMP |
451 | bool "Enable Symmetric Multiprocessing" | |
452 | default n | |
453 | help | |
454 | Enable use of more than one CPU in U-Boot and the Operating System | |
455 | when loaded. Each CPU will be started up and information can be | |
456 | obtained using the 'cpu' command. If this option is disabled, then | |
457 | only one CPU will be enabled regardless of the number of CPUs | |
458 | available. | |
459 | ||
4c71322b BM |
460 | config MAX_CPUS |
461 | int "Maximum number of CPUs permitted" | |
462 | depends on SMP | |
463 | default 4 | |
464 | help | |
465 | When using multi-CPU chips it is possible for U-Boot to start up | |
466 | more than one CPU. The stack memory used by all of these CPUs is | |
467 | pre-allocated so at present U-Boot wants to know the maximum | |
468 | number of CPUs that may be present. Set this to at least as high | |
469 | as the number of CPUs in your system (it uses about 4KB of RAM for | |
470 | each CPU). | |
471 | ||
45b5a378 SG |
472 | config AP_STACK_SIZE |
473 | hex | |
063374d2 | 474 | depends on SMP |
45b5a378 SG |
475 | default 0x1000 |
476 | help | |
477 | Each additional CPU started by U-Boot requires its own stack. This | |
478 | option sets the stack size used by each CPU and directly affects | |
479 | the memory used by this initialisation process. Typically 4KB is | |
480 | enough space. | |
481 | ||
786a08e0 BM |
482 | config HAVE_VGA_BIOS |
483 | bool "Add a VGA BIOS image" | |
484 | help | |
485 | Select this option if you have a VGA BIOS image that you would | |
486 | like to add to your ROM. | |
487 | ||
488 | config VGA_BIOS_FILE | |
489 | string "VGA BIOS image filename" | |
490 | depends on HAVE_VGA_BIOS | |
491 | default "vga.bin" | |
492 | help | |
493 | The filename of the VGA BIOS image in the board directory. | |
494 | ||
495 | config VGA_BIOS_ADDR | |
496 | hex "VGA BIOS image location" | |
497 | depends on HAVE_VGA_BIOS | |
498 | default 0xfff90000 | |
499 | help | |
500 | The location of VGA BIOS image in the SPI flash. For example, base | |
501 | address of 0xfff90000 indicates that the image will be put at offset | |
502 | 0x90000 from the beginning of a 1MB flash device. | |
503 | ||
b5b6b019 | 504 | menu "System tables" |
8744bef5 | 505 | depends on !EFI && !SYS_COREBOOT |
b5b6b019 BM |
506 | |
507 | config GENERATE_PIRQ_TABLE | |
508 | bool "Generate a PIRQ table" | |
509 | default n | |
510 | help | |
511 | Generate a PIRQ routing table for this board. The PIRQ routing table | |
512 | is generated by U-Boot in the system memory from 0xf0000 to 0xfffff | |
513 | at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). | |
514 | It specifies the interrupt router information as well how all the PCI | |
515 | devices' interrupt pins are wired to PIRQs. | |
516 | ||
6388e357 SG |
517 | config GENERATE_SFI_TABLE |
518 | bool "Generate a SFI (Simple Firmware Interface) table" | |
519 | help | |
520 | The Simple Firmware Interface (SFI) provides a lightweight method | |
521 | for platform firmware to pass information to the operating system | |
522 | via static tables in memory. Kernel SFI support is required to | |
523 | boot on SFI-only platforms. If you have ACPI tables then these are | |
524 | used instead. | |
525 | ||
526 | U-Boot writes this table in write_sfi_table() just before booting | |
527 | the OS. | |
528 | ||
529 | For more information, see http://simplefirmware.org | |
530 | ||
07545d86 BM |
531 | config GENERATE_MP_TABLE |
532 | bool "Generate an MP (Multi-Processor) table" | |
533 | default n | |
534 | help | |
535 | Generate an MP (Multi-Processor) table for this board. The MP table | |
536 | provides a way for the operating system to support for symmetric | |
537 | multiprocessing as well as symmetric I/O interrupt handling with | |
538 | the local APIC and I/O APIC. | |
539 | ||
867bcb63 SS |
540 | config GENERATE_ACPI_TABLE |
541 | bool "Generate an ACPI (Advanced Configuration and Power Interface) table" | |
542 | default n | |
fcf5c041 | 543 | select QFW if QEMU |
867bcb63 SS |
544 | help |
545 | The Advanced Configuration and Power Interface (ACPI) specification | |
546 | provides an open standard for device configuration and management | |
547 | by the operating system. It defines platform-independent interfaces | |
548 | for configuration and power management monitoring. | |
549 | ||
b5b6b019 BM |
550 | endmenu |
551 | ||
552 | config MAX_PIRQ_LINKS | |
553 | int | |
554 | default 8 | |
555 | help | |
556 | This variable specifies the number of PIRQ interrupt links which are | |
557 | routable. On most older chipsets, this is 4, PIRQA through PIRQD. | |
558 | Some newer chipsets offer more than four links, commonly up to PIRQH. | |
559 | ||
560 | config IRQ_SLOT_COUNT | |
561 | int | |
562 | default 128 | |
563 | help | |
564 | U-Boot can support up to 254 IRQ slot info in the PIRQ routing table | |
565 | which in turns forms a table of exact 4KiB. The default value 128 | |
566 | should be enough for most boards. If this does not fit your board, | |
567 | change it according to your needs. | |
568 | ||
2d934e57 SG |
569 | config PCIE_ECAM_BASE |
570 | hex | |
ba877efb | 571 | default 0xe0000000 |
2d934e57 SG |
572 | help |
573 | This is the memory-mapped address of PCI configuration space, which | |
574 | is only available through the Enhanced Configuration Access | |
575 | Mechanism (ECAM) with PCI Express. It can be set up almost | |
576 | anywhere. Before it is set up, it is possible to access PCI | |
577 | configuration space through I/O access, but memory access is more | |
578 | convenient. Using this, PCI can be scanned and configured. This | |
579 | should be set to a region that does not conflict with memory | |
580 | assigned to PCI devices - i.e. the memory and prefetch regions, as | |
581 | passed to pci_set_region(). | |
582 | ||
1ed6648b BM |
583 | config PCIE_ECAM_SIZE |
584 | hex | |
585 | default 0x10000000 | |
586 | help | |
587 | This is the size of memory-mapped address of PCI configuration space, | |
588 | which is only available through the Enhanced Configuration Access | |
589 | Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, | |
590 | so a default 0x10000000 size covers all of the 256 buses which is the | |
591 | maximum number of PCI buses as defined by the PCI specification. | |
592 | ||
1eb39a50 BM |
593 | config I8259_PIC |
594 | bool | |
595 | default y | |
596 | help | |
597 | Intel 8259 ISA compatible chipset incorporates two 8259 (master and | |
598 | slave) interrupt controllers. Include this to have U-Boot set up | |
599 | the interrupt correctly. | |
600 | ||
601 | config I8254_TIMER | |
602 | bool | |
603 | default y | |
604 | help | |
605 | Intel 8254 timer contains three counters which have fixed uses. | |
606 | Include this to have U-Boot set up the timer correctly. | |
607 | ||
3cf23719 BM |
608 | config SEABIOS |
609 | bool "Support booting SeaBIOS" | |
610 | help | |
611 | SeaBIOS is an open source implementation of a 16-bit X86 BIOS. | |
612 | It can run in an emulator or natively on X86 hardware with the use | |
613 | of coreboot/U-Boot. By turning on this option, U-Boot prepares | |
614 | all the configuration tables that are necessary to boot SeaBIOS. | |
615 | ||
616 | Check http://www.seabios.org/SeaBIOS for details. | |
617 | ||
789b6dce BM |
618 | config HIGH_TABLE_SIZE |
619 | hex "Size of configuration tables which reside in high memory" | |
620 | default 0x10000 | |
621 | depends on SEABIOS | |
622 | help | |
623 | SeaBIOS itself resides in E seg and F seg, where U-Boot puts all | |
624 | configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot | |
625 | puts a copy of configuration tables in high memory region which | |
626 | is reserved on the stack before relocation. The region size is | |
627 | determined by this option. | |
628 | ||
629 | Increse it if the default size does not fit the board's needs. | |
630 | This is most likely due to a large ACPI DSDT table is used. | |
631 | ||
e49cceac SG |
632 | source "arch/x86/lib/efi/Kconfig" |
633 | ||
dd84058d | 634 | endmenu |