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40fb08e9 SG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright 2019 Google LLC | |
4 | */ | |
5 | ||
d678a59d | 6 | #include <common.h> |
40fb08e9 SG |
7 | #include <dm.h> |
8 | #include <pch.h> | |
9 | #include <spl.h> | |
10 | #include <asm/lpc_common.h> | |
11 | ||
12 | #define BIOS_CTRL 0xdc | |
13 | ||
14 | static int apl_set_spi_protect(struct udevice *dev, bool protect) | |
15 | { | |
16 | if (spl_phase() == PHASE_SPL) | |
17 | return lpc_set_spi_protect(dev, BIOS_CTRL, protect); | |
18 | ||
19 | return 0; | |
20 | } | |
21 | ||
22 | static const struct pch_ops apl_pch_ops = { | |
23 | .set_spi_protect = apl_set_spi_protect, | |
24 | }; | |
25 | ||
95397385 | 26 | #if CONFIG_IS_ENABLED(OF_REAL) |
40fb08e9 SG |
27 | static const struct udevice_id apl_pch_ids[] = { |
28 | { .compatible = "intel,apl-pch" }, | |
29 | { } | |
30 | }; | |
8b842be1 | 31 | #endif |
40fb08e9 | 32 | |
9d20db04 SG |
33 | U_BOOT_DRIVER(intel_apl_pch) = { |
34 | .name = "intel_apl_pch", | |
40fb08e9 | 35 | .id = UCLASS_PCH, |
8b842be1 | 36 | .of_match = of_match_ptr(apl_pch_ids), |
40fb08e9 SG |
37 | .ops = &apl_pch_ops, |
38 | }; |