]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ef5a5b00 GB |
2 | /* |
3 | * Copyright (c) 2011 The Chromium OS Authors. | |
4 | * (C) Copyright 2008 | |
5 | * Graeme Russ, graeme.russ@gmail.com. | |
ef5a5b00 GB |
6 | */ |
7 | ||
d678a59d | 8 | #include <common.h> |
30c7c434 | 9 | #include <cpu_func.h> |
91caa3bb | 10 | #include <event.h> |
f2653e8d | 11 | #include <fdtdec.h> |
691d719d | 12 | #include <init.h> |
ceeee8f7 | 13 | #include <usb.h> |
401d1c4f | 14 | #include <asm/global_data.h> |
300081aa | 15 | #include <asm/io.h> |
65cdd9be | 16 | #include <asm/msr.h> |
aff2523f | 17 | #include <asm/mtrr.h> |
e35b6497 | 18 | #include <asm/cb_sysinfo.h> |
6dbe0cce | 19 | #include <asm/arch/timestamp.h> |
7de8bd03 | 20 | #include <dm/ofnode.h> |
ef5a5b00 | 21 | |
8b37c769 | 22 | int arch_cpu_init(void) |
63f559cd | 23 | { |
2c6b979e SG |
24 | int ret; |
25 | ||
26 | ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : | |
27 | x86_cpu_init_f(); | |
28 | if (ret) | |
29 | return ret; | |
30 | ||
31 | ret = get_coreboot_info(&lib_sysinfo); | |
8b37c769 | 32 | if (ret != 0) { |
63f559cd | 33 | printf("Failed to parse coreboot tables.\n"); |
8b37c769 SG |
34 | return ret; |
35 | } | |
6dbe0cce VB |
36 | |
37 | timestamp_init(); | |
38 | ||
2c6b979e | 39 | return 0; |
63f559cd GB |
40 | } |
41 | ||
76d1d02f SG |
42 | int checkcpu(void) |
43 | { | |
44 | return 0; | |
45 | } | |
46 | ||
727c1a98 SG |
47 | int print_cpuinfo(void) |
48 | { | |
49 | return default_print_cpuinfo(); | |
50 | } | |
51 | ||
4021ee63 | 52 | static void board_final_init(void) |
17de114f | 53 | { |
65cdd9be BM |
54 | /* |
55 | * Un-cache the ROM so the kernel has one | |
17de114f | 56 | * more MTRR available. |
488b8b24 DL |
57 | * |
58 | * Coreboot should have assigned this to the | |
59 | * top available variable MTRR. | |
17de114f | 60 | */ |
aff2523f SG |
61 | u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; |
62 | u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; | |
488b8b24 DL |
63 | |
64 | /* Make sure this MTRR is the correct Write-Protected type */ | |
aff2523f SG |
65 | if (top_type == MTRR_TYPE_WRPROT) { |
66 | struct mtrr_state state; | |
67 | ||
590cee83 | 68 | mtrr_open(&state, true); |
aff2523f SG |
69 | wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); |
70 | wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); | |
590cee83 | 71 | mtrr_close(&state, true); |
488b8b24 | 72 | } |
17de114f | 73 | |
7de8bd03 | 74 | if (!ofnode_conf_read_bool("u-boot,no-apm-finalize")) { |
f2653e8d BM |
75 | /* |
76 | * Issue SMI to coreboot to lock down ME and registers | |
77 | * when allowed via device tree | |
78 | */ | |
79 | printf("Finalizing coreboot\n"); | |
80 | outb(0xcb, 0xb2); | |
81 | } | |
17de114f | 82 | } |
c78a62ac | 83 | |
91caa3bb | 84 | static int last_stage_init(void) |
1e2f7b9e | 85 | { |
91caa3bb SG |
86 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
87 | return 0; | |
88 | ||
4021ee63 | 89 | board_final_init(); |
1e2f7b9e | 90 | |
069f5481 SG |
91 | return 0; |
92 | } | |
91caa3bb | 93 | EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); |