[thirdparty/u-boot.git] / arch / x86 / cpu / ivybridge / sata.c

// SPDX-License-Identifier: GPL-2.0
/*
 * From Coreboot
 * Copyright (C) 2008-2009 coresystems GmbH
 */

#include <common.h>
#include <ahci.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>

DECLARE_GLOBAL_DATA_PTR;

static void common_sata_init(struct udevice *dev, unsigned int port_map)
{
	u32 reg32;
	u16 reg16;

	/* Set IDE I/O Configuration */
	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
	dm_pci_write_config32(dev, IDE_CONFIG, reg32);

	/* Port enable */
	dm_pci_read_config16(dev, 0x92, &reg16);
	reg16 &= ~0x3f;
	reg16 |= port_map;
	dm_pci_write_config16(dev, 0x92, reg16);

	/* SATA Initialization register */
	port_map &= 0xff;
	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
}

static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
{
	unsigned int port_map, speed_support, port_tx;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	const char *mode;
	u32 reg32;
	u16 reg16;

	debug("SATA: Initializing...\n");

	/* SATA configuration */
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	speed_support = fdtdec_get_int(blob, node,
				       "sata_interface_speed_support", 0);

	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (!mode || !strcmp(mode, "ahci")) {
		ulong abar;

		debug("SATA: Controller in AHCI mode\n");

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);

		common_sata_init(dev, 0x8000 | port_map);

		/* Initialize AHCI memory-mapped space */
		abar = dm_pci_read_bar32(dev, 5);
		debug("ABAR: %08lx\n", abar);
		/* CAP (HBA Capabilities) : enable power management */
		reg32 = readl(abar + 0x00);
		reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
		reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
		/* Set ISS, if available */
		if (speed_support) {
			reg32 &= ~0x00f00000;
			reg32 |= (speed_support & 0x03) << 20;
		}
		writel(reg32, abar + 0x00);
		/* PI (Ports implemented) */
		writel(port_map, abar + 0x0c);
		(void) readl(abar + 0x0c); /* Read back 1 */
		(void) readl(abar + 0x0c); /* Read back 2 */
		/* CAP2 (HBA Capabilities Extended)*/
		reg32 = readl(abar + 0x24);
		reg32 &= ~0x00000002;
		writel(reg32, abar + 0x24);
		/* VSP (Vendor Specific Register */
		reg32 = readl(abar + 0xa0);
		reg32 &= ~0x00000005;
		writel(reg32, abar + 0xa0);
	} else if (!strcmp(mode, "combined")) {
		debug("SATA: Controller in combined mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);
		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		dm_pci_write_config8(dev, 0x09, 0x80);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);

		common_sata_init(dev, port_map);
	} else {
		debug("SATA: Controller in plain-ide mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);

		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		/*
		 * Native mode capable on both primary and secondary (0xa)
		 * OR'ed with enabled (0x50) = 0xf
		 */
		dm_pci_write_config8(dev, 0x09, 0x8f);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_SITRE | IDE_ISP_3_CLOCKS |
				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);

		common_sata_init(dev, port_map);
	}

	/* Set Gen3 Transmitter settings if needed */
	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);

	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);

	/* Additional Programming Requirements */
	pch_common_sir_write(dev, 0x04, 0x00001600);
	pch_common_sir_write(dev, 0x28, 0xa0000033);
	reg32 = pch_common_sir_read(dev, 0x54);
	reg32 &= 0xff000000;
	reg32 |= 0x5555aa;
	pch_common_sir_write(dev, 0x54, reg32);
	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	reg32 = pch_common_sir_read(dev, 0x68);
	reg32 &= 0xffff0000;
	reg32 |= 0xcccc;
	pch_common_sir_write(dev, 0x68, reg32);
	reg32 = pch_common_sir_read(dev, 0x78);
	reg32 &= 0x0000ffff;
	reg32 |= 0x88880000;
	pch_common_sir_write(dev, 0x78, reg32);
	pch_common_sir_write(dev, 0x84, 0x001c7000);
	pch_common_sir_write(dev, 0x88, 0x88338822);
	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xd4, 0x10000000);

	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
}

static void bd82x6x_sata_enable(struct udevice *dev)
{
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	unsigned port_map;
	const char *mode;
	u16 map = 0;

	/*
	 * Set SATA controller mode early so the resource allocator can
	 * properly assign IO/Memory resources for the controller.
	 */
	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (mode && !strcmp(mode, "ahci"))
		map = 0x0060;
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);

	map |= (port_map ^ 0x3f) << 8;
	dm_pci_write_config16(dev, 0x90, map);
}

static int bd82x6x_sata_bind(struct udevice *dev)
{
	struct udevice *scsi_dev;
	int ret;

	if (gd->flags & GD_FLG_RELOC) {
		ret = ahci_bind_scsi(dev, &scsi_dev);
		if (ret)
			return ret;
	}

	return 0;
}

static int bd82x6x_sata_probe(struct udevice *dev)
{
	struct udevice *pch;
	int ret;

	ret = uclass_first_device_err(UCLASS_PCH, &pch);
	if (ret)
		return ret;

	if (!(gd->flags & GD_FLG_RELOC))
		bd82x6x_sata_enable(dev);
	else {
		bd82x6x_sata_init(dev, pch);
		ret = ahci_probe_scsi_pci(dev);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct udevice_id bd82x6x_ahci_ids[] = {
	{ .compatible = "intel,pantherpoint-ahci" },
	{ }
};

U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	.name		= "ahci_ivybridge",
	.id		= UCLASS_AHCI,
	.of_match	= bd82x6x_ahci_ids,
	.bind		= bd82x6x_sata_bind,
	.probe		= bd82x6x_sata_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
3ac83935 SG	2	/*
	3	* From Coreboot
	4	* Copyright (C) 2008-2009 coresystems GmbH
3ac83935 SG	5	*/
3ac83935 SG	6
d678a59d	7	#include <common.h>
32e9ec1f	8	#include <ahci.h>
d46f2a68	9	#include <dm.h>
3ac83935	10	#include <fdtdec.h>
f7ae49fc	11	#include <log.h>
401d1c4f	12	#include <asm/global_data.h>
3ac83935	13	#include <asm/io.h>
7e4a6ae6	14	#include <asm/pch_common.h>
3ac83935 SG	15	#include <asm/pci.h>
3ac83935 SG	16	#include <asm/arch/pch.h>
3ac83935	17
d46f2a68 SG	18	DECLARE_GLOBAL_DATA_PTR;
d46f2a68 SG	19
ddf10c20	20	static void common_sata_init(struct udevice *dev, unsigned int port_map)
3ac83935 SG	21	{
	22	u32 reg32;
	23	u16 reg16;
	24
	25	/* Set IDE I/O Configuration */
	26	reg32 = SIG_MODE_PRI_NORMAL \| FAST_PCB1 \| FAST_PCB0 \| PCB1 \| PCB0;
ddf10c20	27	dm_pci_write_config32(dev, IDE_CONFIG, reg32);
3ac83935 SG	28
3ac83935 SG	29	/* Port enable */
ddf10c20	30	dm_pci_read_config16(dev, 0x92, &reg16);
3ac83935 SG	31	reg16 &= ~0x3f;
3ac83935 SG	32	reg16 \|= port_map;
ddf10c20	33	dm_pci_write_config16(dev, 0x92, reg16);
3ac83935 SG	34
	35	/* SATA Initialization register */
	36	port_map &= 0xff;
ddf10c20	37	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) \| 0x183);
3ac83935 SG	38	}
3ac83935 SG	39
9434c7a3	40	static void bd82x6x_sata_init(struct udevice dev, struct udevice pch)
3ac83935 SG	41	{
3ac83935 SG	42	unsigned int port_map, speed_support, port_tx;
ddf10c20	43	const void *blob = gd->fdt_blob;
e160f7d4	44	int node = dev_of_offset(dev);
3ac83935 SG	45	const char *mode;
	46	u32 reg32;
	47	u16 reg16;
	48
	49	debug("SATA: Initializing...\n");
	50
	51	/* SATA configuration */
	52	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	53	speed_support = fdtdec_get_int(blob, node,
	54	"sata_interface_speed_support", 0);
	55
3ac83935 SG	56	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
3ac83935 SG	57	if (!mode \|\| !strcmp(mode, "ahci")) {
c7ccb2c0	58	ulong abar;
3ac83935 SG	59
	60	debug("SATA: Controller in AHCI mode\n");
	61
3ac83935	62	/* Set timings */
ddf10c20	63	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	64	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	65	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	66	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	67	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
	68
	69	/* Sync DMA */
ddf10c20 SG	70	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
ddf10c20 SG	71	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
3ac83935 SG	72
	73	common_sata_init(dev, 0x8000 \| port_map);
	74
	75	/* Initialize AHCI memory-mapped space */
ddf10c20	76	abar = dm_pci_read_bar32(dev, 5);
c7ccb2c0	77	debug("ABAR: %08lx\n", abar);
3ac83935 SG	78	/* CAP (HBA Capabilities) : enable power management */
	79	reg32 = readl(abar + 0x00);
	80	reg32 \|= 0x0c006000; /* set PSC+SSC+SALP+SSS */
	81	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
	82	/* Set ISS, if available */
	83	if (speed_support) {
	84	reg32 &= ~0x00f00000;
	85	reg32 \|= (speed_support & 0x03) << 20;
	86	}
	87	writel(reg32, abar + 0x00);
	88	/* PI (Ports implemented) */
	89	writel(port_map, abar + 0x0c);
	90	(void) readl(abar + 0x0c); /* Read back 1 */
	91	(void) readl(abar + 0x0c); /* Read back 2 */
	92	/* CAP2 (HBA Capabilities Extended)*/
	93	reg32 = readl(abar + 0x24);
	94	reg32 &= ~0x00000002;
	95	writel(reg32, abar + 0x24);
	96	/* VSP (Vendor Specific Register */
	97	reg32 = readl(abar + 0xa0);
	98	reg32 &= ~0x00000005;
	99	writel(reg32, abar + 0xa0);
	100	} else if (!strcmp(mode, "combined")) {
	101	debug("SATA: Controller in combined mode\n");
	102
	103	/* No AHCI: clear AHCI base */
ddf10c20	104	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935	105	/* And without AHCI BAR no memory decoding */
ddf10c20	106	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	107	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	108	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935	109
ddf10c20	110	dm_pci_write_config8(dev, 0x09, 0x80);
3ac83935 SG	111
3ac83935 SG	112	/* Set timings */
ddf10c20	113	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935	114	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
ddf10c20	115	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	116	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
	117	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
	118
	119	/* Sync DMA */
ddf10c20 SG	120	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
ddf10c20 SG	121	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
3ac83935 SG	122
	123	common_sata_init(dev, port_map);
	124	} else {
	125	debug("SATA: Controller in plain-ide mode\n");
	126
	127	/* No AHCI: clear AHCI base */
ddf10c20	128	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935 SG	129
3ac83935 SG	130	/* And without AHCI BAR no memory decoding */
ddf10c20	131	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	132	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	133	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935 SG	134
	135	/*
	136	* Native mode capable on both primary and secondary (0xa)
	137	* OR'ed with enabled (0x50) = 0xf
	138	*/
ddf10c20	139	dm_pci_write_config8(dev, 0x09, 0x8f);
3ac83935 SG	140
3ac83935 SG	141	/* Set timings */
ddf10c20	142	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	143	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	144	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	145	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	146	IDE_SITRE \| IDE_ISP_3_CLOCKS \|
	147	IDE_RCT_1_CLOCKS \| IDE_IE0 \| IDE_TIME0);
	148
	149	/* Sync DMA */
ddf10c20 SG	150	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 \| IDE_PSDE0);
ddf10c20 SG	151	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
3ac83935 SG	152
	153	common_sata_init(dev, port_map);
	154	}
	155
	156	/* Set Gen3 Transmitter settings if needed */
	157	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	158	if (port_tx)
9434c7a3	159	pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
3ac83935 SG	160
	161	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	162	if (port_tx)
9434c7a3	163	pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
3ac83935 SG	164
3ac83935 SG	165	/* Additional Programming Requirements */
7e4a6ae6 SG	166	pch_common_sir_write(dev, 0x04, 0x00001600);
	167	pch_common_sir_write(dev, 0x28, 0xa0000033);
	168	reg32 = pch_common_sir_read(dev, 0x54);
3ac83935 SG	169	reg32 &= 0xff000000;
3ac83935 SG	170	reg32 \|= 0x5555aa;
7e4a6ae6 SG	171	pch_common_sir_write(dev, 0x54, reg32);
	172	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	173	reg32 = pch_common_sir_read(dev, 0x68);
3ac83935 SG	174	reg32 &= 0xffff0000;
3ac83935 SG	175	reg32 \|= 0xcccc;
7e4a6ae6 SG	176	pch_common_sir_write(dev, 0x68, reg32);
7e4a6ae6 SG	177	reg32 = pch_common_sir_read(dev, 0x78);
3ac83935 SG	178	reg32 &= 0x0000ffff;
3ac83935 SG	179	reg32 \|= 0x88880000;
7e4a6ae6 SG	180	pch_common_sir_write(dev, 0x78, reg32);
	181	pch_common_sir_write(dev, 0x84, 0x001c7000);
	182	pch_common_sir_write(dev, 0x88, 0x88338822);
	183	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	184	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	185	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	186	pch_common_sir_write(dev, 0xd4, 0x10000000);
3ac83935	187
9434c7a3 SG	188	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
9434c7a3 SG	189	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
3ac83935 SG	190	}
3ac83935 SG	191
ddf10c20	192	static void bd82x6x_sata_enable(struct udevice *dev)
3ac83935	193	{
ddf10c20	194	const void *blob = gd->fdt_blob;
e160f7d4	195	int node = dev_of_offset(dev);
3ac83935 SG	196	unsigned port_map;
	197	const char *mode;
	198	u16 map = 0;
	199
	200	/*
	201	* Set SATA controller mode early so the resource allocator can
	202	* properly assign IO/Memory resources for the controller.
	203	*/
	204	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	205	if (mode && !strcmp(mode, "ahci"))
	206	map = 0x0060;
	207	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	208
	209	map \|= (port_map ^ 0x3f) << 8;
ddf10c20	210	dm_pci_write_config16(dev, 0x90, map);
3ac83935	211	}
d46f2a68	212
32e9ec1f SG	213	static int bd82x6x_sata_bind(struct udevice *dev)
	214	{
	215	struct udevice *scsi_dev;
	216	int ret;
	217
	218	if (gd->flags & GD_FLG_RELOC) {
	219	ret = ahci_bind_scsi(dev, &scsi_dev);
	220	if (ret)
	221	return ret;
	222	}
	223
	224	return 0;
	225	}
	226
d46f2a68 SG	227	static int bd82x6x_sata_probe(struct udevice *dev)
d46f2a68 SG	228	{
9434c7a3 SG	229	struct udevice *pch;
	230	int ret;
	231
3f603cbb	232	ret = uclass_first_device_err(UCLASS_PCH, &pch);
9434c7a3 SG	233	if (ret)
9434c7a3 SG	234	return ret;
9434c7a3	235
d46f2a68	236	if (!(gd->flags & GD_FLG_RELOC))
ddf10c20	237	bd82x6x_sata_enable(dev);
32e9ec1f	238	else {
9434c7a3	239	bd82x6x_sata_init(dev, pch);
745a94f3	240	ret = ahci_probe_scsi_pci(dev);
32e9ec1f SG	241	if (ret)
	242	return ret;
	243	}
d46f2a68 SG	244
	245	return 0;
	246	}
	247
	248	static const struct udevice_id bd82x6x_ahci_ids[] = {
	249	{ .compatible = "intel,pantherpoint-ahci" },
	250	{ }
	251	};
	252
	253	U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	254	.name = "ahci_ivybridge",
a219639d	255	.id = UCLASS_AHCI,
d46f2a68	256	.of_match = bd82x6x_ahci_ids,
32e9ec1f	257	.bind = bd82x6x_sata_bind,
d46f2a68 SG	258	.probe = bd82x6x_sata_probe,
d46f2a68 SG	259	};