[thirdparty/u-boot.git] / arch / x86 / include / asm / cb_sysinfo.h

/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * This file is part of the libpayload project.
 *
 * Copyright (C) 2008 Advanced Micro Devices, Inc.
 */

#ifndef _COREBOOT_SYSINFO_H
#define _COREBOOT_SYSINFO_H

#include <asm/coreboot_tables.h>

/* Maximum number of memory range definitions */
#define SYSINFO_MAX_MEM_RANGES	32
/* Allow a maximum of 8 GPIOs */
#define SYSINFO_MAX_GPIOS	8
/* Up to 10 MAC addresses */
#define SYSINFO_MAX_MACS 10
/* Track the first 32 unimplemented tags */
#define SYSINFO_MAX_UNIMPL	32

/**
 * struct sysinfo_t - Information passed to U-Boot from coreboot
 *
 * Coreboot passes on a lot of information using a list of individual data
 * structures identified by a numeric tag. These are parsed in U-Boot to produce
 * this struct. Some of the pointers here point back to the tagged data
 * structure, since it is assumed to remain around while U-Boot is running.
 *
 * The 'cbsysinfo' command can display this information.
 *
 * @cpu_khz: CPU frequence in KHz (e.g. 1100000)
 * @serial: Pointer to the serial information, NULL if none
 * @ser_ioport: Not actually provided by a tag and not used on modern hardware,
 *	which typicaally uses a memory-mapped port
 * @ser_base: Not used at all, but present to match up with the coreboot data
 *	structure
 * @n_memranges: Number of memory ranges
 * @memrange: List of memory ranges:
 *	@base: Base address of range
 *	@size: Size of range in bytes
 *	@type: Type of range (CB_MEM_RAM, etc.)
 * @option_table: Provides a pointer to the CMOS RAM options table, which
 *	indicates which options are available. The header is followed by a list
 *	of struct cb_cmos_entries records, so that an option can be found from
 *	its name. This is not used in U-Boot. NULL if not present
 * @cmos_range_start: Start bit of the CMOS checksum range (in fact this must
 *	be a multiple of 8)
 * @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is
 *	the inclusive end.
 * @cmos_checksum_location: Location of checksum, multiplied by 8. This is the
 *	byte offset into the CMOS RAM of the first checksum byte. The second one
 *	follows immediately. The checksum is a simple 16-bit sum of all the
 *	bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive,
 *	in big-endian format (so sum >> 8 is stored in the first byte).
 * @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot
 *	(typically 0x34)
 * @vbnv_size: Number of bytes used by Chromium OS verified boot (typically
 *	0x10)
 * @extra_version: Extra version information, typically ""
 * @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020"
 * @compile_time: Compilation time, e.g. "02:51:58"
 * @compile_by: Who compiled coreboot (never set?)
 * @compile_host: Name of the machine that compiled coreboot (never set?)
 * @compile_domain: Domain name of the machine that compiled coreboot (never
 *	set?)
 * @compiler: Name of the compiler used to build coreboot (never set?)
 * @linker: Name of the linker used to build coreboot (never set?)
 * @assembler: Name of the assembler used to build coreboot (never set?)
 * @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d
 * @framebuffer: Address of framebuffer tag, or NULL if none. See
 *	struct cb_framebuffer for the definition
 * @num_gpios: Number of verified-boot GPIOs
 * @gpios: List of GPIOs:
 *	@port: GPIO number, or 0xffffffff if not a GPIO
 *	@polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH
 *	@value: Value of GPIO (0 or 1)
 *	@name: Name of GPIO
 *
 *	A typical list is:
 *	  id: port     polarity val name
 *	   0:    -  active-high   1 write protect
 *	   1:    -  active-high   0 recovery
 *	   2:    -  active-high   1 lid
 *	   3:    -  active-high   0 power
 *	   4:    -  active-high   0 oprom
 *	   5:   29  active-high   0 EC in RW
 *
 * @num_macs: Number of MAC addresses
 * @macs: List of MAC addresses
 * @serialno: Serial number, or NULL (never set?)
 * @mbtable: Address of the multiboot table, or NULL. This is a
 *	struct multiboot_header, not used in U-Boot
 * @header: Address of header, if there is a CB_TAG_FORWARD, else NULL
 * @mainboard: Pointer to mainboard info or NULL. Typically the vendor is
 *	"Google" and the part number is ""
 * @vboot_handoff: Pointer to Chromium OS verified boot hand-off information.
 *	This is struct vboot_handoff, providing access to internal information
 *	generated by coreboot when this is being used
 * @vboot_handoff_size: Size of hand-off information (typically 0xc0c)
 * @vdat_addr: Pointer to Chromium OS verified boot data, which uses
 *	struct chromeos_acpi. It sits in the Intel Global NVS struct, after the
 *	first 0x100 bytes
 * @vdat_size: Size of this data, typically 0xf00
 * @smbios_start: Address of SMBIOS tables
 * @smbios_size: Size of SMBIOS tables (e.g. 0x800)
 * @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot
 * @tstamp_table: Pointer to timestamp_table, struct timestamp_table
 * @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides
 *	access to the console output generated by coreboot, typically about 64KB
 *	and mostly PCI enumeration info
 * @mrc_cache: Pointer to memory-reference-code cache, typically NULL
 * acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs
 * @board_id: Board ID indicating the board variant, typically 0xffffffff
 * @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff
 * @wifi_calibration: WiFi calibration info, NULL if none
 * @ramoops_buffer: Address of kernel Ramoops buffer
 * @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB
 * @spi_flash: Information about SPI flash:
 *	@size: Size in bytes, e.g. 16MB
 *	@sector_size; Sector size of flash device, e.g. 4KB
 *	@erase_cmd: Command used to erase flash, or 0 if not used
 * @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a
 *	__FMAP__ header. It provides information about the different top-level
 *	sections in the SPI flash, e.g. 0x204000
 * @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for
 *	read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in
 *	the flash map. It holds various coreboot binaries as well as
 *	video-configuration files and graphics data for the Chromium OS
 *	verified boot user interface.
 * @cbfs_size: Size of CBFS, e.g. 0x17b000
 * @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB
 * @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See
 *	https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c
 * @mtc_size: Size of MTC region
 * @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
 *	not used
 * @rsdp: Pointer to ACPI RSDP table
 * @unimpl_count: Number of entries in unimpl_map[]
 * @unimpl: List of unimplemented IDs (bottom 8 bits only)
 * @table_size: Number of bytes taken up by the sysinfo table
 * @rec_count: Number of records in the sysinfo table
 */
struct sysinfo_t {
	unsigned int cpu_khz;
	struct cb_serial *serial;
	unsigned short ser_ioport;
	unsigned long ser_base; // for mmapped serial

	int n_memranges;

	struct memrange {
		unsigned long long base;
		unsigned long long size;
		unsigned int type;
	} memrange[SYSINFO_MAX_MEM_RANGES];

	struct cb_cmos_option_table *option_table;
	u32 cmos_range_start;
	u32 cmos_range_end;
	u32 cmos_checksum_location;
	u32 vbnv_start;
	u32 vbnv_size;

	char *version;
	char *extra_version;
	char *build;
	char *compile_time;
	char *compile_by;
	char *compile_host;
	char *compile_domain;
	char *compiler;
	char *linker;
	char *assembler;

	char *cb_version;

	struct cb_framebuffer *framebuffer;

	int num_gpios;
	struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
	int num_macs;
	struct mac_address macs[SYSINFO_MAX_MACS];
	char *serialno;

	unsigned long *mbtable; /** Pointer to the multiboot table */

	struct cb_header *header;
	struct cb_mainboard *mainboard;

	void	*vboot_handoff;
	u32	vboot_handoff_size;
	void	*vdat_addr;
	u32	vdat_size;
	u64 smbios_start;
	u32 smbios_size;

	int x86_rom_var_mtrr_index;

	void		*tstamp_table;
	void		*cbmem_cons;
	void		*mrc_cache;
	void		*acpi_gnvs;
	u32		board_id;
	u32		ram_code;
	void		*wifi_calibration;
	u64	ramoops_buffer;
	u32	ramoops_buffer_size;
	struct {
		u32 size;
		u32 sector_size;
		u32 erase_cmd;
	} spi_flash;
	u64 fmap_offset;
	u64 cbfs_offset;
	u64 cbfs_size;
	u64 boot_media_size;
	u64 mtc_start;
	u32 mtc_size;
	void	*chromeos_vpd;
	void *rsdp;
	u32 unimpl_count;
	u8 unimpl[SYSINFO_MAX_UNIMPL];
	uint table_size;
	uint rec_count;
};

extern struct sysinfo_t lib_sysinfo;

/**
 * get_coreboot_info() - parse the coreboot sysinfo table
 *
 * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
 * so.
 *
 * @info: Place to put the parsed information
 * Return: 0 if OK, -ENOENT if no table found
 */
int get_coreboot_info(struct sysinfo_t *info);

/**
 * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
 *
 * Return: pointer to sysinfo, or NULL if not available
 */
const struct sysinfo_t *cb_get_sysinfo(void);

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: BSD-3-Clause */
63f559cd GB	2	/*
	3	* This file is part of the libpayload project.
	4	*
	5	* Copyright (C) 2008 Advanced Micro Devices, Inc.
63f559cd GB	6	*/
	7
	8	#ifndef _COREBOOT_SYSINFO_H
	9	#define _COREBOOT_SYSINFO_H
	10
f1d6fda6	11	#include <asm/coreboot_tables.h>
63f559cd	12
89b87081 BM	13	/* Maximum number of memory range definitions */
89b87081 BM	14	#define SYSINFO_MAX_MEM_RANGES 32
402ed004	15	/* Allow a maximum of 8 GPIOs */
89b87081	16	#define SYSINFO_MAX_GPIOS 8
1058ab37 SG	17	/* Up to 10 MAC addresses */
1058ab37 SG	18	#define SYSINFO_MAX_MACS 10
2f5210b7 SG	19	/* Track the first 32 unimplemented tags */
2f5210b7 SG	20	#define SYSINFO_MAX_UNIMPL 32
63f559cd	21
1058ab37 SG	22	/**
	23	* struct sysinfo_t - Information passed to U-Boot from coreboot
	24	*
	25	* Coreboot passes on a lot of information using a list of individual data
	26	* structures identified by a numeric tag. These are parsed in U-Boot to produce
	27	* this struct. Some of the pointers here point back to the tagged data
	28	* structure, since it is assumed to remain around while U-Boot is running.
	29	*
	30	* The 'cbsysinfo' command can display this information.
	31	*
	32	* @cpu_khz: CPU frequence in KHz (e.g. 1100000)
	33	* @serial: Pointer to the serial information, NULL if none
	34	* @ser_ioport: Not actually provided by a tag and not used on modern hardware,
	35	* which typicaally uses a memory-mapped port
	36	* @ser_base: Not used at all, but present to match up with the coreboot data
	37	* structure
	38	* @n_memranges: Number of memory ranges
	39	* @memrange: List of memory ranges:
	40	* @base: Base address of range
	41	* @size: Size of range in bytes
	42	* @type: Type of range (CB_MEM_RAM, etc.)
	43	* @option_table: Provides a pointer to the CMOS RAM options table, which
	44	* indicates which options are available. The header is followed by a list
	45	* of struct cb_cmos_entries records, so that an option can be found from
	46	* its name. This is not used in U-Boot. NULL if not present
	47	* @cmos_range_start: Start bit of the CMOS checksum range (in fact this must
	48	* be a multiple of 8)
	49	* @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is
	50	* the inclusive end.
	51	* @cmos_checksum_location: Location of checksum, multiplied by 8. This is the
	52	* byte offset into the CMOS RAM of the first checksum byte. The second one
	53	* follows immediately. The checksum is a simple 16-bit sum of all the
	54	* bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive,
	55	* in big-endian format (so sum >> 8 is stored in the first byte).
	56	* @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot
	57	* (typically 0x34)
	58	* @vbnv_size: Number of bytes used by Chromium OS verified boot (typically
	59	* 0x10)
	60	* @extra_version: Extra version information, typically ""
	61	* @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020"
	62	* @compile_time: Compilation time, e.g. "02:51:58"
	63	* @compile_by: Who compiled coreboot (never set?)
	64	* @compile_host: Name of the machine that compiled coreboot (never set?)
	65	* @compile_domain: Domain name of the machine that compiled coreboot (never
	66	* set?)
	67	* @compiler: Name of the compiler used to build coreboot (never set?)
	68	* @linker: Name of the linker used to build coreboot (never set?)
	69	* @assembler: Name of the assembler used to build coreboot (never set?)
	70	* @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d
	71	* @framebuffer: Address of framebuffer tag, or NULL if none. See
	72	* struct cb_framebuffer for the definition
	73	* @num_gpios: Number of verified-boot GPIOs
	74	* @gpios: List of GPIOs:
	75	* @port: GPIO number, or 0xffffffff if not a GPIO
	76	* @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH
	77	* @value: Value of GPIO (0 or 1)
	78	* @name: Name of GPIO
	79	*
	80	* A typical list is:
	81	* id: port polarity val name
	82	* 0: - active-high 1 write protect
	83	* 1: - active-high 0 recovery
	84	* 2: - active-high 1 lid
	85	* 3: - active-high 0 power
86	* 4: - active-high 0 oprom
87	* 5: 29 active-high 0 EC in RW
88	*
89	* @num_macs: Number of MAC addresses
90	* @macs: List of MAC addresses
91	* @serialno: Serial number, or NULL (never set?)
92	* @mbtable: Address of the multiboot table, or NULL. This is a
93	* struct multiboot_header, not used in U-Boot
94	* @header: Address of header, if there is a CB_TAG_FORWARD, else NULL
95	* @mainboard: Pointer to mainboard info or NULL. Typically the vendor is
96	* "Google" and the part number is ""
97	* @vboot_handoff: Pointer to Chromium OS verified boot hand-off information.
98	* This is struct vboot_handoff, providing access to internal information
99	* generated by coreboot when this is being used
100	* @vboot_handoff_size: Size of hand-off information (typically 0xc0c)
101	* @vdat_addr: Pointer to Chromium OS verified boot data, which uses
102	* struct chromeos_acpi. It sits in the Intel Global NVS struct, after the
103	* first 0x100 bytes
104	* @vdat_size: Size of this data, typically 0xf00
105	* @smbios_start: Address of SMBIOS tables
106	* @smbios_size: Size of SMBIOS tables (e.g. 0x800)
107	* @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot
108	* @tstamp_table: Pointer to timestamp_table, struct timestamp_table
109	* @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides
110	* access to the console output generated by coreboot, typically about 64KB
111	* and mostly PCI enumeration info
112	* @mrc_cache: Pointer to memory-reference-code cache, typically NULL
113	* acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs
114	* @board_id: Board ID indicating the board variant, typically 0xffffffff
115	* @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff
116	* @wifi_calibration: WiFi calibration info, NULL if none
117	* @ramoops_buffer: Address of kernel Ramoops buffer
118	* @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB
119	* @spi_flash: Information about SPI flash:
120	* @size: Size in bytes, e.g. 16MB
121	* @sector_size; Sector size of flash device, e.g. 4KB
122	* @erase_cmd: Command used to erase flash, or 0 if not used
123	* @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a
124	* __FMAP__ header. It provides information about the different top-level
125	* sections in the SPI flash, e.g. 0x204000
126	* @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for
127	* read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in
128	* the flash map. It holds various coreboot binaries as well as
129	* video-configuration files and graphics data for the Chromium OS
130	* verified boot user interface.
131	* @cbfs_size: Size of CBFS, e.g. 0x17b000
132	* @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB
133	* @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See
134	* https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c
135	* @mtc_size: Size of MTC region
136	* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
137	* not used
368fd564	138	* @rsdp: Pointer to ACPI RSDP table
2f5210b7 SG	139	* @unimpl_count: Number of entries in unimpl_map[]
2f5210b7 SG	140	* @unimpl: List of unimplemented IDs (bottom 8 bits only)
db971a75 SG	141	* @table_size: Number of bytes taken up by the sysinfo table
db971a75 SG	142	* @rec_count: Number of records in the sysinfo table
1058ab37	143	*/
63f559cd	144	struct sysinfo_t {
1058ab37 SG	145	unsigned int cpu_khz;
	146	struct cb_serial *serial;
	147	unsigned short ser_ioport;
	148	unsigned long ser_base; // for mmapped serial
	149
63f559cd	150	int n_memranges;
1058ab37	151
63f559cd GB	152	struct memrange {
	153	unsigned long long base;
	154	unsigned long long size;
	155	unsigned int type;
	156	} memrange[SYSINFO_MAX_MEM_RANGES];
	157
1058ab37	158	struct cb_cmos_option_table *option_table;
63f559cd GB	159	u32 cmos_range_start;
	160	u32 cmos_range_end;
	161	u32 cmos_checksum_location;
402ed004 SG	162	u32 vbnv_start;
	163	u32 vbnv_size;
	164
	165	char *version;
	166	char *extra_version;
	167	char *build;
	168	char *compile_time;
	169	char *compile_by;
	170	char *compile_host;
	171	char *compile_domain;
	172	char *compiler;
	173	char *linker;
	174	char *assembler;
63f559cd	175
1058ab37 SG	176	char *cb_version;
1058ab37 SG	177
63f559cd GB	178	struct cb_framebuffer *framebuffer;
63f559cd GB	179
402ed004 SG	180	int num_gpios;
402ed004 SG	181	struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
1058ab37 SG	182	int num_macs;
	183	struct mac_address macs[SYSINFO_MAX_MACS];
	184	char *serialno;
	185
	186	unsigned long mbtable; /* Pointer to the multiboot table */
402ed004	187
1058ab37 SG	188	struct cb_header *header;
	189	struct cb_mainboard *mainboard;
	190
	191	void *vboot_handoff;
	192	u32 vboot_handoff_size;
402ed004 SG	193	void *vdat_addr;
402ed004 SG	194	u32 vdat_size;
53942b96 CG	195	u64 smbios_start;
53942b96 CG	196	u32 smbios_size;
402ed004	197
1058ab37 SG	198	int x86_rom_var_mtrr_index;
	199
	200	void *tstamp_table;
	201	void *cbmem_cons;
	202	void *mrc_cache;
	203	void *acpi_gnvs;
	204	u32 board_id;
	205	u32 ram_code;
	206	void *wifi_calibration;
	207	u64 ramoops_buffer;
	208	u32 ramoops_buffer_size;
	209	struct {
	210	u32 size;
	211	u32 sector_size;
	212	u32 erase_cmd;
	213	} spi_flash;
	214	u64 fmap_offset;
	215	u64 cbfs_offset;
	216	u64 cbfs_size;
	217	u64 boot_media_size;
	218	u64 mtc_start;
	219	u32 mtc_size;
	220	void *chromeos_vpd;
368fd564	221	void *rsdp;
2f5210b7 SG	222	u32 unimpl_count;
2f5210b7 SG	223	u8 unimpl[SYSINFO_MAX_UNIMPL];
db971a75 SG	224	uint table_size;
db971a75 SG	225	uint rec_count;
63f559cd GB	226	};
	227
	228	extern struct sysinfo_t lib_sysinfo;
	229
c5c62155 SG	230	/**
	231	* get_coreboot_info() - parse the coreboot sysinfo table
	232	*
	233	* Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
	234	* so.
	235	*
	236	* @info: Place to put the parsed information
185f812c	237	* Return: 0 if OK, -ENOENT if no table found
c5c62155	238	*/
1329020d BM	239	int get_coreboot_info(struct sysinfo_t *info);
1329020d BM	240
c5c62155 SG	241	/**
	242	* cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
	243	*
185f812c	244	* Return: pointer to sysinfo, or NULL if not available
c5c62155 SG	245	*/
	246	const struct sysinfo_t *cb_get_sysinfo(void);
	247
63f559cd	248	#endif