[thirdparty/u-boot.git] / arch / x86 / include / asm / global_data.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2002-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 */

#ifndef	__ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H

#ifndef __ASSEMBLY__

#include <linux/types.h>
#include <asm/processor.h>
#include <asm/mrccache.h>

enum pei_boot_mode_t {
	PEI_BOOT_NONE = 0,
	PEI_BOOT_SOFT_RESET,
	PEI_BOOT_RESUME,

};

struct dimm_info {
	uint32_t dimm_size;
	uint16_t ddr_type;
	uint16_t ddr_frequency;
	uint8_t rank_per_dimm;
	uint8_t channel_num;
	uint8_t dimm_num;
	uint8_t bank_locator;
	/* The 5th byte is '\0' for the end of string */
	uint8_t serial[5];
	/* The 19th byte is '\0' for the end of string */
	uint8_t module_part_number[19];
	uint16_t mod_id;
	uint8_t mod_type;
	uint8_t bus_width;
} __packed;

struct pei_memory_info {
	uint8_t dimm_cnt;
	/* Maximum num of dimm is 8 */
	struct dimm_info dimm[8];
} __packed;

struct memory_area {
	uint64_t start;
	uint64_t size;
};

struct memory_info {
	int num_areas;
	uint64_t total_memory;
	uint64_t total_32bit_memory;
	struct memory_area area[CONFIG_NR_DRAM_BANKS];
};

#define MAX_MTRR_REQUESTS	8

/**
 * A request for a memory region to be set up in a particular way. These
 * requests are processed before board_init_r() is called. They are generally
 * optional and can be ignored with some performance impact.
 */
struct mtrr_request {
	int type;		/* MTRR_TYPE_... */
	uint64_t start;
	uint64_t size;
};

/**
 * struct mrc_output - holds the MRC data
 *
 * @buf: MRC training data to save for the next boot. This is set to point to
 *	the raw data after SDRAM init is complete. Then mrccache_setup()
 *	turns it into a proper cache record with a checksum
 * @len: Length of @buf
 * @cache: Resulting cache record
 */
struct mrc_output {
	char *buf;
	uint len;
	struct mrc_data_container *cache;
};

/* Architecture-specific global data */
struct arch_global_data {
	u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
	struct global_data *gd_addr;	/* Location of Global Data */
	uint8_t x86;			/* CPU family */
	uint8_t x86_vendor;		/* CPU vendor */
	uint8_t x86_model;
	uint8_t x86_mask;
	uint32_t x86_device;
	uint64_t tsc_base;		/* Initial value returned by rdtsc() */
	bool tsc_inited;		/* true if tsc is ready for use */
	unsigned long clock_rate;	/* Clock rate of timer in Hz */
	void *new_fdt;			/* Relocated FDT */
	uint32_t bist;			/* Built-in self test value */
	enum pei_boot_mode_t pei_boot_mode;
	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
	struct memory_info meminfo;	/* Memory information */
	struct pei_memory_info pei_meminfo;	/* PEI memory information */
#ifdef CONFIG_USE_HOB
	void *hob_list;			/* FSP HOB list */
#endif
	struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
	int mtrr_req_count;
	int has_mtrr;
	/* MRC training data */
	struct mrc_output mrc[MRC_TYPE_COUNT];
	ulong table;			/* Table pointer from previous loader */
	int turbo_state;		/* Current turbo state */
	struct irq_routing_table *pirq_routing_table;
	int dw_i2c_num_cards;		/* Used by designware i2c driver */
#ifdef CONFIG_SEABIOS
	u32 high_table_ptr;
	u32 high_table_limit;
#endif
	int prev_sleep_state;		/* Previous sleep state ACPI_S0/1../5 */
	ulong backup_mem;		/* Backup memory address for S3 */
#ifdef CONFIG_FSP_VERSION2
	struct fsp_header *fsp_s_hdr;	/* Pointer to FSP-S header */
#endif
	void *itss_priv;		/* Private ITSS data pointer */
	ulong coreboot_table;		/* Address of coreboot table */
	ulong table_start;		/* Start address of x86 tables */
	ulong table_end;		/* End address of x86 tables */
	ulong table_start_high;		/* Start address of high x86 tables */
	ulong table_end_high;		/* End address of high x86 tables */
	ulong smbios_start;		/* Start address of SMBIOS table */
};

#endif

#include <asm-generic/global_data.h>

#ifndef __ASSEMBLY__
# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)

/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
#define gd global_data_ptr

#define DECLARE_GLOBAL_DATA_PTR   extern struct global_data *global_data_ptr
# else
static inline notrace gd_t *get_fs_gd_ptr(void)
{
	gd_t *gd_ptr;

#if CONFIG_IS_ENABLED(X86_64)
	asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
#else
	asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
#endif

	return gd_ptr;
}

#define gd	get_fs_gd_ptr()

#define DECLARE_GLOBAL_DATA_PTR
# endif

#endif

#endif /* __ASM_GBL_DATA_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2262cfee	2	/*
91a76751	3	* (C) Copyright 2002-2010
2262cfee	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2262cfee WD	5	*/
	6
	7	#ifndef __ASM_GBL_DATA_H
	8	#define __ASM_GBL_DATA_H
5cb48582 SG	9
	10	#ifndef __ASSEMBLY__
	11
071cf276	12	#include <linux/types.h>
2db93745	13	#include <asm/processor.h>
37a508f8	14	#include <asm/mrccache.h>
2db93745	15
8e0df066 SG	16	enum pei_boot_mode_t {
	17	PEI_BOOT_NONE = 0,
	18	PEI_BOOT_SOFT_RESET,
	19	PEI_BOOT_RESUME,
	20
	21	};
	22
2627c7e2 SG	23	struct dimm_info {
	24	uint32_t dimm_size;
	25	uint16_t ddr_type;
	26	uint16_t ddr_frequency;
	27	uint8_t rank_per_dimm;
	28	uint8_t channel_num;
	29	uint8_t dimm_num;
	30	uint8_t bank_locator;
	31	/* The 5th byte is '\0' for the end of string */
	32	uint8_t serial[5];
	33	/* The 19th byte is '\0' for the end of string */
	34	uint8_t module_part_number[19];
	35	uint16_t mod_id;
	36	uint8_t mod_type;
	37	uint8_t bus_width;
	38	} __packed;
	39
	40	struct pei_memory_info {
	41	uint8_t dimm_cnt;
	42	/* Maximum num of dimm is 8 */
	43	struct dimm_info dimm[8];
	44	} __packed;
	45
65dd74a6 SG	46	struct memory_area {
	47	uint64_t start;
	48	uint64_t size;
	49	};
	50
	51	struct memory_info {
	52	int num_areas;
	53	uint64_t total_memory;
	54	uint64_t total_32bit_memory;
	55	struct memory_area area[CONFIG_NR_DRAM_BANKS];
	56	};
	57
aff2523f SG	58	#define MAX_MTRR_REQUESTS 8
	59
	60	/**
	61	* A request for a memory region to be set up in a particular way. These
	62	* requests are processed before board_init_r() is called. They are generally
	63	* optional and can be ignored with some performance impact.
	64	*/
	65	struct mtrr_request {
	66	int type; /* MTRR_TYPE_... */
	67	uint64_t start;
	68	uint64_t size;
	69	};
	70
515e8174 SG	71	/**
	72	* struct mrc_output - holds the MRC data
	73	*
	74	* @buf: MRC training data to save for the next boot. This is set to point to
	75	* the raw data after SDRAM init is complete. Then mrccache_setup()
	76	* turns it into a proper cache record with a checksum
	77	* @len: Length of @buf
	78	* @cache: Resulting cache record
	79	*/
	80	struct mrc_output {
	81	char *buf;
	82	uint len;
	83	struct mrc_data_container *cache;
	84	};
	85
5cb48582 SG	86	/* Architecture-specific global data */
5cb48582 SG	87	struct arch_global_data {
2db93745	88	u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
49491669 BM	89	struct global_data gd_addr; / Location of Global Data */
	90	uint8_t x86; /* CPU family */
	91	uint8_t x86_vendor; /* CPU vendor */
	92	uint8_t x86_model;
	93	uint8_t x86_mask;
52f952bf	94	uint32_t x86_device;
bc2df1af	95	uint64_t tsc_base; /* Initial value returned by rdtsc() */
a478a26c	96	bool tsc_inited; /* true if tsc is ready for use */
2ff50f5f	97	unsigned long clock_rate; /* Clock rate of timer in Hz */
f697d528	98	void new_fdt; / Relocated FDT */
f67cd51e	99	uint32_t bist; /* Built-in self test value */
8e0df066	100	enum pei_boot_mode_t pei_boot_mode;
1b4f25ff	101	const struct pch_gpio_map gpio_map; / board GPIO map */
65dd74a6	102	struct memory_info meminfo; /* Memory information */
2627c7e2	103	struct pei_memory_info pei_meminfo; /* PEI memory information */
544293f8	104	#ifdef CONFIG_USE_HOB
49491669	105	void hob_list; / FSP HOB list */
bceb9f0f	106	#endif
aff2523f SG	107	struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
aff2523f SG	108	int mtrr_req_count;
49491669	109	int has_mtrr;
515e8174 SG	110	/* MRC training data */
515e8174 SG	111	struct mrc_output mrc[MRC_TYPE_COUNT];
42fde305	112	ulong table; /* Table pointer from previous loader */
a0c75f90	113	int turbo_state; /* Current turbo state */
1bff8363	114	struct irq_routing_table *pirq_routing_table;
8d72d5bf	115	int dw_i2c_num_cards; /* Used by designware i2c driver */
789b6dce BM	116	#ifdef CONFIG_SEABIOS
	117	u32 high_table_ptr;
	118	u32 high_table_limit;
	119	#endif
e652e130	120	int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */
5ae5aa93	121	ulong backup_mem; /* Backup memory address for S3 */
748ff535 SG	122	#ifdef CONFIG_FSP_VERSION2
	123	struct fsp_header fsp_s_hdr; / Pointer to FSP-S header */
	124	#endif
b95611f6	125	void itss_priv; / Private ITSS data pointer */
9ef16867	126	ulong coreboot_table; /* Address of coreboot table */
6a324897 SG	127	ulong table_start; /* Start address of x86 tables */
	128	ulong table_end; /* End address of x86 tables */
	129	ulong table_start_high; /* Start address of high x86 tables */
	130	ulong table_end_high; /* End address of high x86 tables */
50834884	131	ulong smbios_start; /* Start address of SMBIOS table */
5cb48582 SG	132	};
5cb48582 SG	133
9558b48a	134	#endif
2262cfee	135
43cff66e SG	136	#include <asm-generic/global_data.h>
	137
	138	#ifndef __ASSEMBLY__
a160092a	139	# if defined(CONFIG_EFI_APP) \|\| CONFIG_IS_ENABLED(X86_64)
8f3b9694	140
a160092a	141	/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
8f3b9694 SG	142	#define gd global_data_ptr
	143
	144	#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
	145	# else
33c60a38	146	static inline notrace gd_t *get_fs_gd_ptr(void)
9e6c572f GR	147	{
	148	gd_t *gd_ptr;
	149
a160092a SG	150	#if CONFIG_IS_ENABLED(X86_64)
	151	asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
	152	#else
9e6c572f	153	asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
a160092a	154	#endif
9e6c572f GR	155
	156	return gd_ptr;
	157	}
	158
	159	#define gd get_fs_gd_ptr()
161b3589	160
83ec7de3	161	#define DECLARE_GLOBAL_DATA_PTR
8f3b9694	162	# endif
83ec7de3	163
161b3589 GR	164	#endif
161b3589 GR	165
2262cfee	166	#endif /* __ASM_GBL_DATA_H */