[people/arne_f/kernel.git] / arch / x86 / kernel / idt.c

/*
 * Interrupt descriptor table related code
 *
 * This file is licensed under the GPL V2
 */
#include <linux/interrupt.h>

#include <asm/traps.h>
#include <asm/proto.h>
#include <asm/desc.h>

struct idt_data {
	unsigned int	vector;
	unsigned int	segment;
	struct idt_bits	bits;
	const void	*addr;
};

#define DPL0		0x0
#define DPL3		0x3

#define DEFAULT_STACK	0

#define G(_vector, _addr, _ist, _type, _dpl, _segment)	\
	{						\
		.vector		= _vector,		\
		.bits.ist	= _ist,			\
		.bits.type	= _type,		\
		.bits.dpl	= _dpl,			\
		.bits.p		= 1,			\
		.addr		= _addr,		\
		.segment	= _segment,		\
	}

/* Interrupt gate */
#define INTG(_vector, _addr)				\
	G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)

/* System interrupt gate */
#define SYSG(_vector, _addr)				\
	G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)

/* Interrupt gate with interrupt stack */
#define ISTG(_vector, _addr, _ist)			\
	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)

/* System interrupt gate with interrupt stack */
#define SISTG(_vector, _addr, _ist)			\
	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)

/* Task gate */
#define TSKG(_vector, _gdt)				\
	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)

/*
 * Early traps running on the DEFAULT_STACK because the other interrupt
 * stacks work only after cpu_init().
 */
static const __initdata struct idt_data early_idts[] = {
	INTG(X86_TRAP_DB,		debug),
	SYSG(X86_TRAP_BP,		int3),
#ifdef CONFIG_X86_32
	INTG(X86_TRAP_PF,		page_fault),
#endif
};

/*
 * The default IDT entries which are set up in trap_init() before
 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
 * the traps which use them are reinitialized with IST after cpu_init() has
 * set up TSS.
 */
static const __initdata struct idt_data def_idts[] = {
	INTG(X86_TRAP_DE,		divide_error),
	INTG(X86_TRAP_NMI,		nmi),
	INTG(X86_TRAP_BR,		bounds),
	INTG(X86_TRAP_UD,		invalid_op),
	INTG(X86_TRAP_NM,		device_not_available),
	INTG(X86_TRAP_OLD_MF,		coprocessor_segment_overrun),
	INTG(X86_TRAP_TS,		invalid_TSS),
	INTG(X86_TRAP_NP,		segment_not_present),
	INTG(X86_TRAP_SS,		stack_segment),
	INTG(X86_TRAP_GP,		general_protection),
	INTG(X86_TRAP_SPURIOUS,		spurious_interrupt_bug),
	INTG(X86_TRAP_MF,		coprocessor_error),
	INTG(X86_TRAP_AC,		alignment_check),
	INTG(X86_TRAP_XF,		simd_coprocessor_error),

#ifdef CONFIG_X86_32
	TSKG(X86_TRAP_DF,		GDT_ENTRY_DOUBLEFAULT_TSS),
#else
	INTG(X86_TRAP_DF,		double_fault),
#endif
	INTG(X86_TRAP_DB,		debug),

#ifdef CONFIG_X86_MCE
	INTG(X86_TRAP_MC,		&machine_check),
#endif

	SYSG(X86_TRAP_OF,		overflow),
#if defined(CONFIG_IA32_EMULATION)
	SYSG(IA32_SYSCALL_VECTOR,	entry_INT80_compat),
#elif defined(CONFIG_X86_32)
	SYSG(IA32_SYSCALL_VECTOR,	entry_INT80_32),
#endif
};

/*
 * The APIC and SMP idt entries
 */
static const __initdata struct idt_data apic_idts[] = {
#ifdef CONFIG_SMP
	INTG(RESCHEDULE_VECTOR,		reschedule_interrupt),
	INTG(CALL_FUNCTION_VECTOR,	call_function_interrupt),
	INTG(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt),
	INTG(IRQ_MOVE_CLEANUP_VECTOR,	irq_move_cleanup_interrupt),
	INTG(REBOOT_VECTOR,		reboot_interrupt),
#endif

#ifdef CONFIG_X86_THERMAL_VECTOR
	INTG(THERMAL_APIC_VECTOR,	thermal_interrupt),
#endif

#ifdef CONFIG_X86_MCE_THRESHOLD
	INTG(THRESHOLD_APIC_VECTOR,	threshold_interrupt),
#endif

#ifdef CONFIG_X86_MCE_AMD
	INTG(DEFERRED_ERROR_VECTOR,	deferred_error_interrupt),
#endif

#ifdef CONFIG_X86_LOCAL_APIC
	INTG(LOCAL_TIMER_VECTOR,	apic_timer_interrupt),
	INTG(X86_PLATFORM_IPI_VECTOR,	x86_platform_ipi),
# ifdef CONFIG_HAVE_KVM
	INTG(POSTED_INTR_VECTOR,	kvm_posted_intr_ipi),
	INTG(POSTED_INTR_WAKEUP_VECTOR, kvm_posted_intr_wakeup_ipi),
	INTG(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi),
# endif
# ifdef CONFIG_IRQ_WORK
	INTG(IRQ_WORK_VECTOR,		irq_work_interrupt),
# endif
	INTG(SPURIOUS_APIC_VECTOR,	spurious_interrupt),
	INTG(ERROR_APIC_VECTOR,		error_interrupt),
#endif
};

#ifdef CONFIG_X86_64
/*
 * Early traps running on the DEFAULT_STACK because the other interrupt
 * stacks work only after cpu_init().
 */
static const __initdata struct idt_data early_pf_idts[] = {
	INTG(X86_TRAP_PF,		page_fault),
};

/*
 * Override for the debug_idt. Same as the default, but with interrupt
 * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
 */
static const __initdata struct idt_data dbg_idts[] = {
	INTG(X86_TRAP_DB,	debug),
	INTG(X86_TRAP_BP,	int3),
};
#endif

/* Must be page-aligned because the real IDT is used in a fixmap. */
gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;

struct desc_ptr idt_descr __ro_after_init = {
	.size		= (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1,
	.address	= (unsigned long) idt_table,
};

#ifdef CONFIG_X86_64
/* No need to be aligned, but done to keep all IDTs defined the same way. */
gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;

/*
 * The exceptions which use Interrupt stacks. They are setup after
 * cpu_init() when the TSS has been initialized.
 */
static const __initdata struct idt_data ist_idts[] = {
	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
	SISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
#ifdef CONFIG_X86_MCE
	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),
#endif
};

/*
 * Override for the debug_idt. Same as the default, but with interrupt
 * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
 */
const struct desc_ptr debug_idt_descr = {
	.size		= IDT_ENTRIES * 16 - 1,
	.address	= (unsigned long) debug_idt_table,
};
#endif

static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
{
	unsigned long addr = (unsigned long) d->addr;

	gate->offset_low	= (u16) addr;
	gate->segment		= (u16) d->segment;
	gate->bits		= d->bits;
	gate->offset_middle	= (u16) (addr >> 16);
#ifdef CONFIG_X86_64
	gate->offset_high	= (u32) (addr >> 32);
	gate->reserved		= 0;
#endif
}

static void
idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
{
	gate_desc desc;

	for (; size > 0; t++, size--) {
		idt_init_desc(&desc, t);
		write_idt_entry(idt, t->vector, &desc);
		if (sys)
			set_bit(t->vector, used_vectors);
	}
}

static void set_intr_gate(unsigned int n, const void *addr)
{
	struct idt_data data;

	BUG_ON(n > 0xFF);

	memset(&data, 0, sizeof(data));
	data.vector	= n;
	data.addr	= addr;
	data.segment	= __KERNEL_CS;
	data.bits.type	= GATE_INTERRUPT;
	data.bits.p	= 1;

	idt_setup_from_table(idt_table, &data, 1, false);
}

/**
 * idt_setup_early_traps - Initialize the idt table with early traps
 *
 * On X8664 these traps do not use interrupt stacks as they can't work
 * before cpu_init() is invoked and sets up TSS. The IST variants are
 * installed after that.
 */
void __init idt_setup_early_traps(void)
{
	idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
			     true);
	load_idt(&idt_descr);
}

/**
 * idt_setup_traps - Initialize the idt table with default traps
 */
void __init idt_setup_traps(void)
{
	idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
}

#ifdef CONFIG_X86_64
/**
 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
 *
 * On X8664 this does not use interrupt stacks as they can't work before
 * cpu_init() is invoked and sets up TSS. The IST variant is installed
 * after that.
 *
 * FIXME: Why is 32bit and 64bit installing the PF handler at different
 * places in the early setup code?
 */
void __init idt_setup_early_pf(void)
{
	idt_setup_from_table(idt_table, early_pf_idts,
			     ARRAY_SIZE(early_pf_idts), true);
}

/**
 * idt_setup_ist_traps - Initialize the idt table with traps using IST
 */
void __init idt_setup_ist_traps(void)
{
	idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
}

/**
 * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
 */
void __init idt_setup_debugidt_traps(void)
{
	memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);

	idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts), false);
}
#endif

/**
 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
 */
void __init idt_setup_apic_and_irq_gates(void)
{
	int i = FIRST_EXTERNAL_VECTOR;
	void *entry;

	idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);

	for_each_clear_bit_from(i, used_vectors, FIRST_SYSTEM_VECTOR) {
		entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
		set_intr_gate(i, entry);
	}

	for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
#ifdef CONFIG_X86_LOCAL_APIC
		set_bit(i, used_vectors);
		set_intr_gate(i, spurious_interrupt);
#else
		entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
		set_intr_gate(i, entry);
#endif
	}
}

/**
 * idt_setup_early_handler - Initializes the idt table with early handlers
 */
void __init idt_setup_early_handler(void)
{
	int i;

	for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
		set_intr_gate(i, early_idt_handler_array[i]);
#ifdef CONFIG_X86_32
	for ( ; i < NR_VECTORS; i++)
		set_intr_gate(i, early_ignore_irq);
#endif
	load_idt(&idt_descr);
}

/**
 * idt_invalidate - Invalidate interrupt descriptor table
 * @addr:	The virtual address of the 'invalid' IDT
 */
void idt_invalidate(void *addr)
{
	struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };

	load_idt(&idt);
}

void __init update_intr_gate(unsigned int n, const void *addr)
{
	if (WARN_ON_ONCE(!test_bit(n, used_vectors)))
		return;
	set_intr_gate(n, addr);
}

void alloc_intr_gate(unsigned int n, const void *addr)
{
	BUG_ON(n < FIRST_SYSTEM_VECTOR);
	if (!test_and_set_bit(n, used_vectors))
		set_intr_gate(n, addr);
}
Commit	Line	Data
d8ed9d48 TG	1	/*
	2	* Interrupt descriptor table related code
	3	*
	4	* This file is licensed under the GPL V2
	5	*/
	6	#include <linux/interrupt.h>
	7
3318e974 TG	8	#include <asm/traps.h>
3318e974 TG	9	#include <asm/proto.h>
d8ed9d48 TG	10	#include <asm/desc.h>
d8ed9d48 TG	11
3318e974 TG	12	struct idt_data {
	13	unsigned int vector;
	14	unsigned int segment;
	15	struct idt_bits bits;
	16	const void *addr;
	17	};
	18
	19	#define DPL0 0x0
	20	#define DPL3 0x3
	21
	22	#define DEFAULT_STACK 0
	23
	24	#define G(_vector, _addr, _ist, _type, _dpl, _segment) \
	25	{ \
	26	.vector = _vector, \
	27	.bits.ist = _ist, \
	28	.bits.type = _type, \
	29	.bits.dpl = _dpl, \
	30	.bits.p = 1, \
	31	.addr = _addr, \
	32	.segment = _segment, \
	33	}
	34
	35	/* Interrupt gate */
	36	#define INTG(_vector, _addr) \
	37	G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
	38
	39	/* System interrupt gate */
	40	#define SYSG(_vector, _addr) \
	41	G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
	42
	43	/* Interrupt gate with interrupt stack */
	44	#define ISTG(_vector, _addr, _ist) \
	45	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
	46
c6ef8942 IM	47	/* System interrupt gate with interrupt stack */
	48	#define SISTG(_vector, _addr, _ist) \
	49	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
	50
3318e974 TG	51	/* Task gate */
	52	#define TSKG(_vector, _gdt) \
	53	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
	54
433f8924 TG	55	/*
	56	* Early traps running on the DEFAULT_STACK because the other interrupt
	57	* stacks work only after cpu_init().
	58	*/
	59	static const __initdata struct idt_data early_idts[] = {
	60	INTG(X86_TRAP_DB, debug),
	61	SYSG(X86_TRAP_BP, int3),
	62	#ifdef CONFIG_X86_32
	63	INTG(X86_TRAP_PF, page_fault),
	64	#endif
	65	};
	66
b70543a0 TG	67	/*
	68	* The default IDT entries which are set up in trap_init() before
	69	* cpu_init() is invoked. Interrupt stacks cannot be used at that point and
	70	* the traps which use them are reinitialized with IST after cpu_init() has
	71	* set up TSS.
	72	*/
	73	static const __initdata struct idt_data def_idts[] = {
	74	INTG(X86_TRAP_DE, divide_error),
	75	INTG(X86_TRAP_NMI, nmi),
	76	INTG(X86_TRAP_BR, bounds),
	77	INTG(X86_TRAP_UD, invalid_op),
	78	INTG(X86_TRAP_NM, device_not_available),
	79	INTG(X86_TRAP_OLD_MF, coprocessor_segment_overrun),
	80	INTG(X86_TRAP_TS, invalid_TSS),
	81	INTG(X86_TRAP_NP, segment_not_present),
	82	INTG(X86_TRAP_SS, stack_segment),
	83	INTG(X86_TRAP_GP, general_protection),
	84	INTG(X86_TRAP_SPURIOUS, spurious_interrupt_bug),
	85	INTG(X86_TRAP_MF, coprocessor_error),
	86	INTG(X86_TRAP_AC, alignment_check),
	87	INTG(X86_TRAP_XF, simd_coprocessor_error),
	88
	89	#ifdef CONFIG_X86_32
	90	TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
	91	#else
	92	INTG(X86_TRAP_DF, double_fault),
	93	#endif
	94	INTG(X86_TRAP_DB, debug),
b70543a0 TG	95
	96	#ifdef CONFIG_X86_MCE
	97	INTG(X86_TRAP_MC, &machine_check),
	98	#endif
	99
	100	SYSG(X86_TRAP_OF, overflow),
	101	#if defined(CONFIG_IA32_EMULATION)
	102	SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
	103	#elif defined(CONFIG_X86_32)
	104	SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
	105	#endif
	106	};
	107
636a7598 TG	108	/*
	109	* The APIC and SMP idt entries
	110	*/
	111	static const __initdata struct idt_data apic_idts[] = {
	112	#ifdef CONFIG_SMP
	113	INTG(RESCHEDULE_VECTOR, reschedule_interrupt),
	114	INTG(CALL_FUNCTION_VECTOR, call_function_interrupt),
	115	INTG(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt),
	116	INTG(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt),
	117	INTG(REBOOT_VECTOR, reboot_interrupt),
	118	#endif
	119
	120	#ifdef CONFIG_X86_THERMAL_VECTOR
	121	INTG(THERMAL_APIC_VECTOR, thermal_interrupt),
	122	#endif
	123
	124	#ifdef CONFIG_X86_MCE_THRESHOLD
	125	INTG(THRESHOLD_APIC_VECTOR, threshold_interrupt),
	126	#endif
	127
	128	#ifdef CONFIG_X86_MCE_AMD
	129	INTG(DEFERRED_ERROR_VECTOR, deferred_error_interrupt),
	130	#endif
	131
	132	#ifdef CONFIG_X86_LOCAL_APIC
	133	INTG(LOCAL_TIMER_VECTOR, apic_timer_interrupt),
	134	INTG(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi),
	135	# ifdef CONFIG_HAVE_KVM
	136	INTG(POSTED_INTR_VECTOR, kvm_posted_intr_ipi),
	137	INTG(POSTED_INTR_WAKEUP_VECTOR, kvm_posted_intr_wakeup_ipi),
	138	INTG(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi),
	139	# endif
	140	# ifdef CONFIG_IRQ_WORK
	141	INTG(IRQ_WORK_VECTOR, irq_work_interrupt),
	142	# endif
	143	INTG(SPURIOUS_APIC_VECTOR, spurious_interrupt),
	144	INTG(ERROR_APIC_VECTOR, error_interrupt),
	145	#endif
	146	};
	147
433f8924 TG	148	#ifdef CONFIG_X86_64
	149	/*
	150	* Early traps running on the DEFAULT_STACK because the other interrupt
	151	* stacks work only after cpu_init().
	152	*/
	153	static const __initdata struct idt_data early_pf_idts[] = {
	154	INTG(X86_TRAP_PF, page_fault),
	155	};
0a30908b TG	156
	157	/*
	158	* Override for the debug_idt. Same as the default, but with interrupt
	159	* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
	160	*/
	161	static const __initdata struct idt_data dbg_idts[] = {
	162	INTG(X86_TRAP_DB, debug),
	163	INTG(X86_TRAP_BP, int3),
	164	};
433f8924 TG	165	#endif
433f8924 TG	166
d8ed9d48 TG	167	/* Must be page-aligned because the real IDT is used in a fixmap. */
	168	gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
	169
d8ed9d48	170	struct desc_ptr idt_descr __ro_after_init = {
16bc18d8	171	.size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1,
d8ed9d48 TG	172	.address = (unsigned long) idt_table,
	173	};
	174
16bc18d8 TG	175	#ifdef CONFIG_X86_64
	176	/* No need to be aligned, but done to keep all IDTs defined the same way. */
	177	gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
	178
90f6225f TG	179	/*
	180	* The exceptions which use Interrupt stacks. They are setup after
	181	* cpu_init() when the TSS has been initialized.
	182	*/
	183	static const __initdata struct idt_data ist_idts[] = {
	184	ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
	185	ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
c6ef8942	186	SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
90f6225f TG	187	ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
	188	#ifdef CONFIG_X86_MCE
	189	ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
	190	#endif
	191	};
	192
0a30908b TG	193	/*
	194	* Override for the debug_idt. Same as the default, but with interrupt
	195	* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
	196	*/
d8ed9d48 TG	197	const struct desc_ptr debug_idt_descr = {
	198	.size = IDT_ENTRIES * 16 - 1,
	199	.address = (unsigned long) debug_idt_table,
	200	};
	201	#endif
e802a51e	202
3318e974 TG	203	static inline void idt_init_desc(gate_desc gate, const struct idt_data d)
	204	{
	205	unsigned long addr = (unsigned long) d->addr;
	206
	207	gate->offset_low = (u16) addr;
	208	gate->segment = (u16) d->segment;
	209	gate->bits = d->bits;
	210	gate->offset_middle = (u16) (addr >> 16);
	211	#ifdef CONFIG_X86_64
	212	gate->offset_high = (u32) (addr >> 32);
	213	gate->reserved = 0;
	214	#endif
	215	}
	216
db18da78 TG	217	static void
db18da78 TG	218	idt_setup_from_table(gate_desc idt, const struct idt_data t, int size, bool sys)
3318e974 TG	219	{
	220	gate_desc desc;
	221
	222	for (; size > 0; t++, size--) {
	223	idt_init_desc(&desc, t);
3318e974	224	write_idt_entry(idt, t->vector, &desc);
db18da78 TG	225	if (sys)
db18da78 TG	226	set_bit(t->vector, used_vectors);
3318e974 TG	227	}
	228	}
	229
facaa3e3 TG	230	static void set_intr_gate(unsigned int n, const void *addr)
	231	{
	232	struct idt_data data;
	233
	234	BUG_ON(n > 0xFF);
	235
	236	memset(&data, 0, sizeof(data));
	237	data.vector = n;
	238	data.addr = addr;
	239	data.segment = __KERNEL_CS;
	240	data.bits.type = GATE_INTERRUPT;
	241	data.bits.p = 1;
	242
	243	idt_setup_from_table(idt_table, &data, 1, false);
	244	}
	245
433f8924 TG	246	/**
	247	* idt_setup_early_traps - Initialize the idt table with early traps
	248	*
	249	* On X8664 these traps do not use interrupt stacks as they can't work
	250	* before cpu_init() is invoked and sets up TSS. The IST variants are
	251	* installed after that.
	252	*/
	253	void __init idt_setup_early_traps(void)
	254	{
db18da78 TG	255	idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
db18da78 TG	256	true);
433f8924 TG	257	load_idt(&idt_descr);
	258	}
	259
b70543a0 TG	260	/**
	261	* idt_setup_traps - Initialize the idt table with default traps
	262	*/
	263	void __init idt_setup_traps(void)
	264	{
db18da78	265	idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
b70543a0 TG	266	}
b70543a0 TG	267
433f8924 TG	268	#ifdef CONFIG_X86_64
	269	/**
	270	* idt_setup_early_pf - Initialize the idt table with early pagefault handler
	271	*
	272	* On X8664 this does not use interrupt stacks as they can't work before
	273	* cpu_init() is invoked and sets up TSS. The IST variant is installed
	274	* after that.
	275	*
	276	* FIXME: Why is 32bit and 64bit installing the PF handler at different
	277	* places in the early setup code?
	278	*/
	279	void __init idt_setup_early_pf(void)
	280	{
	281	idt_setup_from_table(idt_table, early_pf_idts,
db18da78	282	ARRAY_SIZE(early_pf_idts), true);
433f8924	283	}
0a30908b	284
90f6225f TG	285	/**
	286	* idt_setup_ist_traps - Initialize the idt table with traps using IST
	287	*/
	288	void __init idt_setup_ist_traps(void)
	289	{
db18da78	290	idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
90f6225f TG	291	}
90f6225f TG	292
0a30908b TG	293	/**
	294	* idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
	295	*/
	296	void __init idt_setup_debugidt_traps(void)
	297	{
	298	memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
	299
db18da78	300	idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts), false);
0a30908b	301	}
433f8924 TG	302	#endif
433f8924 TG	303
636a7598 TG	304	/**
	305	* idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
	306	*/
	307	void __init idt_setup_apic_and_irq_gates(void)
	308	{
dc20b2d5 TG	309	int i = FIRST_EXTERNAL_VECTOR;
	310	void *entry;
	311
db18da78	312	idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
dc20b2d5 TG	313
	314	for_each_clear_bit_from(i, used_vectors, FIRST_SYSTEM_VECTOR) {
	315	entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
	316	set_intr_gate(i, entry);
	317	}
	318
	319	for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
	320	#ifdef CONFIG_X86_LOCAL_APIC
	321	set_bit(i, used_vectors);
	322	set_intr_gate(i, spurious_interrupt);
	323	#else
	324	entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
	325	set_intr_gate(i, entry);
	326	#endif
	327	}
636a7598 TG	328	}
636a7598 TG	329
588787fd TG	330	/**
	331	* idt_setup_early_handler - Initializes the idt table with early handlers
	332	*/
	333	void __init idt_setup_early_handler(void)
	334	{
	335	int i;
	336
	337	for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
	338	set_intr_gate(i, early_idt_handler_array[i]);
87e81786 TG	339	#ifdef CONFIG_X86_32
	340	for ( ; i < NR_VECTORS; i++)
	341	set_intr_gate(i, early_ignore_irq);
	342	#endif
588787fd TG	343	load_idt(&idt_descr);
	344	}
	345
e802a51e TG	346	/**
	347	* idt_invalidate - Invalidate interrupt descriptor table
	348	* @addr: The virtual address of the 'invalid' IDT
	349	*/
	350	void idt_invalidate(void *addr)
	351	{
	352	struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
	353
	354	load_idt(&idt);
	355	}
db18da78	356
facaa3e3	357	void __init update_intr_gate(unsigned int n, const void *addr)
db18da78	358	{
facaa3e3 TG	359	if (WARN_ON_ONCE(!test_bit(n, used_vectors)))
	360	return;
	361	set_intr_gate(n, addr);
db18da78 TG	362	}
	363
	364	void alloc_intr_gate(unsigned int n, const void *addr)
	365	{
4447ac11 TG	366	BUG_ON(n < FIRST_SYSTEM_VECTOR);
	367	if (!test_and_set_bit(n, used_vectors))
	368	set_intr_gate(n, addr);
db18da78	369	}