[thirdparty/u-boot.git] / arch / x86 / lib / i8259.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Graeme Russ, <graeme.russ@gmail.com>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
 */

/*
 * This file provides the interrupt handling functionality for systems
 * based on the standard PC/AT architecture using two cascaded i8259
 * Programmable Interrupt Controllers.
 */

#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/ibmpc.h>
#include <asm/interrupt.h>

int i8259_init(void)
{
	u8 i;

	/* Mask all interrupts */
	outb(0xff, MASTER_PIC + IMR);
	outb(0xff, SLAVE_PIC + IMR);

	/*
	 * Master PIC
	 * Place master PIC interrupts at INT20
	 */
	outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
	outb(0x20, MASTER_PIC + ICW2);
	outb(IR2, MASTER_PIC + ICW3);
	outb(ICW4_PM, MASTER_PIC + ICW4);

	for (i = 0; i < 8; i++)
		outb(OCW2_SEOI | i, MASTER_PIC + OCW2);

	/*
	 * Slave PIC
	 * Place slave PIC interrupts at INT28
	 */
	outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
	outb(0x28, SLAVE_PIC + ICW2);
	outb(0x02, SLAVE_PIC + ICW3);
	outb(ICW4_PM, SLAVE_PIC + ICW4);

	for (i = 0; i < 8; i++)
		outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);

	/*
	 * Enable cascaded interrupts by unmasking the cascade IRQ pin of
	 * the master PIC
	 */
	unmask_irq(2);

	/* Interrupt 9 should be level triggered (SCI). The OS might do this */
	configure_irq_trigger(9, true);

	return 0;
}

void mask_irq(int irq)
{
	int imr_port;

	if (irq >= SYS_NUM_IRQS)
		return;

	if (irq > 7)
		imr_port = SLAVE_PIC + IMR;
	else
		imr_port = MASTER_PIC + IMR;

	outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
}

void unmask_irq(int irq)
{
	int imr_port;

	if (irq >= SYS_NUM_IRQS)
		return;

	if (irq > 7)
		imr_port = SLAVE_PIC + IMR;
	else
		imr_port = MASTER_PIC + IMR;

	outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
}

void specific_eoi(int irq)
{
	if (irq >= SYS_NUM_IRQS)
		return;

	if (irq > 7) {
		/*
		 *  IRQ is on the slave - Issue a corresponding EOI to the
		 *  slave PIC and an EOI for IRQ2 (the cascade interrupt)
		 *  on the master PIC
		 */
		outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
		irq = SEOI_IR2;
	}

	outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
}

void configure_irq_trigger(int int_num, bool is_level_triggered)
{
	u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);

	debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
	if (is_level_triggered)
		int_bits |= (1 << int_num);
	else
		int_bits &= ~(1 << int_num);

	/* Write new values */
	debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
	outb((u8)(int_bits & 0xff), ELCR1);
	outb((u8)(int_bits >> 8), ELCR2);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
abf0cd3d GR	2	/*
abf0cd3d GR	3	* (C) Copyright 2009
dbf7115a	4	* Graeme Russ, <graeme.russ@gmail.com>
abf0cd3d GR	5	*
abf0cd3d GR	6	* (C) Copyright 2002
fa82f871	7	* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
abf0cd3d GR	8	*/
	9
	10	/*
	11	* This file provides the interrupt handling functionality for systems
	12	* based on the standard PC/AT architecture using two cascaded i8259
	13	* Programmable Interrupt Controllers.
	14	*/
	15
d678a59d	16	#include <common.h>
f7ae49fc	17	#include <log.h>
abf0cd3d GR	18	#include <asm/io.h>
	19	#include <asm/i8259.h>
	20	#include <asm/ibmpc.h>
	21	#include <asm/interrupt.h>
	22
1dae2e0e	23	int i8259_init(void)
abf0cd3d GR	24	{
	25	u8 i;
	26
abf0cd3d GR	27	/* Mask all interrupts */
	28	outb(0xff, MASTER_PIC + IMR);
	29	outb(0xff, SLAVE_PIC + IMR);
	30
0a2ea020 BM	31	/*
	32	* Master PIC
	33	* Place master PIC interrupts at INT20
	34	*/
	35	outb(ICW1_SEL \| ICW1_EICW4, MASTER_PIC + ICW1);
abf0cd3d GR	36	outb(0x20, MASTER_PIC + ICW2);
	37	outb(IR2, MASTER_PIC + ICW3);
	38	outb(ICW4_PM, MASTER_PIC + ICW4);
	39
	40	for (i = 0; i < 8; i++)
	41	outb(OCW2_SEOI \| i, MASTER_PIC + OCW2);
	42
0a2ea020 BM	43	/*
	44	* Slave PIC
	45	* Place slave PIC interrupts at INT28
	46	*/
	47	outb(ICW1_SEL \| ICW1_EICW4, SLAVE_PIC + ICW1);
abf0cd3d GR	48	outb(0x28, SLAVE_PIC + ICW2);
	49	outb(0x02, SLAVE_PIC + ICW3);
	50	outb(ICW4_PM, SLAVE_PIC + ICW4);
	51
	52	for (i = 0; i < 8; i++)
	53	outb(OCW2_SEOI \| i, SLAVE_PIC + OCW2);
	54
	55	/*
	56	* Enable cascaded interrupts by unmasking the cascade IRQ pin of
	57	* the master PIC
	58	*/
83088afb	59	unmask_irq(2);
abf0cd3d	60
a0bd851e SG	61	/* Interrupt 9 should be level triggered (SCI). The OS might do this */
	62	configure_irq_trigger(9, true);
	63
abf0cd3d GR	64	return 0;
	65	}
	66
	67	void mask_irq(int irq)
	68	{
	69	int imr_port;
	70
6c505271	71	if (irq >= SYS_NUM_IRQS)
abf0cd3d GR	72	return;
	73
	74	if (irq > 7)
	75	imr_port = SLAVE_PIC + IMR;
	76	else
	77	imr_port = MASTER_PIC + IMR;
	78
	79	outb(inb(imr_port) \| (1 << (irq & 7)), imr_port);
	80	}
	81
	82	void unmask_irq(int irq)
	83	{
	84	int imr_port;
	85
6c505271	86	if (irq >= SYS_NUM_IRQS)
abf0cd3d GR	87	return;
	88
	89	if (irq > 7)
	90	imr_port = SLAVE_PIC + IMR;
	91	else
	92	imr_port = MASTER_PIC + IMR;
	93
	94	outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
	95	}
	96
	97	void specific_eoi(int irq)
	98	{
6c505271	99	if (irq >= SYS_NUM_IRQS)
abf0cd3d GR	100	return;
	101
	102	if (irq > 7) {
	103	/*
	104	* IRQ is on the slave - Issue a corresponding EOI to the
	105	* slave PIC and an EOI for IRQ2 (the cascade interrupt)
	106	* on the master PIC
	107	*/
	108	outb(OCW2_SEOI \| (irq & 7), SLAVE_PIC + OCW2);
	109	irq = SEOI_IR2;
	110	}
	111
	112	outb(OCW2_SEOI \| irq, MASTER_PIC + OCW2);
	113	}
a0bd851e	114
a0bd851e SG	115	void configure_irq_trigger(int int_num, bool is_level_triggered)
	116	{
	117	u16 int_bits = inb(ELCR1) \| (((u16)inb(ELCR2)) << 8);
	118
	119	debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
	120	if (is_level_triggered)
	121	int_bits \|= (1 << int_num);
	122	else
	123	int_bits &= ~(1 << int_num);
	124
	125	/* Write new values */
	126	debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
	127	outb((u8)(int_bits & 0xff), ELCR1);
	128	outb((u8)(int_bits >> 8), ELCR2);
a0bd851e	129	}