[thirdparty/u-boot.git] / arch / x86 / lib / init_helpers.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2011
 * Graeme Russ, <graeme.russ@gmail.com>
 */

#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/mtrr.h>

DECLARE_GLOBAL_DATA_PTR;

int init_cache_f_r(void)
{
	bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
		 IS_ENABLED(CONFIG_FSP_VERSION2) ||
		 (IS_ENABLED(CONFIG_TPL) && IS_ENABLED(CONFIG_HAVE_MRC));
	int ret;

	/*
	 * Supported configurations:
	 *
	 * booting from slimbootloader - MTRRs are already set up
	 * booting with FSPv1 - MTRRs are already set up
	 * booting with FSPv2 or MRC - MTRRs must be set here
	 * booting from coreboot - in this case there is no SPL, so we set up
	 *	the MTRRs here
	 */
	do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
		!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);

	if (do_mtrr) {
		ret = mtrr_commit(false);
		/*
		 * If MTRR MSR is not implemented by the processor, just ignore
		 * it
		 */
		if (ret && ret != -ENOSYS)
			return ret;
	}

	/* Initialise the CPU cache(s) */
	return init_cache();
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d47ab0ec GR	2	/*
	3	* (C) Copyright 2011
	4	* Graeme Russ, <graeme.russ@gmail.com>
d47ab0ec	5	*/
c17ca6b5	6
d678a59d	7	#include <common.h>
67c4e9f8	8	#include <init.h>
401d1c4f	9	#include <asm/global_data.h>
1221ce45	10	#include <linux/errno.h>
db55bd7d	11	#include <asm/mtrr.h>
d47ab0ec GR	12
	13	DECLARE_GLOBAL_DATA_PTR;
	14
a1d57b7a GR	15	int init_cache_f_r(void)
a1d57b7a GR	16	{
cc2d27dc	17	bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) \|\|
cd1ee5d9 SG	18	IS_ENABLED(CONFIG_FSP_VERSION2) \|\|
cd1ee5d9 SG	19	(IS_ENABLED(CONFIG_TPL) && IS_ENABLED(CONFIG_HAVE_MRC));
db55bd7d SG	20	int ret;
db55bd7d SG	21
70529687 SG	22	/*
	23	* Supported configurations:
	24	*
41fbb344	25	* booting from slimbootloader - MTRRs are already set up
70529687	26	* booting with FSPv1 - MTRRs are already set up
cd1ee5d9	27	* booting with FSPv2 or MRC - MTRRs must be set here
70529687 SG	28	* booting from coreboot - in this case there is no SPL, so we set up
70529687 SG	29	* the MTRRs here
70529687	30	*/
41fbb344	31	do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
cc2d27dc SG	32	!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
	33
	34	if (do_mtrr) {
	35	ret = mtrr_commit(false);
	36	/*
	37	* If MTRR MSR is not implemented by the processor, just ignore
	38	* it
	39	*/
	40	if (ret && ret != -ENOSYS)
	41	return ret;
	42	}
	43
a1d57b7a GR	44	/* Initialise the CPU cache(s) */
	45	return init_cache();
	46	}