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7c03caf6 SG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (c) 2018 Google, Inc | |
4 | */ | |
5 | ||
02de9199 SG |
6 | #define LOG_CATEGORY LOGC_BOOT |
7 | ||
d678a59d | 8 | #include <common.h> |
7c03caf6 | 9 | #include <debug_uart.h> |
0ced70a0 | 10 | #include <dm.h> |
db41d65a | 11 | #include <hang.h> |
4d72caa5 | 12 | #include <image.h> |
691d719d | 13 | #include <init.h> |
f7ae49fc | 14 | #include <log.h> |
7c03caf6 SG |
15 | #include <spl.h> |
16 | #include <asm/cpu.h> | |
401d1c4f | 17 | #include <asm/global_data.h> |
7c03caf6 SG |
18 | #include <asm/mtrr.h> |
19 | #include <asm/processor.h> | |
20 | #include <asm-generic/sections.h> | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
7c03caf6 SG |
24 | static int x86_tpl_init(void) |
25 | { | |
26 | int ret; | |
27 | ||
28 | debug("%s starting\n", __func__); | |
0e72ac71 SG |
29 | ret = x86_cpu_init_tpl(); |
30 | if (ret) { | |
31 | debug("%s: x86_cpu_init_tpl() failed\n", __func__); | |
32 | return ret; | |
33 | } | |
7c03caf6 SG |
34 | ret = spl_init(); |
35 | if (ret) { | |
36 | debug("%s: spl_init() failed\n", __func__); | |
37 | return ret; | |
38 | } | |
39 | ret = arch_cpu_init(); | |
40 | if (ret) { | |
41 | debug("%s: arch_cpu_init() failed\n", __func__); | |
42 | return ret; | |
43 | } | |
7c03caf6 | 44 | preloader_console_init(); |
7c03caf6 SG |
45 | |
46 | return 0; | |
47 | } | |
48 | ||
49 | void board_init_f(ulong flags) | |
50 | { | |
51 | int ret; | |
52 | ||
53 | ret = x86_tpl_init(); | |
54 | if (ret) { | |
55 | debug("Error %d\n", ret); | |
3d95688c | 56 | panic("x86_tpl_init fail"); |
7c03caf6 SG |
57 | } |
58 | ||
59 | /* Uninit CAR and jump to board_init_f_r() */ | |
60 | board_init_r(gd, 0); | |
61 | } | |
62 | ||
63 | void board_init_f_r(void) | |
64 | { | |
65 | /* Not used since we never call board_init_f_r_trampoline() */ | |
66 | while (1); | |
67 | } | |
68 | ||
69 | u32 spl_boot_device(void) | |
70 | { | |
96d0aa91 | 71 | return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT : |
daade119 | 72 | BOOT_DEVICE_SPI_MMAP; |
7c03caf6 SG |
73 | } |
74 | ||
75 | int spl_start_uboot(void) | |
76 | { | |
77 | return 0; | |
78 | } | |
79 | ||
80 | void spl_board_announce_boot_device(void) | |
81 | { | |
82 | printf("SPI flash"); | |
83 | } | |
84 | ||
85 | static int spl_board_load_image(struct spl_image_info *spl_image, | |
86 | struct spl_boot_device *bootdev) | |
87 | { | |
88 | spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ | |
89 | spl_image->entry_point = CONFIG_SPL_TEXT_BASE; | |
90 | spl_image->load_addr = CONFIG_SPL_TEXT_BASE; | |
91 | spl_image->os = IH_OS_U_BOOT; | |
92 | spl_image->name = "U-Boot"; | |
93 | ||
94 | debug("Loading to %lx\n", spl_image->load_addr); | |
95 | ||
96 | return 0; | |
97 | } | |
daade119 | 98 | SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image); |
7c03caf6 SG |
99 | |
100 | int spl_spi_load_image(void) | |
101 | { | |
102 | return -EPERM; | |
103 | } | |
104 | ||
105 | void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) | |
106 | { | |
3138e460 SG |
107 | debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()), |
108 | (ulong)spl_image->entry_point); | |
109 | #ifdef DEBUG | |
110 | print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1, | |
111 | 0x20, 0); | |
112 | #endif | |
7c03caf6 | 113 | jump_to_spl(spl_image->entry_point); |
14dd93be | 114 | hang(); |
7c03caf6 SG |
115 | } |
116 | ||
117 | void spl_board_init(void) | |
118 | { | |
119 | preloader_console_init(); | |
120 | } | |
0ced70a0 SG |
121 | |
122 | #if !CONFIG_IS_ENABLED(PCI) | |
123 | /* | |
124 | * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough | |
125 | * to bind the devices on the PCI bus, some of which have early-regs properties | |
126 | * providing fixed BARs. Individual drivers program these BARs themselves so | |
127 | * that they can access the devices. The BARs are allocated statically in the | |
128 | * device tree. | |
129 | * | |
130 | * Once SPL is running it enables PCI properly, but does not auto-assign BARs | |
131 | * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does | |
132 | * the auto allocation (after relocation). | |
133 | */ | |
95397385 | 134 | #if CONFIG_IS_ENABLED(OF_REAL) |
0ced70a0 SG |
135 | static const struct udevice_id tpl_fake_pci_ids[] = { |
136 | { .compatible = "pci-x86" }, | |
137 | { } | |
138 | }; | |
cee58bd2 | 139 | #endif |
0ced70a0 SG |
140 | |
141 | U_BOOT_DRIVER(pci_x86) = { | |
142 | .name = "pci_x86", | |
143 | .id = UCLASS_SIMPLE_BUS, | |
cee58bd2 | 144 | .of_match = of_match_ptr(tpl_fake_pci_ids), |
1d3daaa6 | 145 | DM_PHASE(tpl) |
0ced70a0 SG |
146 | }; |
147 | #endif |