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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c978b524 CZ |
2 | /* |
3 | * (C) Copyright 2008 - 2013 Tensilica Inc. | |
4 | * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. | |
c978b524 CZ |
5 | */ |
6 | ||
7 | /* | |
8 | * CPU specific code | |
9 | */ | |
10 | ||
d678a59d | 11 | #include <common.h> |
c978b524 | 12 | #include <command.h> |
691d719d | 13 | #include <init.h> |
2189d5f1 | 14 | #include <vsprintf.h> |
c978b524 CZ |
15 | #include <linux/stringify.h> |
16 | #include <asm/global_data.h> | |
17 | #include <asm/cache.h> | |
18 | #include <asm/string.h> | |
19 | #include <asm/misc.h> | |
20 | ||
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
236f2ec4 | 23 | gd_t *gd __section(".data"); |
c978b524 CZ |
24 | |
25 | #if defined(CONFIG_DISPLAY_CPUINFO) | |
26 | /* | |
27 | * Print information about the CPU. | |
28 | */ | |
29 | ||
30 | int print_cpuinfo(void) | |
31 | { | |
32 | char buf[120], mhz[8]; | |
33 | uint32_t id0, id1; | |
34 | ||
35 | asm volatile ("rsr %0, 176\n" | |
36 | "rsr %1, 208\n" | |
37 | : "=r"(id0), "=r"(id1)); | |
38 | ||
39 | sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n", | |
40 | XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); | |
41 | puts(buf); | |
42 | return 0; | |
43 | } | |
44 | #endif | |
45 | ||
46 | int arch_cpu_init(void) | |
47 | { | |
aa6e94de | 48 | gd->ram_size = CFG_SYS_SDRAM_SIZE; |
c978b524 CZ |
49 | return 0; |
50 | } | |
f1683aa7 SG |
51 | |
52 | int dram_init(void) | |
53 | { | |
54 | return 0; | |
55 | } |