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2002-03-07 H.J. Lu (hjl@gnu.org)
[thirdparty/binutils-gdb.git] / bfd / coff-sh.c
CommitLineData
252b5132 1/* BFD back-end for Hitachi Super-H COFF binaries.
f4ffd778 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
7898deda 3 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
8This file is part of BFD, the Binary File Descriptor library.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2 of the License, or
13(at your option) any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software
22Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "bfd.h"
25#include "sysdep.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c
NC		 31
32#ifdef COFF_WITH_PE
33#include "coff/pe.h"
86033394
NC		 34
35#ifndef COFF_IMAGE_WITH_PE
cbfe05c4 36static boolean sh_align_load_span
86033394
NC		 37 PARAMS ((bfd *, asection *, bfd_byte *,
38 boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, boolean *));
40
41#define _bfd_sh_align_load_span sh_align_load_span
42#endif
17505c5c
NC		 43#endif
44
252b5132
RH		 45#include "libcoff.h"
46
47/* Internal functions. */
48static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50static long get_symbol_value PARAMS ((asymbol *));
252b5132
RH		 51static boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
53static boolean sh_relax_delete_bytes
54 PARAMS ((bfd *, asection *, bfd_vma, int));
86033394 55#ifndef COFF_IMAGE_WITH_PE
252b5132 56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
86033394 57#endif
252b5132
RH		 58static boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
60static boolean sh_swap_insns
61 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
62static boolean sh_relocate_section
63 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
64 struct internal_reloc *, struct internal_syment *, asection **));
65static bfd_byte *sh_coff_get_relocated_section_contents
66 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
67 bfd_byte *, boolean, asymbol **));
f4ffd778 68static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
252b5132 69
17505c5c
NC		 70#ifdef COFF_WITH_PE
71/* Can't build import tables with 2**4 alignment. */
72#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
73#else
252b5132 74/* Default section alignment to 2**4. */
17505c5c
NC		 75#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
76#endif
77
78#ifdef COFF_IMAGE_WITH_PE
79/* Align PE executables. */
80#define COFF_PAGE_SIZE 0x1000
81#endif
252b5132
RH		 82
83/* Generate long file names. */
84#define COFF_LONG_FILENAMES
85
17505c5c 86#ifdef COFF_WITH_PE
f4ffd778 87static boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
17505c5c
NC		 88/* Return true if this relocation should
89 appear in the output .reloc section. */
90static boolean in_reloc_p (abfd, howto)
91 bfd * abfd ATTRIBUTE_UNUSED;
92 reloc_howto_type * howto;
93{
94 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 95}
17505c5c
NC		 96#endif
97
252b5132
RH		 98/* The supported relocations. There are a lot of relocations defined
99 in coff/internal.h which we do not expect to ever see. */
100static reloc_howto_type sh_coff_howtos[] =
101{
5f771d47
ILT		 102 EMPTY_HOWTO (0),
103 EMPTY_HOWTO (1),
17505c5c
NC		 104#ifdef COFF_WITH_PE
105 /* Windows CE */
106 HOWTO (R_SH_IMM32CE, /* type */
107 0, /* rightshift */
108 2, /* size (0 = byte, 1 = short, 2 = long) */
109 32, /* bitsize */
110 false, /* pc_relative */
111 0, /* bitpos */
112 complain_overflow_bitfield, /* complain_on_overflow */
113 sh_reloc, /* special_function */
114 "r_imm32ce", /* name */
115 true, /* partial_inplace */
116 0xffffffff, /* src_mask */
117 0xffffffff, /* dst_mask */
118 false), /* pcrel_offset */
119#else
5f771d47 120 EMPTY_HOWTO (2),
17505c5c 121#endif
5f771d47
ILT		 122 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
123 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
124 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
125 EMPTY_HOWTO (6), /* R_SH_IMM24 */
126 EMPTY_HOWTO (7), /* R_SH_LOW16 */
127 EMPTY_HOWTO (8),
128 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 129
130 HOWTO (R_SH_PCDISP8BY2, /* type */
131 1, /* rightshift */
132 1, /* size (0 = byte, 1 = short, 2 = long) */
133 8, /* bitsize */
134 true, /* pc_relative */
135 0, /* bitpos */
136 complain_overflow_signed, /* complain_on_overflow */
137 sh_reloc, /* special_function */
138 "r_pcdisp8by2", /* name */
139 true, /* partial_inplace */
140 0xff, /* src_mask */
141 0xff, /* dst_mask */
142 true), /* pcrel_offset */
143
5f771d47 144 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 145
146 HOWTO (R_SH_PCDISP, /* type */
147 1, /* rightshift */
148 1, /* size (0 = byte, 1 = short, 2 = long) */
149 12, /* bitsize */
150 true, /* pc_relative */
151 0, /* bitpos */
152 complain_overflow_signed, /* complain_on_overflow */
153 sh_reloc, /* special_function */
154 "r_pcdisp12by2", /* name */
155 true, /* partial_inplace */
156 0xfff, /* src_mask */
157 0xfff, /* dst_mask */
158 true), /* pcrel_offset */
159
5f771d47 160 EMPTY_HOWTO (13),
252b5132
RH		 161
162 HOWTO (R_SH_IMM32, /* type */
163 0, /* rightshift */
164 2, /* size (0 = byte, 1 = short, 2 = long) */
165 32, /* bitsize */
166 false, /* pc_relative */
167 0, /* bitpos */
168 complain_overflow_bitfield, /* complain_on_overflow */
169 sh_reloc, /* special_function */
170 "r_imm32", /* name */
171 true, /* partial_inplace */
172 0xffffffff, /* src_mask */
173 0xffffffff, /* dst_mask */
174 false), /* pcrel_offset */
175
5f771d47 176 EMPTY_HOWTO (15),
17505c5c 177#ifdef COFF_WITH_PE
cbfe05c4
KH		 178 HOWTO (R_SH_IMAGEBASE, /* type */
179 0, /* rightshift */
180 2, /* size (0 = byte, 1 = short, 2 = long) */
181 32, /* bitsize */
182 false, /* pc_relative */
183 0, /* bitpos */
17505c5c 184 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 185 sh_reloc, /* special_function */
186 "rva32", /* name */
187 true, /* partial_inplace */
188 0xffffffff, /* src_mask */
189 0xffffffff, /* dst_mask */
17505c5c
NC		 190 false), /* pcrel_offset */
191#else
5f771d47 192 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 193#endif
5f771d47
ILT		 194 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
195 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
196 EMPTY_HOWTO (19), /* R_SH_IMM4 */
197 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
198 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 199
200 HOWTO (R_SH_PCRELIMM8BY2, /* type */
201 1, /* rightshift */
202 1, /* size (0 = byte, 1 = short, 2 = long) */
203 8, /* bitsize */
204 true, /* pc_relative */
205 0, /* bitpos */
206 complain_overflow_unsigned, /* complain_on_overflow */
207 sh_reloc, /* special_function */
208 "r_pcrelimm8by2", /* name */
209 true, /* partial_inplace */
210 0xff, /* src_mask */
211 0xff, /* dst_mask */
212 true), /* pcrel_offset */
213
214 HOWTO (R_SH_PCRELIMM8BY4, /* type */
215 2, /* rightshift */
216 1, /* size (0 = byte, 1 = short, 2 = long) */
217 8, /* bitsize */
218 true, /* pc_relative */
219 0, /* bitpos */
220 complain_overflow_unsigned, /* complain_on_overflow */
221 sh_reloc, /* special_function */
222 "r_pcrelimm8by4", /* name */
223 true, /* partial_inplace */
224 0xff, /* src_mask */
225 0xff, /* dst_mask */
226 true), /* pcrel_offset */
227
228 HOWTO (R_SH_IMM16, /* type */
229 0, /* rightshift */
230 1, /* size (0 = byte, 1 = short, 2 = long) */
231 16, /* bitsize */
232 false, /* pc_relative */
233 0, /* bitpos */
234 complain_overflow_bitfield, /* complain_on_overflow */
235 sh_reloc, /* special_function */
236 "r_imm16", /* name */
237 true, /* partial_inplace */
238 0xffff, /* src_mask */
239 0xffff, /* dst_mask */
240 false), /* pcrel_offset */
241
242 HOWTO (R_SH_SWITCH16, /* type */
243 0, /* rightshift */
244 1, /* size (0 = byte, 1 = short, 2 = long) */
245 16, /* bitsize */
246 false, /* pc_relative */
247 0, /* bitpos */
248 complain_overflow_bitfield, /* complain_on_overflow */
249 sh_reloc, /* special_function */
250 "r_switch16", /* name */
251 true, /* partial_inplace */
252 0xffff, /* src_mask */
253 0xffff, /* dst_mask */
254 false), /* pcrel_offset */
255
256 HOWTO (R_SH_SWITCH32, /* type */
257 0, /* rightshift */
258 2, /* size (0 = byte, 1 = short, 2 = long) */
259 32, /* bitsize */
260 false, /* pc_relative */
261 0, /* bitpos */
262 complain_overflow_bitfield, /* complain_on_overflow */
263 sh_reloc, /* special_function */
264 "r_switch32", /* name */
265 true, /* partial_inplace */
266 0xffffffff, /* src_mask */
267 0xffffffff, /* dst_mask */
268 false), /* pcrel_offset */
269
270 HOWTO (R_SH_USES, /* type */
271 0, /* rightshift */
272 1, /* size (0 = byte, 1 = short, 2 = long) */
273 16, /* bitsize */
274 false, /* pc_relative */
275 0, /* bitpos */
276 complain_overflow_bitfield, /* complain_on_overflow */
277 sh_reloc, /* special_function */
278 "r_uses", /* name */
279 true, /* partial_inplace */
280 0xffff, /* src_mask */
281 0xffff, /* dst_mask */
282 false), /* pcrel_offset */
283
284 HOWTO (R_SH_COUNT, /* type */
285 0, /* rightshift */
286 2, /* size (0 = byte, 1 = short, 2 = long) */
287 32, /* bitsize */
288 false, /* pc_relative */
289 0, /* bitpos */
290 complain_overflow_bitfield, /* complain_on_overflow */
291 sh_reloc, /* special_function */
292 "r_count", /* name */
293 true, /* partial_inplace */
294 0xffffffff, /* src_mask */
295 0xffffffff, /* dst_mask */
296 false), /* pcrel_offset */
297
298 HOWTO (R_SH_ALIGN, /* type */
299 0, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
301 32, /* bitsize */
302 false, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_bitfield, /* complain_on_overflow */
305 sh_reloc, /* special_function */
306 "r_align", /* name */
307 true, /* partial_inplace */
308 0xffffffff, /* src_mask */
309 0xffffffff, /* dst_mask */
310 false), /* pcrel_offset */
311
312 HOWTO (R_SH_CODE, /* type */
313 0, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
315 32, /* bitsize */
316 false, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_bitfield, /* complain_on_overflow */
319 sh_reloc, /* special_function */
320 "r_code", /* name */
321 true, /* partial_inplace */
322 0xffffffff, /* src_mask */
323 0xffffffff, /* dst_mask */
324 false), /* pcrel_offset */
325
326 HOWTO (R_SH_DATA, /* type */
327 0, /* rightshift */
328 2, /* size (0 = byte, 1 = short, 2 = long) */
329 32, /* bitsize */
330 false, /* pc_relative */
331 0, /* bitpos */
332 complain_overflow_bitfield, /* complain_on_overflow */
333 sh_reloc, /* special_function */
334 "r_data", /* name */
335 true, /* partial_inplace */
336 0xffffffff, /* src_mask */
337 0xffffffff, /* dst_mask */
338 false), /* pcrel_offset */
339
340 HOWTO (R_SH_LABEL, /* type */
341 0, /* rightshift */
342 2, /* size (0 = byte, 1 = short, 2 = long) */
343 32, /* bitsize */
344 false, /* pc_relative */
345 0, /* bitpos */
346 complain_overflow_bitfield, /* complain_on_overflow */
347 sh_reloc, /* special_function */
348 "r_label", /* name */
349 true, /* partial_inplace */
350 0xffffffff, /* src_mask */
351 0xffffffff, /* dst_mask */
352 false), /* pcrel_offset */
353
354 HOWTO (R_SH_SWITCH8, /* type */
355 0, /* rightshift */
356 0, /* size (0 = byte, 1 = short, 2 = long) */
357 8, /* bitsize */
358 false, /* pc_relative */
359 0, /* bitpos */
360 complain_overflow_bitfield, /* complain_on_overflow */
361 sh_reloc, /* special_function */
362 "r_switch8", /* name */
363 true, /* partial_inplace */
364 0xff, /* src_mask */
365 0xff, /* dst_mask */
366 false) /* pcrel_offset */
367};
368
369#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
370
371/* Check for a bad magic number. */
372#define BADMAG(x) SHBADMAG(x)
373
374/* Customize coffcode.h (this is not currently used). */
375#define SH 1
376
377/* FIXME: This should not be set here. */
378#define __A_MAGIC_SET__
379
17505c5c 380#ifndef COFF_WITH_PE
252b5132 381/* Swap the r_offset field in and out. */
dc810e39
AM		 382#define SWAP_IN_RELOC_OFFSET H_GET_32
383#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 384
385/* Swap out extra information in the reloc structure. */
386#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
387 do \
388 { \
389 dst->r_stuff[0] = 'S'; \
390 dst->r_stuff[1] = 'C'; \
391 } \
392 while (0)
17505c5c 393#endif
252b5132
RH		 394
395/* Get the value of a symbol, when performing a relocation. */
396
397static long
cbfe05c4 398get_symbol_value (symbol)
252b5132 399 asymbol *symbol;
cbfe05c4 400{
252b5132
RH		 401 bfd_vma relocation;
402
403 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 404 relocation = 0;
405 else
252b5132
RH		 406 relocation = (symbol->value +
407 symbol->section->output_section->vma +
408 symbol->section->output_offset);
409
410 return relocation;
411}
412
17505c5c
NC		 413#ifdef COFF_WITH_PE
414/* Convert an rtype to howto for the COFF backend linker.
415 Copied from coff-i386. */
416#define coff_rtype_to_howto coff_sh_rtype_to_howto
f4ffd778 417static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
17505c5c
NC		 418
419static reloc_howto_type *
420coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
86033394 421 bfd * abfd ATTRIBUTE_UNUSED;
17505c5c
NC		 422 asection * sec;
423 struct internal_reloc * rel;
424 struct coff_link_hash_entry * h;
425 struct internal_syment * sym;
426 bfd_vma * addendp;
427{
428 reloc_howto_type * howto;
429
430 howto = sh_coff_howtos + rel->r_type;
431
432 *addendp = 0;
433
434 if (howto->pc_relative)
435 *addendp += sec->vma;
436
437 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
438 {
439 /* This is a common symbol. The section contents include the
440 size (sym->n_value) as an addend. The relocate_section
441 function will be adding in the final value of the symbol. We
442 need to subtract out the current size in order to get the
443 correct result. */
444 BFD_ASSERT (h != NULL);
445 }
446
447 if (howto->pc_relative)
448 {
449 *addendp -= 4;
450
451 /* If the symbol is defined, then the generic code is going to
452 add back the symbol value in order to cancel out an
453 adjustment it made to the addend. However, we set the addend
454 to 0 at the start of this function. We need to adjust here,
455 to avoid the adjustment the generic code will make. FIXME:
456 This is getting a bit hackish. */
457 if (sym != NULL && sym->n_scnum != 0)
458 *addendp -= sym->n_value;
459 }
460
461 if (rel->r_type == R_SH_IMAGEBASE)
462 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
463
464 return howto;
465}
466
993e9275
NC		 467#endif /* COFF_WITH_PE */
468
17505c5c
NC		 469/* This structure is used to map BFD reloc codes to SH PE relocs. */
470struct shcoff_reloc_map
471{
472 unsigned char bfd_reloc_val;
473 unsigned char shcoff_reloc_val;
474};
475
476/* An array mapping BFD reloc codes to SH PE relocs. */
477static const struct shcoff_reloc_map sh_reloc_map[] =
478{
479 { BFD_RELOC_32, R_SH_IMM32CE },
480 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
481 { BFD_RELOC_CTOR, R_SH_IMM32CE },
482};
483
484/* Given a BFD reloc code, return the howto structure for the
485 corresponding SH PE reloc. */
486#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
487
488static reloc_howto_type *
489sh_coff_reloc_type_lookup (abfd, code)
490 bfd * abfd ATTRIBUTE_UNUSED;
491 bfd_reloc_code_real_type code;
492{
493 unsigned int i;
494
993e9275
NC		 495 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
496 if (sh_reloc_map[i].bfd_reloc_val == code)
497 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c
NC		 498
499 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
500 return NULL;
501}
17505c5c 502
252b5132
RH		 503/* This macro is used in coffcode.h to get the howto corresponding to
504 an internal reloc. */
505
506#define RTYPE2HOWTO(relent, internal) \
507 ((relent)->howto = \
508 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
509 ? &sh_coff_howtos[(internal)->r_type] \
510 : (reloc_howto_type *) NULL))
511
512/* This is the same as the macro in coffcode.h, except that it copies
513 r_offset into reloc_entry->addend for some relocs. */
514#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
515 { \
516 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
517 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
518 coffsym = (obj_symbols (abfd) \
519 + (cache_ptr->sym_ptr_ptr - symbols)); \
520 else if (ptr) \
521 coffsym = coff_symbol_from (abfd, ptr); \
522 if (coffsym != (coff_symbol_type *) NULL \
523 && coffsym->native->u.syment.n_scnum == 0) \
524 cache_ptr->addend = 0; \
525 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
526 && ptr->section != (asection *) NULL) \
527 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
528 else \
529 cache_ptr->addend = 0; \
530 if ((reloc).r_type == R_SH_SWITCH8 \
531 || (reloc).r_type == R_SH_SWITCH16 \
532 || (reloc).r_type == R_SH_SWITCH32 \
533 || (reloc).r_type == R_SH_USES \
534 || (reloc).r_type == R_SH_COUNT \
535 || (reloc).r_type == R_SH_ALIGN) \
536 cache_ptr->addend = (reloc).r_offset; \
537 }
538
539/* This is the howto function for the SH relocations. */
540
541static bfd_reloc_status_type
542sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
543 error_message)
544 bfd *abfd;
545 arelent *reloc_entry;
546 asymbol *symbol_in;
547 PTR data;
548 asection *input_section;
549 bfd *output_bfd;
5f771d47 550 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 551{
552 unsigned long insn;
553 bfd_vma sym_value;
554 unsigned short r_type;
555 bfd_vma addr = reloc_entry->address;
556 bfd_byte *hit_data = addr + (bfd_byte *) data;
557
558 r_type = reloc_entry->howto->type;
559
560 if (output_bfd != NULL)
561 {
562 /* Partial linking--do nothing. */
563 reloc_entry->address += input_section->output_offset;
564 return bfd_reloc_ok;
565 }
566
567 /* Almost all relocs have to do with relaxing. If any work must be
568 done for them, it has been done in sh_relax_section. */
569 if (r_type != R_SH_IMM32
17505c5c
NC		 570#ifdef COFF_WITH_PE
571 && r_type != R_SH_IMM32CE
572 && r_type != R_SH_IMAGEBASE
573#endif
252b5132
RH		 574 && (r_type != R_SH_PCDISP
575 || (symbol_in->flags & BSF_LOCAL) != 0))
576 return bfd_reloc_ok;
577
578 if (symbol_in != NULL
579 && bfd_is_und_section (symbol_in->section))
580 return bfd_reloc_undefined;
581
582 sym_value = get_symbol_value (symbol_in);
583
584 switch (r_type)
585 {
586 case R_SH_IMM32:
17505c5c
NC		 587#ifdef COFF_WITH_PE
588 case R_SH_IMM32CE:
589#endif
252b5132
RH		 590 insn = bfd_get_32 (abfd, hit_data);
591 insn += sym_value + reloc_entry->addend;
dc810e39 592 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 593 break;
17505c5c
NC		 594#ifdef COFF_WITH_PE
595 case R_SH_IMAGEBASE:
596 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 597 insn += sym_value + reloc_entry->addend;
598 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
599 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 600 break;
601#endif
252b5132
RH		 602 case R_SH_PCDISP:
603 insn = bfd_get_16 (abfd, hit_data);
604 sym_value += reloc_entry->addend;
605 sym_value -= (input_section->output_section->vma
606 + input_section->output_offset
607 + addr
608 + 4);
609 sym_value += (insn & 0xfff) << 1;
610 if (insn & 0x800)
611 sym_value -= 0x1000;
612 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 613 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 614 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
615 return bfd_reloc_overflow;
616 break;
617 default:
618 abort ();
619 break;
620 }
621
622 return bfd_reloc_ok;
623}
624
875f7f69 625#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 626
627/* We can do relaxing. */
628#define coff_bfd_relax_section sh_relax_section
629
630/* We use the special COFF backend linker. */
631#define coff_relocate_section sh_relocate_section
632
633/* When relaxing, we need to use special code to get the relocated
634 section contents. */
635#define coff_bfd_get_relocated_section_contents \
636 sh_coff_get_relocated_section_contents
637
638#include "coffcode.h"
639\f
640/* This function handles relaxing on the SH.
641
642 Function calls on the SH look like this:
643
644 movl L1,r0
645 ...
646 jsr @r0
647 ...
648 L1:
649 .long function
650
651 The compiler and assembler will cooperate to create R_SH_USES
652 relocs on the jsr instructions. The r_offset field of the
653 R_SH_USES reloc is the PC relative offset to the instruction which
654 loads the register (the r_offset field is computed as though it
655 were a jump instruction, so the offset value is actually from four
656 bytes past the instruction). The linker can use this reloc to
657 determine just which function is being called, and thus decide
658 whether it is possible to replace the jsr with a bsr.
659
660 If multiple function calls are all based on a single register load
661 (i.e., the same function is called multiple times), the compiler
662 guarantees that each function call will have an R_SH_USES reloc.
663 Therefore, if the linker is able to convert each R_SH_USES reloc
664 which refers to that address, it can safely eliminate the register
665 load.
666
667 When the assembler creates an R_SH_USES reloc, it examines it to
668 determine which address is being loaded (L1 in the above example).
669 It then counts the number of references to that address, and
670 creates an R_SH_COUNT reloc at that address. The r_offset field of
671 the R_SH_COUNT reloc will be the number of references. If the
672 linker is able to eliminate a register load, it can use the
673 R_SH_COUNT reloc to see whether it can also eliminate the function
674 address.
675
676 SH relaxing also handles another, unrelated, matter. On the SH, if
677 a load or store instruction is not aligned on a four byte boundary,
678 the memory cycle interferes with the 32 bit instruction fetch,
679 causing a one cycle bubble in the pipeline. Therefore, we try to
680 align load and store instructions on four byte boundaries if we
681 can, by swapping them with one of the adjacent instructions. */
682
cbfe05c4 683static boolean
252b5132
RH		 684sh_relax_section (abfd, sec, link_info, again)
685 bfd *abfd;
686 asection *sec;
687 struct bfd_link_info *link_info;
688 boolean *again;
689{
690 struct internal_reloc *internal_relocs;
691 struct internal_reloc *free_relocs = NULL;
692 boolean have_code;
693 struct internal_reloc *irel, *irelend;
694 bfd_byte *contents = NULL;
695 bfd_byte *free_contents = NULL;
696
697 *again = false;
698
699 if (link_info->relocateable
700 || (sec->flags & SEC_RELOC) == 0
701 || sec->reloc_count == 0)
702 return true;
703
704 /* If this is the first time we have been called for this section,
705 initialize the cooked size. */
706 if (sec->_cooked_size == 0)
707 sec->_cooked_size = sec->_raw_size;
708
709 internal_relocs = (_bfd_coff_read_internal_relocs
710 (abfd, sec, link_info->keep_memory,
711 (bfd_byte *) NULL, false,
712 (struct internal_reloc *) NULL));
713 if (internal_relocs == NULL)
714 goto error_return;
715 if (! link_info->keep_memory)
716 free_relocs = internal_relocs;
717
718 have_code = false;
719
720 irelend = internal_relocs + sec->reloc_count;
721 for (irel = internal_relocs; irel < irelend; irel++)
722 {
723 bfd_vma laddr, paddr, symval;
724 unsigned short insn;
725 struct internal_reloc *irelfn, *irelscan, *irelcount;
726 struct internal_syment sym;
727 bfd_signed_vma foff;
728
729 if (irel->r_type == R_SH_CODE)
730 have_code = true;
731
732 if (irel->r_type != R_SH_USES)
733 continue;
734
735 /* Get the section contents. */
736 if (contents == NULL)
737 {
738 if (coff_section_data (abfd, sec) != NULL
739 && coff_section_data (abfd, sec)->contents != NULL)
740 contents = coff_section_data (abfd, sec)->contents;
741 else
742 {
743 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
744 if (contents == NULL)
745 goto error_return;
746 free_contents = contents;
747
748 if (! bfd_get_section_contents (abfd, sec, contents,
749 (file_ptr) 0, sec->_raw_size))
750 goto error_return;
751 }
752 }
753
754 /* The r_offset field of the R_SH_USES reloc will point us to
755 the register load. The 4 is because the r_offset field is
756 computed as though it were a jump offset, which are based
757 from 4 bytes after the jump instruction. */
758 laddr = irel->r_vaddr - sec->vma + 4;
759 /* Careful to sign extend the 32-bit offset. */
760 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
761 if (laddr >= sec->_raw_size)
762 {
763 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
8f615d07 764 bfd_archive_filename (abfd),
252b5132
RH		 765 (unsigned long) irel->r_vaddr);
766 continue;
767 }
768 insn = bfd_get_16 (abfd, contents + laddr);
769
770 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
771 if ((insn & 0xf000) != 0xd000)
772 {
773 ((*_bfd_error_handler)
774 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
8f615d07 775 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr, insn));
252b5132
RH		 776 continue;
777 }
778
779 /* Get the address from which the register is being loaded. The
780 displacement in the mov.l instruction is quadrupled. It is a
781 displacement from four bytes after the movl instruction, but,
782 before adding in the PC address, two least significant bits
783 of the PC are cleared. We assume that the section is aligned
784 on a four byte boundary. */
785 paddr = insn & 0xff;
786 paddr *= 4;
dc810e39 787 paddr += (laddr + 4) &~ (bfd_vma) 3;
252b5132
RH		 788 if (paddr >= sec->_raw_size)
789 {
790 ((*_bfd_error_handler)
791 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
8f615d07 792 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132
RH		 793 continue;
794 }
795
796 /* Get the reloc for the address from which the register is
797 being loaded. This reloc will tell us which function is
798 actually being called. */
799 paddr += sec->vma;
800 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
801 if (irelfn->r_vaddr == paddr
17505c5c
NC		 802#ifdef COFF_WITH_PE
803 && (irelfn->r_type == R_SH_IMM32
804 || irelfn->r_type == R_SH_IMM32CE
805 || irelfn->r_type == R_SH_IMAGEBASE))
806
807#else
252b5132 808 && irelfn->r_type == R_SH_IMM32)
17505c5c 809#endif
252b5132
RH		 810 break;
811 if (irelfn >= irelend)
812 {
813 ((*_bfd_error_handler)
814 ("%s: 0x%lx: warning: could not find expected reloc",
8f615d07 815 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 816 continue;
817 }
818
819 /* Get the value of the symbol referred to by the reloc. */
820 if (! _bfd_coff_get_external_symbols (abfd))
821 goto error_return;
822 bfd_coff_swap_sym_in (abfd,
823 ((bfd_byte *) obj_coff_external_syms (abfd)
824 + (irelfn->r_symndx
825 * bfd_coff_symesz (abfd))),
826 &sym);
827 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
828 {
829 ((*_bfd_error_handler)
830 ("%s: 0x%lx: warning: symbol in unexpected section",
8f615d07 831 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 832 continue;
833 }
834
835 if (sym.n_sclass != C_EXT)
836 {
837 symval = (sym.n_value
838 - sec->vma
839 + sec->output_section->vma
840 + sec->output_offset);
841 }
842 else
843 {
844 struct coff_link_hash_entry *h;
845
846 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
847 BFD_ASSERT (h != NULL);
848 if (h->root.type != bfd_link_hash_defined
849 && h->root.type != bfd_link_hash_defweak)
850 {
851 /* This appears to be a reference to an undefined
852 symbol. Just ignore it--it will be caught by the
853 regular reloc processing. */
854 continue;
855 }
856
857 symval = (h->root.u.def.value
858 + h->root.u.def.section->output_section->vma
859 + h->root.u.def.section->output_offset);
860 }
861
862 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
863
864 /* See if this function call can be shortened. */
865 foff = (symval
866 - (irel->r_vaddr
867 - sec->vma
868 + sec->output_section->vma
869 + sec->output_offset
870 + 4));
871 if (foff < -0x1000 || foff >= 0x1000)
872 {
873 /* After all that work, we can't shorten this function call. */
874 continue;
875 }
876
877 /* Shorten the function call. */
878
879 /* For simplicity of coding, we are going to modify the section
880 contents, the section relocs, and the BFD symbol table. We
881 must tell the rest of the code not to free up this
882 information. It would be possible to instead create a table
883 of changes which have to be made, as is done in coff-mips.c;
884 that would be more work, but would require less memory when
885 the linker is run. */
886
887 if (coff_section_data (abfd, sec) == NULL)
888 {
dc810e39
AM		 889 bfd_size_type amt = sizeof (struct coff_section_tdata);
890 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
252b5132
RH		 891 if (sec->used_by_bfd == NULL)
892 goto error_return;
893 }
894
895 coff_section_data (abfd, sec)->relocs = internal_relocs;
896 coff_section_data (abfd, sec)->keep_relocs = true;
897 free_relocs = NULL;
898
899 coff_section_data (abfd, sec)->contents = contents;
900 coff_section_data (abfd, sec)->keep_contents = true;
901 free_contents = NULL;
902
903 obj_coff_keep_syms (abfd) = true;
904
905 /* Replace the jsr with a bsr. */
906
907 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
908 replace the jsr with a bsr. */
909 irel->r_type = R_SH_PCDISP;
910 irel->r_symndx = irelfn->r_symndx;
911 if (sym.n_sclass != C_EXT)
912 {
913 /* If this needs to be changed because of future relaxing,
914 it will be handled here like other internal PCDISP
915 relocs. */
916 bfd_put_16 (abfd,
dc810e39 917 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 918 contents + irel->r_vaddr - sec->vma);
919 }
920 else
921 {
922 /* We can't fully resolve this yet, because the external
923 symbol value may be changed by future relaxing. We let
924 the final link phase handle it. */
dc810e39
AM		 925 bfd_put_16 (abfd, (bfd_vma) 0xb000,
926 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 927 }
928
929 /* See if there is another R_SH_USES reloc referring to the same
930 register load. */
931 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
932 if (irelscan->r_type == R_SH_USES
933 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
934 break;
935 if (irelscan < irelend)
936 {
937 /* Some other function call depends upon this register load,
938 and we have not yet converted that function call.
939 Indeed, we may never be able to convert it. There is
940 nothing else we can do at this point. */
941 continue;
942 }
943
944 /* Look for a R_SH_COUNT reloc on the location where the
945 function address is stored. Do this before deleting any
946 bytes, to avoid confusion about the address. */
947 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
948 if (irelcount->r_vaddr == paddr
949 && irelcount->r_type == R_SH_COUNT)
950 break;
951
952 /* Delete the register load. */
953 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
954 goto error_return;
955
956 /* That will change things, so, just in case it permits some
957 other function call to come within range, we should relax
958 again. Note that this is not required, and it may be slow. */
959 *again = true;
960
961 /* Now check whether we got a COUNT reloc. */
962 if (irelcount >= irelend)
963 {
964 ((*_bfd_error_handler)
965 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
8f615d07 966 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 967 continue;
968 }
969
970 /* The number of uses is stored in the r_offset field. We've
971 just deleted one. */
972 if (irelcount->r_offset == 0)
973 {
974 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
8f615d07 975 bfd_archive_filename (abfd),
252b5132
RH		 976 (unsigned long) paddr));
977 continue;
978 }
979
980 --irelcount->r_offset;
981
982 /* If there are no more uses, we can delete the address. Reload
983 the address from irelfn, in case it was changed by the
984 previous call to sh_relax_delete_bytes. */
985 if (irelcount->r_offset == 0)
986 {
987 if (! sh_relax_delete_bytes (abfd, sec,
988 irelfn->r_vaddr - sec->vma, 4))
989 goto error_return;
990 }
991
992 /* We've done all we can with that function call. */
993 }
994
995 /* Look for load and store instructions that we can align on four
996 byte boundaries. */
997 if (have_code)
998 {
999 boolean swapped;
1000
1001 /* Get the section contents. */
1002 if (contents == NULL)
1003 {
1004 if (coff_section_data (abfd, sec) != NULL
1005 && coff_section_data (abfd, sec)->contents != NULL)
1006 contents = coff_section_data (abfd, sec)->contents;
1007 else
1008 {
1009 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
1010 if (contents == NULL)
1011 goto error_return;
1012 free_contents = contents;
1013
1014 if (! bfd_get_section_contents (abfd, sec, contents,
1015 (file_ptr) 0, sec->_raw_size))
1016 goto error_return;
1017 }
1018 }
1019
1020 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1021 goto error_return;
1022
1023 if (swapped)
1024 {
1025 if (coff_section_data (abfd, sec) == NULL)
1026 {
dc810e39
AM		 1027 bfd_size_type amt = sizeof (struct coff_section_tdata);
1028 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
252b5132
RH		 1029 if (sec->used_by_bfd == NULL)
1030 goto error_return;
1031 }
1032
1033 coff_section_data (abfd, sec)->relocs = internal_relocs;
1034 coff_section_data (abfd, sec)->keep_relocs = true;
1035 free_relocs = NULL;
1036
1037 coff_section_data (abfd, sec)->contents = contents;
1038 coff_section_data (abfd, sec)->keep_contents = true;
1039 free_contents = NULL;
1040
1041 obj_coff_keep_syms (abfd) = true;
1042 }
1043 }
1044
1045 if (free_relocs != NULL)
1046 {
1047 free (free_relocs);
1048 free_relocs = NULL;
1049 }
1050
1051 if (free_contents != NULL)
1052 {
1053 if (! link_info->keep_memory)
1054 free (free_contents);
1055 else
1056 {
1057 /* Cache the section contents for coff_link_input_bfd. */
1058 if (coff_section_data (abfd, sec) == NULL)
1059 {
dc810e39
AM		 1060 bfd_size_type amt = sizeof (struct coff_section_tdata);
1061 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
252b5132
RH		 1062 if (sec->used_by_bfd == NULL)
1063 goto error_return;
1064 coff_section_data (abfd, sec)->relocs = NULL;
1065 }
1066 coff_section_data (abfd, sec)->contents = contents;
1067 }
1068 }
1069
1070 return true;
1071
1072 error_return:
1073 if (free_relocs != NULL)
1074 free (free_relocs);
1075 if (free_contents != NULL)
1076 free (free_contents);
1077 return false;
1078}
1079
1080/* Delete some bytes from a section while relaxing. */
1081
1082static boolean
1083sh_relax_delete_bytes (abfd, sec, addr, count)
1084 bfd *abfd;
1085 asection *sec;
1086 bfd_vma addr;
1087 int count;
1088{
1089 bfd_byte *contents;
1090 struct internal_reloc *irel, *irelend;
1091 struct internal_reloc *irelalign;
1092 bfd_vma toaddr;
1093 bfd_byte *esym, *esymend;
1094 bfd_size_type symesz;
1095 struct coff_link_hash_entry **sym_hash;
1096 asection *o;
1097
1098 contents = coff_section_data (abfd, sec)->contents;
1099
1100 /* The deletion must stop at the next ALIGN reloc for an aligment
1101 power larger than the number of bytes we are deleting. */
1102
1103 irelalign = NULL;
1104 toaddr = sec->_cooked_size;
1105
1106 irel = coff_section_data (abfd, sec)->relocs;
1107 irelend = irel + sec->reloc_count;
1108 for (; irel < irelend; irel++)
1109 {
1110 if (irel->r_type == R_SH_ALIGN
1111 && irel->r_vaddr - sec->vma > addr
1112 && count < (1 << irel->r_offset))
1113 {
1114 irelalign = irel;
1115 toaddr = irel->r_vaddr - sec->vma;
1116 break;
1117 }
1118 }
1119
1120 /* Actually delete the bytes. */
dc810e39
AM		 1121 memmove (contents + addr, contents + addr + count,
1122 (size_t) (toaddr - addr - count));
252b5132
RH		 1123 if (irelalign == NULL)
1124 sec->_cooked_size -= count;
1125 else
1126 {
1127 int i;
1128
1129#define NOP_OPCODE (0x0009)
1130
1131 BFD_ASSERT ((count & 1) == 0);
1132 for (i = 0; i < count; i += 2)
dc810e39 1133 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1134 }
1135
1136 /* Adjust all the relocs. */
1137 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1138 {
1139 bfd_vma nraddr, stop;
1140 bfd_vma start = 0;
1141 int insn = 0;
1142 struct internal_syment sym;
1143 int off, adjust, oinsn;
1144 bfd_signed_vma voff = 0;
1145 boolean overflow;
1146
1147 /* Get the new reloc address. */
1148 nraddr = irel->r_vaddr - sec->vma;
1149 if ((irel->r_vaddr - sec->vma > addr
1150 && irel->r_vaddr - sec->vma < toaddr)
1151 || (irel->r_type == R_SH_ALIGN
1152 && irel->r_vaddr - sec->vma == toaddr))
1153 nraddr -= count;
1154
1155 /* See if this reloc was for the bytes we have deleted, in which
1156 case we no longer care about it. Don't delete relocs which
1157 represent addresses, though. */
1158 if (irel->r_vaddr - sec->vma >= addr
1159 && irel->r_vaddr - sec->vma < addr + count
1160 && irel->r_type != R_SH_ALIGN
1161 && irel->r_type != R_SH_CODE
1162 && irel->r_type != R_SH_DATA
1163 && irel->r_type != R_SH_LABEL)
1164 irel->r_type = R_SH_UNUSED;
1165
1166 /* If this is a PC relative reloc, see if the range it covers
1167 includes the bytes we have deleted. */
1168 switch (irel->r_type)
1169 {
1170 default:
1171 break;
1172
1173 case R_SH_PCDISP8BY2:
1174 case R_SH_PCDISP:
1175 case R_SH_PCRELIMM8BY2:
1176 case R_SH_PCRELIMM8BY4:
1177 start = irel->r_vaddr - sec->vma;
1178 insn = bfd_get_16 (abfd, contents + nraddr);
1179 break;
1180 }
1181
1182 switch (irel->r_type)
1183 {
1184 default:
1185 start = stop = addr;
1186 break;
1187
1188 case R_SH_IMM32:
17505c5c
NC		 1189#ifdef COFF_WITH_PE
1190 case R_SH_IMM32CE:
1191 case R_SH_IMAGEBASE:
1192#endif
252b5132
RH		 1193 /* If this reloc is against a symbol defined in this
1194 section, and the symbol will not be adjusted below, we
1195 must check the addend to see it will put the value in
1196 range to be adjusted, and hence must be changed. */
1197 bfd_coff_swap_sym_in (abfd,
1198 ((bfd_byte *) obj_coff_external_syms (abfd)
1199 + (irel->r_symndx
1200 * bfd_coff_symesz (abfd))),
1201 &sym);
1202 if (sym.n_sclass != C_EXT
1203 && sym.n_scnum == sec->target_index
1204 && ((bfd_vma) sym.n_value <= addr
1205 || (bfd_vma) sym.n_value >= toaddr))
1206 {
1207 bfd_vma val;
1208
1209 val = bfd_get_32 (abfd, contents + nraddr);
1210 val += sym.n_value;
1211 if (val > addr && val < toaddr)
1212 bfd_put_32 (abfd, val - count, contents + nraddr);
1213 }
1214 start = stop = addr;
1215 break;
1216
1217 case R_SH_PCDISP8BY2:
1218 off = insn & 0xff;
1219 if (off & 0x80)
1220 off -= 0x100;
1221 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1222 break;
1223
1224 case R_SH_PCDISP:
1225 bfd_coff_swap_sym_in (abfd,
1226 ((bfd_byte *) obj_coff_external_syms (abfd)
1227 + (irel->r_symndx
1228 * bfd_coff_symesz (abfd))),
1229 &sym);
1230 if (sym.n_sclass == C_EXT)
1231 start = stop = addr;
1232 else
1233 {
1234 off = insn & 0xfff;
1235 if (off & 0x800)
1236 off -= 0x1000;
1237 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1238 }
1239 break;
1240
1241 case R_SH_PCRELIMM8BY2:
1242 off = insn & 0xff;
1243 stop = start + 4 + off * 2;
1244 break;
1245
1246 case R_SH_PCRELIMM8BY4:
1247 off = insn & 0xff;
1248 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1249 break;
1250
1251 case R_SH_SWITCH8:
1252 case R_SH_SWITCH16:
1253 case R_SH_SWITCH32:
1254 /* These relocs types represent
1255 .word L2-L1
1256 The r_offset field holds the difference between the reloc
1257 address and L1. That is the start of the reloc, and
1258 adding in the contents gives us the top. We must adjust
1259 both the r_offset field and the section contents. */
1260
1261 start = irel->r_vaddr - sec->vma;
1262 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1263
1264 if (start > addr
1265 && start < toaddr
1266 && (stop <= addr || stop >= toaddr))
1267 irel->r_offset += count;
1268 else if (stop > addr
1269 && stop < toaddr
1270 && (start <= addr || start >= toaddr))
1271 irel->r_offset -= count;
1272
1273 start = stop;
1274
1275 if (irel->r_type == R_SH_SWITCH16)
1276 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1277 else if (irel->r_type == R_SH_SWITCH8)
1278 voff = bfd_get_8 (abfd, contents + nraddr);
1279 else
1280 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1281 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1282
1283 break;
1284
1285 case R_SH_USES:
1286 start = irel->r_vaddr - sec->vma;
1287 stop = (bfd_vma) ((bfd_signed_vma) start
1288 + (long) irel->r_offset
1289 + 4);
1290 break;
1291 }
1292
1293 if (start > addr
1294 && start < toaddr
1295 && (stop <= addr || stop >= toaddr))
1296 adjust = count;
1297 else if (stop > addr
1298 && stop < toaddr
1299 && (start <= addr || start >= toaddr))
1300 adjust = - count;
1301 else
1302 adjust = 0;
1303
1304 if (adjust != 0)
1305 {
1306 oinsn = insn;
1307 overflow = false;
1308 switch (irel->r_type)
1309 {
1310 default:
1311 abort ();
1312 break;
1313
1314 case R_SH_PCDISP8BY2:
1315 case R_SH_PCRELIMM8BY2:
1316 insn += adjust / 2;
1317 if ((oinsn & 0xff00) != (insn & 0xff00))
1318 overflow = true;
dc810e39 1319 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1320 break;
1321
1322 case R_SH_PCDISP:
1323 insn += adjust / 2;
1324 if ((oinsn & 0xf000) != (insn & 0xf000))
1325 overflow = true;
dc810e39 1326 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1327 break;
1328
1329 case R_SH_PCRELIMM8BY4:
1330 BFD_ASSERT (adjust == count || count >= 4);
1331 if (count >= 4)
1332 insn += adjust / 4;
1333 else
1334 {
1335 if ((irel->r_vaddr & 3) == 0)
1336 ++insn;
1337 }
1338 if ((oinsn & 0xff00) != (insn & 0xff00))
1339 overflow = true;
dc810e39 1340 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1341 break;
1342
1343 case R_SH_SWITCH8:
1344 voff += adjust;
1345 if (voff < 0 || voff >= 0xff)
1346 overflow = true;
dc810e39 1347 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1348 break;
1349
1350 case R_SH_SWITCH16:
1351 voff += adjust;
1352 if (voff < - 0x8000 || voff >= 0x8000)
1353 overflow = true;
dc810e39 1354 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1355 break;
1356
1357 case R_SH_SWITCH32:
1358 voff += adjust;
dc810e39 1359 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1360 break;
1361
1362 case R_SH_USES:
1363 irel->r_offset += adjust;
1364 break;
1365 }
1366
1367 if (overflow)
1368 {
1369 ((*_bfd_error_handler)
1370 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
8f615d07 1371 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132
RH		 1372 bfd_set_error (bfd_error_bad_value);
1373 return false;
1374 }
1375 }
1376
1377 irel->r_vaddr = nraddr + sec->vma;
1378 }
1379
1380 /* Look through all the other sections. If there contain any IMM32
1381 relocs against internal symbols which we are not going to adjust
1382 below, we may need to adjust the addends. */
1383 for (o = abfd->sections; o != NULL; o = o->next)
1384 {
1385 struct internal_reloc *internal_relocs;
1386 struct internal_reloc *irelscan, *irelscanend;
1387 bfd_byte *ocontents;
1388
1389 if (o == sec
1390 || (o->flags & SEC_RELOC) == 0
1391 || o->reloc_count == 0)
1392 continue;
1393
1394 /* We always cache the relocs. Perhaps, if info->keep_memory is
1395 false, we should free them, if we are permitted to, when we
1396 leave sh_coff_relax_section. */
1397 internal_relocs = (_bfd_coff_read_internal_relocs
1398 (abfd, o, true, (bfd_byte *) NULL, false,
1399 (struct internal_reloc *) NULL));
1400 if (internal_relocs == NULL)
1401 return false;
1402
1403 ocontents = NULL;
1404 irelscanend = internal_relocs + o->reloc_count;
1405 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1406 {
1407 struct internal_syment sym;
1408
17505c5c
NC		 1409#ifdef COFF_WITH_PE
1410 if (irelscan->r_type != R_SH_IMM32
1411 && irelscan->r_type != R_SH_IMAGEBASE
1412 && irelscan->r_type != R_SH_IMM32CE)
1413#else
252b5132 1414 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1415#endif
252b5132
RH		 1416 continue;
1417
1418 bfd_coff_swap_sym_in (abfd,
1419 ((bfd_byte *) obj_coff_external_syms (abfd)
1420 + (irelscan->r_symndx
1421 * bfd_coff_symesz (abfd))),
1422 &sym);
1423 if (sym.n_sclass != C_EXT
1424 && sym.n_scnum == sec->target_index
1425 && ((bfd_vma) sym.n_value <= addr
1426 || (bfd_vma) sym.n_value >= toaddr))
1427 {
1428 bfd_vma val;
1429
1430 if (ocontents == NULL)
1431 {
1432 if (coff_section_data (abfd, o)->contents != NULL)
1433 ocontents = coff_section_data (abfd, o)->contents;
1434 else
1435 {
1436 /* We always cache the section contents.
1437 Perhaps, if info->keep_memory is false, we
1438 should free them, if we are permitted to,
1439 when we leave sh_coff_relax_section. */
1440 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1441 if (ocontents == NULL)
1442 return false;
1443 if (! bfd_get_section_contents (abfd, o, ocontents,
1444 (file_ptr) 0,
1445 o->_raw_size))
1446 return false;
1447 coff_section_data (abfd, o)->contents = ocontents;
1448 }
1449 }
1450
1451 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1452 val += sym.n_value;
1453 if (val > addr && val < toaddr)
1454 bfd_put_32 (abfd, val - count,
1455 ocontents + irelscan->r_vaddr - o->vma);
1456
1457 coff_section_data (abfd, o)->keep_contents = true;
1458 }
1459 }
1460 }
1461
1462 /* Adjusting the internal symbols will not work if something has
1463 already retrieved the generic symbols. It would be possible to
1464 make this work by adjusting the generic symbols at the same time.
1465 However, this case should not arise in normal usage. */
1466 if (obj_symbols (abfd) != NULL
1467 || obj_raw_syments (abfd) != NULL)
1468 {
1469 ((*_bfd_error_handler)
1470 ("%s: fatal: generic symbols retrieved before relaxing",
8f615d07 1471 bfd_archive_filename (abfd)));
252b5132
RH		 1472 bfd_set_error (bfd_error_invalid_operation);
1473 return false;
1474 }
1475
1476 /* Adjust all the symbols. */
1477 sym_hash = obj_coff_sym_hashes (abfd);
1478 symesz = bfd_coff_symesz (abfd);
1479 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1480 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1481 while (esym < esymend)
1482 {
1483 struct internal_syment isym;
1484
1485 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1486
1487 if (isym.n_scnum == sec->target_index
1488 && (bfd_vma) isym.n_value > addr
1489 && (bfd_vma) isym.n_value < toaddr)
1490 {
1491 isym.n_value -= count;
1492
1493 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1494
1495 if (*sym_hash != NULL)
1496 {
1497 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1498 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1499 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1500 && (*sym_hash)->root.u.def.value < toaddr);
1501 (*sym_hash)->root.u.def.value -= count;
1502 }
1503 }
1504
1505 esym += (isym.n_numaux + 1) * symesz;
1506 sym_hash += isym.n_numaux + 1;
1507 }
1508
1509 /* See if we can move the ALIGN reloc forward. We have adjusted
1510 r_vaddr for it already. */
1511 if (irelalign != NULL)
1512 {
1513 bfd_vma alignto, alignaddr;
1514
1515 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1516 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1517 1 << irelalign->r_offset);
1518 if (alignto != alignaddr)
1519 {
1520 /* Tail recursion. */
1521 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1522 (int) (alignto - alignaddr));
252b5132
RH		 1523 }
1524 }
1525
1526 return true;
1527}
1528\f
1529/* This is yet another version of the SH opcode table, used to rapidly
1530 get information about a particular instruction. */
1531
1532/* The opcode map is represented by an array of these structures. The
1533 array is indexed by the high order four bits in the instruction. */
1534
1535struct sh_major_opcode
1536{
1537 /* A pointer to the instruction list. This is an array which
1538 contains all the instructions with this major opcode. */
1539 const struct sh_minor_opcode *minor_opcodes;
1540 /* The number of elements in minor_opcodes. */
1541 unsigned short count;
1542};
1543
1544/* This structure holds information for a set of SH opcodes. The
1545 instruction code is anded with the mask value, and the resulting
1546 value is used to search the order opcode list. */
1547
1548struct sh_minor_opcode
1549{
1550 /* The sorted opcode list. */
1551 const struct sh_opcode *opcodes;
1552 /* The number of elements in opcodes. */
1553 unsigned short count;
1554 /* The mask value to use when searching the opcode list. */
1555 unsigned short mask;
1556};
1557
1558/* This structure holds information for an SH instruction. An array
1559 of these structures is sorted in order by opcode. */
1560
1561struct sh_opcode
1562{
1563 /* The code for this instruction, after it has been anded with the
1564 mask value in the sh_major_opcode structure. */
1565 unsigned short opcode;
1566 /* Flags for this instruction. */
86033394 1567 unsigned long flags;
252b5132
RH		 1568};
1569
1570/* Flag which appear in the sh_opcode structure. */
1571
1572/* This instruction loads a value from memory. */
1573#define LOAD (0x1)
1574
1575/* This instruction stores a value to memory. */
1576#define STORE (0x2)
1577
1578/* This instruction is a branch. */
1579#define BRANCH (0x4)
1580
1581/* This instruction has a delay slot. */
1582#define DELAY (0x8)
1583
1584/* This instruction uses the value in the register in the field at
1585 mask 0x0f00 of the instruction. */
1586#define USES1 (0x10)
84dcfba7 1587#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1588
1589/* This instruction uses the value in the register in the field at
1590 mask 0x00f0 of the instruction. */
1591#define USES2 (0x20)
84dcfba7 1592#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1593
1594/* This instruction uses the value in register 0. */
1595#define USESR0 (0x40)
1596
1597/* This instruction sets the value in the register in the field at
1598 mask 0x0f00 of the instruction. */
1599#define SETS1 (0x80)
84dcfba7 1600#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1601
1602/* This instruction sets the value in the register in the field at
1603 mask 0x00f0 of the instruction. */
1604#define SETS2 (0x100)
84dcfba7 1605#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1606
1607/* This instruction sets register 0. */
1608#define SETSR0 (0x200)
1609
1610/* This instruction sets a special register. */
1611#define SETSSP (0x400)
1612
1613/* This instruction uses a special register. */
1614#define USESSP (0x800)
1615
1616/* This instruction uses the floating point register in the field at
1617 mask 0x0f00 of the instruction. */
1618#define USESF1 (0x1000)
84dcfba7 1619#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1620
1621/* This instruction uses the floating point register in the field at
1622 mask 0x00f0 of the instruction. */
1623#define USESF2 (0x2000)
84dcfba7 1624#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1625
1626/* This instruction uses floating point register 0. */
1627#define USESF0 (0x4000)
1628
1629/* This instruction sets the floating point register in the field at
1630 mask 0x0f00 of the instruction. */
1631#define SETSF1 (0x8000)
84dcfba7 1632#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1633
d4845d57
JR		 1634#define USESAS (0x10000)
1635#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1636#define USESR8 (0x20000)
1637#define SETSAS (0x40000)
1638#define SETSAS_REG(x) USESAS_REG (x)
1639
86033394 1640#ifndef COFF_IMAGE_WITH_PE
252b5132
RH		 1641static boolean sh_insn_uses_reg
1642 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
84dcfba7
JR		 1643static boolean sh_insn_sets_reg
1644 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1645static boolean sh_insn_uses_or_sets_reg
1646 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
252b5132
RH		 1647static boolean sh_insn_uses_freg
1648 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
84dcfba7
JR		 1649static boolean sh_insn_sets_freg
1650 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1651static boolean sh_insn_uses_or_sets_freg
1652 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
252b5132
RH		 1653static boolean sh_insns_conflict
1654 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1655 const struct sh_opcode *));
1656static boolean sh_load_use
1657 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1658 const struct sh_opcode *));
86033394 1659#endif
252b5132
RH		 1660/* The opcode maps. */
1661
1662#define MAP(a) a, sizeof a / sizeof a[0]
1663
1664static const struct sh_opcode sh_opcode00[] =
1665{
1666 { 0x0008, SETSSP }, /* clrt */
1667 { 0x0009, 0 }, /* nop */
1668 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1669 { 0x0018, SETSSP }, /* sett */
1670 { 0x0019, SETSSP }, /* div0u */
1671 { 0x001b, 0 }, /* sleep */
1672 { 0x0028, SETSSP }, /* clrmac */
1673 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1674 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1675 { 0x0048, SETSSP }, /* clrs */
1676 { 0x0058, SETSSP } /* sets */
1677};
1678
1679static const struct sh_opcode sh_opcode01[] =
1680{
252b5132
RH		 1681 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1682 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1683 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1684 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1685 { 0x0029, SETS1 | USESSP }, /* movt rn */
1686 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1687 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1688 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1689 { 0x0083, LOAD | USES1 }, /* pref @rn */
1690 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1691 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1692 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1693 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1694 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1695};
1696
1697/* These sixteen instructions can be handled with one table entry below. */
1698#if 0
1699 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1700 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1701 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
252b5132
RH		 1702 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1703 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
d4845d57
JR		 1704 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */
1705 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */
1706 { 0x0072, SETS1 | USESSP }, /* stc re,rn */
252b5132 1707 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
252b5132
RH		 1708 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1709 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1710 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1711 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1712 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1713 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1714 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
d4845d57 1715#endif
252b5132
RH		 1716
1717static const struct sh_opcode sh_opcode02[] =
1718{
d4845d57 1719 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1720 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1721 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1722 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1723 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1724 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1725 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1726 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1727 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1728};
1729
1730static const struct sh_minor_opcode sh_opcode0[] =
1731{
1732 { MAP (sh_opcode00), 0xffff },
1733 { MAP (sh_opcode01), 0xf0ff },
1734 { MAP (sh_opcode02), 0xf00f }
1735};
1736
1737static const struct sh_opcode sh_opcode10[] =
1738{
1739 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1740};
1741
1742static const struct sh_minor_opcode sh_opcode1[] =
1743{
1744 { MAP (sh_opcode10), 0xf000 }
1745};
1746
1747static const struct sh_opcode sh_opcode20[] =
1748{
1749 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1750 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1751 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1752 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1753 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1754 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1755 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1756 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1757 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1758 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1759 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1760 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1761 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1762 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1763 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1764};
1765
1766static const struct sh_minor_opcode sh_opcode2[] =
1767{
1768 { MAP (sh_opcode20), 0xf00f }
1769};
1770
1771static const struct sh_opcode sh_opcode30[] =
1772{
1773 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1774 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1775 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1776 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1777 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1778 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1779 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1780 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1781 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1782 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1783 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1784 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1785 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1786 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1787};
1788
1789static const struct sh_minor_opcode sh_opcode3[] =
1790{
1791 { MAP (sh_opcode30), 0xf00f }
1792};
1793
1794static const struct sh_opcode sh_opcode40[] =
1795{
1796 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1797 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1798 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1799 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1800 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1801 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1802 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1803 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1804 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1805 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1806 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1807 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1808 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1809 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1810 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1811 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1812 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1813 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1814 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1815 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1816 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1817 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1818 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1819 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1820 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1821 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1822 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1823 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1824 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1825 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1826 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1827 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1828 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1829 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1830 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1831 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1832 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1833 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1834 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1835 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1836 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1837 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1838 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1839 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1840 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1841 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1842 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1843 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1844 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1845 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1846 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1847#if 0 /* These groups sixteen insns can be
1848 handled with one table entry each below. */
1849 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1850 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1851 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
252b5132 1852 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
252b5132 1853 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
d4845d57
JR		 1854 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */
1855 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */
1856 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */
1857 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */
1858 ..
1859 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */
1860
1861 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1862 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1863 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1864 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
252b5132 1865 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
d4845d57
JR		 1866 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */
1867 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */
1868 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */
1869 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */
1870 ..
1871 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */
1872
1873 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1874 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1875 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1876 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
252b5132 1877 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
d4845d57
JR		 1878 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */
1879 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */
1880 { 0x407e, SETSSP | USES1 } /* ldc rm,re */
1881 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */
1882 ..
1883 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */
1884#endif
252b5132
RH		 1885};
1886
1887static const struct sh_opcode sh_opcode41[] =
1888{
d4845d57
JR		 1889 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1890 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1891 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1892 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1893 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1894 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1895};
1896
1897static const struct sh_minor_opcode sh_opcode4[] =
1898{
1899 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1900 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1901};
1902
1903static const struct sh_opcode sh_opcode50[] =
1904{
1905 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1906};
1907
1908static const struct sh_minor_opcode sh_opcode5[] =
1909{
1910 { MAP (sh_opcode50), 0xf000 }
1911};
1912
1913static const struct sh_opcode sh_opcode60[] =
1914{
1915 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1916 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1917 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1918 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1919 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1920 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1921 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1922 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1923 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1924 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1925 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1926 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1927 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1928 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1929 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1930 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1931};
1932
1933static const struct sh_minor_opcode sh_opcode6[] =
1934{
1935 { MAP (sh_opcode60), 0xf00f }
1936};
1937
1938static const struct sh_opcode sh_opcode70[] =
1939{
1940 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1941};
1942
1943static const struct sh_minor_opcode sh_opcode7[] =
1944{
1945 { MAP (sh_opcode70), 0xf000 }
1946};
1947
1948static const struct sh_opcode sh_opcode80[] =
1949{
1950 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1951 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1952 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1953 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1954 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1955 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1956 { 0x8900, BRANCH | USESSP }, /* bt label */
1957 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1958 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1959 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1960 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1961 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1962};
1963
1964static const struct sh_minor_opcode sh_opcode8[] =
1965{
1966 { MAP (sh_opcode80), 0xff00 }
1967};
1968
1969static const struct sh_opcode sh_opcode90[] =
1970{
1971 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1972};
1973
1974static const struct sh_minor_opcode sh_opcode9[] =
1975{
1976 { MAP (sh_opcode90), 0xf000 }
1977};
1978
1979static const struct sh_opcode sh_opcodea0[] =
1980{
1981 { 0xa000, BRANCH | DELAY } /* bra label */
1982};
1983
1984static const struct sh_minor_opcode sh_opcodea[] =
1985{
1986 { MAP (sh_opcodea0), 0xf000 }
1987};
1988
1989static const struct sh_opcode sh_opcodeb0[] =
1990{
1991 { 0xb000, BRANCH | DELAY } /* bsr label */
1992};
1993
1994static const struct sh_minor_opcode sh_opcodeb[] =
1995{
1996 { MAP (sh_opcodeb0), 0xf000 }
1997};
1998
1999static const struct sh_opcode sh_opcodec0[] =
2000{
2001 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
2002 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
2003 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
2004 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
2005 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
2006 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
2007 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
2008 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
2009 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
2010 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
2011 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
2012 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
2013 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
2014 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
2015 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
2016 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
2017};
2018
2019static const struct sh_minor_opcode sh_opcodec[] =
2020{
2021 { MAP (sh_opcodec0), 0xff00 }
2022};
2023
2024static const struct sh_opcode sh_opcoded0[] =
2025{
2026 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
2027};
2028
2029static const struct sh_minor_opcode sh_opcoded[] =
2030{
2031 { MAP (sh_opcoded0), 0xf000 }
2032};
2033
2034static const struct sh_opcode sh_opcodee0[] =
2035{
2036 { 0xe000, SETS1 } /* mov #imm,rn */
2037};
2038
2039static const struct sh_minor_opcode sh_opcodee[] =
2040{
2041 { MAP (sh_opcodee0), 0xf000 }
2042};
2043
2044static const struct sh_opcode sh_opcodef0[] =
2045{
2046 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
2047 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
2048 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
2049 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
2050 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
2051 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
2052 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
2053 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
2054 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
2055 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
2056 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
2057 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2058 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
2059 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
2060};
2061
2062static const struct sh_opcode sh_opcodef1[] =
2063{
2064 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
2065 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
2066 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
2067 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
2068 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
2069 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
2070 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
2071 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
2072 { 0xf08d, SETSF1 }, /* fldi0 fn */
2073 { 0xf09d, SETSF1 } /* fldi1 fn */
2074};
2075
2076static const struct sh_minor_opcode sh_opcodef[] =
2077{
2078 { MAP (sh_opcodef0), 0xf00f },
2079 { MAP (sh_opcodef1), 0xf0ff }
2080};
2081
f4ffd778 2082#ifndef COFF_IMAGE_WITH_PE
d4845d57 2083static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 2084{
2085 { MAP (sh_opcode0) },
2086 { MAP (sh_opcode1) },
2087 { MAP (sh_opcode2) },
2088 { MAP (sh_opcode3) },
2089 { MAP (sh_opcode4) },
2090 { MAP (sh_opcode5) },
2091 { MAP (sh_opcode6) },
2092 { MAP (sh_opcode7) },
2093 { MAP (sh_opcode8) },
2094 { MAP (sh_opcode9) },
2095 { MAP (sh_opcodea) },
2096 { MAP (sh_opcodeb) },
2097 { MAP (sh_opcodec) },
2098 { MAP (sh_opcoded) },
2099 { MAP (sh_opcodee) },
2100 { MAP (sh_opcodef) }
2101};
f4ffd778 2102#endif
252b5132 2103
d4845d57
JR		 2104/* The double data transfer / parallel processing insns are not
2105 described here. This will cause sh_align_load_span to leave them alone. */
2106
2107static const struct sh_opcode sh_dsp_opcodef0[] =
2108{
2109 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2110 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2111 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2112 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2113 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2114 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2115 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2116 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2117};
2118
2119static const struct sh_minor_opcode sh_dsp_opcodef[] =
2120{
2121 { MAP (sh_dsp_opcodef0), 0xfc0d }
2122};
2123
86033394 2124#ifndef COFF_IMAGE_WITH_PE
252b5132
RH		 2125/* Given an instruction, return a pointer to the corresponding
2126 sh_opcode structure. Return NULL if the instruction is not
2127 recognized. */
2128
2129static const struct sh_opcode *
2130sh_insn_info (insn)
2131 unsigned int insn;
2132{
2133 const struct sh_major_opcode *maj;
2134 const struct sh_minor_opcode *min, *minend;
2135
2136 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2137 min = maj->minor_opcodes;
2138 minend = min + maj->count;
2139 for (; min < minend; min++)
2140 {
2141 unsigned int l;
2142 const struct sh_opcode *op, *opend;
2143
2144 l = insn & min->mask;
2145 op = min->opcodes;
2146 opend = op + min->count;
2147
2148 /* Since the opcodes tables are sorted, we could use a binary
2149 search here if the count were above some cutoff value. */
2150 for (; op < opend; op++)
2151 if (op->opcode == l)
2152 return op;
2153 }
2154
cbfe05c4 2155 return NULL;
252b5132
RH		 2156}
2157
84dcfba7
JR		 2158/* See whether an instruction uses or sets a general purpose register */
2159
2160static boolean
2161sh_insn_uses_or_sets_reg (insn, op, reg)
2162 unsigned int insn;
2163 const struct sh_opcode *op;
2164 unsigned int reg;
2165{
2166 if (sh_insn_uses_reg (insn, op, reg))
2167 return true;
2168
2169 return sh_insn_sets_reg (insn, op, reg);
2170}
2171
252b5132
RH		 2172/* See whether an instruction uses a general purpose register. */
2173
2174static boolean
2175sh_insn_uses_reg (insn, op, reg)
2176 unsigned int insn;
2177 const struct sh_opcode *op;
2178 unsigned int reg;
2179{
2180 unsigned int f;
2181
2182 f = op->flags;
2183
2184 if ((f & USES1) != 0
84dcfba7 2185 && USES1_REG (insn) == reg)
252b5132
RH		 2186 return true;
2187 if ((f & USES2) != 0
84dcfba7 2188 && USES2_REG (insn) == reg)
252b5132
RH		 2189 return true;
2190 if ((f & USESR0) != 0
2191 && reg == 0)
2192 return true;
d4845d57
JR		 2193 if ((f & USESAS) && reg == USESAS_REG (insn))
2194 return true;
2195 if ((f & USESR8) && reg == 8)
2196 return true;
252b5132
RH		 2197
2198 return false;
2199}
17505c5c 2200
84dcfba7
JR		 2201/* See whether an instruction sets a general purpose register. */
2202
2203static boolean
2204sh_insn_sets_reg (insn, op, reg)
2205 unsigned int insn;
2206 const struct sh_opcode *op;
2207 unsigned int reg;
2208{
2209 unsigned int f;
2210
2211 f = op->flags;
2212
2213 if ((f & SETS1) != 0
2214 && SETS1_REG (insn) == reg)
2215 return true;
2216 if ((f & SETS2) != 0
2217 && SETS2_REG (insn) == reg)
2218 return true;
2219 if ((f & SETSR0) != 0
2220 && reg == 0)
2221 return true;
d4845d57
JR		 2222 if ((f & SETSAS) && reg == SETSAS_REG (insn))
2223 return true;
84dcfba7
JR		 2224
2225 return false;
2226}
2227
2228/* See whether an instruction uses or sets a floating point register */
2229
2230static boolean
2231sh_insn_uses_or_sets_freg (insn, op, reg)
2232 unsigned int insn;
2233 const struct sh_opcode *op;
2234 unsigned int reg;
2235{
2236 if (sh_insn_uses_freg (insn, op, reg))
2237 return true;
2238
2239 return sh_insn_sets_freg (insn, op, reg);
2240}
252b5132
RH		 2241
2242/* See whether an instruction uses a floating point register. */
2243
2244static boolean
2245sh_insn_uses_freg (insn, op, freg)
2246 unsigned int insn;
2247 const struct sh_opcode *op;
2248 unsigned int freg;
2249{
2250 unsigned int f;
2251
2252 f = op->flags;
2253
2254 /* We can't tell if this is a double-precision insn, so just play safe
2255 and assume that it might be. So not only have we test FREG against
2256 itself, but also even FREG against FREG+1 - if the using insn uses
2257 just the low part of a double precision value - but also an odd
2258 FREG against FREG-1 - if the setting insn sets just the low part
2259 of a double precision value.
2260 So what this all boils down to is that we have to ignore the lowest
2261 bit of the register number. */
cbfe05c4 2262
252b5132 2263 if ((f & USESF1) != 0
84dcfba7 2264 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
252b5132
RH		 2265 return true;
2266 if ((f & USESF2) != 0
84dcfba7 2267 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
252b5132
RH		 2268 return true;
2269 if ((f & USESF0) != 0
2270 && freg == 0)
2271 return true;
2272
2273 return false;
2274}
2275
84dcfba7
JR		 2276/* See whether an instruction sets a floating point register. */
2277
2278static boolean
2279sh_insn_sets_freg (insn, op, freg)
2280 unsigned int insn;
2281 const struct sh_opcode *op;
2282 unsigned int freg;
2283{
2284 unsigned int f;
2285
2286 f = op->flags;
2287
2288 /* We can't tell if this is a double-precision insn, so just play safe
2289 and assume that it might be. So not only have we test FREG against
2290 itself, but also even FREG against FREG+1 - if the using insn uses
2291 just the low part of a double precision value - but also an odd
2292 FREG against FREG-1 - if the setting insn sets just the low part
2293 of a double precision value.
2294 So what this all boils down to is that we have to ignore the lowest
2295 bit of the register number. */
cbfe05c4 2296
84dcfba7
JR		 2297 if ((f & SETSF1) != 0
2298 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
2299 return true;
2300
2301 return false;
2302}
2303
252b5132
RH		 2304/* See whether instructions I1 and I2 conflict, assuming I1 comes
2305 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2306 This should return true if there is a conflict, or false if the
2307 instructions can be swapped safely. */
2308
2309static boolean
2310sh_insns_conflict (i1, op1, i2, op2)
2311 unsigned int i1;
2312 const struct sh_opcode *op1;
2313 unsigned int i2;
2314 const struct sh_opcode *op2;
2315{
2316 unsigned int f1, f2;
2317
2318 f1 = op1->flags;
2319 f2 = op2->flags;
2320
2321 /* Load of fpscr conflicts with floating point operations.
2322 FIXME: shouldn't test raw opcodes here. */
2323 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2324 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
2325 return true;
2326
2327 if ((f1 & (BRANCH | DELAY)) != 0
2328 || (f2 & (BRANCH | DELAY)) != 0)
2329 return true;
2330
84dcfba7
JR		 2331 if (((f1 | f2) & SETSSP)
2332 && (f1 & (SETSSP | USESSP))
2333 && (f2 & (SETSSP | USESSP)))
252b5132
RH		 2334 return true;
2335
2336 if ((f1 & SETS1) != 0
84dcfba7 2337 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
252b5132
RH		 2338 return true;
2339 if ((f1 & SETS2) != 0
84dcfba7 2340 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
252b5132
RH		 2341 return true;
2342 if ((f1 & SETSR0) != 0
84dcfba7 2343 && sh_insn_uses_or_sets_reg (i2, op2, 0))
252b5132 2344 return true;
d4845d57
JR		 2345 if ((f1 & SETSAS)
2346 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
2347 return true;
252b5132 2348 if ((f1 & SETSF1) != 0
84dcfba7 2349 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
252b5132
RH		 2350 return true;
2351
2352 if ((f2 & SETS1) != 0
84dcfba7 2353 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
252b5132
RH		 2354 return true;
2355 if ((f2 & SETS2) != 0
84dcfba7 2356 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
252b5132
RH		 2357 return true;
2358 if ((f2 & SETSR0) != 0
84dcfba7 2359 && sh_insn_uses_or_sets_reg (i1, op1, 0))
252b5132 2360 return true;
d4845d57
JR		 2361 if ((f2 & SETSAS)
2362 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
2363 return true;
252b5132 2364 if ((f2 & SETSF1) != 0
84dcfba7 2365 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
252b5132
RH		 2366 return true;
2367
2368 /* The instructions do not conflict. */
2369 return false;
2370}
2371
2372/* I1 is a load instruction, and I2 is some other instruction. Return
2373 true if I1 loads a register which I2 uses. */
2374
2375static boolean
2376sh_load_use (i1, op1, i2, op2)
2377 unsigned int i1;
2378 const struct sh_opcode *op1;
2379 unsigned int i2;
2380 const struct sh_opcode *op2;
2381{
2382 unsigned int f1;
2383
2384 f1 = op1->flags;
2385
2386 if ((f1 & LOAD) == 0)
2387 return false;
2388
2389 /* If both SETS1 and SETSSP are set, that means a load to a special
2390 register using postincrement addressing mode, which we don't care
2391 about here. */
2392 if ((f1 & SETS1) != 0
2393 && (f1 & SETSSP) == 0
2394 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2395 return true;
2396
2397 if ((f1 & SETSR0) != 0
2398 && sh_insn_uses_reg (i2, op2, 0))
2399 return true;
2400
2401 if ((f1 & SETSF1) != 0
2402 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2403 return true;
2404
2405 return false;
2406}
2407
2408/* Try to align loads and stores within a span of memory. This is
2409 called by both the ELF and the COFF sh targets. ABFD and SEC are
2410 the BFD and section we are examining. CONTENTS is the contents of
2411 the section. SWAP is the routine to call to swap two instructions.
2412 RELOCS is a pointer to the internal relocation information, to be
2413 passed to SWAP. PLABEL is a pointer to the current label in a
2414 sorted list of labels; LABEL_END is the end of the list. START and
2415 STOP are the range of memory to examine. If a swap is made,
2416 *PSWAPPED is set to true. */
2417
86033394
NC		 2418#ifdef COFF_WITH_PE
2419static
2420#endif
252b5132
RH		 2421boolean
2422_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2423 plabel, label_end, start, stop, pswapped)
2424 bfd *abfd;
2425 asection *sec;
2426 bfd_byte *contents;
2427 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2428 PTR relocs;
2429 bfd_vma **plabel;
2430 bfd_vma *label_end;
2431 bfd_vma start;
2432 bfd_vma stop;
2433 boolean *pswapped;
2434{
d4845d57
JR		 2435 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2436 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2437 bfd_vma i;
2438
d4845d57
JR		 2439 /* The SH4 has a Harvard architecture, hence aligning loads is not
2440 desirable. In fact, it is counter-productive, since it interferes
2441 with the schedules generated by the compiler. */
2442 if (abfd->arch_info->mach == bfd_mach_sh4)
2443 return true;
2444
2445 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2446 instructions. */
2447 if (dsp)
2448 {
2449 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2450 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2451 }
2452
252b5132
RH		 2453 /* Instructions should be aligned on 2 byte boundaries. */
2454 if ((start & 1) == 1)
2455 ++start;
2456
2457 /* Now look through the unaligned addresses. */
2458 i = start;
2459 if ((i & 2) == 0)
2460 i += 2;
2461 for (; i < stop; i += 4)
2462 {
2463 unsigned int insn;
2464 const struct sh_opcode *op;
2465 unsigned int prev_insn = 0;
2466 const struct sh_opcode *prev_op = NULL;
2467
2468 insn = bfd_get_16 (abfd, contents + i);
2469 op = sh_insn_info (insn);
2470 if (op == NULL
2471 || (op->flags & (LOAD | STORE)) == 0)
2472 continue;
2473
2474 /* This is a load or store which is not on a four byte boundary. */
2475
2476 while (*plabel < label_end && **plabel < i)
2477 ++*plabel;
2478
2479 if (i > start)
2480 {
2481 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2482 /* If INSN is the field b of a parallel processing insn, it is not
2483 a load / store after all. Note that the test here might mistake
2484 the field_b of a pcopy insn for the starting code of a parallel
2485 processing insn; this might miss a swapping opportunity, but at
2486 least we're on the safe side. */
2487 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2488 continue;
2489
2490 /* Check if prev_insn is actually the field b of a parallel
2491 processing insn. Again, this can give a spurious match
2492 after a pcopy. */
2493 if (dsp && i - 2 > start)
2494 {
2495 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2496
d4845d57
JR		 2497 if ((pprev_insn & 0xfc00) == 0xf800)
2498 prev_op = NULL;
2499 else
2500 prev_op = sh_insn_info (prev_insn);
2501 }
2502 else
2503 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2504
2505 /* If the load/store instruction is in a delay slot, we
2506 can't swap. */
2507 if (prev_op == NULL
2508 || (prev_op->flags & DELAY) != 0)
2509 continue;
2510 }
2511 if (i > start
2512 && (*plabel >= label_end || **plabel != i)
2513 && prev_op != NULL
2514 && (prev_op->flags & (LOAD | STORE)) == 0
2515 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2516 {
2517 boolean ok;
2518
2519 /* The load/store instruction does not have a label, and
2520 there is a previous instruction; PREV_INSN is not
2521 itself a load/store instruction, and PREV_INSN and
2522 INSN do not conflict. */
2523
2524 ok = true;
2525
2526 if (i >= start + 4)
2527 {
2528 unsigned int prev2_insn;
2529 const struct sh_opcode *prev2_op;
2530
2531 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2532 prev2_op = sh_insn_info (prev2_insn);
2533
2534 /* If the instruction before PREV_INSN has a delay
2535 slot--that is, PREV_INSN is in a delay slot--we
2536 can not swap. */
2537 if (prev2_op == NULL
2538 || (prev2_op->flags & DELAY) != 0)
2539 ok = false;
2540
2541 /* If the instruction before PREV_INSN is a load,
2542 and it sets a register which INSN uses, then
2543 putting INSN immediately after PREV_INSN will
2544 cause a pipeline bubble, so there is no point to
2545 making the swap. */
2546 if (ok
2547 && (prev2_op->flags & LOAD) != 0
2548 && sh_load_use (prev2_insn, prev2_op, insn, op))
2549 ok = false;
2550 }
2551
2552 if (ok)
2553 {
2554 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2555 return false;
2556 *pswapped = true;
2557 continue;
2558 }
2559 }
2560
2561 while (*plabel < label_end && **plabel < i + 2)
2562 ++*plabel;
2563
2564 if (i + 2 < stop
2565 && (*plabel >= label_end || **plabel != i + 2))
2566 {
2567 unsigned int next_insn;
2568 const struct sh_opcode *next_op;
2569
2570 /* There is an instruction after the load/store
2571 instruction, and it does not have a label. */
2572 next_insn = bfd_get_16 (abfd, contents + i + 2);
2573 next_op = sh_insn_info (next_insn);
2574 if (next_op != NULL
2575 && (next_op->flags & (LOAD | STORE)) == 0
2576 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2577 {
2578 boolean ok;
2579
2580 /* NEXT_INSN is not itself a load/store instruction,
2581 and it does not conflict with INSN. */
2582
2583 ok = true;
2584
2585 /* If PREV_INSN is a load, and it sets a register
2586 which NEXT_INSN uses, then putting NEXT_INSN
2587 immediately after PREV_INSN will cause a pipeline
2588 bubble, so there is no reason to make this swap. */
2589 if (prev_op != NULL
2590 && (prev_op->flags & LOAD) != 0
2591 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2592 ok = false;
2593
2594 /* If INSN is a load, and it sets a register which
2595 the insn after NEXT_INSN uses, then doing the
2596 swap will cause a pipeline bubble, so there is no
2597 reason to make the swap. However, if the insn
2598 after NEXT_INSN is itself a load or store
2599 instruction, then it is misaligned, so
2600 optimistically hope that it will be swapped
2601 itself, and just live with the pipeline bubble if
2602 it isn't. */
2603 if (ok
2604 && i + 4 < stop
2605 && (op->flags & LOAD) != 0)
2606 {
2607 unsigned int next2_insn;
2608 const struct sh_opcode *next2_op;
2609
2610 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2611 next2_op = sh_insn_info (next2_insn);
2612 if ((next2_op->flags & (LOAD | STORE)) == 0
2613 && sh_load_use (insn, op, next2_insn, next2_op))
2614 ok = false;
2615 }
2616
2617 if (ok)
2618 {
2619 if (! (*swap) (abfd, sec, relocs, contents, i))
2620 return false;
2621 *pswapped = true;
2622 continue;
2623 }
2624 }
2625 }
2626 }
2627
2628 return true;
2629}
86033394 2630#endif /* not COFF_IMAGE_WITH_PE */
252b5132
RH		 2631
2632/* Look for loads and stores which we can align to four byte
2633 boundaries. See the longer comment above sh_relax_section for why
2634 this is desirable. This sets *PSWAPPED if some instruction was
2635 swapped. */
2636
2637static boolean
2638sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2639 bfd *abfd;
2640 asection *sec;
2641 struct internal_reloc *internal_relocs;
2642 bfd_byte *contents;
2643 boolean *pswapped;
2644{
2645 struct internal_reloc *irel, *irelend;
2646 bfd_vma *labels = NULL;
2647 bfd_vma *label, *label_end;
dc810e39 2648 bfd_size_type amt;
252b5132
RH		 2649
2650 *pswapped = false;
2651
2652 irelend = internal_relocs + sec->reloc_count;
2653
2654 /* Get all the addresses with labels on them. */
dc810e39
AM		 2655 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2656 labels = (bfd_vma *) bfd_malloc (amt);
252b5132
RH		 2657 if (labels == NULL)
2658 goto error_return;
2659 label_end = labels;
2660 for (irel = internal_relocs; irel < irelend; irel++)
2661 {
2662 if (irel->r_type == R_SH_LABEL)
2663 {
2664 *label_end = irel->r_vaddr - sec->vma;
2665 ++label_end;
2666 }
2667 }
2668
2669 /* Note that the assembler currently always outputs relocs in
2670 address order. If that ever changes, this code will need to sort
2671 the label values and the relocs. */
2672
2673 label = labels;
2674
2675 for (irel = internal_relocs; irel < irelend; irel++)
2676 {
2677 bfd_vma start, stop;
2678
2679 if (irel->r_type != R_SH_CODE)
2680 continue;
2681
2682 start = irel->r_vaddr - sec->vma;
2683
2684 for (irel++; irel < irelend; irel++)
2685 if (irel->r_type == R_SH_DATA)
2686 break;
2687 if (irel < irelend)
2688 stop = irel->r_vaddr - sec->vma;
2689 else
2690 stop = sec->_cooked_size;
2691
2692 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2693 (PTR) internal_relocs, &label,
2694 label_end, start, stop, pswapped))
2695 goto error_return;
2696 }
2697
2698 free (labels);
2699
2700 return true;
2701
2702 error_return:
2703 if (labels != NULL)
2704 free (labels);
2705 return false;
2706}
2707
2708/* Swap two SH instructions. */
2709
2710static boolean
2711sh_swap_insns (abfd, sec, relocs, contents, addr)
2712 bfd *abfd;
2713 asection *sec;
2714 PTR relocs;
2715 bfd_byte *contents;
2716 bfd_vma addr;
2717{
2718 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2719 unsigned short i1, i2;
2720 struct internal_reloc *irel, *irelend;
2721
2722 /* Swap the instructions themselves. */
2723 i1 = bfd_get_16 (abfd, contents + addr);
2724 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2725 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2726 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2727
2728 /* Adjust all reloc addresses. */
2729 irelend = internal_relocs + sec->reloc_count;
2730 for (irel = internal_relocs; irel < irelend; irel++)
2731 {
2732 int type, add;
2733
2734 /* There are a few special types of relocs that we don't want to
2735 adjust. These relocs do not apply to the instruction itself,
2736 but are only associated with the address. */
2737 type = irel->r_type;
2738 if (type == R_SH_ALIGN
2739 || type == R_SH_CODE
2740 || type == R_SH_DATA
2741 || type == R_SH_LABEL)
2742 continue;
2743
2744 /* If an R_SH_USES reloc points to one of the addresses being
2745 swapped, we must adjust it. It would be incorrect to do this
2746 for a jump, though, since we want to execute both
2747 instructions after the jump. (We have avoided swapping
2748 around a label, so the jump will not wind up executing an
2749 instruction it shouldn't). */
2750 if (type == R_SH_USES)
2751 {
2752 bfd_vma off;
2753
2754 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2755 if (off == addr)
2756 irel->r_offset += 2;
2757 else if (off == addr + 2)
2758 irel->r_offset -= 2;
2759 }
2760
2761 if (irel->r_vaddr - sec->vma == addr)
2762 {
2763 irel->r_vaddr += 2;
2764 add = -2;
2765 }
2766 else if (irel->r_vaddr - sec->vma == addr + 2)
2767 {
2768 irel->r_vaddr -= 2;
2769 add = 2;
2770 }
2771 else
2772 add = 0;
2773
2774 if (add != 0)
2775 {
2776 bfd_byte *loc;
2777 unsigned short insn, oinsn;
2778 boolean overflow;
2779
2780 loc = contents + irel->r_vaddr - sec->vma;
2781 overflow = false;
2782 switch (type)
2783 {
2784 default:
2785 break;
2786
2787 case R_SH_PCDISP8BY2:
2788 case R_SH_PCRELIMM8BY2:
2789 insn = bfd_get_16 (abfd, loc);
2790 oinsn = insn;
2791 insn += add / 2;
2792 if ((oinsn & 0xff00) != (insn & 0xff00))
2793 overflow = true;
dc810e39 2794 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2795 break;
2796
2797 case R_SH_PCDISP:
2798 insn = bfd_get_16 (abfd, loc);
2799 oinsn = insn;
2800 insn += add / 2;
2801 if ((oinsn & 0xf000) != (insn & 0xf000))
2802 overflow = true;
dc810e39 2803 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2804 break;
2805
2806 case R_SH_PCRELIMM8BY4:
2807 /* This reloc ignores the least significant 3 bits of
2808 the program counter before adding in the offset.
2809 This means that if ADDR is at an even address, the
2810 swap will not affect the offset. If ADDR is an at an
2811 odd address, then the instruction will be crossing a
2812 four byte boundary, and must be adjusted. */
2813 if ((addr & 3) != 0)
2814 {
2815 insn = bfd_get_16 (abfd, loc);
2816 oinsn = insn;
2817 insn += add / 2;
2818 if ((oinsn & 0xff00) != (insn & 0xff00))
2819 overflow = true;
dc810e39 2820 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2821 }
2822
2823 break;
2824 }
2825
2826 if (overflow)
2827 {
2828 ((*_bfd_error_handler)
2829 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
8f615d07 2830 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132
RH		 2831 bfd_set_error (bfd_error_bad_value);
2832 return false;
2833 }
2834 }
2835 }
2836
2837 return true;
2838}
2839\f
2840/* This is a modification of _bfd_coff_generic_relocate_section, which
2841 will handle SH relaxing. */
2842
2843static boolean
2844sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2845 relocs, syms, sections)
5f771d47 2846 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2847 struct bfd_link_info *info;
2848 bfd *input_bfd;
2849 asection *input_section;
2850 bfd_byte *contents;
2851 struct internal_reloc *relocs;
2852 struct internal_syment *syms;
2853 asection **sections;
2854{
2855 struct internal_reloc *rel;
2856 struct internal_reloc *relend;
2857
2858 rel = relocs;
2859 relend = rel + input_section->reloc_count;
2860 for (; rel < relend; rel++)
2861 {
2862 long symndx;
2863 struct coff_link_hash_entry *h;
2864 struct internal_syment *sym;
2865 bfd_vma addend;
2866 bfd_vma val;
2867 reloc_howto_type *howto;
2868 bfd_reloc_status_type rstat;
2869
2870 /* Almost all relocs have to do with relaxing. If any work must
2871 be done for them, it has been done in sh_relax_section. */
2872 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2873#ifdef COFF_WITH_PE
2874 && rel->r_type != R_SH_IMM32CE
2875 && rel->r_type != R_SH_IMAGEBASE
2876#endif
252b5132
RH		 2877 && rel->r_type != R_SH_PCDISP)
2878 continue;
2879
2880 symndx = rel->r_symndx;
2881
2882 if (symndx == -1)
2883 {
2884 h = NULL;
2885 sym = NULL;
2886 }
2887 else
cbfe05c4 2888 {
252b5132
RH		 2889 if (symndx < 0
2890 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2891 {
2892 (*_bfd_error_handler)
2893 ("%s: illegal symbol index %ld in relocs",
8f615d07 2894 bfd_archive_filename (input_bfd), symndx);
252b5132
RH		 2895 bfd_set_error (bfd_error_bad_value);
2896 return false;
2897 }
2898 h = obj_coff_sym_hashes (input_bfd)[symndx];
2899 sym = syms + symndx;
2900 }
2901
2902 if (sym != NULL && sym->n_scnum != 0)
2903 addend = - sym->n_value;
2904 else
2905 addend = 0;
2906
2907 if (rel->r_type == R_SH_PCDISP)
2908 addend -= 4;
2909
2910 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2911 howto = NULL;
2912 else
2913 howto = &sh_coff_howtos[rel->r_type];
2914
2915 if (howto == NULL)
2916 {
2917 bfd_set_error (bfd_error_bad_value);
2918 return false;
2919 }
2920
17505c5c
NC		 2921#ifdef COFF_WITH_PE
2922 if (rel->r_type == R_SH_IMAGEBASE)
2923 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2924#endif
cbfe05c4 2925
252b5132
RH		 2926 val = 0;
2927
2928 if (h == NULL)
2929 {
2930 asection *sec;
2931
2932 /* There is nothing to do for an internal PCDISP reloc. */
2933 if (rel->r_type == R_SH_PCDISP)
2934 continue;
2935
2936 if (symndx == -1)
2937 {
2938 sec = bfd_abs_section_ptr;
2939 val = 0;
2940 }
2941 else
2942 {
2943 sec = sections[symndx];
2944 val = (sec->output_section->vma
2945 + sec->output_offset
2946 + sym->n_value
2947 - sec->vma);
2948 }
2949 }
2950 else
2951 {
2952 if (h->root.type == bfd_link_hash_defined
2953 || h->root.type == bfd_link_hash_defweak)
2954 {
2955 asection *sec;
2956
2957 sec = h->root.u.def.section;
2958 val = (h->root.u.def.value
2959 + sec->output_section->vma
2960 + sec->output_offset);
2961 }
2962 else if (! info->relocateable)
2963 {
2964 if (! ((*info->callbacks->undefined_symbol)
2965 (info, h->root.root.string, input_bfd, input_section,
5cc7c785 2966 rel->r_vaddr - input_section->vma, true)))
252b5132
RH		 2967 return false;
2968 }
2969 }
2970
2971 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2972 contents,
2973 rel->r_vaddr - input_section->vma,
2974 val, addend);
2975
2976 switch (rstat)
2977 {
2978 default:
2979 abort ();
2980 case bfd_reloc_ok:
2981 break;
2982 case bfd_reloc_overflow:
2983 {
2984 const char *name;
2985 char buf[SYMNMLEN + 1];
2986
2987 if (symndx == -1)
2988 name = "*ABS*";
2989 else if (h != NULL)
2990 name = h->root.root.string;
2991 else if (sym->_n._n_n._n_zeroes == 0
2992 && sym->_n._n_n._n_offset != 0)
2993 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2994 else
2995 {
2996 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2997 buf[SYMNMLEN] = '\0';
2998 name = buf;
2999 }
3000
3001 if (! ((*info->callbacks->reloc_overflow)
3002 (info, name, howto->name, (bfd_vma) 0, input_bfd,
3003 input_section, rel->r_vaddr - input_section->vma)))
3004 return false;
3005 }
3006 }
3007 }
3008
3009 return true;
3010}
3011
3012/* This is a version of bfd_generic_get_relocated_section_contents
3013 which uses sh_relocate_section. */
3014
3015static bfd_byte *
3016sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
3017 data, relocateable, symbols)
3018 bfd *output_bfd;
3019 struct bfd_link_info *link_info;
3020 struct bfd_link_order *link_order;
3021 bfd_byte *data;
3022 boolean relocateable;
3023 asymbol **symbols;
3024{
3025 asection *input_section = link_order->u.indirect.section;
3026 bfd *input_bfd = input_section->owner;
3027 asection **sections = NULL;
3028 struct internal_reloc *internal_relocs = NULL;
3029 struct internal_syment *internal_syms = NULL;
3030
3031 /* We only need to handle the case of relaxing, or of having a
3032 particular set of section contents, specially. */
3033 if (relocateable
3034 || coff_section_data (input_bfd, input_section) == NULL
3035 || coff_section_data (input_bfd, input_section)->contents == NULL)
3036 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
3037 link_order, data,
3038 relocateable,
3039 symbols);
3040
3041 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
dc810e39 3042 (size_t) input_section->_raw_size);
252b5132
RH		 3043
3044 if ((input_section->flags & SEC_RELOC) != 0
3045 && input_section->reloc_count > 0)
3046 {
3047 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
3048 bfd_byte *esym, *esymend;
3049 struct internal_syment *isymp;
3050 asection **secpp;
dc810e39 3051 bfd_size_type amt;
252b5132
RH		 3052
3053 if (! _bfd_coff_get_external_symbols (input_bfd))
3054 goto error_return;
3055
3056 internal_relocs = (_bfd_coff_read_internal_relocs
3057 (input_bfd, input_section, false, (bfd_byte *) NULL,
3058 false, (struct internal_reloc *) NULL));
3059 if (internal_relocs == NULL)
3060 goto error_return;
3061
dc810e39
AM		 3062 amt = obj_raw_syment_count (input_bfd);
3063 amt *= sizeof (struct internal_syment);
3064 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 3065 if (internal_syms == NULL)
3066 goto error_return;
3067
dc810e39
AM		 3068 amt = obj_raw_syment_count (input_bfd);
3069 amt *= sizeof (asection *);
3070 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 3071 if (sections == NULL)
3072 goto error_return;
3073
3074 isymp = internal_syms;
3075 secpp = sections;
3076 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3077 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3078 while (esym < esymend)
3079 {
3080 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3081
3082 if (isymp->n_scnum != 0)
3083 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3084 else
3085 {
3086 if (isymp->n_value == 0)
3087 *secpp = bfd_und_section_ptr;
3088 else
3089 *secpp = bfd_com_section_ptr;
3090 }
3091
3092 esym += (isymp->n_numaux + 1) * symesz;
3093 secpp += isymp->n_numaux + 1;
3094 isymp += isymp->n_numaux + 1;
3095 }
3096
3097 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3098 input_section, data, internal_relocs,
3099 internal_syms, sections))
3100 goto error_return;
3101
3102 free (sections);
3103 sections = NULL;
3104 free (internal_syms);
3105 internal_syms = NULL;
3106 free (internal_relocs);
3107 internal_relocs = NULL;
3108 }
3109
3110 return data;
3111
3112 error_return:
3113 if (internal_relocs != NULL)
3114 free (internal_relocs);
3115 if (internal_syms != NULL)
3116 free (internal_syms);
3117 if (sections != NULL)
3118 free (sections);
3119 return NULL;
3120}
3121
3122/* The target vectors. */
3123
17505c5c 3124#ifndef TARGET_SHL_SYM
c3c89269 3125CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL)
17505c5c 3126#endif
252b5132 3127
c3c89269
NC		 3128#ifdef TARGET_SHL_SYM
3129#define TARGET_SYM TARGET_SHL_SYM
3130#else
3131#define TARGET_SYM shlcoff_vec
3132#endif
cbfe05c4 3133
c3c89269
NC		 3134#ifndef TARGET_SHL_NAME
3135#define TARGET_SHL_NAME "coff-shl"
3136#endif
252b5132 3137
17505c5c
NC		 3138#ifdef COFF_WITH_PE
3139CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3140 SEC_CODE | SEC_DATA, '_', NULL);
3141#else
86033394
NC		 3142CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3143 0, '_', NULL)
17505c5c 3144#endif
86033394 3145
17505c5c 3146#ifndef TARGET_SHL_SYM
f4ffd778
NC		 3147static const bfd_target * coff_small_object_p PARAMS ((bfd *));
3148static boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
252b5132
RH		 3149/* Some people want versions of the SH COFF target which do not align
3150 to 16 byte boundaries. We implement that by adding a couple of new
3151 target vectors. These are just like the ones above, but they
3152 change the default section alignment. To generate them in the
3153 assembler, use -small. To use them in the linker, use -b
3154 coff-sh{l}-small and -oformat coff-sh{l}-small.
3155
3156 Yes, this is a horrible hack. A general solution for setting
3157 section alignment in COFF is rather complex. ELF handles this
3158 correctly. */
3159
3160/* Only recognize the small versions if the target was not defaulted.
3161 Otherwise we won't recognize the non default endianness. */
3162
3163static const bfd_target *
3164coff_small_object_p (abfd)
3165 bfd *abfd;
3166{
3167 if (abfd->target_defaulted)
3168 {
3169 bfd_set_error (bfd_error_wrong_format);
3170 return NULL;
3171 }
3172 return coff_object_p (abfd);
3173}
3174
3175/* Set the section alignment for the small versions. */
3176
3177static boolean
3178coff_small_new_section_hook (abfd, section)
3179 bfd *abfd;
3180 asection *section;
3181{
3182 if (! coff_new_section_hook (abfd, section))
3183 return false;
3184
3185 /* We must align to at least a four byte boundary, because longword
3186 accesses must be on a four byte boundary. */
3187 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3188 section->alignment_power = 2;
3189
3190 return true;
3191}
3192
3193/* This is copied from bfd_coff_std_swap_table so that we can change
3194 the default section alignment power. */
3195
3196static const bfd_coff_backend_data bfd_coff_small_swap_table =
3197{
3198 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3199 coff_swap_aux_out, coff_swap_sym_out,
3200 coff_swap_lineno_out, coff_swap_reloc_out,
3201 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3202 coff_swap_scnhdr_out,
692b7d62 3203 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132
RH		 3204#ifdef COFF_LONG_FILENAMES
3205 true,
3206#else
3207 false,
3208#endif
3209#ifdef COFF_LONG_SECTION_NAMES
3210 true,
3211#else
3212 false,
3213#endif
3214 2,
ecefdb58
CP		 3215#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3216 true,
3217#else
3218 false,
3219#endif
3220#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3221 4,
3222#else
3223 2,
3224#endif
252b5132
RH		 3225 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3226 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3227 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3228 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3229 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3230 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3231 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3232 coff_adjust_symndx, coff_link_add_one_symbol,
3233 coff_link_output_has_begun, coff_final_link_postscript
3234};
3235
3236#define coff_small_close_and_cleanup \
3237 coff_close_and_cleanup
3238#define coff_small_bfd_free_cached_info \
3239 coff_bfd_free_cached_info
3240#define coff_small_get_section_contents \
3241 coff_get_section_contents
3242#define coff_small_get_section_contents_in_window \
3243 coff_get_section_contents_in_window
3244
c3c89269
NC		 3245extern const bfd_target shlcoff_small_vec;
3246
252b5132
RH		 3247const bfd_target shcoff_small_vec =
3248{
3249 "coff-sh-small", /* name */
3250 bfd_target_coff_flavour,
3251 BFD_ENDIAN_BIG, /* data byte order is big */
3252 BFD_ENDIAN_BIG, /* header byte order is big */
3253
3254 (HAS_RELOC | EXEC_P | /* object flags */
3255 HAS_LINENO | HAS_DEBUG |
3256 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3257
3258 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3259 '_', /* leading symbol underscore */
3260 '/', /* ar_pad_char */
3261 15, /* ar_max_namelen */
3262 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3263 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3264 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3265 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3266 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3267 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3268
3269 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3270 bfd_generic_archive_p, _bfd_dummy_target},
3271 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3272 bfd_false},
3273 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3274 _bfd_write_archive_contents, bfd_false},
3275
3276 BFD_JUMP_TABLE_GENERIC (coff_small),
3277 BFD_JUMP_TABLE_COPY (coff),
3278 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3279 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3280 BFD_JUMP_TABLE_SYMBOLS (coff),
3281 BFD_JUMP_TABLE_RELOCS (coff),
3282 BFD_JUMP_TABLE_WRITE (coff),
3283 BFD_JUMP_TABLE_LINK (coff),
3284 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3285
c3c89269 3286 & shlcoff_small_vec,
cbfe05c4 3287
252b5132
RH		 3288 (PTR) &bfd_coff_small_swap_table
3289};
3290
3291const bfd_target shlcoff_small_vec =
3292{
3293 "coff-shl-small", /* name */
3294 bfd_target_coff_flavour,
3295 BFD_ENDIAN_LITTLE, /* data byte order is little */
3296 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3297
3298 (HAS_RELOC | EXEC_P | /* object flags */
3299 HAS_LINENO | HAS_DEBUG |
3300 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3301
3302 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3303 '_', /* leading symbol underscore */
3304 '/', /* ar_pad_char */
3305 15, /* ar_max_namelen */
3306 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3307 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3308 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3309 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3310 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3311 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3312
3313 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3314 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3315 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3316 bfd_false},
3317 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3318 _bfd_write_archive_contents, bfd_false},
3319
3320 BFD_JUMP_TABLE_GENERIC (coff_small),
3321 BFD_JUMP_TABLE_COPY (coff),
3322 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3323 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3324 BFD_JUMP_TABLE_SYMBOLS (coff),
3325 BFD_JUMP_TABLE_RELOCS (coff),
3326 BFD_JUMP_TABLE_WRITE (coff),
3327 BFD_JUMP_TABLE_LINK (coff),
3328 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3329
c3c89269 3330 & shcoff_small_vec,
cbfe05c4 3331
252b5132
RH		 3332 (PTR) &bfd_coff_small_swap_table
3333};
17505c5c 3334#endif
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