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Put .dynbss and .rel.bss shortcuts in main elf hash table
[thirdparty/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0
TP		 3569 /* Force return logic to be reviewed for each new architecture. */
3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3571 || arch == TAG_CPU_ARCH_V8M_BASE
3572 || arch == TAG_CPU_ARCH_V8M_MAIN);
3573
2fd158eb
TP		 3574 if (arch == TAG_CPU_ARCH_V6_M
3575 || arch == TAG_CPU_ARCH_V6S_M
3576 || arch == TAG_CPU_ARCH_V7E_M
3577 || arch == TAG_CPU_ARCH_V8M_BASE
3578 || arch == TAG_CPU_ARCH_V8M_MAIN)
3579 return TRUE;
eed94f8f 3580
2fd158eb 3581 return FALSE;
eed94f8f
NC		 3582}
3583
3584/* Determine if we're dealing with a Thumb-2 object. */
3585
3586static bfd_boolean
3587using_thumb2 (struct elf32_arm_link_hash_table *globals)
3588{
60a019a0
TP		 3589 int arch;
3590 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3591 Tag_THUMB_ISA_use);
3592
3593 if (thumb_isa)
3594 return thumb_isa == 2;
3595
3596 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3597
3598 /* Force return logic to be reviewed for each new architecture. */
3599 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3600 || arch == TAG_CPU_ARCH_V8M_BASE
3601 || arch == TAG_CPU_ARCH_V8M_MAIN);
3602
3603 return (arch == TAG_CPU_ARCH_V6T2
3604 || arch == TAG_CPU_ARCH_V7
3605 || arch == TAG_CPU_ARCH_V7E_M
3606 || arch == TAG_CPU_ARCH_V8
3607 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3608}
3609
5e866f5a
TP		 3610/* Determine whether Thumb-2 BL instruction is available. */
3611
3612static bfd_boolean
3613using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3614{
3615 int arch =
3616 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3617
3618 /* Force return logic to be reviewed for each new architecture. */
3619 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3620 || arch == TAG_CPU_ARCH_V8M_BASE
3621 || arch == TAG_CPU_ARCH_V8M_MAIN);
3622
3623 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3624 return (arch == TAG_CPU_ARCH_V6T2
3625 || arch >= TAG_CPU_ARCH_V7);
3626}
3627
00a97672
RS		 3628/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3629 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3630 hash table. */
3631
3632static bfd_boolean
57e8b36a 3633elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3634{
3635 struct elf32_arm_link_hash_table *htab;
3636
3637 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3638 if (htab == NULL)
3639 return FALSE;
3640
362d30a1 3641 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3642 return FALSE;
3643
3644 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3645 return FALSE;
3646
00a97672
RS		 3647 if (htab->vxworks_p)
3648 {
3649 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3650 return FALSE;
3651
0e1862bb 3652 if (bfd_link_pic (info))
00a97672
RS		 3653 {
3654 htab->plt_header_size = 0;
3655 htab->plt_entry_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3657 }
3658 else
3659 {
3660 htab->plt_header_size
3661 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3662 htab->plt_entry_size
3663 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3664 }
aebf9be7
NC		 3665
3666 if (elf_elfheader (dynobj))
3667 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3668 }
eed94f8f
NC		 3669 else
3670 {
3671 /* PR ld/16017
3672 Test for thumb only architectures. Note - we cannot just call
3673 using_thumb_only() as the attributes in the output bfd have not been
3674 initialised at this point, so instead we use the input bfd. */
3675 bfd * saved_obfd = htab->obfd;
3676
3677 htab->obfd = dynobj;
3678 if (using_thumb_only (htab))
3679 {
3680 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3681 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3682 }
3683 htab->obfd = saved_obfd;
3684 }
5e681ec4 3685
362d30a1
RS		 3686 if (!htab->root.splt
3687 || !htab->root.srelplt
9d19e4fd
AM		 3688 || !htab->root.sdynbss
3689 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3690 abort ();
3691
3692 return TRUE;
3693}
3694
906e58ca
NC		 3695/* Copy the extra info we tack onto an elf_link_hash_entry. */
3696
3697static void
3698elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3699 struct elf_link_hash_entry *dir,
3700 struct elf_link_hash_entry *ind)
3701{
3702 struct elf32_arm_link_hash_entry *edir, *eind;
3703
3704 edir = (struct elf32_arm_link_hash_entry *) dir;
3705 eind = (struct elf32_arm_link_hash_entry *) ind;
3706
0bdcacaf 3707 if (eind->dyn_relocs != NULL)
906e58ca 3708 {
0bdcacaf 3709 if (edir->dyn_relocs != NULL)
906e58ca 3710 {
0bdcacaf
RS		 3711 struct elf_dyn_relocs **pp;
3712 struct elf_dyn_relocs *p;
906e58ca
NC		 3713
3714 /* Add reloc counts against the indirect sym to the direct sym
3715 list. Merge any entries against the same section. */
0bdcacaf 3716 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3717 {
0bdcacaf 3718 struct elf_dyn_relocs *q;
906e58ca 3719
0bdcacaf
RS		 3720 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3721 if (q->sec == p->sec)
906e58ca
NC		 3722 {
3723 q->pc_count += p->pc_count;
3724 q->count += p->count;
3725 *pp = p->next;
3726 break;
3727 }
3728 if (q == NULL)
3729 pp = &p->next;
3730 }
0bdcacaf 3731 *pp = edir->dyn_relocs;
906e58ca
NC		 3732 }
3733
0bdcacaf
RS		 3734 edir->dyn_relocs = eind->dyn_relocs;
3735 eind->dyn_relocs = NULL;
906e58ca
NC		 3736 }
3737
3738 if (ind->root.type == bfd_link_hash_indirect)
3739 {
3740 /* Copy over PLT info. */
34e77a92
RS		 3741 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3742 eind->plt.thumb_refcount = 0;
3743 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3744 eind->plt.maybe_thumb_refcount = 0;
3745 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3746 eind->plt.noncall_refcount = 0;
3747
3748 /* We should only allocate a function to .iplt once the final
3749 symbol information is known. */
3750 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3751
3752 if (dir->got.refcount <= 0)
3753 {
3754 edir->tls_type = eind->tls_type;
3755 eind->tls_type = GOT_UNKNOWN;
3756 }
3757 }
3758
3759 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3760}
3761
68faa637
AM		 3762/* Destroy an ARM elf linker hash table. */
3763
3764static void
d495ab0d 3765elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3766{
3767 struct elf32_arm_link_hash_table *ret
d495ab0d 3768 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3769
3770 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3771 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3772}
3773
906e58ca
NC		 3774/* Create an ARM elf linker hash table. */
3775
3776static struct bfd_link_hash_table *
3777elf32_arm_link_hash_table_create (bfd *abfd)
3778{
3779 struct elf32_arm_link_hash_table *ret;
3780 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3781
7bf52ea2 3782 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3783 if (ret == NULL)
3784 return NULL;
3785
3786 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3787 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3788 sizeof (struct elf32_arm_link_hash_entry),
3789 ARM_ELF_DATA))
906e58ca
NC		 3790 {
3791 free (ret);
3792 return NULL;
3793 }
3794
906e58ca 3795 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3796 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3797#ifdef FOUR_WORD_PLT
3798 ret->plt_header_size = 16;
3799 ret->plt_entry_size = 16;
3800#else
3801 ret->plt_header_size = 20;
1db37fe6 3802 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3803#endif
906e58ca 3804 ret->use_rel = 1;
906e58ca 3805 ret->obfd = abfd;
906e58ca
NC		 3806
3807 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3808 sizeof (struct elf32_arm_stub_hash_entry)))
3809 {
d495ab0d 3810 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3811 return NULL;
3812 }
d495ab0d 3813 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3814
3815 return &ret->root.root;
3816}
3817
cd1dac3d
DG		 3818/* Determine what kind of NOPs are available. */
3819
3820static bfd_boolean
3821arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3822{
3823 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3824 Tag_CPU_arch);
cd1dac3d 3825
60a019a0
TP		 3826 /* Force return logic to be reviewed for each new architecture. */
3827 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8M_BASE
3829 || arch == TAG_CPU_ARCH_V8M_MAIN);
3830
3831 return (arch == TAG_CPU_ARCH_V6T2
3832 || arch == TAG_CPU_ARCH_V6K
3833 || arch == TAG_CPU_ARCH_V7
3834 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3835}
3836
f4ac8484
DJ		 3837static bfd_boolean
3838arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3839{
3840 switch (stub_type)
3841 {
fea2b4d6 3842 case arm_stub_long_branch_thumb_only:
80c135e5 3843 case arm_stub_long_branch_thumb2_only:
d5a67c02 3844 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3845 case arm_stub_long_branch_v4t_thumb_arm:
3846 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3847 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3848 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3849 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3850 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3851 return TRUE;
3852 case arm_stub_none:
3853 BFD_FAIL ();
3854 return FALSE;
3855 break;
3856 default:
3857 return FALSE;
3858 }
3859}
3860
906e58ca
NC		 3861/* Determine the type of stub needed, if any, for a call. */
3862
3863static enum elf32_arm_stub_type
3864arm_type_of_stub (struct bfd_link_info *info,
3865 asection *input_sec,
3866 const Elf_Internal_Rela *rel,
34e77a92 3867 unsigned char st_type,
35fc36a8 3868 enum arm_st_branch_type *actual_branch_type,
906e58ca 3869 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3870 bfd_vma destination,
3871 asection *sym_sec,
3872 bfd *input_bfd,
3873 const char *name)
906e58ca
NC		 3874{
3875 bfd_vma location;
3876 bfd_signed_vma branch_offset;
3877 unsigned int r_type;
3878 struct elf32_arm_link_hash_table * globals;
5e866f5a 3879 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3880 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3881 int use_plt = 0;
35fc36a8 3882 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3883 union gotplt_union *root_plt;
3884 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3885 int arch;
3886 int thumb2_movw;
906e58ca 3887
35fc36a8 3888 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3889 return stub_type;
3890
906e58ca 3891 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3892 if (globals == NULL)
3893 return stub_type;
906e58ca
NC		 3894
3895 thumb_only = using_thumb_only (globals);
906e58ca 3896 thumb2 = using_thumb2 (globals);
5e866f5a 3897 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3898
d5a67c02
AV		 3899 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3900
3901 /* True for architectures that implement the thumb2 movw instruction. */
3902 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3903
906e58ca
NC		 3904 /* Determine where the call point is. */
3905 location = (input_sec->output_offset
3906 + input_sec->output_section->vma
3907 + rel->r_offset);
3908
906e58ca
NC		 3909 r_type = ELF32_R_TYPE (rel->r_info);
3910
39f21624
NC		 3911 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3912 are considering a function call relocation. */
c5423981
TG		 3913 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3914 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3915 && branch_type == ST_BRANCH_TO_ARM)
3916 branch_type = ST_BRANCH_TO_THUMB;
3917
34e77a92
RS		 3918 /* For TLS call relocs, it is the caller's responsibility to provide
3919 the address of the appropriate trampoline. */
3920 if (r_type != R_ARM_TLS_CALL
3921 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3922 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3923 ELF32_R_SYM (rel->r_info), &root_plt,
3924 &arm_plt)
34e77a92 3925 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3926 {
34e77a92 3927 asection *splt;
fe33d2fa 3928
34e77a92
RS		 3929 if (hash == NULL || hash->is_iplt)
3930 splt = globals->root.iplt;
3931 else
3932 splt = globals->root.splt;
3933 if (splt != NULL)
b38cadfb 3934 {
34e77a92
RS		 3935 use_plt = 1;
3936
3937 /* Note when dealing with PLT entries: the main PLT stub is in
3938 ARM mode, so if the branch is in Thumb mode, another
3939 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3940 PLT stub. If a long branch stub is needed, we'll add a
3941 Thumb->Arm one and branch directly to the ARM PLT entry.
3942 Here, we have to check if a pre-PLT Thumb->ARM stub
3943 is needed and if it will be close enough. */
34e77a92
RS		 3944
3945 destination = (splt->output_section->vma
3946 + splt->output_offset
3947 + root_plt->offset);
3948 st_type = STT_FUNC;
2df2751d
CL		 3949
3950 /* Thumb branch/call to PLT: it can become a branch to ARM
3951 or to Thumb. We must perform the same checks and
3952 corrections as in elf32_arm_final_link_relocate. */
3953 if ((r_type == R_ARM_THM_CALL)
3954 || (r_type == R_ARM_THM_JUMP24))
3955 {
3956 if (globals->use_blx
3957 && r_type == R_ARM_THM_CALL
3958 && !thumb_only)
3959 {
3960 /* If the Thumb BLX instruction is available, convert
3961 the BL to a BLX instruction to call the ARM-mode
3962 PLT entry. */
3963 branch_type = ST_BRANCH_TO_ARM;
3964 }
3965 else
3966 {
3967 if (!thumb_only)
3968 /* Target the Thumb stub before the ARM PLT entry. */
3969 destination -= PLT_THUMB_STUB_SIZE;
3970 branch_type = ST_BRANCH_TO_THUMB;
3971 }
3972 }
3973 else
3974 {
3975 branch_type = ST_BRANCH_TO_ARM;
3976 }
34e77a92 3977 }
5fa9e92f 3978 }
34e77a92
RS		 3979 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3980 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3981
fe33d2fa
CL		 3982 branch_offset = (bfd_signed_vma)(destination - location);
3983
0855e32b 3984 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3985 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3986 {
5fa9e92f
CL		 3987 /* Handle cases where:
3988 - this call goes too far (different Thumb/Thumb2 max
99059e56 3989 distance)
155d87d7 3990 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3991 Thumb->Arm branch (not bl). A stub is needed in this case,
3992 but only if this call is not through a PLT entry. Indeed,
695344c0 3993 PLT stubs handle mode switching already. */
5e866f5a 3994 if ((!thumb2_bl
906e58ca
NC		 3995 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3996 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3997 || (thumb2_bl
906e58ca
NC		 3998 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3999 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4000 || (thumb2
4001 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4002 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4003 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4004 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4005 && (((r_type == R_ARM_THM_CALL
4006 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4007 || (r_type == R_ARM_THM_JUMP24)
4008 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4009 && !use_plt))
906e58ca 4010 {
2df2751d
CL		 4011 /* If we need to insert a Thumb-Thumb long branch stub to a
4012 PLT, use one that branches directly to the ARM PLT
4013 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4014 stub, undo this now. */
695344c0
NC		 4015 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4016 {
4017 branch_type = ST_BRANCH_TO_ARM;
4018 branch_offset += PLT_THUMB_STUB_SIZE;
4019 }
2df2751d 4020
35fc36a8 4021 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4022 {
4023 /* Thumb to thumb. */
4024 if (!thumb_only)
4025 {
d5a67c02 4026 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4027 _bfd_error_handler (_("\
4028%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4029attribute is only supported for M-profile targets that implement the movw instruction."),
4030 input_sec);
d5a67c02 4031
0e1862bb 4032 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4033 /* PIC stubs. */
155d87d7 4034 ? ((globals->use_blx
9553db3c 4035 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4036 /* V5T and above. Stub starts with ARM code, so
4037 we must be able to switch mode before
4038 reaching it, which is only possible for 'bl'
4039 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4040 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4041 /* On V4T, use Thumb code only. */
d3626fb0 4042 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4043
4044 /* non-PIC stubs. */
155d87d7 4045 : ((globals->use_blx
9553db3c 4046 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4047 /* V5T and above. */
4048 ? arm_stub_long_branch_any_any
4049 /* V4T. */
d3626fb0 4050 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4051 }
4052 else
4053 {
d5a67c02
AV		 4054 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4055 stub_type = arm_stub_long_branch_thumb2_only_pure;
4056 else
4057 {
4058 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4059 _bfd_error_handler (_("\
4060%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4061attribute is only supported for M-profile targets that implement the movw instruction."),
4062 input_sec);
d5a67c02
AV		 4063
4064 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4065 /* PIC stub. */
4066 ? arm_stub_long_branch_thumb_only_pic
4067 /* non-PIC stub. */
4068 : (thumb2 ? arm_stub_long_branch_thumb2_only
4069 : arm_stub_long_branch_thumb_only);
4070 }
906e58ca
NC		 4071 }
4072 }
4073 else
4074 {
d5a67c02 4075 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4076 _bfd_error_handler (_("%B(%s): warning: long branch "
4077 " veneers used in section with "
4078 "SHF_ARM_PURECODE section "
4079 "attribute is only supported"
4080 " for M-profile targets that "
4081 "implement the movw "
4082 "instruction."));
d5a67c02 4083
906e58ca 4084 /* Thumb to arm. */
c820be07
NC		 4085 if (sym_sec != NULL
4086 && sym_sec->owner != NULL
4087 && !INTERWORK_FLAG (sym_sec->owner))
4088 {
4eca0228 4089 _bfd_error_handler
c820be07
NC		 4090 (_("%B(%s): warning: interworking not enabled.\n"
4091 " first occurrence: %B: Thumb call to ARM"),
4092 sym_sec->owner, input_bfd, name);
4093 }
4094
0855e32b 4095 stub_type =
0e1862bb 4096 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4097 /* PIC stubs. */
0855e32b 4098 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4099 /* TLS PIC stubs. */
0855e32b
NS		 4100 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4101 : arm_stub_long_branch_v4t_thumb_tls_pic)
4102 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4103 /* V5T PIC and above. */
4104 ? arm_stub_long_branch_any_arm_pic
4105 /* V4T PIC stub. */
4106 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4107
4108 /* non-PIC stubs. */
0855e32b 4109 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4110 /* V5T and above. */
4111 ? arm_stub_long_branch_any_any
4112 /* V4T. */
4113 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4114
4115 /* Handle v4t short branches. */
fea2b4d6 4116 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4117 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4118 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4119 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4120 }
4121 }
4122 }
fe33d2fa
CL		 4123 else if (r_type == R_ARM_CALL
4124 || r_type == R_ARM_JUMP24
0855e32b
NS		 4125 || r_type == R_ARM_PLT32
4126 || r_type == R_ARM_TLS_CALL)
906e58ca 4127 {
d5a67c02 4128 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4129 _bfd_error_handler (_("%B(%s): warning: long branch "
4130 " veneers used in section with "
4131 "SHF_ARM_PURECODE section "
4132 "attribute is only supported"
4133 " for M-profile targets that "
4134 "implement the movw "
4135 "instruction."));
35fc36a8 4136 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4137 {
4138 /* Arm to thumb. */
c820be07
NC		 4139
4140 if (sym_sec != NULL
4141 && sym_sec->owner != NULL
4142 && !INTERWORK_FLAG (sym_sec->owner))
4143 {
4eca0228 4144 _bfd_error_handler
c820be07 4145 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4146 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4147 sym_sec->owner, input_bfd, name);
4148 }
4149
4150 /* We have an extra 2-bytes reach because of
4151 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4152 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4153 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4154 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4155 || (r_type == R_ARM_JUMP24)
4156 || (r_type == R_ARM_PLT32))
906e58ca 4157 {
0e1862bb 4158 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4159 /* PIC stubs. */
ebe24dd4
CL		 4160 ? ((globals->use_blx)
4161 /* V5T and above. */
4162 ? arm_stub_long_branch_any_thumb_pic
4163 /* V4T stub. */
4164 : arm_stub_long_branch_v4t_arm_thumb_pic)
4165
c2b4a39d
CL		 4166 /* non-PIC stubs. */
4167 : ((globals->use_blx)
4168 /* V5T and above. */
4169 ? arm_stub_long_branch_any_any
4170 /* V4T. */
4171 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4172 }
4173 }
4174 else
4175 {
4176 /* Arm to arm. */
4177 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4178 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4179 {
0855e32b 4180 stub_type =
0e1862bb 4181 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4182 /* PIC stubs. */
0855e32b 4183 ? (r_type == R_ARM_TLS_CALL
6a631e86 4184 /* TLS PIC Stub. */
0855e32b 4185 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4186 : (globals->nacl_p
4187 ? arm_stub_long_branch_arm_nacl_pic
4188 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4189 /* non-PIC stubs. */
7a89b94e
NC		 4190 : (globals->nacl_p
4191 ? arm_stub_long_branch_arm_nacl
4192 : arm_stub_long_branch_any_any);
906e58ca
NC		 4193 }
4194 }
4195 }
4196
fe33d2fa
CL		 4197 /* If a stub is needed, record the actual destination type. */
4198 if (stub_type != arm_stub_none)
35fc36a8 4199 *actual_branch_type = branch_type;
fe33d2fa 4200
906e58ca
NC		 4201 return stub_type;
4202}
4203
4204/* Build a name for an entry in the stub hash table. */
4205
4206static char *
4207elf32_arm_stub_name (const asection *input_section,
4208 const asection *sym_sec,
4209 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4210 const Elf_Internal_Rela *rel,
4211 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4212{
4213 char *stub_name;
4214 bfd_size_type len;
4215
4216 if (hash)
4217 {
fe33d2fa 4218 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4219 stub_name = (char *) bfd_malloc (len);
906e58ca 4220 if (stub_name != NULL)
fe33d2fa 4221 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4222 input_section->id & 0xffffffff,
4223 hash->root.root.root.string,
fe33d2fa
CL		 4224 (int) rel->r_addend & 0xffffffff,
4225 (int) stub_type);
906e58ca
NC		 4226 }
4227 else
4228 {
fe33d2fa 4229 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4230 stub_name = (char *) bfd_malloc (len);
906e58ca 4231 if (stub_name != NULL)
fe33d2fa 4232 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4233 input_section->id & 0xffffffff,
4234 sym_sec->id & 0xffffffff,
0855e32b
NS		 4235 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4236 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4237 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4238 (int) rel->r_addend & 0xffffffff,
4239 (int) stub_type);
906e58ca
NC		 4240 }
4241
4242 return stub_name;
4243}
4244
4245/* Look up an entry in the stub hash. Stub entries are cached because
4246 creating the stub name takes a bit of time. */
4247
4248static struct elf32_arm_stub_hash_entry *
4249elf32_arm_get_stub_entry (const asection *input_section,
4250 const asection *sym_sec,
4251 struct elf_link_hash_entry *hash,
4252 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4253 struct elf32_arm_link_hash_table *htab,
4254 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4255{
4256 struct elf32_arm_stub_hash_entry *stub_entry;
4257 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4258 const asection *id_sec;
4259
4260 if ((input_section->flags & SEC_CODE) == 0)
4261 return NULL;
4262
4263 /* If this input section is part of a group of sections sharing one
4264 stub section, then use the id of the first section in the group.
4265 Stub names need to include a section id, as there may well be
4266 more than one stub used to reach say, printf, and we need to
4267 distinguish between them. */
c2abbbeb 4268 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4269 id_sec = htab->stub_group[input_section->id].link_sec;
4270
4271 if (h != NULL && h->stub_cache != NULL
4272 && h->stub_cache->h == h
fe33d2fa
CL		 4273 && h->stub_cache->id_sec == id_sec
4274 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4275 {
4276 stub_entry = h->stub_cache;
4277 }
4278 else
4279 {
4280 char *stub_name;
4281
fe33d2fa 4282 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4283 if (stub_name == NULL)
4284 return NULL;
4285
4286 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4287 stub_name, FALSE, FALSE);
4288 if (h != NULL)
4289 h->stub_cache = stub_entry;
4290
4291 free (stub_name);
4292 }
4293
4294 return stub_entry;
4295}
4296
daa4adae
TP		 4297/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4298 section. */
4299
4300static bfd_boolean
4301arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4302{
4303 if (stub_type >= max_stub_type)
4304 abort (); /* Should be unreachable. */
4305
4ba2ef8f
TP		 4306 switch (stub_type)
4307 {
4308 case arm_stub_cmse_branch_thumb_only:
4309 return TRUE;
4310
4311 default:
4312 return FALSE;
4313 }
4314
4315 abort (); /* Should be unreachable. */
daa4adae
TP		 4316}
4317
4318/* Required alignment (as a power of 2) for the dedicated section holding
4319 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4320 with input sections. */
4321
4322static int
4323arm_dedicated_stub_output_section_required_alignment
4324 (enum elf32_arm_stub_type stub_type)
4325{
4326 if (stub_type >= max_stub_type)
4327 abort (); /* Should be unreachable. */
4328
4ba2ef8f
TP		 4329 switch (stub_type)
4330 {
4331 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4332 boundary. */
4333 case arm_stub_cmse_branch_thumb_only:
4334 return 5;
4335
4336 default:
4337 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4338 return 0;
4339 }
4340
4341 abort (); /* Should be unreachable. */
daa4adae
TP		 4342}
4343
4344/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4345 NULL if veneers of this type are interspersed with input sections. */
4346
4347static const char *
4348arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4349{
4350 if (stub_type >= max_stub_type)
4351 abort (); /* Should be unreachable. */
4352
4ba2ef8f
TP		 4353 switch (stub_type)
4354 {
4355 case arm_stub_cmse_branch_thumb_only:
4356 return ".gnu.sgstubs";
4357
4358 default:
4359 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4360 return NULL;
4361 }
4362
4363 abort (); /* Should be unreachable. */
daa4adae
TP		 4364}
4365
4366/* If veneers of type STUB_TYPE should go in a dedicated output section,
4367 returns the address of the hash table field in HTAB holding a pointer to the
4368 corresponding input section. Otherwise, returns NULL. */
4369
4370static asection **
4ba2ef8f
TP		 4371arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4372 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4373{
4374 if (stub_type >= max_stub_type)
4375 abort (); /* Should be unreachable. */
4376
4ba2ef8f
TP		 4377 switch (stub_type)
4378 {
4379 case arm_stub_cmse_branch_thumb_only:
4380 return &htab->cmse_stub_sec;
4381
4382 default:
4383 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4384 return NULL;
4385 }
4386
4387 abort (); /* Should be unreachable. */
daa4adae
TP		 4388}
4389
4390/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4391 is the section that branch into veneer and can be NULL if stub should go in
4392 a dedicated output section. Returns a pointer to the stub section, and the
4393 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4394 LINK_SEC_P may be NULL. */
906e58ca 4395
48229727
JB		 4396static asection *
4397elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4398 struct elf32_arm_link_hash_table *htab,
4399 enum elf32_arm_stub_type stub_type)
906e58ca 4400{
daa4adae
TP		 4401 asection *link_sec, *out_sec, **stub_sec_p;
4402 const char *stub_sec_prefix;
4403 bfd_boolean dedicated_output_section =
4404 arm_dedicated_stub_output_section_required (stub_type);
4405 int align;
906e58ca 4406
daa4adae 4407 if (dedicated_output_section)
906e58ca 4408 {
daa4adae
TP		 4409 bfd *output_bfd = htab->obfd;
4410 const char *out_sec_name =
4411 arm_dedicated_stub_output_section_name (stub_type);
4412 link_sec = NULL;
4413 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4414 stub_sec_prefix = out_sec_name;
4415 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4416 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4417 if (out_sec == NULL)
906e58ca 4418 {
4eca0228
AM		 4419 _bfd_error_handler (_("No address assigned to the veneers output "
4420 "section %s"), out_sec_name);
daa4adae 4421 return NULL;
906e58ca 4422 }
daa4adae
TP		 4423 }
4424 else
4425 {
c2abbbeb 4426 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4427 link_sec = htab->stub_group[section->id].link_sec;
4428 BFD_ASSERT (link_sec != NULL);
4429 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4430 if (*stub_sec_p == NULL)
4431 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4432 stub_sec_prefix = link_sec->name;
4433 out_sec = link_sec->output_section;
4434 align = htab->nacl_p ? 4 : 3;
906e58ca 4435 }
b38cadfb 4436
daa4adae
TP		 4437 if (*stub_sec_p == NULL)
4438 {
4439 size_t namelen;
4440 bfd_size_type len;
4441 char *s_name;
4442
4443 namelen = strlen (stub_sec_prefix);
4444 len = namelen + sizeof (STUB_SUFFIX);
4445 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4446 if (s_name == NULL)
4447 return NULL;
4448
4449 memcpy (s_name, stub_sec_prefix, namelen);
4450 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4451 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4452 align);
4453 if (*stub_sec_p == NULL)
4454 return NULL;
4455
4456 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4457 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4458 | SEC_KEEP;
4459 }
4460
4461 if (!dedicated_output_section)
4462 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4463
48229727
JB		 4464 if (link_sec_p)
4465 *link_sec_p = link_sec;
b38cadfb 4466
daa4adae 4467 return *stub_sec_p;
48229727
JB		 4468}
4469
4470/* Add a new stub entry to the stub hash. Not all fields of the new
4471 stub entry are initialised. */
4472
4473static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4474elf32_arm_add_stub (const char *stub_name, asection *section,
4475 struct elf32_arm_link_hash_table *htab,
4476 enum elf32_arm_stub_type stub_type)
48229727
JB		 4477{
4478 asection *link_sec;
4479 asection *stub_sec;
4480 struct elf32_arm_stub_hash_entry *stub_entry;
4481
daa4adae
TP		 4482 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4483 stub_type);
48229727
JB		 4484 if (stub_sec == NULL)
4485 return NULL;
906e58ca
NC		 4486
4487 /* Enter this entry into the linker stub hash table. */
4488 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4489 TRUE, FALSE);
4490 if (stub_entry == NULL)
4491 {
6bde4c52
TP		 4492 if (section == NULL)
4493 section = stub_sec;
4eca0228
AM		 4494 _bfd_error_handler (_("%s: cannot create stub entry %s"),
4495 section->owner, stub_name);
906e58ca
NC		 4496 return NULL;
4497 }
4498
4499 stub_entry->stub_sec = stub_sec;
0955507f 4500 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4501 stub_entry->id_sec = link_sec;
4502
906e58ca
NC		 4503 return stub_entry;
4504}
4505
4506/* Store an Arm insn into an output section not processed by
4507 elf32_arm_write_section. */
4508
4509static void
8029a119
NC		 4510put_arm_insn (struct elf32_arm_link_hash_table * htab,
4511 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4512{
4513 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4514 bfd_putl32 (val, ptr);
4515 else
4516 bfd_putb32 (val, ptr);
4517}
4518
4519/* Store a 16-bit Thumb insn into an output section not processed by
4520 elf32_arm_write_section. */
4521
4522static void
8029a119
NC		 4523put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4524 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4525{
4526 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4527 bfd_putl16 (val, ptr);
4528 else
4529 bfd_putb16 (val, ptr);
4530}
4531
a504d23a
LA		 4532/* Store a Thumb2 insn into an output section not processed by
4533 elf32_arm_write_section. */
4534
4535static void
4536put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4537 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4538{
4539 /* T2 instructions are 16-bit streamed. */
4540 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4541 {
4542 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4543 bfd_putl16 ((val & 0xffff), ptr + 2);
4544 }
4545 else
4546 {
4547 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4548 bfd_putb16 ((val & 0xffff), ptr + 2);
4549 }
4550}
4551
0855e32b
NS		 4552/* If it's possible to change R_TYPE to a more efficient access
4553 model, return the new reloc type. */
4554
4555static unsigned
b38cadfb 4556elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4557 struct elf_link_hash_entry *h)
4558{
4559 int is_local = (h == NULL);
4560
0e1862bb
L		 4561 if (bfd_link_pic (info)
4562 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4563 return r_type;
4564
b38cadfb 4565 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4566 switch (r_type)
4567 {
4568 case R_ARM_TLS_GOTDESC:
4569 case R_ARM_TLS_CALL:
4570 case R_ARM_THM_TLS_CALL:
4571 case R_ARM_TLS_DESCSEQ:
4572 case R_ARM_THM_TLS_DESCSEQ:
4573 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4574 }
4575
4576 return r_type;
4577}
4578
48229727
JB		 4579static bfd_reloc_status_type elf32_arm_final_link_relocate
4580 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4581 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4582 const char *, unsigned char, enum arm_st_branch_type,
4583 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4584
4563a860
JB		 4585static unsigned int
4586arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4587{
4588 switch (stub_type)
4589 {
4590 case arm_stub_a8_veneer_b_cond:
4591 case arm_stub_a8_veneer_b:
4592 case arm_stub_a8_veneer_bl:
4593 return 2;
4594
4595 case arm_stub_long_branch_any_any:
4596 case arm_stub_long_branch_v4t_arm_thumb:
4597 case arm_stub_long_branch_thumb_only:
80c135e5 4598 case arm_stub_long_branch_thumb2_only:
d5a67c02 4599 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4600 case arm_stub_long_branch_v4t_thumb_thumb:
4601 case arm_stub_long_branch_v4t_thumb_arm:
4602 case arm_stub_short_branch_v4t_thumb_arm:
4603 case arm_stub_long_branch_any_arm_pic:
4604 case arm_stub_long_branch_any_thumb_pic:
4605 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4606 case arm_stub_long_branch_v4t_arm_thumb_pic:
4607 case arm_stub_long_branch_v4t_thumb_arm_pic:
4608 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4609 case arm_stub_long_branch_any_tls_pic:
4610 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4611 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4612 case arm_stub_a8_veneer_blx:
4613 return 4;
b38cadfb 4614
7a89b94e
NC		 4615 case arm_stub_long_branch_arm_nacl:
4616 case arm_stub_long_branch_arm_nacl_pic:
4617 return 16;
4618
4563a860
JB		 4619 default:
4620 abort (); /* Should be unreachable. */
4621 }
4622}
4623
4f4faa4d
TP		 4624/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4625 veneering (TRUE) or have their own symbol (FALSE). */
4626
4627static bfd_boolean
4628arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4629{
4630 if (stub_type >= max_stub_type)
4631 abort (); /* Should be unreachable. */
4632
4ba2ef8f
TP		 4633 switch (stub_type)
4634 {
4635 case arm_stub_cmse_branch_thumb_only:
4636 return TRUE;
4637
4638 default:
4639 return FALSE;
4640 }
4641
4642 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4643}
4644
d7c5bd02
TP		 4645/* Returns the padding needed for the dedicated section used stubs of type
4646 STUB_TYPE. */
4647
4648static int
4649arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4650{
4651 if (stub_type >= max_stub_type)
4652 abort (); /* Should be unreachable. */
4653
4ba2ef8f
TP		 4654 switch (stub_type)
4655 {
4656 case arm_stub_cmse_branch_thumb_only:
4657 return 32;
4658
4659 default:
4660 return 0;
4661 }
4662
4663 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4664}
4665
0955507f
TP		 4666/* If veneers of type STUB_TYPE should go in a dedicated output section,
4667 returns the address of the hash table field in HTAB holding the offset at
4668 which new veneers should be layed out in the stub section. */
4669
4670static bfd_vma*
4671arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4672 enum elf32_arm_stub_type stub_type)
4673{
4674 switch (stub_type)
4675 {
4676 case arm_stub_cmse_branch_thumb_only:
4677 return &htab->new_cmse_stub_offset;
4678
4679 default:
4680 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4681 return NULL;
4682 }
4683}
4684
906e58ca
NC		 4685static bfd_boolean
4686arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4687 void * in_arg)
4688{
7a89b94e 4689#define MAXRELOCS 3
0955507f 4690 bfd_boolean removed_sg_veneer;
906e58ca 4691 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4692 struct elf32_arm_link_hash_table *globals;
906e58ca 4693 struct bfd_link_info *info;
906e58ca
NC		 4694 asection *stub_sec;
4695 bfd *stub_bfd;
906e58ca
NC		 4696 bfd_byte *loc;
4697 bfd_vma sym_value;
4698 int template_size;
4699 int size;
d3ce72d0 4700 const insn_sequence *template_sequence;
906e58ca 4701 int i;
48229727
JB		 4702 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4703 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4704 int nrelocs = 0;
0955507f 4705 int just_allocated = 0;
906e58ca
NC		 4706
4707 /* Massage our args to the form they really have. */
4708 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4709 info = (struct bfd_link_info *) in_arg;
4710
4711 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4712 if (globals == NULL)
4713 return FALSE;
906e58ca 4714
906e58ca
NC		 4715 stub_sec = stub_entry->stub_sec;
4716
4dfe6ac6 4717 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4718 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4719 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4720 return TRUE;
fe33d2fa 4721
0955507f
TP		 4722 /* Assign a slot at the end of section if none assigned yet. */
4723 if (stub_entry->stub_offset == (bfd_vma) -1)
4724 {
4725 stub_entry->stub_offset = stub_sec->size;
4726 just_allocated = 1;
4727 }
906e58ca
NC		 4728 loc = stub_sec->contents + stub_entry->stub_offset;
4729
4730 stub_bfd = stub_sec->owner;
4731
906e58ca
NC		 4732 /* This is the address of the stub destination. */
4733 sym_value = (stub_entry->target_value
4734 + stub_entry->target_section->output_offset
4735 + stub_entry->target_section->output_section->vma);
4736
d3ce72d0 4737 template_sequence = stub_entry->stub_template;
461a49ca 4738 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4739
4740 size = 0;
461a49ca 4741 for (i = 0; i < template_size; i++)
906e58ca 4742 {
d3ce72d0 4743 switch (template_sequence[i].type)
461a49ca
DJ		 4744 {
4745 case THUMB16_TYPE:
48229727 4746 {
d3ce72d0
NC		 4747 bfd_vma data = (bfd_vma) template_sequence[i].data;
4748 if (template_sequence[i].reloc_addend != 0)
48229727 4749 {
99059e56
RM		 4750 /* We've borrowed the reloc_addend field to mean we should
4751 insert a condition code into this (Thumb-1 branch)
4752 instruction. See THUMB16_BCOND_INSN. */
4753 BFD_ASSERT ((data & 0xff00) == 0xd000);
4754 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4755 }
fe33d2fa 4756 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4757 size += 2;
4758 }
461a49ca 4759 break;
906e58ca 4760
48229727 4761 case THUMB32_TYPE:
fe33d2fa
CL		 4762 bfd_put_16 (stub_bfd,
4763 (template_sequence[i].data >> 16) & 0xffff,
4764 loc + size);
4765 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4766 loc + size + 2);
99059e56
RM		 4767 if (template_sequence[i].r_type != R_ARM_NONE)
4768 {
4769 stub_reloc_idx[nrelocs] = i;
4770 stub_reloc_offset[nrelocs++] = size;
4771 }
4772 size += 4;
4773 break;
48229727 4774
461a49ca 4775 case ARM_TYPE:
fe33d2fa
CL		 4776 bfd_put_32 (stub_bfd, template_sequence[i].data,
4777 loc + size);
461a49ca
DJ		 4778 /* Handle cases where the target is encoded within the
4779 instruction. */
d3ce72d0 4780 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4781 {
48229727
JB		 4782 stub_reloc_idx[nrelocs] = i;
4783 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4784 }
4785 size += 4;
4786 break;
4787
4788 case DATA_TYPE:
d3ce72d0 4789 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4790 stub_reloc_idx[nrelocs] = i;
4791 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4792 size += 4;
4793 break;
4794
4795 default:
4796 BFD_FAIL ();
4797 return FALSE;
4798 }
906e58ca 4799 }
461a49ca 4800
0955507f
TP		 4801 if (just_allocated)
4802 stub_sec->size += size;
906e58ca 4803
461a49ca
DJ		 4804 /* Stub size has already been computed in arm_size_one_stub. Check
4805 consistency. */
4806 BFD_ASSERT (size == stub_entry->stub_size);
4807
906e58ca 4808 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4809 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4810 sym_value |= 1;
4811
0955507f
TP		 4812 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4813 to relocate in each stub. */
4814 removed_sg_veneer =
4815 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4816 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4817
48229727 4818 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4819 {
4820 Elf_Internal_Rela rel;
4821 bfd_boolean unresolved_reloc;
4822 char *error_message;
4823 bfd_vma points_to =
4824 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4825
4826 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4827 rel.r_info = ELF32_R_INFO (0,
4828 template_sequence[stub_reloc_idx[i]].r_type);
4829 rel.r_addend = 0;
4830
4831 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4832 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4833 template should refer back to the instruction after the original
4834 branch. We use target_section as Cortex-A8 erratum workaround stubs
4835 are only generated when both source and target are in the same
4836 section. */
4837 points_to = stub_entry->target_section->output_section->vma
4838 + stub_entry->target_section->output_offset
4839 + stub_entry->source_value;
4840
4841 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4842 (template_sequence[stub_reloc_idx[i]].r_type),
4843 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4844 points_to, info, stub_entry->target_section, "", STT_FUNC,
4845 stub_entry->branch_type,
4846 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4847 &error_message);
4848 }
906e58ca
NC		 4849
4850 return TRUE;
48229727 4851#undef MAXRELOCS
906e58ca
NC		 4852}
4853
48229727
JB		 4854/* Calculate the template, template size and instruction size for a stub.
4855 Return value is the instruction size. */
906e58ca 4856
48229727
JB		 4857static unsigned int
4858find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4859 const insn_sequence **stub_template,
4860 int *stub_template_size)
906e58ca 4861{
d3ce72d0 4862 const insn_sequence *template_sequence = NULL;
48229727
JB		 4863 int template_size = 0, i;
4864 unsigned int size;
906e58ca 4865
d3ce72d0 4866 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4867 if (stub_template)
4868 *stub_template = template_sequence;
4869
48229727 4870 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4871 if (stub_template_size)
4872 *stub_template_size = template_size;
906e58ca
NC		 4873
4874 size = 0;
461a49ca
DJ		 4875 for (i = 0; i < template_size; i++)
4876 {
d3ce72d0 4877 switch (template_sequence[i].type)
461a49ca
DJ		 4878 {
4879 case THUMB16_TYPE:
4880 size += 2;
4881 break;
4882
4883 case ARM_TYPE:
48229727 4884 case THUMB32_TYPE:
461a49ca
DJ		 4885 case DATA_TYPE:
4886 size += 4;
4887 break;
4888
4889 default:
4890 BFD_FAIL ();
2a229407 4891 return 0;
461a49ca
DJ		 4892 }
4893 }
4894
48229727
JB		 4895 return size;
4896}
4897
4898/* As above, but don't actually build the stub. Just bump offset so
4899 we know stub section sizes. */
4900
4901static bfd_boolean
4902arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4903 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4904{
4905 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4906 const insn_sequence *template_sequence;
48229727
JB		 4907 int template_size, size;
4908
4909 /* Massage our args to the form they really have. */
4910 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4911
4912 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4913 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4914
d3ce72d0 4915 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4916 &template_size);
4917
0955507f
TP		 4918 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4919 if (stub_entry->stub_template_size)
4920 {
4921 stub_entry->stub_size = size;
4922 stub_entry->stub_template = template_sequence;
4923 stub_entry->stub_template_size = template_size;
4924 }
4925
4926 /* Already accounted for. */
4927 if (stub_entry->stub_offset != (bfd_vma) -1)
4928 return TRUE;
461a49ca 4929
906e58ca
NC		 4930 size = (size + 7) & ~7;
4931 stub_entry->stub_sec->size += size;
461a49ca 4932
906e58ca
NC		 4933 return TRUE;
4934}
4935
4936/* External entry points for sizing and building linker stubs. */
4937
4938/* Set up various things so that we can make a list of input sections
4939 for each output section included in the link. Returns -1 on error,
4940 0 when no stubs will be needed, and 1 on success. */
4941
4942int
4943elf32_arm_setup_section_lists (bfd *output_bfd,
4944 struct bfd_link_info *info)
4945{
4946 bfd *input_bfd;
4947 unsigned int bfd_count;
7292b3ac 4948 unsigned int top_id, top_index;
906e58ca
NC		 4949 asection *section;
4950 asection **input_list, **list;
4951 bfd_size_type amt;
4952 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4953
4dfe6ac6
NC		 4954 if (htab == NULL)
4955 return 0;
906e58ca
NC		 4956 if (! is_elf_hash_table (htab))
4957 return 0;
4958
4959 /* Count the number of input BFDs and find the top input section id. */
4960 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4961 input_bfd != NULL;
c72f2fb2 4962 input_bfd = input_bfd->link.next)
906e58ca
NC		 4963 {
4964 bfd_count += 1;
4965 for (section = input_bfd->sections;
4966 section != NULL;
4967 section = section->next)
4968 {
4969 if (top_id < section->id)
4970 top_id = section->id;
4971 }
4972 }
4973 htab->bfd_count = bfd_count;
4974
4975 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4976 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4977 if (htab->stub_group == NULL)
4978 return -1;
fe33d2fa 4979 htab->top_id = top_id;
906e58ca
NC		 4980
4981 /* We can't use output_bfd->section_count here to find the top output
4982 section index as some sections may have been removed, and
4983 _bfd_strip_section_from_output doesn't renumber the indices. */
4984 for (section = output_bfd->sections, top_index = 0;
4985 section != NULL;
4986 section = section->next)
4987 {
4988 if (top_index < section->index)
4989 top_index = section->index;
4990 }
4991
4992 htab->top_index = top_index;
4993 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4994 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4995 htab->input_list = input_list;
4996 if (input_list == NULL)
4997 return -1;
4998
4999 /* For sections we aren't interested in, mark their entries with a
5000 value we can check later. */
5001 list = input_list + top_index;
5002 do
5003 *list = bfd_abs_section_ptr;
5004 while (list-- != input_list);
5005
5006 for (section = output_bfd->sections;
5007 section != NULL;
5008 section = section->next)
5009 {
5010 if ((section->flags & SEC_CODE) != 0)
5011 input_list[section->index] = NULL;
5012 }
5013
5014 return 1;
5015}
5016
5017/* The linker repeatedly calls this function for each input section,
5018 in the order that input sections are linked into output sections.
5019 Build lists of input sections to determine groupings between which
5020 we may insert linker stubs. */
5021
5022void
5023elf32_arm_next_input_section (struct bfd_link_info *info,
5024 asection *isec)
5025{
5026 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5027
4dfe6ac6
NC		 5028 if (htab == NULL)
5029 return;
5030
906e58ca
NC		 5031 if (isec->output_section->index <= htab->top_index)
5032 {
5033 asection **list = htab->input_list + isec->output_section->index;
5034
a7470592 5035 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5036 {
5037 /* Steal the link_sec pointer for our list. */
5038#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5039 /* This happens to make the list in reverse order,
07d72278 5040 which we reverse later. */
906e58ca
NC		 5041 PREV_SEC (isec) = *list;
5042 *list = isec;
5043 }
5044 }
5045}
5046
5047/* See whether we can group stub sections together. Grouping stub
5048 sections may result in fewer stubs. More importantly, we need to
07d72278 5049 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5050 .fini output sections respectively, because glibc splits the
5051 _init and _fini functions into multiple parts. Putting a stub in
5052 the middle of a function is not a good idea. */
5053
5054static void
5055group_sections (struct elf32_arm_link_hash_table *htab,
5056 bfd_size_type stub_group_size,
07d72278 5057 bfd_boolean stubs_always_after_branch)
906e58ca 5058{
07d72278 5059 asection **list = htab->input_list;
906e58ca
NC		 5060
5061 do
5062 {
5063 asection *tail = *list;
07d72278 5064 asection *head;
906e58ca
NC		 5065
5066 if (tail == bfd_abs_section_ptr)
5067 continue;
5068
07d72278
DJ		 5069 /* Reverse the list: we must avoid placing stubs at the
5070 beginning of the section because the beginning of the text
5071 section may be required for an interrupt vector in bare metal
5072 code. */
5073#define NEXT_SEC PREV_SEC
e780aef2
CL		 5074 head = NULL;
5075 while (tail != NULL)
99059e56
RM		 5076 {
5077 /* Pop from tail. */
5078 asection *item = tail;
5079 tail = PREV_SEC (item);
e780aef2 5080
99059e56
RM		 5081 /* Push on head. */
5082 NEXT_SEC (item) = head;
5083 head = item;
5084 }
07d72278
DJ		 5085
5086 while (head != NULL)
906e58ca
NC		 5087 {
5088 asection *curr;
07d72278 5089 asection *next;
e780aef2
CL		 5090 bfd_vma stub_group_start = head->output_offset;
5091 bfd_vma end_of_next;
906e58ca 5092
07d72278 5093 curr = head;
e780aef2 5094 while (NEXT_SEC (curr) != NULL)
8cd931b7 5095 {
e780aef2
CL		 5096 next = NEXT_SEC (curr);
5097 end_of_next = next->output_offset + next->size;
5098 if (end_of_next - stub_group_start >= stub_group_size)
5099 /* End of NEXT is too far from start, so stop. */
8cd931b7 5100 break;
e780aef2
CL		 5101 /* Add NEXT to the group. */
5102 curr = next;
8cd931b7 5103 }
906e58ca 5104
07d72278 5105 /* OK, the size from the start to the start of CURR is less
906e58ca 5106 than stub_group_size and thus can be handled by one stub
07d72278 5107 section. (Or the head section is itself larger than
906e58ca
NC		 5108 stub_group_size, in which case we may be toast.)
5109 We should really be keeping track of the total size of
5110 stubs added here, as stubs contribute to the final output
7fb9f789 5111 section size. */
906e58ca
NC		 5112 do
5113 {
07d72278 5114 next = NEXT_SEC (head);
906e58ca 5115 /* Set up this stub group. */
07d72278 5116 htab->stub_group[head->id].link_sec = curr;
906e58ca 5117 }
07d72278 5118 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5119
5120 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5121 bytes after the stub section can be handled by it too. */
5122 if (!stubs_always_after_branch)
906e58ca 5123 {
e780aef2
CL		 5124 stub_group_start = curr->output_offset + curr->size;
5125
8cd931b7 5126 while (next != NULL)
906e58ca 5127 {
e780aef2
CL		 5128 end_of_next = next->output_offset + next->size;
5129 if (end_of_next - stub_group_start >= stub_group_size)
5130 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5131 break;
e780aef2 5132 /* Add NEXT to the stub group. */
07d72278
DJ		 5133 head = next;
5134 next = NEXT_SEC (head);
5135 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5136 }
5137 }
07d72278 5138 head = next;
906e58ca
NC		 5139 }
5140 }
07d72278 5141 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5142
5143 free (htab->input_list);
5144#undef PREV_SEC
07d72278 5145#undef NEXT_SEC
906e58ca
NC		 5146}
5147
48229727
JB		 5148/* Comparison function for sorting/searching relocations relating to Cortex-A8
5149 erratum fix. */
5150
5151static int
5152a8_reloc_compare (const void *a, const void *b)
5153{
21d799b5
NC		 5154 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5155 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5156
5157 if (ra->from < rb->from)
5158 return -1;
5159 else if (ra->from > rb->from)
5160 return 1;
5161 else
5162 return 0;
5163}
5164
5165static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5166 const char *, char **);
5167
5168/* Helper function to scan code for sequences which might trigger the Cortex-A8
5169 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5170 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5171 otherwise. */
5172
81694485
NC		 5173static bfd_boolean
5174cortex_a8_erratum_scan (bfd *input_bfd,
5175 struct bfd_link_info *info,
48229727
JB		 5176 struct a8_erratum_fix **a8_fixes_p,
5177 unsigned int *num_a8_fixes_p,
5178 unsigned int *a8_fix_table_size_p,
5179 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5180 unsigned int num_a8_relocs,
5181 unsigned prev_num_a8_fixes,
5182 bfd_boolean *stub_changed_p)
48229727
JB		 5183{
5184 asection *section;
5185 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5186 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5187 unsigned int num_a8_fixes = *num_a8_fixes_p;
5188 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5189
4dfe6ac6
NC		 5190 if (htab == NULL)
5191 return FALSE;
5192
48229727
JB		 5193 for (section = input_bfd->sections;
5194 section != NULL;
5195 section = section->next)
5196 {
5197 bfd_byte *contents = NULL;
5198 struct _arm_elf_section_data *sec_data;
5199 unsigned int span;
5200 bfd_vma base_vma;
5201
5202 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5203 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5204 || (section->flags & SEC_EXCLUDE) != 0
5205 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5206 || (section->output_section == bfd_abs_section_ptr))
5207 continue;
48229727
JB		 5208
5209 base_vma = section->output_section->vma + section->output_offset;
5210
5211 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5212 contents = elf_section_data (section)->this_hdr.contents;
48229727 5213 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5214 return TRUE;
48229727
JB		 5215
5216 sec_data = elf32_arm_section_data (section);
5217
5218 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5219 {
5220 unsigned int span_start = sec_data->map[span].vma;
5221 unsigned int span_end = (span == sec_data->mapcount - 1)
5222 ? section->size : sec_data->map[span + 1].vma;
5223 unsigned int i;
5224 char span_type = sec_data->map[span].type;
5225 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5226
5227 if (span_type != 't')
5228 continue;
5229
5230 /* Span is entirely within a single 4KB region: skip scanning. */
5231 if (((base_vma + span_start) & ~0xfff)
48229727 5232 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5233 continue;
5234
5235 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5236
5237 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5238 * The branch target is in the same 4KB region as the
5239 first half of the branch.
5240 * The instruction before the branch is a 32-bit
5241 length non-branch instruction. */
5242 for (i = span_start; i < span_end;)
5243 {
5244 unsigned int insn = bfd_getl16 (&contents[i]);
5245 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5246 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5247
99059e56
RM		 5248 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5249 insn_32bit = TRUE;
48229727
JB		 5250
5251 if (insn_32bit)
99059e56
RM		 5252 {
5253 /* Load the rest of the insn (in manual-friendly order). */
5254 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5255
5256 /* Encoding T4: B<c>.W. */
5257 is_b = (insn & 0xf800d000) == 0xf0009000;
5258 /* Encoding T1: BL<c>.W. */
5259 is_bl = (insn & 0xf800d000) == 0xf000d000;
5260 /* Encoding T2: BLX<c>.W. */
5261 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5262 /* Encoding T3: B<c>.W (not permitted in IT block). */
5263 is_bcc = (insn & 0xf800d000) == 0xf0008000
5264 && (insn & 0x07f00000) != 0x03800000;
5265 }
5266
5267 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5268
99059e56 5269 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5270 && insn_32bit
5271 && is_32bit_branch
5272 && last_was_32bit
5273 && ! last_was_branch)
99059e56
RM		 5274 {
5275 bfd_signed_vma offset = 0;
5276 bfd_boolean force_target_arm = FALSE;
48229727 5277 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5278 bfd_vma target;
5279 enum elf32_arm_stub_type stub_type = arm_stub_none;
5280 struct a8_erratum_reloc key, *found;
5281 bfd_boolean use_plt = FALSE;
48229727 5282
99059e56
RM		 5283 key.from = base_vma + i;
5284 found = (struct a8_erratum_reloc *)
5285 bsearch (&key, a8_relocs, num_a8_relocs,
5286 sizeof (struct a8_erratum_reloc),
5287 &a8_reloc_compare);
48229727
JB		 5288
5289 if (found)
5290 {
5291 char *error_message = NULL;
5292 struct elf_link_hash_entry *entry;
5293
5294 /* We don't care about the error returned from this
99059e56 5295 function, only if there is glue or not. */
48229727
JB		 5296 entry = find_thumb_glue (info, found->sym_name,
5297 &error_message);
5298
5299 if (entry)
5300 found->non_a8_stub = TRUE;
5301
92750f34 5302 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5303 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5304 && found->hash->root.plt.offset != (bfd_vma) -1)
5305 use_plt = TRUE;
5306
5307 if (found->r_type == R_ARM_THM_CALL)
5308 {
35fc36a8
RS		 5309 if (found->branch_type == ST_BRANCH_TO_ARM
5310 || use_plt)
92750f34
DJ		 5311 force_target_arm = TRUE;
5312 else
5313 force_target_thumb = TRUE;
5314 }
48229727
JB		 5315 }
5316
99059e56 5317 /* Check if we have an offending branch instruction. */
48229727
JB		 5318
5319 if (found && found->non_a8_stub)
5320 /* We've already made a stub for this instruction, e.g.
5321 it's a long branch or a Thumb->ARM stub. Assume that
5322 stub will suffice to work around the A8 erratum (see
5323 setting of always_after_branch above). */
5324 ;
99059e56
RM		 5325 else if (is_bcc)
5326 {
5327 offset = (insn & 0x7ff) << 1;
5328 offset |= (insn & 0x3f0000) >> 4;
5329 offset |= (insn & 0x2000) ? 0x40000 : 0;
5330 offset |= (insn & 0x800) ? 0x80000 : 0;
5331 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5332 if (offset & 0x100000)
5333 offset |= ~ ((bfd_signed_vma) 0xfffff);
5334 stub_type = arm_stub_a8_veneer_b_cond;
5335 }
5336 else if (is_b || is_bl || is_blx)
5337 {
5338 int s = (insn & 0x4000000) != 0;
5339 int j1 = (insn & 0x2000) != 0;
5340 int j2 = (insn & 0x800) != 0;
5341 int i1 = !(j1 ^ s);
5342 int i2 = !(j2 ^ s);
5343
5344 offset = (insn & 0x7ff) << 1;
5345 offset |= (insn & 0x3ff0000) >> 4;
5346 offset |= i2 << 22;
5347 offset |= i1 << 23;
5348 offset |= s << 24;
5349 if (offset & 0x1000000)
5350 offset |= ~ ((bfd_signed_vma) 0xffffff);
5351
5352 if (is_blx)
5353 offset &= ~ ((bfd_signed_vma) 3);
5354
5355 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5356 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5357 }
5358
5359 if (stub_type != arm_stub_none)
5360 {
5361 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5362
5363 /* The original instruction is a BL, but the target is
99059e56 5364 an ARM instruction. If we were not making a stub,
48229727
JB		 5365 the BL would have been converted to a BLX. Use the
5366 BLX stub instead in that case. */
5367 if (htab->use_blx && force_target_arm
5368 && stub_type == arm_stub_a8_veneer_bl)
5369 {
5370 stub_type = arm_stub_a8_veneer_blx;
5371 is_blx = TRUE;
5372 is_bl = FALSE;
5373 }
5374 /* Conversely, if the original instruction was
5375 BLX but the target is Thumb mode, use the BL
5376 stub. */
5377 else if (force_target_thumb
5378 && stub_type == arm_stub_a8_veneer_blx)
5379 {
5380 stub_type = arm_stub_a8_veneer_bl;
5381 is_blx = FALSE;
5382 is_bl = TRUE;
5383 }
5384
99059e56
RM		 5385 if (is_blx)
5386 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5387
99059e56
RM		 5388 /* If we found a relocation, use the proper destination,
5389 not the offset in the (unrelocated) instruction.
48229727
JB		 5390 Note this is always done if we switched the stub type
5391 above. */
99059e56
RM		 5392 if (found)
5393 offset =
81694485 5394 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5395
99059e56
RM		 5396 /* If the stub will use a Thumb-mode branch to a
5397 PLT target, redirect it to the preceding Thumb
5398 entry point. */
5399 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5400 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5401
99059e56 5402 target = pc_for_insn + offset;
48229727 5403
99059e56
RM		 5404 /* The BLX stub is ARM-mode code. Adjust the offset to
5405 take the different PC value (+8 instead of +4) into
48229727 5406 account. */
99059e56
RM		 5407 if (stub_type == arm_stub_a8_veneer_blx)
5408 offset += 4;
5409
5410 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5411 {
5412 char *stub_name = NULL;
5413
5414 if (num_a8_fixes == a8_fix_table_size)
5415 {
5416 a8_fix_table_size *= 2;
5417 a8_fixes = (struct a8_erratum_fix *)
5418 bfd_realloc (a8_fixes,
5419 sizeof (struct a8_erratum_fix)
5420 * a8_fix_table_size);
5421 }
48229727 5422
eb7c4339
NS		 5423 if (num_a8_fixes < prev_num_a8_fixes)
5424 {
5425 /* If we're doing a subsequent scan,
5426 check if we've found the same fix as
5427 before, and try and reuse the stub
5428 name. */
5429 stub_name = a8_fixes[num_a8_fixes].stub_name;
5430 if ((a8_fixes[num_a8_fixes].section != section)
5431 || (a8_fixes[num_a8_fixes].offset != i))
5432 {
5433 free (stub_name);
5434 stub_name = NULL;
5435 *stub_changed_p = TRUE;
5436 }
5437 }
5438
5439 if (!stub_name)
5440 {
21d799b5 5441 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5442 if (stub_name != NULL)
5443 sprintf (stub_name, "%x:%x", section->id, i);
5444 }
48229727 5445
99059e56
RM		 5446 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5447 a8_fixes[num_a8_fixes].section = section;
5448 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5449 a8_fixes[num_a8_fixes].target_offset =
5450 target - base_vma;
99059e56
RM		 5451 a8_fixes[num_a8_fixes].orig_insn = insn;
5452 a8_fixes[num_a8_fixes].stub_name = stub_name;
5453 a8_fixes[num_a8_fixes].stub_type = stub_type;
5454 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5455 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5456
99059e56
RM		 5457 num_a8_fixes++;
5458 }
5459 }
5460 }
48229727 5461
99059e56
RM		 5462 i += insn_32bit ? 4 : 2;
5463 last_was_32bit = insn_32bit;
48229727 5464 last_was_branch = is_32bit_branch;
99059e56
RM		 5465 }
5466 }
48229727
JB		 5467
5468 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5469 free (contents);
48229727 5470 }
fe33d2fa 5471
48229727
JB		 5472 *a8_fixes_p = a8_fixes;
5473 *num_a8_fixes_p = num_a8_fixes;
5474 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5475
81694485 5476 return FALSE;
48229727
JB		 5477}
5478
b715f643
TP		 5479/* Create or update a stub entry depending on whether the stub can already be
5480 found in HTAB. The stub is identified by:
5481 - its type STUB_TYPE
5482 - its source branch (note that several can share the same stub) whose
5483 section and relocation (if any) are given by SECTION and IRELA
5484 respectively
5485 - its target symbol whose input section, hash, name, value and branch type
5486 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5487 respectively
5488
5489 If found, the value of the stub's target symbol is updated from SYM_VALUE
5490 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5491 TRUE and the stub entry is initialized.
5492
0955507f
TP		 5493 Returns the stub that was created or updated, or NULL if an error
5494 occurred. */
b715f643 5495
0955507f 5496static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5497elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5498 enum elf32_arm_stub_type stub_type, asection *section,
5499 Elf_Internal_Rela *irela, asection *sym_sec,
5500 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5501 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5502 bfd_boolean *new_stub)
5503{
5504 const asection *id_sec;
5505 char *stub_name;
5506 struct elf32_arm_stub_hash_entry *stub_entry;
5507 unsigned int r_type;
4f4faa4d 5508 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5509
5510 BFD_ASSERT (stub_type != arm_stub_none);
5511 *new_stub = FALSE;
5512
4f4faa4d
TP		 5513 if (sym_claimed)
5514 stub_name = sym_name;
5515 else
5516 {
5517 BFD_ASSERT (irela);
5518 BFD_ASSERT (section);
c2abbbeb 5519 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5520
4f4faa4d
TP		 5521 /* Support for grouping stub sections. */
5522 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5523
4f4faa4d
TP		 5524 /* Get the name of this stub. */
5525 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5526 stub_type);
5527 if (!stub_name)
0955507f 5528 return NULL;
4f4faa4d 5529 }
b715f643
TP		 5530
5531 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5532 FALSE);
5533 /* The proper stub has already been created, just update its value. */
5534 if (stub_entry != NULL)
5535 {
4f4faa4d
TP		 5536 if (!sym_claimed)
5537 free (stub_name);
b715f643 5538 stub_entry->target_value = sym_value;
0955507f 5539 return stub_entry;
b715f643
TP		 5540 }
5541
daa4adae 5542 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5543 if (stub_entry == NULL)
5544 {
4f4faa4d
TP		 5545 if (!sym_claimed)
5546 free (stub_name);
0955507f 5547 return NULL;
b715f643
TP		 5548 }
5549
5550 stub_entry->target_value = sym_value;
5551 stub_entry->target_section = sym_sec;
5552 stub_entry->stub_type = stub_type;
5553 stub_entry->h = hash;
5554 stub_entry->branch_type = branch_type;
5555
4f4faa4d
TP		 5556 if (sym_claimed)
5557 stub_entry->output_name = sym_name;
5558 else
b715f643 5559 {
4f4faa4d
TP		 5560 if (sym_name == NULL)
5561 sym_name = "unnamed";
5562 stub_entry->output_name = (char *)
5563 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5564 + strlen (sym_name));
5565 if (stub_entry->output_name == NULL)
5566 {
5567 free (stub_name);
0955507f 5568 return NULL;
4f4faa4d 5569 }
b715f643 5570
4f4faa4d
TP		 5571 /* For historical reasons, use the existing names for ARM-to-Thumb and
5572 Thumb-to-ARM stubs. */
5573 r_type = ELF32_R_TYPE (irela->r_info);
5574 if ((r_type == (unsigned int) R_ARM_THM_CALL
5575 || r_type == (unsigned int) R_ARM_THM_JUMP24
5576 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5577 && branch_type == ST_BRANCH_TO_ARM)
5578 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5579 else if ((r_type == (unsigned int) R_ARM_CALL
5580 || r_type == (unsigned int) R_ARM_JUMP24)
5581 && branch_type == ST_BRANCH_TO_THUMB)
5582 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5583 else
5584 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5585 }
b715f643
TP		 5586
5587 *new_stub = TRUE;
0955507f 5588 return stub_entry;
b715f643
TP		 5589}
5590
4ba2ef8f
TP		 5591/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5592 gateway veneer to transition from non secure to secure state and create them
5593 accordingly.
5594
5595 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5596 defines the conditions that govern Secure Gateway veneer creation for a
5597 given symbol <SYM> as follows:
5598 - it has function type
5599 - it has non local binding
5600 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5601 same type, binding and value as <SYM> (called normal symbol).
5602 An entry function can handle secure state transition itself in which case
5603 its special symbol would have a different value from the normal symbol.
5604
5605 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5606 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5607 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5608 created.
4ba2ef8f 5609
0955507f 5610 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5611
5612static bfd_boolean
5613cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5614 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5615 int *cmse_stub_created)
4ba2ef8f
TP		 5616{
5617 const struct elf_backend_data *bed;
5618 Elf_Internal_Shdr *symtab_hdr;
5619 unsigned i, j, sym_count, ext_start;
5620 Elf_Internal_Sym *cmse_sym, *local_syms;
5621 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5622 enum arm_st_branch_type branch_type;
5623 char *sym_name, *lsym_name;
5624 bfd_vma sym_value;
5625 asection *section;
0955507f
TP		 5626 struct elf32_arm_stub_hash_entry *stub_entry;
5627 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5628
5629 bed = get_elf_backend_data (input_bfd);
5630 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5631 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5632 ext_start = symtab_hdr->sh_info;
5633 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5634 && out_attr[Tag_CPU_arch_profile].i == 'M');
5635
5636 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5637 if (local_syms == NULL)
5638 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5639 symtab_hdr->sh_info, 0, NULL, NULL,
5640 NULL);
5641 if (symtab_hdr->sh_info && local_syms == NULL)
5642 return FALSE;
5643
5644 /* Scan symbols. */
5645 for (i = 0; i < sym_count; i++)
5646 {
5647 cmse_invalid = FALSE;
5648
5649 if (i < ext_start)
5650 {
5651 cmse_sym = &local_syms[i];
5652 /* Not a special symbol. */
5653 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5654 continue;
5655 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5656 symtab_hdr->sh_link,
5657 cmse_sym->st_name);
5658 /* Special symbol with local binding. */
5659 cmse_invalid = TRUE;
5660 }
5661 else
5662 {
5663 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5664 sym_name = (char *) cmse_hash->root.root.root.string;
5665
5666 /* Not a special symbol. */
5667 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5668 continue;
5669
5670 /* Special symbol has incorrect binding or type. */
5671 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5672 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5673 || cmse_hash->root.type != STT_FUNC)
5674 cmse_invalid = TRUE;
5675 }
5676
5677 if (!is_v8m)
5678 {
4eca0228
AM		 5679 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5680 "ARMv8-M architecture or later."),
5681 input_bfd, sym_name);
4ba2ef8f
TP		 5682 is_v8m = TRUE; /* Avoid multiple warning. */
5683 ret = FALSE;
5684 }
5685
5686 if (cmse_invalid)
5687 {
4eca0228
AM		 5688 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5689 input_bfd, sym_name);
5690 _bfd_error_handler (_("It must be a global or weak function "
5691 "symbol."));
4ba2ef8f
TP		 5692 ret = FALSE;
5693 if (i < ext_start)
5694 continue;
5695 }
5696
5697 sym_name += strlen (CMSE_PREFIX);
5698 hash = (struct elf32_arm_link_hash_entry *)
5699 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5700
5701 /* No associated normal symbol or it is neither global nor weak. */
5702 if (!hash
5703 || (hash->root.root.type != bfd_link_hash_defined
5704 && hash->root.root.type != bfd_link_hash_defweak)
5705 || hash->root.type != STT_FUNC)
5706 {
5707 /* Initialize here to avoid warning about use of possibly
5708 uninitialized variable. */
5709 j = 0;
5710
5711 if (!hash)
5712 {
5713 /* Searching for a normal symbol with local binding. */
5714 for (; j < ext_start; j++)
5715 {
5716 lsym_name =
5717 bfd_elf_string_from_elf_section (input_bfd,
5718 symtab_hdr->sh_link,
5719 local_syms[j].st_name);
5720 if (!strcmp (sym_name, lsym_name))
5721 break;
5722 }
5723 }
5724
5725 if (hash || j < ext_start)
5726 {
4eca0228 5727 _bfd_error_handler
4ba2ef8f 5728 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5729 _bfd_error_handler
4ba2ef8f
TP		 5730 (_("It must be a global or weak function symbol."));
5731 }
5732 else
4eca0228 5733 _bfd_error_handler
4ba2ef8f
TP		 5734 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5735 ret = FALSE;
5736 if (!hash)
5737 continue;
5738 }
5739
5740 sym_value = hash->root.root.u.def.value;
5741 section = hash->root.root.u.def.section;
5742
5743 if (cmse_hash->root.root.u.def.section != section)
5744 {
4eca0228 5745 _bfd_error_handler
4ba2ef8f
TP		 5746 (_("%B: `%s' and its special symbol are in different sections."),
5747 input_bfd, sym_name);
5748 ret = FALSE;
5749 }
5750 if (cmse_hash->root.root.u.def.value != sym_value)
5751 continue; /* Ignore: could be an entry function starting with SG. */
5752
5753 /* If this section is a link-once section that will be discarded, then
5754 don't create any stubs. */
5755 if (section->output_section == NULL)
5756 {
4eca0228 5757 _bfd_error_handler
4ba2ef8f
TP		 5758 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5759 continue;
5760 }
5761
5762 if (hash->root.size == 0)
5763 {
4eca0228 5764 _bfd_error_handler
4ba2ef8f
TP		 5765 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5766 ret = FALSE;
5767 }
5768
5769 if (!ret)
5770 continue;
5771 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5772 stub_entry
4ba2ef8f
TP		 5773 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5774 NULL, NULL, section, hash, sym_name,
5775 sym_value, branch_type, &new_stub);
5776
0955507f 5777 if (stub_entry == NULL)
4ba2ef8f
TP		 5778 ret = FALSE;
5779 else
5780 {
5781 BFD_ASSERT (new_stub);
0955507f 5782 (*cmse_stub_created)++;
4ba2ef8f
TP		 5783 }
5784 }
5785
5786 if (!symtab_hdr->contents)
5787 free (local_syms);
5788 return ret;
5789}
5790
0955507f
TP		 5791/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5792 code entry function, ie can be called from non secure code without using a
5793 veneer. */
5794
5795static bfd_boolean
5796cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5797{
42484486 5798 bfd_byte contents[4];
0955507f
TP		 5799 uint32_t first_insn;
5800 asection *section;
5801 file_ptr offset;
5802 bfd *abfd;
5803
5804 /* Defined symbol of function type. */
5805 if (hash->root.root.type != bfd_link_hash_defined
5806 && hash->root.root.type != bfd_link_hash_defweak)
5807 return FALSE;
5808 if (hash->root.type != STT_FUNC)
5809 return FALSE;
5810
5811 /* Read first instruction. */
5812 section = hash->root.root.u.def.section;
5813 abfd = section->owner;
5814 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5815 if (!bfd_get_section_contents (abfd, section, contents, offset,
5816 sizeof (contents)))
0955507f
TP		 5817 return FALSE;
5818
42484486
TP		 5819 first_insn = bfd_get_32 (abfd, contents);
5820
5821 /* Starts by SG instruction. */
0955507f
TP		 5822 return first_insn == 0xe97fe97f;
5823}
5824
5825/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5826 secure gateway veneers (ie. the veneers was not in the input import library)
5827 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5828
5829static bfd_boolean
5830arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5831{
5832 struct elf32_arm_stub_hash_entry *stub_entry;
5833 struct bfd_link_info *info;
5834
5835 /* Massage our args to the form they really have. */
5836 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5837 info = (struct bfd_link_info *) gen_info;
5838
5839 if (info->out_implib_bfd)
5840 return TRUE;
5841
5842 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5843 return TRUE;
5844
5845 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5846 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5847
5848 return TRUE;
5849}
5850
5851/* Set offset of each secure gateway veneers so that its address remain
5852 identical to the one in the input import library referred by
5853 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5854 (present in input import library but absent from the executable being
5855 linked) or if new veneers appeared and there is no output import library
5856 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5857 number of secure gateway veneers found in the input import library.
5858
5859 The function returns whether an error occurred. If no error occurred,
5860 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5861 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5862 veneer observed set for new veneers to be layed out after. */
5863
5864static bfd_boolean
5865set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5866 struct elf32_arm_link_hash_table *htab,
5867 int *cmse_stub_created)
5868{
5869 long symsize;
5870 char *sym_name;
5871 flagword flags;
5872 long i, symcount;
5873 bfd *in_implib_bfd;
5874 asection *stub_out_sec;
5875 bfd_boolean ret = TRUE;
5876 Elf_Internal_Sym *intsym;
5877 const char *out_sec_name;
5878 bfd_size_type cmse_stub_size;
5879 asymbol **sympp = NULL, *sym;
5880 struct elf32_arm_link_hash_entry *hash;
5881 const insn_sequence *cmse_stub_template;
5882 struct elf32_arm_stub_hash_entry *stub_entry;
5883 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5884 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5885 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5886
5887 /* No input secure gateway import library. */
5888 if (!htab->in_implib_bfd)
5889 return TRUE;
5890
5891 in_implib_bfd = htab->in_implib_bfd;
5892 if (!htab->cmse_implib)
5893 {
4eca0228
AM		 5894 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5895 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5896 return FALSE;
5897 }
5898
5899 /* Get symbol table size. */
5900 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5901 if (symsize < 0)
5902 return FALSE;
5903
5904 /* Read in the input secure gateway import library's symbol table. */
5905 sympp = (asymbol **) xmalloc (symsize);
5906 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5907 if (symcount < 0)
5908 {
5909 ret = FALSE;
5910 goto free_sym_buf;
5911 }
5912
5913 htab->new_cmse_stub_offset = 0;
5914 cmse_stub_size =
5915 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5916 &cmse_stub_template,
5917 &cmse_stub_template_size);
5918 out_sec_name =
5919 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5920 stub_out_sec =
5921 bfd_get_section_by_name (htab->obfd, out_sec_name);
5922 if (stub_out_sec != NULL)
5923 cmse_stub_sec_vma = stub_out_sec->vma;
5924
5925 /* Set addresses of veneers mentionned in input secure gateway import
5926 library's symbol table. */
5927 for (i = 0; i < symcount; i++)
5928 {
5929 sym = sympp[i];
5930 flags = sym->flags;
5931 sym_name = (char *) bfd_asymbol_name (sym);
5932 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5933
5934 if (sym->section != bfd_abs_section_ptr
5935 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5936 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5937 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5938 != ST_BRANCH_TO_THUMB))
5939 {
4eca0228
AM		 5940 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5941 in_implib_bfd, sym_name);
5942 _bfd_error_handler (_("Symbol should be absolute, global and "
5943 "refer to Thumb functions."));
0955507f
TP		 5944 ret = FALSE;
5945 continue;
5946 }
5947
5948 veneer_value = bfd_asymbol_value (sym);
5949 stub_offset = veneer_value - cmse_stub_sec_vma;
5950 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5951 FALSE, FALSE);
5952 hash = (struct elf32_arm_link_hash_entry *)
5953 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5954
5955 /* Stub entry should have been created by cmse_scan or the symbol be of
5956 a secure function callable from non secure code. */
5957 if (!stub_entry && !hash)
5958 {
5959 bfd_boolean new_stub;
5960
4eca0228 5961 _bfd_error_handler
0955507f
TP		 5962 (_("Entry function `%s' disappeared from secure code."), sym_name);
5963 hash = (struct elf32_arm_link_hash_entry *)
5964 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5965 stub_entry
5966 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5967 NULL, NULL, bfd_abs_section_ptr, hash,
5968 sym_name, veneer_value,
5969 ST_BRANCH_TO_THUMB, &new_stub);
5970 if (stub_entry == NULL)
5971 ret = FALSE;
5972 else
5973 {
5974 BFD_ASSERT (new_stub);
5975 new_cmse_stubs_created++;
5976 (*cmse_stub_created)++;
5977 }
5978 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5979 stub_entry->stub_offset = stub_offset;
5980 }
5981 /* Symbol found is not callable from non secure code. */
5982 else if (!stub_entry)
5983 {
5984 if (!cmse_entry_fct_p (hash))
5985 {
4eca0228
AM		 5986 _bfd_error_handler (_("`%s' refers to a non entry function."),
5987 sym_name);
0955507f
TP		 5988 ret = FALSE;
5989 }
5990 continue;
5991 }
5992 else
5993 {
5994 /* Only stubs for SG veneers should have been created. */
5995 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5996
5997 /* Check visibility hasn't changed. */
5998 if (!!(flags & BSF_GLOBAL)
5999 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6000 _bfd_error_handler
0955507f
TP		 6001 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6002 sym_name);
6003
6004 stub_entry->stub_offset = stub_offset;
6005 }
6006
6007 /* Size should match that of a SG veneer. */
6008 if (intsym->st_size != cmse_stub_size)
6009 {
4eca0228
AM		 6010 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6011 in_implib_bfd, sym_name);
0955507f
TP		 6012 ret = FALSE;
6013 }
6014
6015 /* Previous veneer address is before current SG veneer section. */
6016 if (veneer_value < cmse_stub_sec_vma)
6017 {
6018 /* Avoid offset underflow. */
6019 if (stub_entry)
6020 stub_entry->stub_offset = 0;
6021 stub_offset = 0;
6022 ret = FALSE;
6023 }
6024
6025 /* Complain if stub offset not a multiple of stub size. */
6026 if (stub_offset % cmse_stub_size)
6027 {
4eca0228 6028 _bfd_error_handler
0955507f
TP		 6029 (_("Offset of veneer for entry function `%s' not a multiple of "
6030 "its size."), sym_name);
6031 ret = FALSE;
6032 }
6033
6034 if (!ret)
6035 continue;
6036
6037 new_cmse_stubs_created--;
6038 if (veneer_value < cmse_stub_array_start)
6039 cmse_stub_array_start = veneer_value;
6040 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6041 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6042 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6043 }
6044
6045 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6046 {
6047 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6048 _bfd_error_handler
0955507f
TP		 6049 (_("new entry function(s) introduced but no output import library "
6050 "specified:"));
6051 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6052 }
6053
6054 if (cmse_stub_array_start != cmse_stub_sec_vma)
6055 {
4eca0228 6056 _bfd_error_handler
0955507f
TP		 6057 (_("Start address of `%s' is different from previous link."),
6058 out_sec_name);
6059 ret = FALSE;
6060 }
6061
6062free_sym_buf:
6063 free (sympp);
6064 return ret;
6065}
6066
906e58ca
NC		 6067/* Determine and set the size of the stub section for a final link.
6068
6069 The basic idea here is to examine all the relocations looking for
6070 PC-relative calls to a target that is unreachable with a "bl"
6071 instruction. */
6072
6073bfd_boolean
6074elf32_arm_size_stubs (bfd *output_bfd,
6075 bfd *stub_bfd,
6076 struct bfd_link_info *info,
6077 bfd_signed_vma group_size,
7a89b94e 6078 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6079 asection *,
7a89b94e 6080 unsigned int),
906e58ca
NC		 6081 void (*layout_sections_again) (void))
6082{
0955507f 6083 bfd_boolean ret = TRUE;
4ba2ef8f 6084 obj_attribute *out_attr;
0955507f 6085 int cmse_stub_created = 0;
906e58ca 6086 bfd_size_type stub_group_size;
4ba2ef8f 6087 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6088 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6089 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6090 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6091 struct a8_erratum_reloc *a8_relocs = NULL;
6092 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6093
4dfe6ac6
NC		 6094 if (htab == NULL)
6095 return FALSE;
6096
48229727
JB		 6097 if (htab->fix_cortex_a8)
6098 {
21d799b5 6099 a8_fixes = (struct a8_erratum_fix *)
99059e56 6100 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6101 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6102 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6103 }
906e58ca
NC		 6104
6105 /* Propagate mach to stub bfd, because it may not have been
6106 finalized when we created stub_bfd. */
6107 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6108 bfd_get_mach (output_bfd));
6109
6110 /* Stash our params away. */
6111 htab->stub_bfd = stub_bfd;
6112 htab->add_stub_section = add_stub_section;
6113 htab->layout_sections_again = layout_sections_again;
07d72278 6114 stubs_always_after_branch = group_size < 0;
48229727 6115
4ba2ef8f
TP		 6116 out_attr = elf_known_obj_attributes_proc (output_bfd);
6117 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6118
48229727
JB		 6119 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6120 as the first half of a 32-bit branch straddling two 4K pages. This is a
6121 crude way of enforcing that. */
6122 if (htab->fix_cortex_a8)
6123 stubs_always_after_branch = 1;
6124
906e58ca
NC		 6125 if (group_size < 0)
6126 stub_group_size = -group_size;
6127 else
6128 stub_group_size = group_size;
6129
6130 if (stub_group_size == 1)
6131 {
6132 /* Default values. */
6133 /* Thumb branch range is +-4MB has to be used as the default
6134 maximum size (a given section can contain both ARM and Thumb
6135 code, so the worst case has to be taken into account).
6136
6137 This value is 24K less than that, which allows for 2025
6138 12-byte stubs. If we exceed that, then we will fail to link.
6139 The user will have to relink with an explicit group size
6140 option. */
6141 stub_group_size = 4170000;
6142 }
6143
07d72278 6144 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6145
3ae046cc
NS		 6146 /* If we're applying the cortex A8 fix, we need to determine the
6147 program header size now, because we cannot change it later --
6148 that could alter section placements. Notice the A8 erratum fix
6149 ends up requiring the section addresses to remain unchanged
6150 modulo the page size. That's something we cannot represent
6151 inside BFD, and we don't want to force the section alignment to
6152 be the page size. */
6153 if (htab->fix_cortex_a8)
6154 (*htab->layout_sections_again) ();
6155
906e58ca
NC		 6156 while (1)
6157 {
6158 bfd *input_bfd;
6159 unsigned int bfd_indx;
6160 asection *stub_sec;
d7c5bd02 6161 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6162 bfd_boolean stub_changed = FALSE;
6163 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6164
48229727 6165 num_a8_fixes = 0;
906e58ca
NC		 6166 for (input_bfd = info->input_bfds, bfd_indx = 0;
6167 input_bfd != NULL;
c72f2fb2 6168 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6169 {
6170 Elf_Internal_Shdr *symtab_hdr;
6171 asection *section;
6172 Elf_Internal_Sym *local_syms = NULL;
6173
99059e56
RM		 6174 if (!is_arm_elf (input_bfd))
6175 continue;
adbcc655 6176
48229727
JB		 6177 num_a8_relocs = 0;
6178
906e58ca
NC		 6179 /* We'll need the symbol table in a second. */
6180 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6181 if (symtab_hdr->sh_info == 0)
6182 continue;
6183
4ba2ef8f
TP		 6184 /* Limit scan of symbols to object file whose profile is
6185 Microcontroller to not hinder performance in the general case. */
6186 if (m_profile && first_veneer_scan)
6187 {
6188 struct elf_link_hash_entry **sym_hashes;
6189
6190 sym_hashes = elf_sym_hashes (input_bfd);
6191 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6192 &cmse_stub_created))
4ba2ef8f 6193 goto error_ret_free_local;
0955507f
TP		 6194
6195 if (cmse_stub_created != 0)
6196 stub_changed = TRUE;
4ba2ef8f
TP		 6197 }
6198
906e58ca
NC		 6199 /* Walk over each section attached to the input bfd. */
6200 for (section = input_bfd->sections;
6201 section != NULL;
6202 section = section->next)
6203 {
6204 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6205
6206 /* If there aren't any relocs, then there's nothing more
6207 to do. */
6208 if ((section->flags & SEC_RELOC) == 0
6209 || section->reloc_count == 0
6210 || (section->flags & SEC_CODE) == 0)
6211 continue;
6212
6213 /* If this section is a link-once section that will be
6214 discarded, then don't create any stubs. */
6215 if (section->output_section == NULL
6216 || section->output_section->owner != output_bfd)
6217 continue;
6218
6219 /* Get the relocs. */
6220 internal_relocs
6221 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6222 NULL, info->keep_memory);
6223 if (internal_relocs == NULL)
6224 goto error_ret_free_local;
6225
6226 /* Now examine each relocation. */
6227 irela = internal_relocs;
6228 irelaend = irela + section->reloc_count;
6229 for (; irela < irelaend; irela++)
6230 {
6231 unsigned int r_type, r_indx;
906e58ca
NC		 6232 asection *sym_sec;
6233 bfd_vma sym_value;
6234 bfd_vma destination;
6235 struct elf32_arm_link_hash_entry *hash;
7413f23f 6236 const char *sym_name;
34e77a92 6237 unsigned char st_type;
35fc36a8 6238 enum arm_st_branch_type branch_type;
48229727 6239 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6240
6241 r_type = ELF32_R_TYPE (irela->r_info);
6242 r_indx = ELF32_R_SYM (irela->r_info);
6243
6244 if (r_type >= (unsigned int) R_ARM_max)
6245 {
6246 bfd_set_error (bfd_error_bad_value);
6247 error_ret_free_internal:
6248 if (elf_section_data (section)->relocs == NULL)
6249 free (internal_relocs);
15dd01b1
TP		 6250 /* Fall through. */
6251 error_ret_free_local:
6252 if (local_syms != NULL
6253 && (symtab_hdr->contents
6254 != (unsigned char *) local_syms))
6255 free (local_syms);
6256 return FALSE;
906e58ca 6257 }
b38cadfb 6258
0855e32b
NS		 6259 hash = NULL;
6260 if (r_indx >= symtab_hdr->sh_info)
6261 hash = elf32_arm_hash_entry
6262 (elf_sym_hashes (input_bfd)
6263 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6264
0855e32b
NS		 6265 /* Only look for stubs on branch instructions, or
6266 non-relaxed TLSCALL */
906e58ca 6267 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6268 && (r_type != (unsigned int) R_ARM_THM_CALL)
6269 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6270 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6271 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6272 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6273 && (r_type != (unsigned int) R_ARM_PLT32)
6274 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6275 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6276 && r_type == elf32_arm_tls_transition
6277 (info, r_type, &hash->root)
6278 && ((hash ? hash->tls_type
6279 : (elf32_arm_local_got_tls_type
6280 (input_bfd)[r_indx]))
6281 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6282 continue;
6283
6284 /* Now determine the call target, its name, value,
6285 section. */
6286 sym_sec = NULL;
6287 sym_value = 0;
6288 destination = 0;
7413f23f 6289 sym_name = NULL;
b38cadfb 6290
0855e32b
NS		 6291 if (r_type == (unsigned int) R_ARM_TLS_CALL
6292 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6293 {
6294 /* A non-relaxed TLS call. The target is the
6295 plt-resident trampoline and nothing to do
6296 with the symbol. */
6297 BFD_ASSERT (htab->tls_trampoline > 0);
6298 sym_sec = htab->root.splt;
6299 sym_value = htab->tls_trampoline;
6300 hash = 0;
34e77a92 6301 st_type = STT_FUNC;
35fc36a8 6302 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6303 }
6304 else if (!hash)
906e58ca
NC		 6305 {
6306 /* It's a local symbol. */
6307 Elf_Internal_Sym *sym;
906e58ca
NC		 6308
6309 if (local_syms == NULL)
6310 {
6311 local_syms
6312 = (Elf_Internal_Sym *) symtab_hdr->contents;
6313 if (local_syms == NULL)
6314 local_syms
6315 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6316 symtab_hdr->sh_info, 0,
6317 NULL, NULL, NULL);
6318 if (local_syms == NULL)
6319 goto error_ret_free_internal;
6320 }
6321
6322 sym = local_syms + r_indx;
f6d250ce
TS		 6323 if (sym->st_shndx == SHN_UNDEF)
6324 sym_sec = bfd_und_section_ptr;
6325 else if (sym->st_shndx == SHN_ABS)
6326 sym_sec = bfd_abs_section_ptr;
6327 else if (sym->st_shndx == SHN_COMMON)
6328 sym_sec = bfd_com_section_ptr;
6329 else
6330 sym_sec =
6331 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6332
ffcb4889
NS		 6333 if (!sym_sec)
6334 /* This is an undefined symbol. It can never
6a631e86 6335 be resolved. */
ffcb4889 6336 continue;
fe33d2fa 6337
906e58ca
NC		 6338 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6339 sym_value = sym->st_value;
6340 destination = (sym_value + irela->r_addend
6341 + sym_sec->output_offset
6342 + sym_sec->output_section->vma);
34e77a92 6343 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6344 branch_type =
6345 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6346 sym_name
6347 = bfd_elf_string_from_elf_section (input_bfd,
6348 symtab_hdr->sh_link,
6349 sym->st_name);
906e58ca
NC		 6350 }
6351 else
6352 {
6353 /* It's an external symbol. */
906e58ca
NC		 6354 while (hash->root.root.type == bfd_link_hash_indirect
6355 || hash->root.root.type == bfd_link_hash_warning)
6356 hash = ((struct elf32_arm_link_hash_entry *)
6357 hash->root.root.u.i.link);
6358
6359 if (hash->root.root.type == bfd_link_hash_defined
6360 || hash->root.root.type == bfd_link_hash_defweak)
6361 {
6362 sym_sec = hash->root.root.u.def.section;
6363 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6364
6365 struct elf32_arm_link_hash_table *globals =
6366 elf32_arm_hash_table (info);
6367
6368 /* For a destination in a shared library,
6369 use the PLT stub as target address to
6370 decide whether a branch stub is
6371 needed. */
4dfe6ac6 6372 if (globals != NULL
362d30a1 6373 && globals->root.splt != NULL
4dfe6ac6 6374 && hash != NULL
022f8312
CL		 6375 && hash->root.plt.offset != (bfd_vma) -1)
6376 {
362d30a1 6377 sym_sec = globals->root.splt;
022f8312
CL		 6378 sym_value = hash->root.plt.offset;
6379 if (sym_sec->output_section != NULL)
6380 destination = (sym_value
6381 + sym_sec->output_offset
6382 + sym_sec->output_section->vma);
6383 }
6384 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6385 destination = (sym_value + irela->r_addend
6386 + sym_sec->output_offset
6387 + sym_sec->output_section->vma);
6388 }
69c5861e
CL		 6389 else if ((hash->root.root.type == bfd_link_hash_undefined)
6390 || (hash->root.root.type == bfd_link_hash_undefweak))
6391 {
6392 /* For a shared library, use the PLT stub as
6393 target address to decide whether a long
6394 branch stub is needed.
6395 For absolute code, they cannot be handled. */
6396 struct elf32_arm_link_hash_table *globals =
6397 elf32_arm_hash_table (info);
6398
4dfe6ac6 6399 if (globals != NULL
362d30a1 6400 && globals->root.splt != NULL
4dfe6ac6 6401 && hash != NULL
69c5861e
CL		 6402 && hash->root.plt.offset != (bfd_vma) -1)
6403 {
362d30a1 6404 sym_sec = globals->root.splt;
69c5861e
CL		 6405 sym_value = hash->root.plt.offset;
6406 if (sym_sec->output_section != NULL)
6407 destination = (sym_value
6408 + sym_sec->output_offset
6409 + sym_sec->output_section->vma);
6410 }
6411 else
6412 continue;
6413 }
906e58ca
NC		 6414 else
6415 {
6416 bfd_set_error (bfd_error_bad_value);
6417 goto error_ret_free_internal;
6418 }
34e77a92 6419 st_type = hash->root.type;
39d911fc
TP		 6420 branch_type =
6421 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6422 sym_name = hash->root.root.root.string;
906e58ca
NC		 6423 }
6424
48229727 6425 do
7413f23f 6426 {
b715f643 6427 bfd_boolean new_stub;
0955507f 6428 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6429
48229727
JB		 6430 /* Determine what (if any) linker stub is needed. */
6431 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6432 st_type, &branch_type,
6433 hash, destination, sym_sec,
48229727
JB		 6434 input_bfd, sym_name);
6435 if (stub_type == arm_stub_none)
6436 break;
6437
48229727
JB		 6438 /* We've either created a stub for this reloc already,
6439 or we are about to. */
0955507f 6440 stub_entry =
b715f643
TP		 6441 elf32_arm_create_stub (htab, stub_type, section, irela,
6442 sym_sec, hash,
6443 (char *) sym_name, sym_value,
6444 branch_type, &new_stub);
7413f23f 6445
0955507f 6446 created_stub = stub_entry != NULL;
b715f643
TP		 6447 if (!created_stub)
6448 goto error_ret_free_internal;
6449 else if (!new_stub)
6450 break;
99059e56 6451 else
b715f643 6452 stub_changed = TRUE;
99059e56
RM		 6453 }
6454 while (0);
6455
6456 /* Look for relocations which might trigger Cortex-A8
6457 erratum. */
6458 if (htab->fix_cortex_a8
6459 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6460 || r_type == (unsigned int) R_ARM_THM_JUMP19
6461 || r_type == (unsigned int) R_ARM_THM_CALL
6462 || r_type == (unsigned int) R_ARM_THM_XPC22))
6463 {
6464 bfd_vma from = section->output_section->vma
6465 + section->output_offset
6466 + irela->r_offset;
6467
6468 if ((from & 0xfff) == 0xffe)
6469 {
6470 /* Found a candidate. Note we haven't checked the
6471 destination is within 4K here: if we do so (and
6472 don't create an entry in a8_relocs) we can't tell
6473 that a branch should have been relocated when
6474 scanning later. */
6475 if (num_a8_relocs == a8_reloc_table_size)
6476 {
6477 a8_reloc_table_size *= 2;
6478 a8_relocs = (struct a8_erratum_reloc *)
6479 bfd_realloc (a8_relocs,
6480 sizeof (struct a8_erratum_reloc)
6481 * a8_reloc_table_size);
6482 }
6483
6484 a8_relocs[num_a8_relocs].from = from;
6485 a8_relocs[num_a8_relocs].destination = destination;
6486 a8_relocs[num_a8_relocs].r_type = r_type;
6487 a8_relocs[num_a8_relocs].branch_type = branch_type;
6488 a8_relocs[num_a8_relocs].sym_name = sym_name;
6489 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6490 a8_relocs[num_a8_relocs].hash = hash;
6491
6492 num_a8_relocs++;
6493 }
6494 }
906e58ca
NC		 6495 }
6496
99059e56
RM		 6497 /* We're done with the internal relocs, free them. */
6498 if (elf_section_data (section)->relocs == NULL)
6499 free (internal_relocs);
6500 }
48229727 6501
99059e56 6502 if (htab->fix_cortex_a8)
48229727 6503 {
99059e56
RM		 6504 /* Sort relocs which might apply to Cortex-A8 erratum. */
6505 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6506 sizeof (struct a8_erratum_reloc),
99059e56 6507 &a8_reloc_compare);
48229727 6508
99059e56
RM		 6509 /* Scan for branches which might trigger Cortex-A8 erratum. */
6510 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6511 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6512 a8_relocs, num_a8_relocs,
6513 prev_num_a8_fixes, &stub_changed)
6514 != 0)
48229727 6515 goto error_ret_free_local;
5e681ec4 6516 }
7f991970
AM		 6517
6518 if (local_syms != NULL
6519 && symtab_hdr->contents != (unsigned char *) local_syms)
6520 {
6521 if (!info->keep_memory)
6522 free (local_syms);
6523 else
6524 symtab_hdr->contents = (unsigned char *) local_syms;
6525 }
5e681ec4
PB		 6526 }
6527
0955507f
TP		 6528 if (first_veneer_scan
6529 && !set_cmse_veneer_addr_from_implib (info, htab,
6530 &cmse_stub_created))
6531 ret = FALSE;
6532
eb7c4339 6533 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6534 stub_changed = TRUE;
48229727 6535
906e58ca
NC		 6536 if (!stub_changed)
6537 break;
5e681ec4 6538
906e58ca
NC		 6539 /* OK, we've added some stubs. Find out the new size of the
6540 stub sections. */
6541 for (stub_sec = htab->stub_bfd->sections;
6542 stub_sec != NULL;
6543 stub_sec = stub_sec->next)
3e6b1042
DJ		 6544 {
6545 /* Ignore non-stub sections. */
6546 if (!strstr (stub_sec->name, STUB_SUFFIX))
6547 continue;
6548
6549 stub_sec->size = 0;
6550 }
b34b2d70 6551
0955507f
TP		 6552 /* Add new SG veneers after those already in the input import
6553 library. */
6554 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6555 stub_type++)
6556 {
6557 bfd_vma *start_offset_p;
6558 asection **stub_sec_p;
6559
6560 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6561 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6562 if (start_offset_p == NULL)
6563 continue;
6564
6565 BFD_ASSERT (stub_sec_p != NULL);
6566 if (*stub_sec_p != NULL)
6567 (*stub_sec_p)->size = *start_offset_p;
6568 }
6569
d7c5bd02 6570 /* Compute stub section size, considering padding. */
906e58ca 6571 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6572 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6573 stub_type++)
6574 {
6575 int size, padding;
6576 asection **stub_sec_p;
6577
6578 padding = arm_dedicated_stub_section_padding (stub_type);
6579 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6580 /* Skip if no stub input section or no stub section padding
6581 required. */
6582 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6583 continue;
6584 /* Stub section padding required but no dedicated section. */
6585 BFD_ASSERT (stub_sec_p);
6586
6587 size = (*stub_sec_p)->size;
6588 size = (size + padding - 1) & ~(padding - 1);
6589 (*stub_sec_p)->size = size;
6590 }
906e58ca 6591
48229727
JB		 6592 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6593 if (htab->fix_cortex_a8)
99059e56
RM		 6594 for (i = 0; i < num_a8_fixes; i++)
6595 {
48229727 6596 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6597 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6598
6599 if (stub_sec == NULL)
7f991970 6600 return FALSE;
48229727 6601
99059e56
RM		 6602 stub_sec->size
6603 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6604 NULL);
6605 }
48229727
JB		 6606
6607
906e58ca
NC		 6608 /* Ask the linker to do its stuff. */
6609 (*htab->layout_sections_again) ();
4ba2ef8f 6610 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6611 }
6612
48229727
JB		 6613 /* Add stubs for Cortex-A8 erratum fixes now. */
6614 if (htab->fix_cortex_a8)
6615 {
6616 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6617 {
6618 struct elf32_arm_stub_hash_entry *stub_entry;
6619 char *stub_name = a8_fixes[i].stub_name;
6620 asection *section = a8_fixes[i].section;
6621 unsigned int section_id = a8_fixes[i].section->id;
6622 asection *link_sec = htab->stub_group[section_id].link_sec;
6623 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6624 const insn_sequence *template_sequence;
6625 int template_size, size = 0;
6626
6627 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6628 TRUE, FALSE);
6629 if (stub_entry == NULL)
6630 {
4eca0228
AM		 6631 _bfd_error_handler (_("%s: cannot create stub entry %s"),
6632 section->owner, stub_name);
99059e56
RM		 6633 return FALSE;
6634 }
6635
6636 stub_entry->stub_sec = stub_sec;
0955507f 6637 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6638 stub_entry->id_sec = link_sec;
6639 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6640 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6641 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6642 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6643 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6644 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6645
99059e56
RM		 6646 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6647 &template_sequence,
6648 &template_size);
48229727 6649
99059e56
RM		 6650 stub_entry->stub_size = size;
6651 stub_entry->stub_template = template_sequence;
6652 stub_entry->stub_template_size = template_size;
6653 }
48229727
JB		 6654
6655 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6656 elf32_arm_write_section(). */
48229727
JB		 6657 htab->a8_erratum_fixes = a8_fixes;
6658 htab->num_a8_erratum_fixes = num_a8_fixes;
6659 }
6660 else
6661 {
6662 htab->a8_erratum_fixes = NULL;
6663 htab->num_a8_erratum_fixes = 0;
6664 }
0955507f 6665 return ret;
5e681ec4
PB		 6666}
6667
906e58ca
NC		 6668/* Build all the stubs associated with the current output file. The
6669 stubs are kept in a hash table attached to the main linker hash
6670 table. We also set up the .plt entries for statically linked PIC
6671 functions here. This function is called via arm_elf_finish in the
6672 linker. */
252b5132 6673
906e58ca
NC		 6674bfd_boolean
6675elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6676{
906e58ca
NC		 6677 asection *stub_sec;
6678 struct bfd_hash_table *table;
0955507f 6679 enum elf32_arm_stub_type stub_type;
906e58ca 6680 struct elf32_arm_link_hash_table *htab;
252b5132 6681
906e58ca 6682 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6683 if (htab == NULL)
6684 return FALSE;
252b5132 6685
906e58ca
NC		 6686 for (stub_sec = htab->stub_bfd->sections;
6687 stub_sec != NULL;
6688 stub_sec = stub_sec->next)
252b5132 6689 {
906e58ca
NC		 6690 bfd_size_type size;
6691
8029a119 6692 /* Ignore non-stub sections. */
906e58ca
NC		 6693 if (!strstr (stub_sec->name, STUB_SUFFIX))
6694 continue;
6695
d7c5bd02 6696 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6697 must at least be done for stub section requiring padding and for SG
6698 veneers to ensure that a non secure code branching to a removed SG
6699 veneer causes an error. */
906e58ca 6700 size = stub_sec->size;
21d799b5 6701 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6702 if (stub_sec->contents == NULL && size != 0)
6703 return FALSE;
0955507f 6704
906e58ca 6705 stub_sec->size = 0;
252b5132
RH		 6706 }
6707
0955507f
TP		 6708 /* Add new SG veneers after those already in the input import library. */
6709 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6710 {
6711 bfd_vma *start_offset_p;
6712 asection **stub_sec_p;
6713
6714 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6715 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6716 if (start_offset_p == NULL)
6717 continue;
6718
6719 BFD_ASSERT (stub_sec_p != NULL);
6720 if (*stub_sec_p != NULL)
6721 (*stub_sec_p)->size = *start_offset_p;
6722 }
6723
906e58ca
NC		 6724 /* Build the stubs as directed by the stub hash table. */
6725 table = &htab->stub_hash_table;
6726 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6727 if (htab->fix_cortex_a8)
6728 {
6729 /* Place the cortex a8 stubs last. */
6730 htab->fix_cortex_a8 = -1;
6731 bfd_hash_traverse (table, arm_build_one_stub, info);
6732 }
252b5132 6733
906e58ca 6734 return TRUE;
252b5132
RH		 6735}
6736
9b485d32
NC		 6737/* Locate the Thumb encoded calling stub for NAME. */
6738
252b5132 6739static struct elf_link_hash_entry *
57e8b36a
NC		 6740find_thumb_glue (struct bfd_link_info *link_info,
6741 const char *name,
f2a9dd69 6742 char **error_message)
252b5132
RH		 6743{
6744 char *tmp_name;
6745 struct elf_link_hash_entry *hash;
6746 struct elf32_arm_link_hash_table *hash_table;
6747
6748 /* We need a pointer to the armelf specific hash table. */
6749 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6750 if (hash_table == NULL)
6751 return NULL;
252b5132 6752
21d799b5 6753 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6754 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6755
6756 BFD_ASSERT (tmp_name);
6757
6758 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6759
6760 hash = elf_link_hash_lookup
b34976b6 6761 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6762
b1657152
AM		 6763 if (hash == NULL
6764 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6765 tmp_name, name) == -1)
6766 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6767
6768 free (tmp_name);
6769
6770 return hash;
6771}
6772
9b485d32
NC		 6773/* Locate the ARM encoded calling stub for NAME. */
6774
252b5132 6775static struct elf_link_hash_entry *
57e8b36a
NC		 6776find_arm_glue (struct bfd_link_info *link_info,
6777 const char *name,
f2a9dd69 6778 char **error_message)
252b5132
RH		 6779{
6780 char *tmp_name;
6781 struct elf_link_hash_entry *myh;
6782 struct elf32_arm_link_hash_table *hash_table;
6783
6784 /* We need a pointer to the elfarm specific hash table. */
6785 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6786 if (hash_table == NULL)
6787 return NULL;
252b5132 6788
21d799b5 6789 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6790 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6791
6792 BFD_ASSERT (tmp_name);
6793
6794 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6795
6796 myh = elf_link_hash_lookup
b34976b6 6797 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6798
b1657152
AM		 6799 if (myh == NULL
6800 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6801 tmp_name, name) == -1)
6802 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6803
6804 free (tmp_name);
6805
6806 return myh;
6807}
6808
8f6277f5 6809/* ARM->Thumb glue (static images):
252b5132
RH		 6810
6811 .arm
6812 __func_from_arm:
6813 ldr r12, __func_addr
6814 bx r12
6815 __func_addr:
906e58ca 6816 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6817
26079076
PB		 6818 (v5t static images)
6819 .arm
6820 __func_from_arm:
6821 ldr pc, __func_addr
6822 __func_addr:
906e58ca 6823 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6824
8f6277f5
PB		 6825 (relocatable images)
6826 .arm
6827 __func_from_arm:
6828 ldr r12, __func_offset
6829 add r12, r12, pc
6830 bx r12
6831 __func_offset:
8029a119 6832 .word func - . */
8f6277f5
PB		 6833
6834#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6835static const insn32 a2t1_ldr_insn = 0xe59fc000;
6836static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6837static const insn32 a2t3_func_addr_insn = 0x00000001;
6838
26079076
PB		 6839#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6840static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6841static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6842
8f6277f5
PB		 6843#define ARM2THUMB_PIC_GLUE_SIZE 16
6844static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6845static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6846static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6847
9b485d32 6848/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6849
8029a119
NC		 6850 .thumb .thumb
6851 .align 2 .align 2
6852 __func_from_thumb: __func_from_thumb:
6853 bx pc push {r6, lr}
6854 nop ldr r6, __func_addr
6855 .arm mov lr, pc
6856 b func bx r6
99059e56
RM		 6857 .arm
6858 ;; back_to_thumb
6859 ldmia r13! {r6, lr}
6860 bx lr
6861 __func_addr:
6862 .word func */
252b5132
RH		 6863
6864#define THUMB2ARM_GLUE_SIZE 8
6865static const insn16 t2a1_bx_pc_insn = 0x4778;
6866static const insn16 t2a2_noop_insn = 0x46c0;
6867static const insn32 t2a3_b_insn = 0xea000000;
6868
c7b8f16e 6869#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6870#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6871#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6872
845b51d6
PB		 6873#define ARM_BX_VENEER_SIZE 12
6874static const insn32 armbx1_tst_insn = 0xe3100001;
6875static const insn32 armbx2_moveq_insn = 0x01a0f000;
6876static const insn32 armbx3_bx_insn = 0xe12fff10;
6877
7e392df6 6878#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6879static void
6880arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6881{
6882 asection * s;
8029a119 6883 bfd_byte * contents;
252b5132 6884
8029a119 6885 if (size == 0)
3e6b1042
DJ		 6886 {
6887 /* Do not include empty glue sections in the output. */
6888 if (abfd != NULL)
6889 {
3d4d4302 6890 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6891 if (s != NULL)
6892 s->flags |= SEC_EXCLUDE;
6893 }
6894 return;
6895 }
252b5132 6896
8029a119 6897 BFD_ASSERT (abfd != NULL);
252b5132 6898
3d4d4302 6899 s = bfd_get_linker_section (abfd, name);
8029a119 6900 BFD_ASSERT (s != NULL);
252b5132 6901
21d799b5 6902 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6903
8029a119
NC		 6904 BFD_ASSERT (s->size == size);
6905 s->contents = contents;
6906}
906e58ca 6907
8029a119
NC		 6908bfd_boolean
6909bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6910{
6911 struct elf32_arm_link_hash_table * globals;
906e58ca 6912
8029a119
NC		 6913 globals = elf32_arm_hash_table (info);
6914 BFD_ASSERT (globals != NULL);
906e58ca 6915
8029a119
NC		 6916 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6917 globals->arm_glue_size,
6918 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6919
8029a119
NC		 6920 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6921 globals->thumb_glue_size,
6922 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6923
8029a119
NC		 6924 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6925 globals->vfp11_erratum_glue_size,
6926 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6927
a504d23a
LA		 6928 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6929 globals->stm32l4xx_erratum_glue_size,
6930 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6931
8029a119
NC		 6932 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6933 globals->bx_glue_size,
845b51d6
PB		 6934 ARM_BX_GLUE_SECTION_NAME);
6935
b34976b6 6936 return TRUE;
252b5132
RH		 6937}
6938
a4fd1a8e 6939/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6940 returns the symbol identifying the stub. */
6941
a4fd1a8e 6942static struct elf_link_hash_entry *
57e8b36a
NC		 6943record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6944 struct elf_link_hash_entry * h)
252b5132
RH		 6945{
6946 const char * name = h->root.root.string;
63b0f745 6947 asection * s;
252b5132
RH		 6948 char * tmp_name;
6949 struct elf_link_hash_entry * myh;
14a793b2 6950 struct bfd_link_hash_entry * bh;
252b5132 6951 struct elf32_arm_link_hash_table * globals;
dc810e39 6952 bfd_vma val;
2f475487 6953 bfd_size_type size;
252b5132
RH		 6954
6955 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6956 BFD_ASSERT (globals != NULL);
6957 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6958
3d4d4302 6959 s = bfd_get_linker_section
252b5132
RH		 6960 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6961
252b5132
RH		 6962 BFD_ASSERT (s != NULL);
6963
21d799b5 6964 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6965 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6966
6967 BFD_ASSERT (tmp_name);
6968
6969 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6970
6971 myh = elf_link_hash_lookup
b34976b6 6972 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6973
6974 if (myh != NULL)
6975 {
9b485d32 6976 /* We've already seen this guy. */
252b5132 6977 free (tmp_name);
a4fd1a8e 6978 return myh;
252b5132
RH		 6979 }
6980
57e8b36a
NC		 6981 /* The only trick here is using hash_table->arm_glue_size as the value.
6982 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6983 putting it. The +1 on the value marks that the stub has not been
6984 output yet - not that it is a Thumb function. */
14a793b2 6985 bh = NULL;
dc810e39
AM		 6986 val = globals->arm_glue_size + 1;
6987 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6988 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6989 NULL, TRUE, FALSE, &bh);
252b5132 6990
b7693d02
DJ		 6991 myh = (struct elf_link_hash_entry *) bh;
6992 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6993 myh->forced_local = 1;
6994
252b5132
RH		 6995 free (tmp_name);
6996
0e1862bb
L		 6997 if (bfd_link_pic (link_info)
6998 || globals->root.is_relocatable_executable
27e55c4d 6999 || globals->pic_veneer)
2f475487 7000 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7001 else if (globals->use_blx)
7002 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7003 else
2f475487
AM		 7004 size = ARM2THUMB_STATIC_GLUE_SIZE;
7005
7006 s->size += size;
7007 globals->arm_glue_size += size;
252b5132 7008
a4fd1a8e 7009 return myh;
252b5132
RH		 7010}
7011
845b51d6
PB		 7012/* Allocate space for ARMv4 BX veneers. */
7013
7014static void
7015record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7016{
7017 asection * s;
7018 struct elf32_arm_link_hash_table *globals;
7019 char *tmp_name;
7020 struct elf_link_hash_entry *myh;
7021 struct bfd_link_hash_entry *bh;
7022 bfd_vma val;
7023
7024 /* BX PC does not need a veneer. */
7025 if (reg == 15)
7026 return;
7027
7028 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7029 BFD_ASSERT (globals != NULL);
7030 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7031
7032 /* Check if this veneer has already been allocated. */
7033 if (globals->bx_glue_offset[reg])
7034 return;
7035
3d4d4302 7036 s = bfd_get_linker_section
845b51d6
PB		 7037 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7038
7039 BFD_ASSERT (s != NULL);
7040
7041 /* Add symbol for veneer. */
21d799b5
NC		 7042 tmp_name = (char *)
7043 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7044
845b51d6 7045 BFD_ASSERT (tmp_name);
906e58ca 7046
845b51d6 7047 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7048
845b51d6
PB		 7049 myh = elf_link_hash_lookup
7050 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7051
845b51d6 7052 BFD_ASSERT (myh == NULL);
906e58ca 7053
845b51d6
PB		 7054 bh = NULL;
7055 val = globals->bx_glue_size;
7056 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7057 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7058 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7059
7060 myh = (struct elf_link_hash_entry *) bh;
7061 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7062 myh->forced_local = 1;
7063
7064 s->size += ARM_BX_VENEER_SIZE;
7065 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7066 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7067}
7068
7069
c7b8f16e
JB		 7070/* Add an entry to the code/data map for section SEC. */
7071
7072static void
7073elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7074{
7075 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7076 unsigned int newidx;
906e58ca 7077
c7b8f16e
JB		 7078 if (sec_data->map == NULL)
7079 {
21d799b5 7080 sec_data->map = (elf32_arm_section_map *)
99059e56 7081 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7082 sec_data->mapcount = 0;
7083 sec_data->mapsize = 1;
7084 }
906e58ca 7085
c7b8f16e 7086 newidx = sec_data->mapcount++;
906e58ca 7087
c7b8f16e
JB		 7088 if (sec_data->mapcount > sec_data->mapsize)
7089 {
7090 sec_data->mapsize *= 2;
21d799b5 7091 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7092 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7093 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7094 }
7095
7096 if (sec_data->map)
7097 {
7098 sec_data->map[newidx].vma = vma;
7099 sec_data->map[newidx].type = type;
c7b8f16e 7100 }
c7b8f16e
JB		 7101}
7102
7103
7104/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7105 veneers are handled for now. */
7106
7107static bfd_vma
7108record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7109 elf32_vfp11_erratum_list *branch,
7110 bfd *branch_bfd,
7111 asection *branch_sec,
7112 unsigned int offset)
c7b8f16e
JB		 7113{
7114 asection *s;
7115 struct elf32_arm_link_hash_table *hash_table;
7116 char *tmp_name;
7117 struct elf_link_hash_entry *myh;
7118 struct bfd_link_hash_entry *bh;
7119 bfd_vma val;
7120 struct _arm_elf_section_data *sec_data;
c7b8f16e 7121 elf32_vfp11_erratum_list *newerr;
906e58ca 7122
c7b8f16e 7123 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7124 BFD_ASSERT (hash_table != NULL);
7125 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7126
3d4d4302 7127 s = bfd_get_linker_section
c7b8f16e 7128 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7129
c7b8f16e 7130 sec_data = elf32_arm_section_data (s);
906e58ca 7131
c7b8f16e 7132 BFD_ASSERT (s != NULL);
906e58ca 7133
21d799b5 7134 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7135 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7136
c7b8f16e 7137 BFD_ASSERT (tmp_name);
906e58ca 7138
c7b8f16e
JB		 7139 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7140 hash_table->num_vfp11_fixes);
906e58ca 7141
c7b8f16e
JB		 7142 myh = elf_link_hash_lookup
7143 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7144
c7b8f16e 7145 BFD_ASSERT (myh == NULL);
906e58ca 7146
c7b8f16e
JB		 7147 bh = NULL;
7148 val = hash_table->vfp11_erratum_glue_size;
7149 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7150 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7151 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7152
7153 myh = (struct elf_link_hash_entry *) bh;
7154 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7155 myh->forced_local = 1;
7156
7157 /* Link veneer back to calling location. */
c7e2358a 7158 sec_data->erratumcount += 1;
21d799b5
NC		 7159 newerr = (elf32_vfp11_erratum_list *)
7160 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7161
c7b8f16e
JB		 7162 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7163 newerr->vma = -1;
7164 newerr->u.v.branch = branch;
7165 newerr->u.v.id = hash_table->num_vfp11_fixes;
7166 branch->u.b.veneer = newerr;
7167
7168 newerr->next = sec_data->erratumlist;
7169 sec_data->erratumlist = newerr;
7170
7171 /* A symbol for the return from the veneer. */
7172 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7173 hash_table->num_vfp11_fixes);
7174
7175 myh = elf_link_hash_lookup
7176 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7177
c7b8f16e
JB		 7178 if (myh != NULL)
7179 abort ();
7180
7181 bh = NULL;
7182 val = offset + 4;
7183 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7184 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7185
c7b8f16e
JB		 7186 myh = (struct elf_link_hash_entry *) bh;
7187 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7188 myh->forced_local = 1;
7189
7190 free (tmp_name);
906e58ca 7191
c7b8f16e
JB		 7192 /* Generate a mapping symbol for the veneer section, and explicitly add an
7193 entry for that symbol to the code/data map for the section. */
7194 if (hash_table->vfp11_erratum_glue_size == 0)
7195 {
7196 bh = NULL;
7197 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7198 ever requires this erratum fix. */
c7b8f16e
JB		 7199 _bfd_generic_link_add_one_symbol (link_info,
7200 hash_table->bfd_of_glue_owner, "$a",
7201 BSF_LOCAL, s, 0, NULL,
99059e56 7202 TRUE, FALSE, &bh);
c7b8f16e
JB		 7203
7204 myh = (struct elf_link_hash_entry *) bh;
7205 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7206 myh->forced_local = 1;
906e58ca 7207
c7b8f16e 7208 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7209 BFDs. We must make a note of this generated mapping symbol
7210 ourselves so that code byteswapping works properly in
7211 elf32_arm_write_section. */
c7b8f16e
JB		 7212 elf32_arm_section_map_add (s, 'a', 0);
7213 }
906e58ca 7214
c7b8f16e
JB		 7215 s->size += VFP11_ERRATUM_VENEER_SIZE;
7216 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7217 hash_table->num_vfp11_fixes++;
906e58ca 7218
c7b8f16e
JB		 7219 /* The offset of the veneer. */
7220 return val;
7221}
7222
a504d23a
LA		 7223/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7224 veneers need to be handled because used only in Cortex-M. */
7225
7226static bfd_vma
7227record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7228 elf32_stm32l4xx_erratum_list *branch,
7229 bfd *branch_bfd,
7230 asection *branch_sec,
7231 unsigned int offset,
7232 bfd_size_type veneer_size)
7233{
7234 asection *s;
7235 struct elf32_arm_link_hash_table *hash_table;
7236 char *tmp_name;
7237 struct elf_link_hash_entry *myh;
7238 struct bfd_link_hash_entry *bh;
7239 bfd_vma val;
7240 struct _arm_elf_section_data *sec_data;
7241 elf32_stm32l4xx_erratum_list *newerr;
7242
7243 hash_table = elf32_arm_hash_table (link_info);
7244 BFD_ASSERT (hash_table != NULL);
7245 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7246
7247 s = bfd_get_linker_section
7248 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7249
7250 BFD_ASSERT (s != NULL);
7251
7252 sec_data = elf32_arm_section_data (s);
7253
7254 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7255 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7256
7257 BFD_ASSERT (tmp_name);
7258
7259 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7260 hash_table->num_stm32l4xx_fixes);
7261
7262 myh = elf_link_hash_lookup
7263 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7264
7265 BFD_ASSERT (myh == NULL);
7266
7267 bh = NULL;
7268 val = hash_table->stm32l4xx_erratum_glue_size;
7269 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7270 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7271 NULL, TRUE, FALSE, &bh);
7272
7273 myh = (struct elf_link_hash_entry *) bh;
7274 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7275 myh->forced_local = 1;
7276
7277 /* Link veneer back to calling location. */
7278 sec_data->stm32l4xx_erratumcount += 1;
7279 newerr = (elf32_stm32l4xx_erratum_list *)
7280 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7281
7282 newerr->type = STM32L4XX_ERRATUM_VENEER;
7283 newerr->vma = -1;
7284 newerr->u.v.branch = branch;
7285 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7286 branch->u.b.veneer = newerr;
7287
7288 newerr->next = sec_data->stm32l4xx_erratumlist;
7289 sec_data->stm32l4xx_erratumlist = newerr;
7290
7291 /* A symbol for the return from the veneer. */
7292 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7293 hash_table->num_stm32l4xx_fixes);
7294
7295 myh = elf_link_hash_lookup
7296 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7297
7298 if (myh != NULL)
7299 abort ();
7300
7301 bh = NULL;
7302 val = offset + 4;
7303 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7304 branch_sec, val, NULL, TRUE, FALSE, &bh);
7305
7306 myh = (struct elf_link_hash_entry *) bh;
7307 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7308 myh->forced_local = 1;
7309
7310 free (tmp_name);
7311
7312 /* Generate a mapping symbol for the veneer section, and explicitly add an
7313 entry for that symbol to the code/data map for the section. */
7314 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7315 {
7316 bh = NULL;
7317 /* Creates a THUMB symbol since there is no other choice. */
7318 _bfd_generic_link_add_one_symbol (link_info,
7319 hash_table->bfd_of_glue_owner, "$t",
7320 BSF_LOCAL, s, 0, NULL,
7321 TRUE, FALSE, &bh);
7322
7323 myh = (struct elf_link_hash_entry *) bh;
7324 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7325 myh->forced_local = 1;
7326
7327 /* The elf32_arm_init_maps function only cares about symbols from input
7328 BFDs. We must make a note of this generated mapping symbol
7329 ourselves so that code byteswapping works properly in
7330 elf32_arm_write_section. */
7331 elf32_arm_section_map_add (s, 't', 0);
7332 }
7333
7334 s->size += veneer_size;
7335 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7336 hash_table->num_stm32l4xx_fixes++;
7337
7338 /* The offset of the veneer. */
7339 return val;
7340}
7341
8029a119 7342#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7343 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7344 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7345
7346/* Create a fake section for use by the ARM backend of the linker. */
7347
7348static bfd_boolean
7349arm_make_glue_section (bfd * abfd, const char * name)
7350{
7351 asection * sec;
7352
3d4d4302 7353 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7354 if (sec != NULL)
7355 /* Already made. */
7356 return TRUE;
7357
3d4d4302 7358 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7359
7360 if (sec == NULL
7361 || !bfd_set_section_alignment (abfd, sec, 2))
7362 return FALSE;
7363
7364 /* Set the gc mark to prevent the section from being removed by garbage
7365 collection, despite the fact that no relocs refer to this section. */
7366 sec->gc_mark = 1;
7367
7368 return TRUE;
7369}
7370
1db37fe6
YG		 7371/* Set size of .plt entries. This function is called from the
7372 linker scripts in ld/emultempl/{armelf}.em. */
7373
7374void
7375bfd_elf32_arm_use_long_plt (void)
7376{
7377 elf32_arm_use_long_plt_entry = TRUE;
7378}
7379
8afb0e02
NC		 7380/* Add the glue sections to ABFD. This function is called from the
7381 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7382
b34976b6 7383bfd_boolean
57e8b36a
NC		 7384bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7385 struct bfd_link_info *info)
252b5132 7386{
a504d23a
LA		 7387 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7388 bfd_boolean dostm32l4xx = globals
7389 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7390 bfd_boolean addglue;
7391
8afb0e02
NC		 7392 /* If we are only performing a partial
7393 link do not bother adding the glue. */
0e1862bb 7394 if (bfd_link_relocatable (info))
b34976b6 7395 return TRUE;
252b5132 7396
a504d23a 7397 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7398 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7399 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7400 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7401
7402 if (!dostm32l4xx)
7403 return addglue;
7404
7405 return addglue
7406 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7407}
7408
daa4adae
TP		 7409/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7410 ensures they are not marked for deletion by
7411 strip_excluded_output_sections () when veneers are going to be created
7412 later. Not doing so would trigger assert on empty section size in
7413 lang_size_sections_1 (). */
7414
7415void
7416bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7417{
7418 enum elf32_arm_stub_type stub_type;
7419
7420 /* If we are only performing a partial
7421 link do not bother adding the glue. */
7422 if (bfd_link_relocatable (info))
7423 return;
7424
7425 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7426 {
7427 asection *out_sec;
7428 const char *out_sec_name;
7429
7430 if (!arm_dedicated_stub_output_section_required (stub_type))
7431 continue;
7432
7433 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7434 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7435 if (out_sec != NULL)
7436 out_sec->flags |= SEC_KEEP;
7437 }
7438}
7439
8afb0e02
NC		 7440/* Select a BFD to be used to hold the sections used by the glue code.
7441 This function is called from the linker scripts in ld/emultempl/
8029a119 7442 {armelf/pe}.em. */
8afb0e02 7443
b34976b6 7444bfd_boolean
57e8b36a 7445bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7446{
7447 struct elf32_arm_link_hash_table *globals;
7448
7449 /* If we are only performing a partial link
7450 do not bother getting a bfd to hold the glue. */
0e1862bb 7451 if (bfd_link_relocatable (info))
b34976b6 7452 return TRUE;
8afb0e02 7453
b7693d02
DJ		 7454 /* Make sure we don't attach the glue sections to a dynamic object. */
7455 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7456
8afb0e02 7457 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7458 BFD_ASSERT (globals != NULL);
7459
7460 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7461 return TRUE;
8afb0e02 7462
252b5132
RH		 7463 /* Save the bfd for later use. */
7464 globals->bfd_of_glue_owner = abfd;
cedb70c5 7465
b34976b6 7466 return TRUE;
252b5132
RH		 7467}
7468
906e58ca
NC		 7469static void
7470check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7471{
2de70689
MGD		 7472 int cpu_arch;
7473
b38cadfb 7474 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7475 Tag_CPU_arch);
7476
7477 if (globals->fix_arm1176)
7478 {
7479 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7480 globals->use_blx = 1;
7481 }
7482 else
7483 {
7484 if (cpu_arch > TAG_CPU_ARCH_V4T)
7485 globals->use_blx = 1;
7486 }
39b41c9c
PB		 7487}
7488
b34976b6 7489bfd_boolean
57e8b36a 7490bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7491 struct bfd_link_info *link_info)
252b5132
RH		 7492{
7493 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7494 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7495 Elf_Internal_Rela *irel, *irelend;
7496 bfd_byte *contents = NULL;
252b5132
RH		 7497
7498 asection *sec;
7499 struct elf32_arm_link_hash_table *globals;
7500
7501 /* If we are only performing a partial link do not bother
7502 to construct any glue. */
0e1862bb 7503 if (bfd_link_relocatable (link_info))
b34976b6 7504 return TRUE;
252b5132 7505
39ce1a6a
NC		 7506 /* Here we have a bfd that is to be included on the link. We have a
7507 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7508 globals = elf32_arm_hash_table (link_info);
252b5132 7509 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7510
7511 check_use_blx (globals);
252b5132 7512
d504ffc8 7513 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7514 {
d003868e
AM		 7515 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7516 abfd);
e489d0ae
PB		 7517 return FALSE;
7518 }
f21f3fe0 7519
39ce1a6a
NC		 7520 /* PR 5398: If we have not decided to include any loadable sections in
7521 the output then we will not have a glue owner bfd. This is OK, it
7522 just means that there is nothing else for us to do here. */
7523 if (globals->bfd_of_glue_owner == NULL)
7524 return TRUE;
7525
252b5132
RH		 7526 /* Rummage around all the relocs and map the glue vectors. */
7527 sec = abfd->sections;
7528
7529 if (sec == NULL)
b34976b6 7530 return TRUE;
252b5132
RH		 7531
7532 for (; sec != NULL; sec = sec->next)
7533 {
7534 if (sec->reloc_count == 0)
7535 continue;
7536
2f475487
AM		 7537 if ((sec->flags & SEC_EXCLUDE) != 0)
7538 continue;
7539
0ffa91dd 7540 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7541
9b485d32 7542 /* Load the relocs. */
6cdc0ccc 7543 internal_relocs
906e58ca 7544 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7545
6cdc0ccc
AM		 7546 if (internal_relocs == NULL)
7547 goto error_return;
252b5132 7548
6cdc0ccc
AM		 7549 irelend = internal_relocs + sec->reloc_count;
7550 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7551 {
7552 long r_type;
7553 unsigned long r_index;
252b5132
RH		 7554
7555 struct elf_link_hash_entry *h;
7556
7557 r_type = ELF32_R_TYPE (irel->r_info);
7558 r_index = ELF32_R_SYM (irel->r_info);
7559
9b485d32 7560 /* These are the only relocation types we care about. */
ba96a88f 7561 if ( r_type != R_ARM_PC24
845b51d6 7562 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7563 continue;
7564
7565 /* Get the section contents if we haven't done so already. */
7566 if (contents == NULL)
7567 {
7568 /* Get cached copy if it exists. */
7569 if (elf_section_data (sec)->this_hdr.contents != NULL)
7570 contents = elf_section_data (sec)->this_hdr.contents;
7571 else
7572 {
7573 /* Go get them off disk. */
57e8b36a 7574 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7575 goto error_return;
7576 }
7577 }
7578
845b51d6
PB		 7579 if (r_type == R_ARM_V4BX)
7580 {
7581 int reg;
7582
7583 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7584 record_arm_bx_glue (link_info, reg);
7585 continue;
7586 }
7587
a7c10850 7588 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7589 h = NULL;
7590
9b485d32 7591 /* We don't care about local symbols. */
252b5132
RH		 7592 if (r_index < symtab_hdr->sh_info)
7593 continue;
7594
9b485d32 7595 /* This is an external symbol. */
252b5132
RH		 7596 r_index -= symtab_hdr->sh_info;
7597 h = (struct elf_link_hash_entry *)
7598 elf_sym_hashes (abfd)[r_index];
7599
7600 /* If the relocation is against a static symbol it must be within
7601 the current section and so cannot be a cross ARM/Thumb relocation. */
7602 if (h == NULL)
7603 continue;
7604
d504ffc8
DJ		 7605 /* If the call will go through a PLT entry then we do not need
7606 glue. */
362d30a1 7607 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7608 continue;
7609
252b5132
RH		 7610 switch (r_type)
7611 {
7612 case R_ARM_PC24:
7613 /* This one is a call from arm code. We need to look up
99059e56
RM		 7614 the target of the call. If it is a thumb target, we
7615 insert glue. */
39d911fc
TP		 7616 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7617 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7618 record_arm_to_thumb_glue (link_info, h);
7619 break;
7620
252b5132 7621 default:
c6596c5e 7622 abort ();
252b5132
RH		 7623 }
7624 }
6cdc0ccc
AM		 7625
7626 if (contents != NULL
7627 && elf_section_data (sec)->this_hdr.contents != contents)
7628 free (contents);
7629 contents = NULL;
7630
7631 if (internal_relocs != NULL
7632 && elf_section_data (sec)->relocs != internal_relocs)
7633 free (internal_relocs);
7634 internal_relocs = NULL;
252b5132
RH		 7635 }
7636
b34976b6 7637 return TRUE;
9a5aca8c 7638
252b5132 7639error_return:
6cdc0ccc
AM		 7640 if (contents != NULL
7641 && elf_section_data (sec)->this_hdr.contents != contents)
7642 free (contents);
7643 if (internal_relocs != NULL
7644 && elf_section_data (sec)->relocs != internal_relocs)
7645 free (internal_relocs);
9a5aca8c 7646
b34976b6 7647 return FALSE;
252b5132 7648}
7e392df6 7649#endif
252b5132 7650
eb043451 7651
c7b8f16e
JB		 7652/* Initialise maps of ARM/Thumb/data for input BFDs. */
7653
7654void
7655bfd_elf32_arm_init_maps (bfd *abfd)
7656{
7657 Elf_Internal_Sym *isymbuf;
7658 Elf_Internal_Shdr *hdr;
7659 unsigned int i, localsyms;
7660
af1f4419
NC		 7661 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7662 if (! is_arm_elf (abfd))
7663 return;
7664
c7b8f16e
JB		 7665 if ((abfd->flags & DYNAMIC) != 0)
7666 return;
7667
0ffa91dd 7668 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7669 localsyms = hdr->sh_info;
7670
7671 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7672 should contain the number of local symbols, which should come before any
7673 global symbols. Mapping symbols are always local. */
7674 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7675 NULL);
7676
7677 /* No internal symbols read? Skip this BFD. */
7678 if (isymbuf == NULL)
7679 return;
7680
7681 for (i = 0; i < localsyms; i++)
7682 {
7683 Elf_Internal_Sym *isym = &isymbuf[i];
7684 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7685 const char *name;
906e58ca 7686
c7b8f16e 7687 if (sec != NULL
99059e56
RM		 7688 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7689 {
7690 name = bfd_elf_string_from_elf_section (abfd,
7691 hdr->sh_link, isym->st_name);
906e58ca 7692
99059e56 7693 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7694 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7695 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7696 }
c7b8f16e
JB		 7697 }
7698}
7699
7700
48229727
JB		 7701/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7702 say what they wanted. */
7703
7704void
7705bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7706{
7707 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7708 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7709
4dfe6ac6
NC		 7710 if (globals == NULL)
7711 return;
7712
48229727
JB		 7713 if (globals->fix_cortex_a8 == -1)
7714 {
7715 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7716 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7717 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7718 || out_attr[Tag_CPU_arch_profile].i == 0))
7719 globals->fix_cortex_a8 = 1;
7720 else
7721 globals->fix_cortex_a8 = 0;
7722 }
7723}
7724
7725
c7b8f16e
JB		 7726void
7727bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7728{
7729 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7730 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7731
4dfe6ac6
NC		 7732 if (globals == NULL)
7733 return;
c7b8f16e
JB		 7734 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7735 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7736 {
7737 switch (globals->vfp11_fix)
99059e56
RM		 7738 {
7739 case BFD_ARM_VFP11_FIX_DEFAULT:
7740 case BFD_ARM_VFP11_FIX_NONE:
7741 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7742 break;
7743
7744 default:
7745 /* Give a warning, but do as the user requests anyway. */
4eca0228 7746 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7747 "workaround is not necessary for target architecture"), obfd);
7748 }
c7b8f16e
JB		 7749 }
7750 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7751 /* For earlier architectures, we might need the workaround, but do not
7752 enable it by default. If users is running with broken hardware, they
7753 must enable the erratum fix explicitly. */
7754 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7755}
7756
a504d23a
LA		 7757void
7758bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7759{
7760 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7761 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7762
7763 if (globals == NULL)
7764 return;
7765
7766 /* We assume only Cortex-M4 may require the fix. */
7767 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7768 || out_attr[Tag_CPU_arch_profile].i != 'M')
7769 {
7770 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7771 /* Give a warning, but do as the user requests anyway. */
4eca0228 7772 _bfd_error_handler
a504d23a
LA		 7773 (_("%B: warning: selected STM32L4XX erratum "
7774 "workaround is not necessary for target architecture"), obfd);
7775 }
7776}
c7b8f16e 7777
906e58ca
NC		 7778enum bfd_arm_vfp11_pipe
7779{
c7b8f16e
JB		 7780 VFP11_FMAC,
7781 VFP11_LS,
7782 VFP11_DS,
7783 VFP11_BAD
7784};
7785
7786/* Return a VFP register number. This is encoded as RX:X for single-precision
7787 registers, or X:RX for double-precision registers, where RX is the group of
7788 four bits in the instruction encoding and X is the single extension bit.
7789 RX and X fields are specified using their lowest (starting) bit. The return
7790 value is:
7791
7792 0...31: single-precision registers s0...s31
7793 32...63: double-precision registers d0...d31.
906e58ca 7794
c7b8f16e
JB		 7795 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7796 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7797
c7b8f16e
JB		 7798static unsigned int
7799bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7800 unsigned int x)
c7b8f16e
JB		 7801{
7802 if (is_double)
7803 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7804 else
7805 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7806}
7807
7808/* Set bits in *WMASK according to a register number REG as encoded by
7809 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7810
7811static void
7812bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7813{
7814 if (reg < 32)
7815 *wmask |= 1 << reg;
7816 else if (reg < 48)
7817 *wmask |= 3 << ((reg - 32) * 2);
7818}
7819
7820/* Return TRUE if WMASK overwrites anything in REGS. */
7821
7822static bfd_boolean
7823bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7824{
7825 int i;
906e58ca 7826
c7b8f16e
JB		 7827 for (i = 0; i < numregs; i++)
7828 {
7829 unsigned int reg = regs[i];
7830
7831 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7832 return TRUE;
906e58ca 7833
c7b8f16e
JB		 7834 reg -= 32;
7835
7836 if (reg >= 16)
99059e56 7837 continue;
906e58ca 7838
c7b8f16e 7839 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7840 return TRUE;
c7b8f16e 7841 }
906e58ca 7842
c7b8f16e
JB		 7843 return FALSE;
7844}
7845
7846/* In this function, we're interested in two things: finding input registers
7847 for VFP data-processing instructions, and finding the set of registers which
7848 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7849 hold the written set, so FLDM etc. are easy to deal with (we're only
7850 interested in 32 SP registers or 16 dp registers, due to the VFP version
7851 implemented by the chip in question). DP registers are marked by setting
7852 both SP registers in the write mask). */
7853
7854static enum bfd_arm_vfp11_pipe
7855bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7856 int *numregs)
c7b8f16e 7857{
91d6fa6a 7858 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7859 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7860
7861 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7862 {
7863 unsigned int pqrs;
7864 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7865 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7866
7867 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7868 | ((insn & 0x00300000) >> 19)
7869 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7870
7871 switch (pqrs)
99059e56
RM		 7872 {
7873 case 0: /* fmac[sd]. */
7874 case 1: /* fnmac[sd]. */
7875 case 2: /* fmsc[sd]. */
7876 case 3: /* fnmsc[sd]. */
7877 vpipe = VFP11_FMAC;
7878 bfd_arm_vfp11_write_mask (destmask, fd);
7879 regs[0] = fd;
7880 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7881 regs[2] = fm;
7882 *numregs = 3;
7883 break;
7884
7885 case 4: /* fmul[sd]. */
7886 case 5: /* fnmul[sd]. */
7887 case 6: /* fadd[sd]. */
7888 case 7: /* fsub[sd]. */
7889 vpipe = VFP11_FMAC;
7890 goto vfp_binop;
7891
7892 case 8: /* fdiv[sd]. */
7893 vpipe = VFP11_DS;
7894 vfp_binop:
7895 bfd_arm_vfp11_write_mask (destmask, fd);
7896 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7897 regs[1] = fm;
7898 *numregs = 2;
7899 break;
7900
7901 case 15: /* extended opcode. */
7902 {
7903 unsigned int extn = ((insn >> 15) & 0x1e)
7904 | ((insn >> 7) & 1);
7905
7906 switch (extn)
7907 {
7908 case 0: /* fcpy[sd]. */
7909 case 1: /* fabs[sd]. */
7910 case 2: /* fneg[sd]. */
7911 case 8: /* fcmp[sd]. */
7912 case 9: /* fcmpe[sd]. */
7913 case 10: /* fcmpz[sd]. */
7914 case 11: /* fcmpez[sd]. */
7915 case 16: /* fuito[sd]. */
7916 case 17: /* fsito[sd]. */
7917 case 24: /* ftoui[sd]. */
7918 case 25: /* ftouiz[sd]. */
7919 case 26: /* ftosi[sd]. */
7920 case 27: /* ftosiz[sd]. */
7921 /* These instructions will not bounce due to underflow. */
7922 *numregs = 0;
7923 vpipe = VFP11_FMAC;
7924 break;
7925
7926 case 3: /* fsqrt[sd]. */
7927 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7928 registers to cause the erratum in previous instructions. */
7929 bfd_arm_vfp11_write_mask (destmask, fd);
7930 vpipe = VFP11_DS;
7931 break;
7932
7933 case 15: /* fcvt{ds,sd}. */
7934 {
7935 int rnum = 0;
7936
7937 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7938
7939 /* Only FCVTSD can underflow. */
99059e56
RM		 7940 if ((insn & 0x100) != 0)
7941 regs[rnum++] = fm;
c7b8f16e 7942
99059e56 7943 *numregs = rnum;
c7b8f16e 7944
99059e56
RM		 7945 vpipe = VFP11_FMAC;
7946 }
7947 break;
c7b8f16e 7948
99059e56
RM		 7949 default:
7950 return VFP11_BAD;
7951 }
7952 }
7953 break;
c7b8f16e 7954
99059e56
RM		 7955 default:
7956 return VFP11_BAD;
7957 }
c7b8f16e
JB		 7958 }
7959 /* Two-register transfer. */
7960 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7961 {
7962 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7963
c7b8f16e
JB		 7964 if ((insn & 0x100000) == 0)
7965 {
99059e56
RM		 7966 if (is_double)
7967 bfd_arm_vfp11_write_mask (destmask, fm);
7968 else
7969 {
7970 bfd_arm_vfp11_write_mask (destmask, fm);
7971 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7972 }
c7b8f16e
JB		 7973 }
7974
91d6fa6a 7975 vpipe = VFP11_LS;
c7b8f16e
JB		 7976 }
7977 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7978 {
7979 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7980 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7981
c7b8f16e 7982 switch (puw)
99059e56
RM		 7983 {
7984 case 0: /* Two-reg transfer. We should catch these above. */
7985 abort ();
906e58ca 7986
99059e56
RM		 7987 case 2: /* fldm[sdx]. */
7988 case 3:
7989 case 5:
7990 {
7991 unsigned int i, offset = insn & 0xff;
c7b8f16e 7992
99059e56
RM		 7993 if (is_double)
7994 offset >>= 1;
c7b8f16e 7995
99059e56
RM		 7996 for (i = fd; i < fd + offset; i++)
7997 bfd_arm_vfp11_write_mask (destmask, i);
7998 }
7999 break;
906e58ca 8000
99059e56
RM		 8001 case 4: /* fld[sd]. */
8002 case 6:
8003 bfd_arm_vfp11_write_mask (destmask, fd);
8004 break;
906e58ca 8005
99059e56
RM		 8006 default:
8007 return VFP11_BAD;
8008 }
c7b8f16e 8009
91d6fa6a 8010 vpipe = VFP11_LS;
c7b8f16e
JB		 8011 }
8012 /* Single-register transfer. Note L==0. */
8013 else if ((insn & 0x0f100e10) == 0x0e000a10)
8014 {
8015 unsigned int opcode = (insn >> 21) & 7;
8016 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8017
8018 switch (opcode)
99059e56
RM		 8019 {
8020 case 0: /* fmsr/fmdlr. */
8021 case 1: /* fmdhr. */
8022 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8023 destination register. I don't know if this is exactly right,
8024 but it is the conservative choice. */
8025 bfd_arm_vfp11_write_mask (destmask, fn);
8026 break;
8027
8028 case 7: /* fmxr. */
8029 break;
8030 }
c7b8f16e 8031
91d6fa6a 8032 vpipe = VFP11_LS;
c7b8f16e
JB		 8033 }
8034
91d6fa6a 8035 return vpipe;
c7b8f16e
JB		 8036}
8037
8038
8039static int elf32_arm_compare_mapping (const void * a, const void * b);
8040
8041
8042/* Look for potentially-troublesome code sequences which might trigger the
8043 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8044 (available from ARM) for details of the erratum. A short version is
8045 described in ld.texinfo. */
8046
8047bfd_boolean
8048bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8049{
8050 asection *sec;
8051 bfd_byte *contents = NULL;
8052 int state = 0;
8053 int regs[3], numregs = 0;
8054 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8055 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8056
4dfe6ac6
NC		 8057 if (globals == NULL)
8058 return FALSE;
8059
c7b8f16e
JB		 8060 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8061 The states transition as follows:
906e58ca 8062
c7b8f16e 8063 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8064 A VFP FMAC-pipeline instruction has been seen. Fill
8065 regs[0]..regs[numregs-1] with its input operands. Remember this
8066 instruction in 'first_fmac'.
c7b8f16e
JB		 8067
8068 1 -> 2
99059e56
RM		 8069 Any instruction, except for a VFP instruction which overwrites
8070 regs[*].
906e58ca 8071
c7b8f16e
JB		 8072 1 -> 3 [ -> 0 ] or
8073 2 -> 3 [ -> 0 ]
99059e56
RM		 8074 A VFP instruction has been seen which overwrites any of regs[*].
8075 We must make a veneer! Reset state to 0 before examining next
8076 instruction.
906e58ca 8077
c7b8f16e 8078 2 -> 0
99059e56
RM		 8079 If we fail to match anything in state 2, reset to state 0 and reset
8080 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8081
8082 If the VFP11 vector mode is in use, there must be at least two unrelated
8083 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8084 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8085
8086 /* If we are only performing a partial link do not bother
8087 to construct any glue. */
0e1862bb 8088 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8089 return TRUE;
8090
0ffa91dd
NC		 8091 /* Skip if this bfd does not correspond to an ELF image. */
8092 if (! is_arm_elf (abfd))
8093 return TRUE;
906e58ca 8094
c7b8f16e
JB		 8095 /* We should have chosen a fix type by the time we get here. */
8096 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8097
8098 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8099 return TRUE;
2e6030b9 8100
33a7ffc2
JM		 8101 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8102 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8103 return TRUE;
8104
c7b8f16e
JB		 8105 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8106 {
8107 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8108 struct _arm_elf_section_data *sec_data;
8109
8110 /* If we don't have executable progbits, we're not interested in this
99059e56 8111 section. Also skip if section is to be excluded. */
c7b8f16e 8112 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8113 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8114 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8115 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8116 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8117 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8118 continue;
c7b8f16e
JB		 8119
8120 sec_data = elf32_arm_section_data (sec);
906e58ca 8121
c7b8f16e 8122 if (sec_data->mapcount == 0)
99059e56 8123 continue;
906e58ca 8124
c7b8f16e
JB		 8125 if (elf_section_data (sec)->this_hdr.contents != NULL)
8126 contents = elf_section_data (sec)->this_hdr.contents;
8127 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8128 goto error_return;
8129
8130 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8131 elf32_arm_compare_mapping);
8132
8133 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8134 {
8135 unsigned int span_start = sec_data->map[span].vma;
8136 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8137 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8138 char span_type = sec_data->map[span].type;
8139
8140 /* FIXME: Only ARM mode is supported at present. We may need to
8141 support Thumb-2 mode also at some point. */
8142 if (span_type != 'a')
8143 continue;
8144
8145 for (i = span_start; i < span_end;)
8146 {
8147 unsigned int next_i = i + 4;
8148 unsigned int insn = bfd_big_endian (abfd)
8149 ? (contents[i] << 24)
8150 | (contents[i + 1] << 16)
8151 | (contents[i + 2] << 8)
8152 | contents[i + 3]
8153 : (contents[i + 3] << 24)
8154 | (contents[i + 2] << 16)
8155 | (contents[i + 1] << 8)
8156 | contents[i];
8157 unsigned int writemask = 0;
8158 enum bfd_arm_vfp11_pipe vpipe;
8159
8160 switch (state)
8161 {
8162 case 0:
8163 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8164 &numregs);
8165 /* I'm assuming the VFP11 erratum can trigger with denorm
8166 operands on either the FMAC or the DS pipeline. This might
8167 lead to slightly overenthusiastic veneer insertion. */
8168 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8169 {
8170 state = use_vector ? 1 : 2;
8171 first_fmac = i;
8172 veneer_of_insn = insn;
8173 }
8174 break;
8175
8176 case 1:
8177 {
8178 int other_regs[3], other_numregs;
8179 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8180 other_regs,
99059e56
RM		 8181 &other_numregs);
8182 if (vpipe != VFP11_BAD
8183 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8184 numregs))
99059e56
RM		 8185 state = 3;
8186 else
8187 state = 2;
8188 }
8189 break;
8190
8191 case 2:
8192 {
8193 int other_regs[3], other_numregs;
8194 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8195 other_regs,
99059e56
RM		 8196 &other_numregs);
8197 if (vpipe != VFP11_BAD
8198 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8199 numregs))
99059e56
RM		 8200 state = 3;
8201 else
8202 {
8203 state = 0;
8204 next_i = first_fmac + 4;
8205 }
8206 }
8207 break;
8208
8209 case 3:
8210 abort (); /* Should be unreachable. */
8211 }
8212
8213 if (state == 3)
8214 {
8215 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8216 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8217
8218 elf32_arm_section_data (sec)->erratumcount += 1;
8219
8220 newerr->u.b.vfp_insn = veneer_of_insn;
8221
8222 switch (span_type)
8223 {
8224 case 'a':
8225 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8226 break;
8227
8228 default:
8229 abort ();
8230 }
8231
8232 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8233 first_fmac);
8234
99059e56 8235 newerr->vma = -1;
c7b8f16e 8236
99059e56
RM		 8237 newerr->next = sec_data->erratumlist;
8238 sec_data->erratumlist = newerr;
c7b8f16e 8239
99059e56
RM		 8240 state = 0;
8241 }
c7b8f16e 8242
99059e56
RM		 8243 i = next_i;
8244 }
8245 }
906e58ca 8246
c7b8f16e 8247 if (contents != NULL
99059e56
RM		 8248 && elf_section_data (sec)->this_hdr.contents != contents)
8249 free (contents);
c7b8f16e
JB		 8250 contents = NULL;
8251 }
8252
8253 return TRUE;
8254
8255error_return:
8256 if (contents != NULL
8257 && elf_section_data (sec)->this_hdr.contents != contents)
8258 free (contents);
906e58ca 8259
c7b8f16e
JB		 8260 return FALSE;
8261}
8262
8263/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8264 after sections have been laid out, using specially-named symbols. */
8265
8266void
8267bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8268 struct bfd_link_info *link_info)
8269{
8270 asection *sec;
8271 struct elf32_arm_link_hash_table *globals;
8272 char *tmp_name;
906e58ca 8273
0e1862bb 8274 if (bfd_link_relocatable (link_info))
c7b8f16e 8275 return;
2e6030b9
MS		 8276
8277 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8278 if (! is_arm_elf (abfd))
2e6030b9
MS		 8279 return;
8280
c7b8f16e 8281 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8282 if (globals == NULL)
8283 return;
906e58ca 8284
21d799b5 8285 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8286 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8287
8288 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8289 {
8290 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8291 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8292
c7b8f16e 8293 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8294 {
8295 struct elf_link_hash_entry *myh;
8296 bfd_vma vma;
8297
8298 switch (errnode->type)
8299 {
8300 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8301 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8302 /* Find veneer symbol. */
8303 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8304 errnode->u.b.veneer->u.v.id);
8305
99059e56
RM		 8306 myh = elf_link_hash_lookup
8307 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8308
a504d23a 8309 if (myh == NULL)
4eca0228
AM		 8310 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8311 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8312
8313 vma = myh->root.u.def.section->output_section->vma
8314 + myh->root.u.def.section->output_offset
8315 + myh->root.u.def.value;
8316
8317 errnode->u.b.veneer->vma = vma;
8318 break;
8319
8320 case VFP11_ERRATUM_ARM_VENEER:
8321 case VFP11_ERRATUM_THUMB_VENEER:
8322 /* Find return location. */
8323 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8324 errnode->u.v.id);
8325
8326 myh = elf_link_hash_lookup
8327 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8328
8329 if (myh == NULL)
4eca0228
AM		 8330 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8331 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8332
8333 vma = myh->root.u.def.section->output_section->vma
8334 + myh->root.u.def.section->output_offset
8335 + myh->root.u.def.value;
8336
8337 errnode->u.v.branch->vma = vma;
8338 break;
8339
8340 default:
8341 abort ();
8342 }
8343 }
8344 }
8345
8346 free (tmp_name);
8347}
8348
8349/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8350 return locations after sections have been laid out, using
8351 specially-named symbols. */
8352
8353void
8354bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8355 struct bfd_link_info *link_info)
8356{
8357 asection *sec;
8358 struct elf32_arm_link_hash_table *globals;
8359 char *tmp_name;
8360
8361 if (bfd_link_relocatable (link_info))
8362 return;
8363
8364 /* Skip if this bfd does not correspond to an ELF image. */
8365 if (! is_arm_elf (abfd))
8366 return;
8367
8368 globals = elf32_arm_hash_table (link_info);
8369 if (globals == NULL)
8370 return;
8371
8372 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8373 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8374
8375 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8376 {
8377 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8378 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8379
8380 for (; errnode != NULL; errnode = errnode->next)
8381 {
8382 struct elf_link_hash_entry *myh;
8383 bfd_vma vma;
8384
8385 switch (errnode->type)
8386 {
8387 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8388 /* Find veneer symbol. */
8389 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8390 errnode->u.b.veneer->u.v.id);
8391
8392 myh = elf_link_hash_lookup
8393 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8394
8395 if (myh == NULL)
4eca0228
AM		 8396 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8397 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8398
8399 vma = myh->root.u.def.section->output_section->vma
8400 + myh->root.u.def.section->output_offset
8401 + myh->root.u.def.value;
8402
8403 errnode->u.b.veneer->vma = vma;
8404 break;
8405
8406 case STM32L4XX_ERRATUM_VENEER:
8407 /* Find return location. */
8408 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8409 errnode->u.v.id);
8410
8411 myh = elf_link_hash_lookup
8412 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8413
8414 if (myh == NULL)
4eca0228
AM		 8415 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8416 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8417
8418 vma = myh->root.u.def.section->output_section->vma
8419 + myh->root.u.def.section->output_offset
8420 + myh->root.u.def.value;
8421
8422 errnode->u.v.branch->vma = vma;
8423 break;
8424
8425 default:
8426 abort ();
8427 }
8428 }
8429 }
8430
8431 free (tmp_name);
8432}
8433
8434static inline bfd_boolean
8435is_thumb2_ldmia (const insn32 insn)
8436{
8437 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8438 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8439 return (insn & 0xffd02000) == 0xe8900000;
8440}
8441
8442static inline bfd_boolean
8443is_thumb2_ldmdb (const insn32 insn)
8444{
8445 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8446 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8447 return (insn & 0xffd02000) == 0xe9100000;
8448}
8449
8450static inline bfd_boolean
8451is_thumb2_vldm (const insn32 insn)
8452{
8453 /* A6.5 Extension register load or store instruction
8454 A7.7.229
9239bbd3
CM		 8455 We look for SP 32-bit and DP 64-bit registers.
8456 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8457 <list> is consecutive 64-bit registers
8458 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8459 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8460 <list> is consecutive 32-bit registers
8461 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8462 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8463 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8464 return
9239bbd3
CM		 8465 (((insn & 0xfe100f00) == 0xec100b00) ||
8466 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8467 && /* (IA without !). */
8468 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8469 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8470 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8471 /* (DB with !). */
8472 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8473}
8474
8475/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8476 VLDM opcode and:
8477 - computes the number and the mode of memory accesses
8478 - decides if the replacement should be done:
8479 . replaces only if > 8-word accesses
8480 . or (testing purposes only) replaces all accesses. */
8481
8482static bfd_boolean
8483stm32l4xx_need_create_replacing_stub (const insn32 insn,
8484 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8485{
9239bbd3 8486 int nb_words = 0;
a504d23a
LA		 8487
8488 /* The field encoding the register list is the same for both LDMIA
8489 and LDMDB encodings. */
8490 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8491 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8492 else if (is_thumb2_vldm (insn))
9239bbd3 8493 nb_words = (insn & 0xff);
a504d23a
LA		 8494
8495 /* DEFAULT mode accounts for the real bug condition situation,
8496 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8497 return
9239bbd3 8498 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8499 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8500}
8501
8502/* Look for potentially-troublesome code sequences which might trigger
8503 the STM STM32L4XX erratum. */
8504
8505bfd_boolean
8506bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8507 struct bfd_link_info *link_info)
8508{
8509 asection *sec;
8510 bfd_byte *contents = NULL;
8511 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8512
8513 if (globals == NULL)
8514 return FALSE;
8515
8516 /* If we are only performing a partial link do not bother
8517 to construct any glue. */
8518 if (bfd_link_relocatable (link_info))
8519 return TRUE;
8520
8521 /* Skip if this bfd does not correspond to an ELF image. */
8522 if (! is_arm_elf (abfd))
8523 return TRUE;
8524
8525 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8526 return TRUE;
8527
8528 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8529 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8530 return TRUE;
8531
8532 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8533 {
8534 unsigned int i, span;
8535 struct _arm_elf_section_data *sec_data;
8536
8537 /* If we don't have executable progbits, we're not interested in this
8538 section. Also skip if section is to be excluded. */
8539 if (elf_section_type (sec) != SHT_PROGBITS
8540 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8541 || (sec->flags & SEC_EXCLUDE) != 0
8542 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8543 || sec->output_section == bfd_abs_section_ptr
8544 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8545 continue;
8546
8547 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8548
a504d23a
LA		 8549 if (sec_data->mapcount == 0)
8550 continue;
c7b8f16e 8551
a504d23a
LA		 8552 if (elf_section_data (sec)->this_hdr.contents != NULL)
8553 contents = elf_section_data (sec)->this_hdr.contents;
8554 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8555 goto error_return;
c7b8f16e 8556
a504d23a
LA		 8557 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8558 elf32_arm_compare_mapping);
c7b8f16e 8559
a504d23a
LA		 8560 for (span = 0; span < sec_data->mapcount; span++)
8561 {
8562 unsigned int span_start = sec_data->map[span].vma;
8563 unsigned int span_end = (span == sec_data->mapcount - 1)
8564 ? sec->size : sec_data->map[span + 1].vma;
8565 char span_type = sec_data->map[span].type;
8566 int itblock_current_pos = 0;
c7b8f16e 8567
a504d23a
LA		 8568 /* Only Thumb2 mode need be supported with this CM4 specific
8569 code, we should not encounter any arm mode eg span_type
8570 != 'a'. */
8571 if (span_type != 't')
8572 continue;
c7b8f16e 8573
a504d23a
LA		 8574 for (i = span_start; i < span_end;)
8575 {
8576 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8577 bfd_boolean insn_32bit = FALSE;
8578 bfd_boolean is_ldm = FALSE;
8579 bfd_boolean is_vldm = FALSE;
8580 bfd_boolean is_not_last_in_it_block = FALSE;
8581
8582 /* The first 16-bits of all 32-bit thumb2 instructions start
8583 with opcode[15..13]=0b111 and the encoded op1 can be anything
8584 except opcode[12..11]!=0b00.
8585 See 32-bit Thumb instruction encoding. */
8586 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8587 insn_32bit = TRUE;
c7b8f16e 8588
a504d23a
LA		 8589 /* Compute the predicate that tells if the instruction
8590 is concerned by the IT block
8591 - Creates an error if there is a ldm that is not
8592 last in the IT block thus cannot be replaced
8593 - Otherwise we can create a branch at the end of the
8594 IT block, it will be controlled naturally by IT
8595 with the proper pseudo-predicate
8596 - So the only interesting predicate is the one that
8597 tells that we are not on the last item of an IT
8598 block. */
8599 if (itblock_current_pos != 0)
8600 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8601
a504d23a
LA		 8602 if (insn_32bit)
8603 {
8604 /* Load the rest of the insn (in manual-friendly order). */
8605 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8606 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8607 is_vldm = is_thumb2_vldm (insn);
8608
8609 /* Veneers are created for (v)ldm depending on
8610 option flags and memory accesses conditions; but
8611 if the instruction is not the last instruction of
8612 an IT block, we cannot create a jump there, so we
8613 bail out. */
5025eb7c
AO		 8614 if ((is_ldm || is_vldm)
8615 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8616 (insn, globals->stm32l4xx_fix))
8617 {
8618 if (is_not_last_in_it_block)
8619 {
4eca0228 8620 _bfd_error_handler
a504d23a 8621 /* Note - overlong line used here to allow for translation. */
695344c0 8622 /* xgettext:c-format */
a504d23a
LA		 8623 (_("\
8624%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8625 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
695344c0 8626 abfd, sec, (long) i);
a504d23a
LA		 8627 }
8628 else
8629 {
8630 elf32_stm32l4xx_erratum_list *newerr =
8631 (elf32_stm32l4xx_erratum_list *)
8632 bfd_zmalloc
8633 (sizeof (elf32_stm32l4xx_erratum_list));
8634
8635 elf32_arm_section_data (sec)
8636 ->stm32l4xx_erratumcount += 1;
8637 newerr->u.b.insn = insn;
8638 /* We create only thumb branches. */
8639 newerr->type =
8640 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8641 record_stm32l4xx_erratum_veneer
8642 (link_info, newerr, abfd, sec,
8643 i,
8644 is_ldm ?
8645 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8646 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8647 newerr->vma = -1;
8648 newerr->next = sec_data->stm32l4xx_erratumlist;
8649 sec_data->stm32l4xx_erratumlist = newerr;
8650 }
8651 }
8652 }
8653 else
8654 {
8655 /* A7.7.37 IT p208
8656 IT blocks are only encoded in T1
8657 Encoding T1: IT{x{y{z}}} <firstcond>
8658 1 0 1 1 - 1 1 1 1 - firstcond - mask
8659 if mask = '0000' then see 'related encodings'
8660 We don't deal with UNPREDICTABLE, just ignore these.
8661 There can be no nested IT blocks so an IT block
8662 is naturally a new one for which it is worth
8663 computing its size. */
5025eb7c
AO		 8664 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8665 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8666 /* If we have a new IT block we compute its size. */
8667 if (is_newitblock)
8668 {
8669 /* Compute the number of instructions controlled
8670 by the IT block, it will be used to decide
8671 whether we are inside an IT block or not. */
8672 unsigned int mask = insn & 0x000f;
8673 itblock_current_pos = 4 - ctz (mask);
8674 }
8675 }
8676
8677 i += insn_32bit ? 4 : 2;
99059e56
RM		 8678 }
8679 }
a504d23a
LA		 8680
8681 if (contents != NULL
8682 && elf_section_data (sec)->this_hdr.contents != contents)
8683 free (contents);
8684 contents = NULL;
c7b8f16e 8685 }
906e58ca 8686
a504d23a
LA		 8687 return TRUE;
8688
8689error_return:
8690 if (contents != NULL
8691 && elf_section_data (sec)->this_hdr.contents != contents)
8692 free (contents);
c7b8f16e 8693
a504d23a
LA		 8694 return FALSE;
8695}
c7b8f16e 8696
eb043451
PB		 8697/* Set target relocation values needed during linking. */
8698
8699void
68c39892 8700bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8701 struct bfd_link_info *link_info,
68c39892 8702 struct elf32_arm_params *params)
eb043451
PB		 8703{
8704 struct elf32_arm_link_hash_table *globals;
8705
8706 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8707 if (globals == NULL)
8708 return;
eb043451 8709
68c39892
TP		 8710 globals->target1_is_rel = params->target1_is_rel;
8711 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8712 globals->target2_reloc = R_ARM_REL32;
68c39892 8713 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8714 globals->target2_reloc = R_ARM_ABS32;
68c39892 8715 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8716 globals->target2_reloc = R_ARM_GOT_PREL;
8717 else
8718 {
8719 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8720 params->target2_type);
eb043451 8721 }
68c39892
TP		 8722 globals->fix_v4bx = params->fix_v4bx;
8723 globals->use_blx |= params->use_blx;
8724 globals->vfp11_fix = params->vfp11_denorm_fix;
8725 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8726 globals->pic_veneer = params->pic_veneer;
8727 globals->fix_cortex_a8 = params->fix_cortex_a8;
8728 globals->fix_arm1176 = params->fix_arm1176;
8729 globals->cmse_implib = params->cmse_implib;
8730 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8731
0ffa91dd 8732 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8733 elf_arm_tdata (output_bfd)->no_enum_size_warning
8734 = params->no_enum_size_warning;
8735 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8736 = params->no_wchar_size_warning;
eb043451 8737}
eb043451 8738
12a0a0fd 8739/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8740
12a0a0fd
PB		 8741static void
8742insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8743{
8744 bfd_vma upper;
8745 bfd_vma lower;
8746 int reloc_sign;
8747
8748 BFD_ASSERT ((offset & 1) == 0);
8749
8750 upper = bfd_get_16 (abfd, insn);
8751 lower = bfd_get_16 (abfd, insn + 2);
8752 reloc_sign = (offset < 0) ? 1 : 0;
8753 upper = (upper & ~(bfd_vma) 0x7ff)
8754 | ((offset >> 12) & 0x3ff)
8755 | (reloc_sign << 10);
906e58ca 8756 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8757 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8758 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8759 | ((offset >> 1) & 0x7ff);
8760 bfd_put_16 (abfd, upper, insn);
8761 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8762}
8763
9b485d32
NC		 8764/* Thumb code calling an ARM function. */
8765
252b5132 8766static int
57e8b36a
NC		 8767elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8768 const char * name,
8769 bfd * input_bfd,
8770 bfd * output_bfd,
8771 asection * input_section,
8772 bfd_byte * hit_data,
8773 asection * sym_sec,
8774 bfd_vma offset,
8775 bfd_signed_vma addend,
f2a9dd69
DJ		 8776 bfd_vma val,
8777 char **error_message)
252b5132 8778{
bcbdc74c 8779 asection * s = 0;
dc810e39 8780 bfd_vma my_offset;
252b5132 8781 long int ret_offset;
bcbdc74c
NC		 8782 struct elf_link_hash_entry * myh;
8783 struct elf32_arm_link_hash_table * globals;
252b5132 8784
f2a9dd69 8785 myh = find_thumb_glue (info, name, error_message);
252b5132 8786 if (myh == NULL)
b34976b6 8787 return FALSE;
252b5132
RH		 8788
8789 globals = elf32_arm_hash_table (info);
252b5132
RH		 8790 BFD_ASSERT (globals != NULL);
8791 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8792
8793 my_offset = myh->root.u.def.value;
8794
3d4d4302
AM		 8795 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8796 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8797
8798 BFD_ASSERT (s != NULL);
8799 BFD_ASSERT (s->contents != NULL);
8800 BFD_ASSERT (s->output_section != NULL);
8801
8802 if ((my_offset & 0x01) == 0x01)
8803 {
8804 if (sym_sec != NULL
8805 && sym_sec->owner != NULL
8806 && !INTERWORK_FLAG (sym_sec->owner))
8807 {
4eca0228 8808 _bfd_error_handler
d003868e 8809 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8810 " first occurrence: %B: Thumb call to ARM"),
d003868e 8811 sym_sec->owner, input_bfd, name);
252b5132 8812
b34976b6 8813 return FALSE;
252b5132
RH		 8814 }
8815
8816 --my_offset;
8817 myh->root.u.def.value = my_offset;
8818
52ab56c2
PB		 8819 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8820 s->contents + my_offset);
252b5132 8821
52ab56c2
PB		 8822 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8823 s->contents + my_offset + 2);
252b5132
RH		 8824
8825 ret_offset =
9b485d32
NC		 8826 /* Address of destination of the stub. */
8827 ((bfd_signed_vma) val)
252b5132 8828 - ((bfd_signed_vma)
57e8b36a
NC		 8829 /* Offset from the start of the current section
8830 to the start of the stubs. */
9b485d32
NC		 8831 (s->output_offset
8832 /* Offset of the start of this stub from the start of the stubs. */
8833 + my_offset
8834 /* Address of the start of the current section. */
8835 + s->output_section->vma)
8836 /* The branch instruction is 4 bytes into the stub. */
8837 + 4
8838 /* ARM branches work from the pc of the instruction + 8. */
8839 + 8);
252b5132 8840
52ab56c2
PB		 8841 put_arm_insn (globals, output_bfd,
8842 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8843 s->contents + my_offset + 4);
252b5132
RH		 8844 }
8845
8846 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8847
427bfd90
NC		 8848 /* Now go back and fix up the original BL insn to point to here. */
8849 ret_offset =
8850 /* Address of where the stub is located. */
8851 (s->output_section->vma + s->output_offset + my_offset)
8852 /* Address of where the BL is located. */
57e8b36a
NC		 8853 - (input_section->output_section->vma + input_section->output_offset
8854 + offset)
427bfd90
NC		 8855 /* Addend in the relocation. */
8856 - addend
8857 /* Biassing for PC-relative addressing. */
8858 - 8;
252b5132 8859
12a0a0fd 8860 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8861
b34976b6 8862 return TRUE;
252b5132
RH		 8863}
8864
a4fd1a8e 8865/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8866
a4fd1a8e
PB		 8867static struct elf_link_hash_entry *
8868elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8869 const char * name,
8870 bfd * input_bfd,
8871 bfd * output_bfd,
8872 asection * sym_sec,
8873 bfd_vma val,
8029a119
NC		 8874 asection * s,
8875 char ** error_message)
252b5132 8876{
dc810e39 8877 bfd_vma my_offset;
252b5132 8878 long int ret_offset;
bcbdc74c
NC		 8879 struct elf_link_hash_entry * myh;
8880 struct elf32_arm_link_hash_table * globals;
252b5132 8881
f2a9dd69 8882 myh = find_arm_glue (info, name, error_message);
252b5132 8883 if (myh == NULL)
a4fd1a8e 8884 return NULL;
252b5132
RH		 8885
8886 globals = elf32_arm_hash_table (info);
252b5132
RH		 8887 BFD_ASSERT (globals != NULL);
8888 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8889
8890 my_offset = myh->root.u.def.value;
252b5132
RH		 8891
8892 if ((my_offset & 0x01) == 0x01)
8893 {
8894 if (sym_sec != NULL
8895 && sym_sec->owner != NULL
8896 && !INTERWORK_FLAG (sym_sec->owner))
8897 {
4eca0228 8898 _bfd_error_handler
d003868e
AM		 8899 (_("%B(%s): warning: interworking not enabled.\n"
8900 " first occurrence: %B: arm call to thumb"),
8901 sym_sec->owner, input_bfd, name);
252b5132 8902 }
9b485d32 8903
252b5132
RH		 8904 --my_offset;
8905 myh->root.u.def.value = my_offset;
8906
0e1862bb
L		 8907 if (bfd_link_pic (info)
8908 || globals->root.is_relocatable_executable
27e55c4d 8909 || globals->pic_veneer)
8f6277f5
PB		 8910 {
8911 /* For relocatable objects we can't use absolute addresses,
8912 so construct the address from a relative offset. */
8913 /* TODO: If the offset is small it's probably worth
8914 constructing the address with adds. */
52ab56c2
PB		 8915 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8916 s->contents + my_offset);
8917 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8918 s->contents + my_offset + 4);
8919 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8920 s->contents + my_offset + 8);
8f6277f5
PB		 8921 /* Adjust the offset by 4 for the position of the add,
8922 and 8 for the pipeline offset. */
8923 ret_offset = (val - (s->output_offset
8924 + s->output_section->vma
8925 + my_offset + 12))
8926 | 1;
8927 bfd_put_32 (output_bfd, ret_offset,
8928 s->contents + my_offset + 12);
8929 }
26079076
PB		 8930 else if (globals->use_blx)
8931 {
8932 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8933 s->contents + my_offset);
8934
8935 /* It's a thumb address. Add the low order bit. */
8936 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8937 s->contents + my_offset + 4);
8938 }
8f6277f5
PB		 8939 else
8940 {
52ab56c2
PB		 8941 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8942 s->contents + my_offset);
252b5132 8943
52ab56c2
PB		 8944 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8945 s->contents + my_offset + 4);
252b5132 8946
8f6277f5
PB		 8947 /* It's a thumb address. Add the low order bit. */
8948 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8949 s->contents + my_offset + 8);
8029a119
NC		 8950
8951 my_offset += 12;
8f6277f5 8952 }
252b5132
RH		 8953 }
8954
8955 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8956
a4fd1a8e
PB		 8957 return myh;
8958}
8959
8960/* Arm code calling a Thumb function. */
8961
8962static int
8963elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8964 const char * name,
8965 bfd * input_bfd,
8966 bfd * output_bfd,
8967 asection * input_section,
8968 bfd_byte * hit_data,
8969 asection * sym_sec,
8970 bfd_vma offset,
8971 bfd_signed_vma addend,
f2a9dd69
DJ		 8972 bfd_vma val,
8973 char **error_message)
a4fd1a8e
PB		 8974{
8975 unsigned long int tmp;
8976 bfd_vma my_offset;
8977 asection * s;
8978 long int ret_offset;
8979 struct elf_link_hash_entry * myh;
8980 struct elf32_arm_link_hash_table * globals;
8981
8982 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8983 BFD_ASSERT (globals != NULL);
8984 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8985
3d4d4302
AM		 8986 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8987 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8988 BFD_ASSERT (s != NULL);
8989 BFD_ASSERT (s->contents != NULL);
8990 BFD_ASSERT (s->output_section != NULL);
8991
8992 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8993 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8994 if (!myh)
8995 return FALSE;
8996
8997 my_offset = myh->root.u.def.value;
252b5132
RH		 8998 tmp = bfd_get_32 (input_bfd, hit_data);
8999 tmp = tmp & 0xFF000000;
9000
9b485d32 9001 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9002 ret_offset = (s->output_offset
9003 + my_offset
9004 + s->output_section->vma
9005 - (input_section->output_offset
9006 + input_section->output_section->vma
9007 + offset + addend)
9008 - 8);
9a5aca8c 9009
252b5132
RH		 9010 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9011
dc810e39 9012 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9013
b34976b6 9014 return TRUE;
252b5132
RH		 9015}
9016
a4fd1a8e
PB		 9017/* Populate Arm stub for an exported Thumb function. */
9018
9019static bfd_boolean
9020elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9021{
9022 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9023 asection * s;
9024 struct elf_link_hash_entry * myh;
9025 struct elf32_arm_link_hash_entry *eh;
9026 struct elf32_arm_link_hash_table * globals;
9027 asection *sec;
9028 bfd_vma val;
f2a9dd69 9029 char *error_message;
a4fd1a8e 9030
906e58ca 9031 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9032 /* Allocate stubs for exported Thumb functions on v4t. */
9033 if (eh->export_glue == NULL)
9034 return TRUE;
9035
9036 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9037 BFD_ASSERT (globals != NULL);
9038 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9039
3d4d4302
AM		 9040 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9041 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9042 BFD_ASSERT (s != NULL);
9043 BFD_ASSERT (s->contents != NULL);
9044 BFD_ASSERT (s->output_section != NULL);
9045
9046 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9047
9048 BFD_ASSERT (sec->output_section != NULL);
9049
a4fd1a8e
PB		 9050 val = eh->export_glue->root.u.def.value + sec->output_offset
9051 + sec->output_section->vma;
8029a119 9052
a4fd1a8e
PB		 9053 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9054 h->root.u.def.section->owner,
f2a9dd69
DJ		 9055 globals->obfd, sec, val, s,
9056 &error_message);
a4fd1a8e
PB		 9057 BFD_ASSERT (myh);
9058 return TRUE;
9059}
9060
845b51d6
PB		 9061/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9062
9063static bfd_vma
9064elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9065{
9066 bfd_byte *p;
9067 bfd_vma glue_addr;
9068 asection *s;
9069 struct elf32_arm_link_hash_table *globals;
9070
9071 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9072 BFD_ASSERT (globals != NULL);
9073 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9074
3d4d4302
AM		 9075 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9076 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9077 BFD_ASSERT (s != NULL);
9078 BFD_ASSERT (s->contents != NULL);
9079 BFD_ASSERT (s->output_section != NULL);
9080
9081 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9082
9083 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9084
9085 if ((globals->bx_glue_offset[reg] & 1) == 0)
9086 {
9087 p = s->contents + glue_addr;
9088 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9089 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9090 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9091 globals->bx_glue_offset[reg] |= 1;
9092 }
9093
9094 return glue_addr + s->output_section->vma + s->output_offset;
9095}
9096
a4fd1a8e
PB		 9097/* Generate Arm stubs for exported Thumb symbols. */
9098static void
906e58ca 9099elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9100 struct bfd_link_info *link_info)
9101{
9102 struct elf32_arm_link_hash_table * globals;
9103
8029a119
NC		 9104 if (link_info == NULL)
9105 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9106 return;
9107
9108 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9109 if (globals == NULL)
9110 return;
9111
84c08195
PB		 9112 /* If blx is available then exported Thumb symbols are OK and there is
9113 nothing to do. */
a4fd1a8e
PB		 9114 if (globals->use_blx)
9115 return;
9116
9117 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9118 link_info);
9119}
9120
47beaa6a
RS		 9121/* Reserve space for COUNT dynamic relocations in relocation selection
9122 SRELOC. */
9123
9124static void
9125elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9126 bfd_size_type count)
9127{
9128 struct elf32_arm_link_hash_table *htab;
9129
9130 htab = elf32_arm_hash_table (info);
9131 BFD_ASSERT (htab->root.dynamic_sections_created);
9132 if (sreloc == NULL)
9133 abort ();
9134 sreloc->size += RELOC_SIZE (htab) * count;
9135}
9136
34e77a92
RS		 9137/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9138 dynamic, the relocations should go in SRELOC, otherwise they should
9139 go in the special .rel.iplt section. */
9140
9141static void
9142elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9143 bfd_size_type count)
9144{
9145 struct elf32_arm_link_hash_table *htab;
9146
9147 htab = elf32_arm_hash_table (info);
9148 if (!htab->root.dynamic_sections_created)
9149 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9150 else
9151 {
9152 BFD_ASSERT (sreloc != NULL);
9153 sreloc->size += RELOC_SIZE (htab) * count;
9154 }
9155}
9156
47beaa6a
RS		 9157/* Add relocation REL to the end of relocation section SRELOC. */
9158
9159static void
9160elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9161 asection *sreloc, Elf_Internal_Rela *rel)
9162{
9163 bfd_byte *loc;
9164 struct elf32_arm_link_hash_table *htab;
9165
9166 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9167 if (!htab->root.dynamic_sections_created
9168 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9169 sreloc = htab->root.irelplt;
47beaa6a
RS		 9170 if (sreloc == NULL)
9171 abort ();
9172 loc = sreloc->contents;
9173 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9174 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9175 abort ();
9176 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9177}
9178
34e77a92
RS		 9179/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9180 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9181 to .plt. */
9182
9183static void
9184elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9185 bfd_boolean is_iplt_entry,
9186 union gotplt_union *root_plt,
9187 struct arm_plt_info *arm_plt)
9188{
9189 struct elf32_arm_link_hash_table *htab;
9190 asection *splt;
9191 asection *sgotplt;
9192
9193 htab = elf32_arm_hash_table (info);
9194
9195 if (is_iplt_entry)
9196 {
9197 splt = htab->root.iplt;
9198 sgotplt = htab->root.igotplt;
9199
99059e56
RM		 9200 /* NaCl uses a special first entry in .iplt too. */
9201 if (htab->nacl_p && splt->size == 0)
9202 splt->size += htab->plt_header_size;
9203
34e77a92
RS		 9204 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9205 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9206 }
9207 else
9208 {
9209 splt = htab->root.splt;
9210 sgotplt = htab->root.sgotplt;
9211
9212 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9213 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9214
9215 /* If this is the first .plt entry, make room for the special
9216 first entry. */
9217 if (splt->size == 0)
9218 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9219
9220 htab->next_tls_desc_index++;
34e77a92
RS		 9221 }
9222
9223 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9224 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9225 splt->size += PLT_THUMB_STUB_SIZE;
9226 root_plt->offset = splt->size;
9227 splt->size += htab->plt_entry_size;
9228
9229 if (!htab->symbian_p)
9230 {
9231 /* We also need to make an entry in the .got.plt section, which
9232 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9233 if (is_iplt_entry)
9234 arm_plt->got_offset = sgotplt->size;
9235 else
9236 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9237 sgotplt->size += 4;
9238 }
9239}
9240
b38cadfb
NC		 9241static bfd_vma
9242arm_movw_immediate (bfd_vma value)
9243{
9244 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9245}
9246
9247static bfd_vma
9248arm_movt_immediate (bfd_vma value)
9249{
9250 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9251}
9252
34e77a92
RS		 9253/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9254 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9255 Otherwise, DYNINDX is the index of the symbol in the dynamic
9256 symbol table and SYM_VALUE is undefined.
9257
9258 ROOT_PLT points to the offset of the PLT entry from the start of its
9259 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9260 bookkeeping information.
34e77a92 9261
57460bcf
NC		 9262 Returns FALSE if there was a problem. */
9263
9264static bfd_boolean
34e77a92
RS		 9265elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9266 union gotplt_union *root_plt,
9267 struct arm_plt_info *arm_plt,
9268 int dynindx, bfd_vma sym_value)
9269{
9270 struct elf32_arm_link_hash_table *htab;
9271 asection *sgot;
9272 asection *splt;
9273 asection *srel;
9274 bfd_byte *loc;
9275 bfd_vma plt_index;
9276 Elf_Internal_Rela rel;
9277 bfd_vma plt_header_size;
9278 bfd_vma got_header_size;
9279
9280 htab = elf32_arm_hash_table (info);
9281
9282 /* Pick the appropriate sections and sizes. */
9283 if (dynindx == -1)
9284 {
9285 splt = htab->root.iplt;
9286 sgot = htab->root.igotplt;
9287 srel = htab->root.irelplt;
9288
9289 /* There are no reserved entries in .igot.plt, and no special
9290 first entry in .iplt. */
9291 got_header_size = 0;
9292 plt_header_size = 0;
9293 }
9294 else
9295 {
9296 splt = htab->root.splt;
9297 sgot = htab->root.sgotplt;
9298 srel = htab->root.srelplt;
9299
9300 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9301 plt_header_size = htab->plt_header_size;
9302 }
9303 BFD_ASSERT (splt != NULL && srel != NULL);
9304
9305 /* Fill in the entry in the procedure linkage table. */
9306 if (htab->symbian_p)
9307 {
9308 BFD_ASSERT (dynindx >= 0);
9309 put_arm_insn (htab, output_bfd,
9310 elf32_arm_symbian_plt_entry[0],
9311 splt->contents + root_plt->offset);
9312 bfd_put_32 (output_bfd,
9313 elf32_arm_symbian_plt_entry[1],
9314 splt->contents + root_plt->offset + 4);
9315
9316 /* Fill in the entry in the .rel.plt section. */
9317 rel.r_offset = (splt->output_section->vma
9318 + splt->output_offset
9319 + root_plt->offset + 4);
9320 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9321
9322 /* Get the index in the procedure linkage table which
9323 corresponds to this symbol. This is the index of this symbol
9324 in all the symbols for which we are making plt entries. The
9325 first entry in the procedure linkage table is reserved. */
9326 plt_index = ((root_plt->offset - plt_header_size)
9327 / htab->plt_entry_size);
9328 }
9329 else
9330 {
9331 bfd_vma got_offset, got_address, plt_address;
9332 bfd_vma got_displacement, initial_got_entry;
9333 bfd_byte * ptr;
9334
9335 BFD_ASSERT (sgot != NULL);
9336
9337 /* Get the offset into the .(i)got.plt table of the entry that
9338 corresponds to this function. */
9339 got_offset = (arm_plt->got_offset & -2);
9340
9341 /* Get the index in the procedure linkage table which
9342 corresponds to this symbol. This is the index of this symbol
9343 in all the symbols for which we are making plt entries.
9344 After the reserved .got.plt entries, all symbols appear in
9345 the same order as in .plt. */
9346 plt_index = (got_offset - got_header_size) / 4;
9347
9348 /* Calculate the address of the GOT entry. */
9349 got_address = (sgot->output_section->vma
9350 + sgot->output_offset
9351 + got_offset);
9352
9353 /* ...and the address of the PLT entry. */
9354 plt_address = (splt->output_section->vma
9355 + splt->output_offset
9356 + root_plt->offset);
9357
9358 ptr = splt->contents + root_plt->offset;
0e1862bb 9359 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9360 {
9361 unsigned int i;
9362 bfd_vma val;
9363
9364 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9365 {
9366 val = elf32_arm_vxworks_shared_plt_entry[i];
9367 if (i == 2)
9368 val |= got_address - sgot->output_section->vma;
9369 if (i == 5)
9370 val |= plt_index * RELOC_SIZE (htab);
9371 if (i == 2 || i == 5)
9372 bfd_put_32 (output_bfd, val, ptr);
9373 else
9374 put_arm_insn (htab, output_bfd, val, ptr);
9375 }
9376 }
9377 else if (htab->vxworks_p)
9378 {
9379 unsigned int i;
9380 bfd_vma val;
9381
9382 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9383 {
9384 val = elf32_arm_vxworks_exec_plt_entry[i];
9385 if (i == 2)
9386 val |= got_address;
9387 if (i == 4)
9388 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9389 if (i == 5)
9390 val |= plt_index * RELOC_SIZE (htab);
9391 if (i == 2 || i == 5)
9392 bfd_put_32 (output_bfd, val, ptr);
9393 else
9394 put_arm_insn (htab, output_bfd, val, ptr);
9395 }
9396
9397 loc = (htab->srelplt2->contents
9398 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9399
9400 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9401 referencing the GOT for this PLT entry. */
9402 rel.r_offset = plt_address + 8;
9403 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9404 rel.r_addend = got_offset;
9405 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9406 loc += RELOC_SIZE (htab);
9407
9408 /* Create the R_ARM_ABS32 relocation referencing the
9409 beginning of the PLT for this GOT entry. */
9410 rel.r_offset = got_address;
9411 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9412 rel.r_addend = 0;
9413 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9414 }
b38cadfb
NC		 9415 else if (htab->nacl_p)
9416 {
9417 /* Calculate the displacement between the PLT slot and the
9418 common tail that's part of the special initial PLT slot. */
6034aab8 9419 int32_t tail_displacement
b38cadfb
NC		 9420 = ((splt->output_section->vma + splt->output_offset
9421 + ARM_NACL_PLT_TAIL_OFFSET)
9422 - (plt_address + htab->plt_entry_size + 4));
9423 BFD_ASSERT ((tail_displacement & 3) == 0);
9424 tail_displacement >>= 2;
9425
9426 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9427 || (-tail_displacement & 0xff000000) == 0);
9428
9429 /* Calculate the displacement between the PLT slot and the entry
9430 in the GOT. The offset accounts for the value produced by
9431 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9432 got_displacement = (got_address
99059e56 9433 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9434
9435 /* NaCl does not support interworking at all. */
9436 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9437
9438 put_arm_insn (htab, output_bfd,
9439 elf32_arm_nacl_plt_entry[0]
9440 | arm_movw_immediate (got_displacement),
9441 ptr + 0);
9442 put_arm_insn (htab, output_bfd,
9443 elf32_arm_nacl_plt_entry[1]
9444 | arm_movt_immediate (got_displacement),
9445 ptr + 4);
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[2],
9448 ptr + 8);
9449 put_arm_insn (htab, output_bfd,
9450 elf32_arm_nacl_plt_entry[3]
9451 | (tail_displacement & 0x00ffffff),
9452 ptr + 12);
9453 }
57460bcf
NC		 9454 else if (using_thumb_only (htab))
9455 {
eed94f8f 9456 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9457 if (!using_thumb2 (htab))
eed94f8f
NC		 9458 {
9459 /* FIXME: We ought to be able to generate thumb-1 PLT
9460 instructions... */
9461 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9462 output_bfd);
9463 return FALSE;
9464 }
57460bcf 9465
eed94f8f
NC		 9466 /* Calculate the displacement between the PLT slot and the entry in
9467 the GOT. The 12-byte offset accounts for the value produced by
9468 adding to pc in the 3rd instruction of the PLT stub. */
9469 got_displacement = got_address - (plt_address + 12);
9470
9471 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9472 instead of 'put_thumb_insn'. */
9473 put_arm_insn (htab, output_bfd,
9474 elf32_thumb2_plt_entry[0]
9475 | ((got_displacement & 0x000000ff) << 16)
9476 | ((got_displacement & 0x00000700) << 20)
9477 | ((got_displacement & 0x00000800) >> 1)
9478 | ((got_displacement & 0x0000f000) >> 12),
9479 ptr + 0);
9480 put_arm_insn (htab, output_bfd,
9481 elf32_thumb2_plt_entry[1]
9482 | ((got_displacement & 0x00ff0000) )
9483 | ((got_displacement & 0x07000000) << 4)
9484 | ((got_displacement & 0x08000000) >> 17)
9485 | ((got_displacement & 0xf0000000) >> 28),
9486 ptr + 4);
9487 put_arm_insn (htab, output_bfd,
9488 elf32_thumb2_plt_entry[2],
9489 ptr + 8);
9490 put_arm_insn (htab, output_bfd,
9491 elf32_thumb2_plt_entry[3],
9492 ptr + 12);
57460bcf 9493 }
34e77a92
RS		 9494 else
9495 {
9496 /* Calculate the displacement between the PLT slot and the
9497 entry in the GOT. The eight-byte offset accounts for the
9498 value produced by adding to pc in the first instruction
9499 of the PLT stub. */
9500 got_displacement = got_address - (plt_address + 8);
9501
34e77a92
RS		 9502 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9503 {
9504 put_thumb_insn (htab, output_bfd,
9505 elf32_arm_plt_thumb_stub[0], ptr - 4);
9506 put_thumb_insn (htab, output_bfd,
9507 elf32_arm_plt_thumb_stub[1], ptr - 2);
9508 }
9509
1db37fe6
YG		 9510 if (!elf32_arm_use_long_plt_entry)
9511 {
9512 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9513
9514 put_arm_insn (htab, output_bfd,
9515 elf32_arm_plt_entry_short[0]
9516 | ((got_displacement & 0x0ff00000) >> 20),
9517 ptr + 0);
9518 put_arm_insn (htab, output_bfd,
9519 elf32_arm_plt_entry_short[1]
9520 | ((got_displacement & 0x000ff000) >> 12),
9521 ptr+ 4);
9522 put_arm_insn (htab, output_bfd,
9523 elf32_arm_plt_entry_short[2]
9524 | (got_displacement & 0x00000fff),
9525 ptr + 8);
34e77a92 9526#ifdef FOUR_WORD_PLT
1db37fe6 9527 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9528#endif
1db37fe6
YG		 9529 }
9530 else
9531 {
9532 put_arm_insn (htab, output_bfd,
9533 elf32_arm_plt_entry_long[0]
9534 | ((got_displacement & 0xf0000000) >> 28),
9535 ptr + 0);
9536 put_arm_insn (htab, output_bfd,
9537 elf32_arm_plt_entry_long[1]
9538 | ((got_displacement & 0x0ff00000) >> 20),
9539 ptr + 4);
9540 put_arm_insn (htab, output_bfd,
9541 elf32_arm_plt_entry_long[2]
9542 | ((got_displacement & 0x000ff000) >> 12),
9543 ptr+ 8);
9544 put_arm_insn (htab, output_bfd,
9545 elf32_arm_plt_entry_long[3]
9546 | (got_displacement & 0x00000fff),
9547 ptr + 12);
9548 }
34e77a92
RS		 9549 }
9550
9551 /* Fill in the entry in the .rel(a).(i)plt section. */
9552 rel.r_offset = got_address;
9553 rel.r_addend = 0;
9554 if (dynindx == -1)
9555 {
9556 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9557 The dynamic linker or static executable then calls SYM_VALUE
9558 to determine the correct run-time value of the .igot.plt entry. */
9559 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9560 initial_got_entry = sym_value;
9561 }
9562 else
9563 {
9564 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9565 initial_got_entry = (splt->output_section->vma
9566 + splt->output_offset);
9567 }
9568
9569 /* Fill in the entry in the global offset table. */
9570 bfd_put_32 (output_bfd, initial_got_entry,
9571 sgot->contents + got_offset);
9572 }
9573
aba8c3de
WN		 9574 if (dynindx == -1)
9575 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9576 else
9577 {
9578 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9579 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9580 }
57460bcf
NC		 9581
9582 return TRUE;
34e77a92
RS		 9583}
9584
eb043451
PB		 9585/* Some relocations map to different relocations depending on the
9586 target. Return the real relocation. */
8029a119 9587
eb043451
PB		 9588static int
9589arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9590 int r_type)
9591{
9592 switch (r_type)
9593 {
9594 case R_ARM_TARGET1:
9595 if (globals->target1_is_rel)
9596 return R_ARM_REL32;
9597 else
9598 return R_ARM_ABS32;
9599
9600 case R_ARM_TARGET2:
9601 return globals->target2_reloc;
9602
9603 default:
9604 return r_type;
9605 }
9606}
eb043451 9607
ba93b8ac
DJ		 9608/* Return the base VMA address which should be subtracted from real addresses
9609 when resolving @dtpoff relocation.
9610 This is PT_TLS segment p_vaddr. */
9611
9612static bfd_vma
9613dtpoff_base (struct bfd_link_info *info)
9614{
9615 /* If tls_sec is NULL, we should have signalled an error already. */
9616 if (elf_hash_table (info)->tls_sec == NULL)
9617 return 0;
9618 return elf_hash_table (info)->tls_sec->vma;
9619}
9620
9621/* Return the relocation value for @tpoff relocation
9622 if STT_TLS virtual address is ADDRESS. */
9623
9624static bfd_vma
9625tpoff (struct bfd_link_info *info, bfd_vma address)
9626{
9627 struct elf_link_hash_table *htab = elf_hash_table (info);
9628 bfd_vma base;
9629
9630 /* If tls_sec is NULL, we should have signalled an error already. */
9631 if (htab->tls_sec == NULL)
9632 return 0;
9633 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9634 return address - htab->tls_sec->vma + base;
9635}
9636
00a97672
RS		 9637/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9638 VALUE is the relocation value. */
9639
9640static bfd_reloc_status_type
9641elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9642{
9643 if (value > 0xfff)
9644 return bfd_reloc_overflow;
9645
9646 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9647 bfd_put_32 (abfd, value, data);
9648 return bfd_reloc_ok;
9649}
9650
0855e32b
NS		 9651/* Handle TLS relaxations. Relaxing is possible for symbols that use
9652 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9653 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9654
9655 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9656 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9657 case of error.
9658
9659 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9660 the pre-relaxed code. It would be nice if the relocs were updated
9661 to match the optimization. */
0855e32b 9662
b38cadfb 9663static bfd_reloc_status_type
0855e32b 9664elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9665 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9666 Elf_Internal_Rela *rel, unsigned long is_local)
9667{
9668 unsigned long insn;
b38cadfb 9669
0855e32b
NS		 9670 switch (ELF32_R_TYPE (rel->r_info))
9671 {
9672 default:
9673 return bfd_reloc_notsupported;
b38cadfb 9674
0855e32b
NS		 9675 case R_ARM_TLS_GOTDESC:
9676 if (is_local)
9677 insn = 0;
9678 else
9679 {
9680 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9681 if (insn & 1)
9682 insn -= 5; /* THUMB */
9683 else
9684 insn -= 8; /* ARM */
9685 }
9686 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9687 return bfd_reloc_continue;
9688
9689 case R_ARM_THM_TLS_DESCSEQ:
9690 /* Thumb insn. */
9691 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9692 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9693 {
9694 if (is_local)
9695 /* nop */
9696 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9697 }
9698 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9699 {
9700 if (is_local)
9701 /* nop */
9702 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9703 else
9704 /* ldr rx,[ry] */
9705 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9706 }
9707 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9708 {
9709 if (is_local)
9710 /* nop */
9711 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9712 else
9713 /* mov r0, rx */
9714 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9715 contents + rel->r_offset);
9716 }
9717 else
9718 {
9719 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9720 /* It's a 32 bit instruction, fetch the rest of it for
9721 error generation. */
9722 insn = (insn << 16)
9723 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9724 _bfd_error_handler
695344c0
NC		 9725 /* xgettext:c-format */
9726 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9727 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9728 return bfd_reloc_notsupported;
9729 }
9730 break;
b38cadfb 9731
0855e32b
NS		 9732 case R_ARM_TLS_DESCSEQ:
9733 /* arm insn. */
9734 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9735 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9736 {
9737 if (is_local)
9738 /* mov rx, ry */
9739 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9740 contents + rel->r_offset);
9741 }
9742 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9743 {
9744 if (is_local)
9745 /* nop */
9746 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9747 else
9748 /* ldr rx,[ry] */
9749 bfd_put_32 (input_bfd, insn & 0xfffff000,
9750 contents + rel->r_offset);
9751 }
9752 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9753 {
9754 if (is_local)
9755 /* nop */
9756 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9757 else
9758 /* mov r0, rx */
9759 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9760 contents + rel->r_offset);
9761 }
9762 else
9763 {
4eca0228 9764 _bfd_error_handler
695344c0
NC		 9765 /* xgettext:c-format */
9766 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9767 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9768 return bfd_reloc_notsupported;
9769 }
9770 break;
9771
9772 case R_ARM_TLS_CALL:
9773 /* GD->IE relaxation, turn the instruction into 'nop' or
9774 'ldr r0, [pc,r0]' */
9775 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9776 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9777 break;
b38cadfb 9778
0855e32b 9779 case R_ARM_THM_TLS_CALL:
6a631e86 9780 /* GD->IE relaxation. */
0855e32b
NS		 9781 if (!is_local)
9782 /* add r0,pc; ldr r0, [r0] */
9783 insn = 0x44786800;
60a019a0 9784 else if (using_thumb2 (globals))
0855e32b
NS		 9785 /* nop.w */
9786 insn = 0xf3af8000;
9787 else
9788 /* nop; nop */
9789 insn = 0xbf00bf00;
b38cadfb 9790
0855e32b
NS		 9791 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9792 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9793 break;
9794 }
9795 return bfd_reloc_ok;
9796}
9797
4962c51a
MS		 9798/* For a given value of n, calculate the value of G_n as required to
9799 deal with group relocations. We return it in the form of an
9800 encoded constant-and-rotation, together with the final residual. If n is
9801 specified as less than zero, then final_residual is filled with the
9802 input value and no further action is performed. */
9803
9804static bfd_vma
9805calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9806{
9807 int current_n;
9808 bfd_vma g_n;
9809 bfd_vma encoded_g_n = 0;
9810 bfd_vma residual = value; /* Also known as Y_n. */
9811
9812 for (current_n = 0; current_n <= n; current_n++)
9813 {
9814 int shift;
9815
9816 /* Calculate which part of the value to mask. */
9817 if (residual == 0)
99059e56 9818 shift = 0;
4962c51a 9819 else
99059e56
RM		 9820 {
9821 int msb;
9822
9823 /* Determine the most significant bit in the residual and
9824 align the resulting value to a 2-bit boundary. */
9825 for (msb = 30; msb >= 0; msb -= 2)
9826 if (residual & (3 << msb))
9827 break;
9828
9829 /* The desired shift is now (msb - 6), or zero, whichever
9830 is the greater. */
9831 shift = msb - 6;
9832 if (shift < 0)
9833 shift = 0;
9834 }
4962c51a
MS		 9835
9836 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9837 g_n = residual & (0xff << shift);
9838 encoded_g_n = (g_n >> shift)
99059e56 9839 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9840
9841 /* Calculate the residual for the next time around. */
9842 residual &= ~g_n;
9843 }
9844
9845 *final_residual = residual;
9846
9847 return encoded_g_n;
9848}
9849
9850/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9851 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9852
4962c51a 9853static int
906e58ca 9854identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9855{
9856 int opcode = insn & 0x1e00000;
9857
9858 if (opcode == 1 << 23) /* ADD */
9859 return 1;
9860
9861 if (opcode == 1 << 22) /* SUB */
9862 return -1;
9863
9864 return 0;
9865}
9866
252b5132 9867/* Perform a relocation as part of a final link. */
9b485d32 9868
252b5132 9869static bfd_reloc_status_type
57e8b36a
NC		 9870elf32_arm_final_link_relocate (reloc_howto_type * howto,
9871 bfd * input_bfd,
9872 bfd * output_bfd,
9873 asection * input_section,
9874 bfd_byte * contents,
9875 Elf_Internal_Rela * rel,
9876 bfd_vma value,
9877 struct bfd_link_info * info,
9878 asection * sym_sec,
9879 const char * sym_name,
34e77a92
RS		 9880 unsigned char st_type,
9881 enum arm_st_branch_type branch_type,
0945cdfd 9882 struct elf_link_hash_entry * h,
f2a9dd69 9883 bfd_boolean * unresolved_reloc_p,
8029a119 9884 char ** error_message)
252b5132
RH		 9885{
9886 unsigned long r_type = howto->type;
9887 unsigned long r_symndx;
9888 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9889 bfd_vma * local_got_offsets;
0855e32b 9890 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9891 asection * sgot;
9892 asection * splt;
252b5132 9893 asection * sreloc = NULL;
362d30a1 9894 asection * srelgot;
252b5132 9895 bfd_vma addend;
ba96a88f 9896 bfd_signed_vma signed_addend;
34e77a92
RS		 9897 unsigned char dynreloc_st_type;
9898 bfd_vma dynreloc_value;
ba96a88f 9899 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9900 struct elf32_arm_link_hash_entry *eh;
9901 union gotplt_union *root_plt;
9902 struct arm_plt_info *arm_plt;
9903 bfd_vma plt_offset;
9904 bfd_vma gotplt_offset;
9905 bfd_boolean has_iplt_entry;
f21f3fe0 9906
9c504268 9907 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9908 if (globals == NULL)
9909 return bfd_reloc_notsupported;
9c504268 9910
0ffa91dd
NC		 9911 BFD_ASSERT (is_arm_elf (input_bfd));
9912
9913 /* Some relocation types map to different relocations depending on the
9c504268 9914 target. We pick the right one here. */
eb043451 9915 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9916
9917 /* It is possible to have linker relaxations on some TLS access
9918 models. Update our information here. */
9919 r_type = elf32_arm_tls_transition (info, r_type, h);
9920
eb043451
PB		 9921 if (r_type != howto->type)
9922 howto = elf32_arm_howto_from_type (r_type);
9c504268 9923
34e77a92 9924 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9925 sgot = globals->root.sgot;
252b5132 9926 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9927 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9928
34e77a92
RS		 9929 if (globals->root.dynamic_sections_created)
9930 srelgot = globals->root.srelgot;
9931 else
9932 srelgot = NULL;
9933
252b5132
RH		 9934 r_symndx = ELF32_R_SYM (rel->r_info);
9935
4e7fd91e 9936 if (globals->use_rel)
ba96a88f 9937 {
4e7fd91e
PB		 9938 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9939
9940 if (addend & ((howto->src_mask + 1) >> 1))
9941 {
9942 signed_addend = -1;
9943 signed_addend &= ~ howto->src_mask;
9944 signed_addend |= addend;
9945 }
9946 else
9947 signed_addend = addend;
ba96a88f
NC		 9948 }
9949 else
4e7fd91e 9950 addend = signed_addend = rel->r_addend;
f21f3fe0 9951
39f21624
NC		 9952 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9953 are resolving a function call relocation. */
9954 if (using_thumb_only (globals)
9955 && (r_type == R_ARM_THM_CALL
9956 || r_type == R_ARM_THM_JUMP24)
9957 && branch_type == ST_BRANCH_TO_ARM)
9958 branch_type = ST_BRANCH_TO_THUMB;
9959
34e77a92
RS		 9960 /* Record the symbol information that should be used in dynamic
9961 relocations. */
9962 dynreloc_st_type = st_type;
9963 dynreloc_value = value;
9964 if (branch_type == ST_BRANCH_TO_THUMB)
9965 dynreloc_value |= 1;
9966
9967 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9968 VALUE appropriately for relocations that we resolve at link time. */
9969 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9970 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9971 &arm_plt)
34e77a92
RS		 9972 && root_plt->offset != (bfd_vma) -1)
9973 {
9974 plt_offset = root_plt->offset;
9975 gotplt_offset = arm_plt->got_offset;
9976
9977 if (h == NULL || eh->is_iplt)
9978 {
9979 has_iplt_entry = TRUE;
9980 splt = globals->root.iplt;
9981
9982 /* Populate .iplt entries here, because not all of them will
9983 be seen by finish_dynamic_symbol. The lower bit is set if
9984 we have already populated the entry. */
9985 if (plt_offset & 1)
9986 plt_offset--;
9987 else
9988 {
57460bcf
NC		 9989 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9990 -1, dynreloc_value))
9991 root_plt->offset |= 1;
9992 else
9993 return bfd_reloc_notsupported;
34e77a92
RS		 9994 }
9995
9996 /* Static relocations always resolve to the .iplt entry. */
9997 st_type = STT_FUNC;
9998 value = (splt->output_section->vma
9999 + splt->output_offset
10000 + plt_offset);
10001 branch_type = ST_BRANCH_TO_ARM;
10002
10003 /* If there are non-call relocations that resolve to the .iplt
10004 entry, then all dynamic ones must too. */
10005 if (arm_plt->noncall_refcount != 0)
10006 {
10007 dynreloc_st_type = st_type;
10008 dynreloc_value = value;
10009 }
10010 }
10011 else
10012 /* We populate the .plt entry in finish_dynamic_symbol. */
10013 splt = globals->root.splt;
10014 }
10015 else
10016 {
10017 splt = NULL;
10018 plt_offset = (bfd_vma) -1;
10019 gotplt_offset = (bfd_vma) -1;
10020 }
10021
252b5132
RH		 10022 switch (r_type)
10023 {
10024 case R_ARM_NONE:
28a094c2
DJ		 10025 /* We don't need to find a value for this symbol. It's just a
10026 marker. */
10027 *unresolved_reloc_p = FALSE;
252b5132
RH		 10028 return bfd_reloc_ok;
10029
00a97672
RS		 10030 case R_ARM_ABS12:
10031 if (!globals->vxworks_p)
10032 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10033 /* Fall through. */
00a97672 10034
252b5132
RH		 10035 case R_ARM_PC24:
10036 case R_ARM_ABS32:
bb224fc3 10037 case R_ARM_ABS32_NOI:
252b5132 10038 case R_ARM_REL32:
bb224fc3 10039 case R_ARM_REL32_NOI:
5b5bb741
PB		 10040 case R_ARM_CALL:
10041 case R_ARM_JUMP24:
dfc5f959 10042 case R_ARM_XPC25:
eb043451 10043 case R_ARM_PREL31:
7359ea65 10044 case R_ARM_PLT32:
7359ea65
DJ		 10045 /* Handle relocations which should use the PLT entry. ABS32/REL32
10046 will use the symbol's value, which may point to a PLT entry, but we
10047 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10048 branches in this object should go to it, except if the PLT is too
10049 far away, in which case a long branch stub should be inserted. */
bb224fc3 10050 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10051 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10052 && r_type != R_ARM_CALL
10053 && r_type != R_ARM_JUMP24
10054 && r_type != R_ARM_PLT32)
34e77a92 10055 && plt_offset != (bfd_vma) -1)
7359ea65 10056 {
34e77a92
RS		 10057 /* If we've created a .plt section, and assigned a PLT entry
10058 to this function, it must either be a STT_GNU_IFUNC reference
10059 or not be known to bind locally. In other cases, we should
10060 have cleared the PLT entry by now. */
10061 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10062
10063 value = (splt->output_section->vma
10064 + splt->output_offset
34e77a92 10065 + plt_offset);
0945cdfd 10066 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10067 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10068 contents, rel->r_offset, value,
00a97672 10069 rel->r_addend);
7359ea65
DJ		 10070 }
10071
67687978
PB		 10072 /* When generating a shared object or relocatable executable, these
10073 relocations are copied into the output file to be resolved at
10074 run time. */
0e1862bb
L		 10075 if ((bfd_link_pic (info)
10076 || globals->root.is_relocatable_executable)
7359ea65 10077 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10078 && !(globals->vxworks_p
3348747a
NS		 10079 && strcmp (input_section->output_section->name,
10080 ".tls_vars") == 0)
bb224fc3 10081 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10082 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10083 && !(input_bfd == globals->stub_bfd
10084 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10085 && (h == NULL
10086 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10087 || h->root.type != bfd_link_hash_undefweak)
10088 && r_type != R_ARM_PC24
5b5bb741
PB		 10089 && r_type != R_ARM_CALL
10090 && r_type != R_ARM_JUMP24
ee06dc07 10091 && r_type != R_ARM_PREL31
7359ea65 10092 && r_type != R_ARM_PLT32)
252b5132 10093 {
947216bf 10094 Elf_Internal_Rela outrel;
b34976b6 10095 bfd_boolean skip, relocate;
f21f3fe0 10096
52db4ec2
JW		 10097 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10098 && !h->def_regular)
10099 {
10100 char *v = _("shared object");
10101
0e1862bb 10102 if (bfd_link_executable (info))
52db4ec2
JW		 10103 v = _("PIE executable");
10104
4eca0228 10105 _bfd_error_handler
52db4ec2
JW		 10106 (_("%B: relocation %s against external or undefined symbol `%s'"
10107 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10108 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10109 return bfd_reloc_notsupported;
10110 }
10111
0945cdfd
DJ		 10112 *unresolved_reloc_p = FALSE;
10113
34e77a92 10114 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10115 {
83bac4b0
NC		 10116 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10117 ! globals->use_rel);
f21f3fe0 10118
83bac4b0 10119 if (sreloc == NULL)
252b5132 10120 return bfd_reloc_notsupported;
252b5132 10121 }
f21f3fe0 10122
b34976b6
AM		 10123 skip = FALSE;
10124 relocate = FALSE;
f21f3fe0 10125
00a97672 10126 outrel.r_addend = addend;
c629eae0
JJ		 10127 outrel.r_offset =
10128 _bfd_elf_section_offset (output_bfd, info, input_section,
10129 rel->r_offset);
10130 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10131 skip = TRUE;
0bb2d96a 10132 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10133 skip = TRUE, relocate = TRUE;
252b5132
RH		 10134 outrel.r_offset += (input_section->output_section->vma
10135 + input_section->output_offset);
f21f3fe0 10136
252b5132 10137 if (skip)
0bb2d96a 10138 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10139 else if (h != NULL
10140 && h->dynindx != -1
0e1862bb 10141 && (!bfd_link_pic (info)
1dcb9720
JW		 10142 || !(bfd_link_pie (info)
10143 || SYMBOLIC_BIND (info, h))
f5385ebf 10144 || !h->def_regular))
5e681ec4 10145 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10146 else
10147 {
a16385dc
MM		 10148 int symbol;
10149
5e681ec4 10150 /* This symbol is local, or marked to become local. */
34e77a92 10151 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10152 if (globals->symbian_p)
6366ff1e 10153 {
74541ad4
AM		 10154 asection *osec;
10155
6366ff1e
MM		 10156 /* On Symbian OS, the data segment and text segement
10157 can be relocated independently. Therefore, we
10158 must indicate the segment to which this
10159 relocation is relative. The BPABI allows us to
10160 use any symbol in the right segment; we just use
10161 the section symbol as it is convenient. (We
10162 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10163 will not appear in the dynamic symbol table.)
10164
10165 Note that the dynamic linker ignores the section
10166 symbol value, so we don't subtract osec->vma
10167 from the emitted reloc addend. */
10dbd1f3 10168 if (sym_sec)
74541ad4 10169 osec = sym_sec->output_section;
10dbd1f3 10170 else
74541ad4
AM		 10171 osec = input_section->output_section;
10172 symbol = elf_section_data (osec)->dynindx;
10173 if (symbol == 0)
10174 {
10175 struct elf_link_hash_table *htab = elf_hash_table (info);
10176
10177 if ((osec->flags & SEC_READONLY) == 0
10178 && htab->data_index_section != NULL)
10179 osec = htab->data_index_section;
10180 else
10181 osec = htab->text_index_section;
10182 symbol = elf_section_data (osec)->dynindx;
10183 }
6366ff1e
MM		 10184 BFD_ASSERT (symbol != 0);
10185 }
a16385dc
MM		 10186 else
10187 /* On SVR4-ish systems, the dynamic loader cannot
10188 relocate the text and data segments independently,
10189 so the symbol does not matter. */
10190 symbol = 0;
34e77a92
RS		 10191 if (dynreloc_st_type == STT_GNU_IFUNC)
10192 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10193 to the .iplt entry. Instead, every non-call reference
10194 must use an R_ARM_IRELATIVE relocation to obtain the
10195 correct run-time address. */
10196 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10197 else
10198 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10199 if (globals->use_rel)
10200 relocate = TRUE;
10201 else
34e77a92 10202 outrel.r_addend += dynreloc_value;
252b5132 10203 }
f21f3fe0 10204
47beaa6a 10205 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10206
f21f3fe0 10207 /* If this reloc is against an external symbol, we do not want to
252b5132 10208 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10209 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10210 if (! relocate)
10211 return bfd_reloc_ok;
9a5aca8c 10212
f21f3fe0 10213 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10214 contents, rel->r_offset,
10215 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10216 }
10217 else switch (r_type)
10218 {
00a97672
RS		 10219 case R_ARM_ABS12:
10220 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10221
dfc5f959 10222 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10223 case R_ARM_CALL:
10224 case R_ARM_JUMP24:
8029a119 10225 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10226 case R_ARM_PLT32:
906e58ca 10227 {
906e58ca
NC		 10228 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10229
dfc5f959 10230 if (r_type == R_ARM_XPC25)
252b5132 10231 {
dfc5f959
NC		 10232 /* Check for Arm calling Arm function. */
10233 /* FIXME: Should we translate the instruction into a BL
10234 instruction instead ? */
35fc36a8 10235 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10236 _bfd_error_handler
d003868e
AM		 10237 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10238 input_bfd,
10239 h ? h->root.root.string : "(local)");
dfc5f959 10240 }
155d87d7 10241 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10242 {
10243 /* Check for Arm calling Thumb function. */
35fc36a8 10244 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10245 {
f2a9dd69
DJ		 10246 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10247 output_bfd, input_section,
10248 hit_data, sym_sec, rel->r_offset,
10249 signed_addend, value,
10250 error_message))
10251 return bfd_reloc_ok;
10252 else
10253 return bfd_reloc_dangerous;
dfc5f959 10254 }
252b5132 10255 }
ba96a88f 10256
906e58ca 10257 /* Check if a stub has to be inserted because the
8029a119 10258 destination is too far or we are changing mode. */
155d87d7
CL		 10259 if ( r_type == R_ARM_CALL
10260 || r_type == R_ARM_JUMP24
10261 || r_type == R_ARM_PLT32)
906e58ca 10262 {
fe33d2fa
CL		 10263 enum elf32_arm_stub_type stub_type = arm_stub_none;
10264 struct elf32_arm_link_hash_entry *hash;
10265
10266 hash = (struct elf32_arm_link_hash_entry *) h;
10267 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10268 st_type, &branch_type,
10269 hash, value, sym_sec,
fe33d2fa 10270 input_bfd, sym_name);
5fa9e92f 10271
fe33d2fa 10272 if (stub_type != arm_stub_none)
906e58ca
NC		 10273 {
10274 /* The target is out of reach, so redirect the
10275 branch to the local stub for this function. */
906e58ca
NC		 10276 stub_entry = elf32_arm_get_stub_entry (input_section,
10277 sym_sec, h,
fe33d2fa
CL		 10278 rel, globals,
10279 stub_type);
9cd3e4e5
NC		 10280 {
10281 if (stub_entry != NULL)
10282 value = (stub_entry->stub_offset
10283 + stub_entry->stub_sec->output_offset
10284 + stub_entry->stub_sec->output_section->vma);
10285
10286 if (plt_offset != (bfd_vma) -1)
10287 *unresolved_reloc_p = FALSE;
10288 }
906e58ca 10289 }
fe33d2fa
CL		 10290 else
10291 {
10292 /* If the call goes through a PLT entry, make sure to
10293 check distance to the right destination address. */
34e77a92 10294 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10295 {
10296 value = (splt->output_section->vma
10297 + splt->output_offset
34e77a92 10298 + plt_offset);
fe33d2fa
CL		 10299 *unresolved_reloc_p = FALSE;
10300 /* The PLT entry is in ARM mode, regardless of the
10301 target function. */
35fc36a8 10302 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10303 }
10304 }
906e58ca
NC		 10305 }
10306
dea514f5
PB		 10307 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10308 where:
10309 S is the address of the symbol in the relocation.
10310 P is address of the instruction being relocated.
10311 A is the addend (extracted from the instruction) in bytes.
10312
10313 S is held in 'value'.
10314 P is the base address of the section containing the
10315 instruction plus the offset of the reloc into that
10316 section, ie:
10317 (input_section->output_section->vma +
10318 input_section->output_offset +
10319 rel->r_offset).
10320 A is the addend, converted into bytes, ie:
10321 (signed_addend * 4)
10322
10323 Note: None of these operations have knowledge of the pipeline
10324 size of the processor, thus it is up to the assembler to
10325 encode this information into the addend. */
10326 value -= (input_section->output_section->vma
10327 + input_section->output_offset);
10328 value -= rel->r_offset;
4e7fd91e
PB		 10329 if (globals->use_rel)
10330 value += (signed_addend << howto->size);
10331 else
10332 /* RELA addends do not have to be adjusted by howto->size. */
10333 value += signed_addend;
23080146 10334
dcb5e6e6
NC		 10335 signed_addend = value;
10336 signed_addend >>= howto->rightshift;
9a5aca8c 10337
5ab79981 10338 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10339 the next instruction unless a PLT entry will be created.
77b4f08f 10340 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10341 The jump to the next instruction is optimized as a NOP depending
10342 on the architecture. */
ffcb4889 10343 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10344 && plt_offset == (bfd_vma) -1)
77b4f08f 10345 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10346 {
cd1dac3d
DG		 10347 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10348
10349 if (arch_has_arm_nop (globals))
10350 value |= 0x0320f000;
10351 else
10352 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10353 }
10354 else
59f2c4e7 10355 {
9b485d32 10356 /* Perform a signed range check. */
dcb5e6e6 10357 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10358 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10359 return bfd_reloc_overflow;
9a5aca8c 10360
5ab79981 10361 addend = (value & 2);
39b41c9c 10362
5ab79981
PB		 10363 value = (signed_addend & howto->dst_mask)
10364 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10365
5ab79981
PB		 10366 if (r_type == R_ARM_CALL)
10367 {
155d87d7 10368 /* Set the H bit in the BLX instruction. */
35fc36a8 10369 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10370 {
10371 if (addend)
10372 value |= (1 << 24);
10373 else
10374 value &= ~(bfd_vma)(1 << 24);
10375 }
10376
5ab79981 10377 /* Select the correct instruction (BL or BLX). */
906e58ca 10378 /* Only if we are not handling a BL to a stub. In this
8029a119 10379 case, mode switching is performed by the stub. */
35fc36a8 10380 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10381 value |= (1 << 28);
63e1a0fc 10382 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10383 {
10384 value &= ~(bfd_vma)(1 << 28);
10385 value |= (1 << 24);
10386 }
39b41c9c
PB		 10387 }
10388 }
906e58ca 10389 }
252b5132 10390 break;
f21f3fe0 10391
252b5132
RH		 10392 case R_ARM_ABS32:
10393 value += addend;
35fc36a8 10394 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10395 value |= 1;
10396 break;
f21f3fe0 10397
bb224fc3
MS		 10398 case R_ARM_ABS32_NOI:
10399 value += addend;
10400 break;
10401
252b5132 10402 case R_ARM_REL32:
a8bc6c78 10403 value += addend;
35fc36a8 10404 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10405 value |= 1;
252b5132 10406 value -= (input_section->output_section->vma
62efb346 10407 + input_section->output_offset + rel->r_offset);
252b5132 10408 break;
eb043451 10409
bb224fc3
MS		 10410 case R_ARM_REL32_NOI:
10411 value += addend;
10412 value -= (input_section->output_section->vma
10413 + input_section->output_offset + rel->r_offset);
10414 break;
10415
eb043451
PB		 10416 case R_ARM_PREL31:
10417 value -= (input_section->output_section->vma
10418 + input_section->output_offset + rel->r_offset);
10419 value += signed_addend;
10420 if (! h || h->root.type != bfd_link_hash_undefweak)
10421 {
8029a119 10422 /* Check for overflow. */
eb043451
PB		 10423 if ((value ^ (value >> 1)) & (1 << 30))
10424 return bfd_reloc_overflow;
10425 }
10426 value &= 0x7fffffff;
10427 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10428 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10429 value |= 1;
10430 break;
252b5132 10431 }
f21f3fe0 10432
252b5132
RH		 10433 bfd_put_32 (input_bfd, value, hit_data);
10434 return bfd_reloc_ok;
10435
10436 case R_ARM_ABS8:
fd0fd00c
MJ		 10437 /* PR 16202: Refectch the addend using the correct size. */
10438 if (globals->use_rel)
10439 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10440 value += addend;
4e67d4ca
DG		 10441
10442 /* There is no way to tell whether the user intended to use a signed or
10443 unsigned addend. When checking for overflow we accept either,
10444 as specified by the AAELF. */
10445 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10446 return bfd_reloc_overflow;
10447
10448 bfd_put_8 (input_bfd, value, hit_data);
10449 return bfd_reloc_ok;
10450
10451 case R_ARM_ABS16:
fd0fd00c
MJ		 10452 /* PR 16202: Refectch the addend using the correct size. */
10453 if (globals->use_rel)
10454 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10455 value += addend;
10456
4e67d4ca
DG		 10457 /* See comment for R_ARM_ABS8. */
10458 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10459 return bfd_reloc_overflow;
10460
10461 bfd_put_16 (input_bfd, value, hit_data);
10462 return bfd_reloc_ok;
10463
252b5132 10464 case R_ARM_THM_ABS5:
9b485d32 10465 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10466 if (globals->use_rel)
10467 {
10468 /* Need to refetch addend. */
10469 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10470 /* ??? Need to determine shift amount from operand size. */
10471 addend >>= howto->rightshift;
10472 }
252b5132
RH		 10473 value += addend;
10474
10475 /* ??? Isn't value unsigned? */
10476 if ((long) value > 0x1f || (long) value < -0x10)
10477 return bfd_reloc_overflow;
10478
10479 /* ??? Value needs to be properly shifted into place first. */
10480 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10481 bfd_put_16 (input_bfd, value, hit_data);
10482 return bfd_reloc_ok;
10483
2cab6cc3
MS		 10484 case R_ARM_THM_ALU_PREL_11_0:
10485 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10486 {
10487 bfd_vma insn;
10488 bfd_signed_vma relocation;
10489
10490 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10491 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10492
99059e56
RM		 10493 if (globals->use_rel)
10494 {
10495 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10496 | ((insn & (1 << 26)) >> 15);
10497 if (insn & 0xf00000)
10498 signed_addend = -signed_addend;
10499 }
2cab6cc3
MS		 10500
10501 relocation = value + signed_addend;
79f08007 10502 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10503 + input_section->output_offset
10504 + rel->r_offset);
2cab6cc3 10505
b6518b38 10506 value = relocation;
2cab6cc3 10507
99059e56
RM		 10508 if (value >= 0x1000)
10509 return bfd_reloc_overflow;
2cab6cc3
MS		 10510
10511 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10512 | ((value & 0x700) << 4)
10513 | ((value & 0x800) << 15);
10514 if (relocation < 0)
10515 insn |= 0xa00000;
2cab6cc3
MS		 10516
10517 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10518 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10519
99059e56 10520 return bfd_reloc_ok;
2cab6cc3
MS		 10521 }
10522
e1ec24c6
NC		 10523 case R_ARM_THM_PC8:
10524 /* PR 10073: This reloc is not generated by the GNU toolchain,
10525 but it is supported for compatibility with third party libraries
10526 generated by other compilers, specifically the ARM/IAR. */
10527 {
10528 bfd_vma insn;
10529 bfd_signed_vma relocation;
10530
10531 insn = bfd_get_16 (input_bfd, hit_data);
10532
99059e56 10533 if (globals->use_rel)
79f08007 10534 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10535
10536 relocation = value + addend;
79f08007 10537 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10538 + input_section->output_offset
10539 + rel->r_offset);
e1ec24c6 10540
b6518b38 10541 value = relocation;
e1ec24c6
NC		 10542
10543 /* We do not check for overflow of this reloc. Although strictly
10544 speaking this is incorrect, it appears to be necessary in order
10545 to work with IAR generated relocs. Since GCC and GAS do not
10546 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10547 a problem for them. */
10548 value &= 0x3fc;
10549
10550 insn = (insn & 0xff00) | (value >> 2);
10551
10552 bfd_put_16 (input_bfd, insn, hit_data);
10553
99059e56 10554 return bfd_reloc_ok;
e1ec24c6
NC		 10555 }
10556
2cab6cc3
MS		 10557 case R_ARM_THM_PC12:
10558 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10559 {
10560 bfd_vma insn;
10561 bfd_signed_vma relocation;
10562
10563 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10564 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10565
99059e56
RM		 10566 if (globals->use_rel)
10567 {
10568 signed_addend = insn & 0xfff;
10569 if (!(insn & (1 << 23)))
10570 signed_addend = -signed_addend;
10571 }
2cab6cc3
MS		 10572
10573 relocation = value + signed_addend;
79f08007 10574 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10575 + input_section->output_offset
10576 + rel->r_offset);
2cab6cc3 10577
b6518b38 10578 value = relocation;
2cab6cc3 10579
99059e56
RM		 10580 if (value >= 0x1000)
10581 return bfd_reloc_overflow;
2cab6cc3
MS		 10582
10583 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10584 if (relocation >= 0)
10585 insn |= (1 << 23);
2cab6cc3
MS		 10586
10587 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10588 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10589
99059e56 10590 return bfd_reloc_ok;
2cab6cc3
MS		 10591 }
10592
dfc5f959 10593 case R_ARM_THM_XPC22:
c19d1205 10594 case R_ARM_THM_CALL:
bd97cb95 10595 case R_ARM_THM_JUMP24:
dfc5f959 10596 /* Thumb BL (branch long instruction). */
252b5132 10597 {
b34976b6 10598 bfd_vma relocation;
99059e56 10599 bfd_vma reloc_sign;
b34976b6
AM		 10600 bfd_boolean overflow = FALSE;
10601 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10602 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10603 bfd_signed_vma reloc_signed_max;
10604 bfd_signed_vma reloc_signed_min;
b34976b6 10605 bfd_vma check;
252b5132 10606 bfd_signed_vma signed_check;
e95de063 10607 int bitsize;
cd1dac3d 10608 const int thumb2 = using_thumb2 (globals);
5e866f5a 10609 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10610
5ab79981 10611 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10612 the next instruction unless a PLT entry will be created.
10613 The jump to the next instruction is optimized as a NOP.W for
10614 Thumb-2 enabled architectures. */
19540007 10615 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10616 && plt_offset == (bfd_vma) -1)
5ab79981 10617 {
60a019a0 10618 if (thumb2)
cd1dac3d
DG		 10619 {
10620 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10621 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10622 }
10623 else
10624 {
10625 bfd_put_16 (input_bfd, 0xe000, hit_data);
10626 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10627 }
5ab79981
PB		 10628 return bfd_reloc_ok;
10629 }
10630
e95de063 10631 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10632 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10633 if (globals->use_rel)
10634 {
99059e56
RM		 10635 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10636 bfd_vma upper = upper_insn & 0x3ff;
10637 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10638 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10639 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10640 bfd_vma i1 = j1 ^ s ? 0 : 1;
10641 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10642
99059e56
RM		 10643 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10644 /* Sign extend. */
10645 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10646
4e7fd91e
PB		 10647 signed_addend = addend;
10648 }
cb1afa5c 10649
dfc5f959
NC		 10650 if (r_type == R_ARM_THM_XPC22)
10651 {
10652 /* Check for Thumb to Thumb call. */
10653 /* FIXME: Should we translate the instruction into a BL
10654 instruction instead ? */
35fc36a8 10655 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10656 _bfd_error_handler
d003868e
AM		 10657 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10658 input_bfd,
10659 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10660 }
10661 else
252b5132 10662 {
dfc5f959
NC		 10663 /* If it is not a call to Thumb, assume call to Arm.
10664 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10665 function call at all, but rather a long jump. Calls through
10666 the PLT do not require stubs. */
34e77a92 10667 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10668 {
bd97cb95 10669 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10670 {
10671 /* Convert BL to BLX. */
10672 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10673 }
155d87d7
CL		 10674 else if (( r_type != R_ARM_THM_CALL)
10675 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10676 {
10677 if (elf32_thumb_to_arm_stub
10678 (info, sym_name, input_bfd, output_bfd, input_section,
10679 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10680 error_message))
10681 return bfd_reloc_ok;
10682 else
10683 return bfd_reloc_dangerous;
10684 }
da5938a2 10685 }
35fc36a8
RS		 10686 else if (branch_type == ST_BRANCH_TO_THUMB
10687 && globals->use_blx
bd97cb95 10688 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10689 {
10690 /* Make sure this is a BL. */
10691 lower_insn |= 0x1800;
10692 }
252b5132 10693 }
f21f3fe0 10694
fe33d2fa 10695 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10696 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10697 {
10698 /* Check if a stub has to be inserted because the destination
8029a119 10699 is too far. */
fe33d2fa
CL		 10700 struct elf32_arm_stub_hash_entry *stub_entry;
10701 struct elf32_arm_link_hash_entry *hash;
10702
10703 hash = (struct elf32_arm_link_hash_entry *) h;
10704
10705 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10706 st_type, &branch_type,
10707 hash, value, sym_sec,
fe33d2fa
CL		 10708 input_bfd, sym_name);
10709
10710 if (stub_type != arm_stub_none)
906e58ca
NC		 10711 {
10712 /* The target is out of reach or we are changing modes, so
10713 redirect the branch to the local stub for this
10714 function. */
10715 stub_entry = elf32_arm_get_stub_entry (input_section,
10716 sym_sec, h,
fe33d2fa
CL		 10717 rel, globals,
10718 stub_type);
906e58ca 10719 if (stub_entry != NULL)
9cd3e4e5
NC		 10720 {
10721 value = (stub_entry->stub_offset
10722 + stub_entry->stub_sec->output_offset
10723 + stub_entry->stub_sec->output_section->vma);
10724
10725 if (plt_offset != (bfd_vma) -1)
10726 *unresolved_reloc_p = FALSE;
10727 }
906e58ca 10728
f4ac8484 10729 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10730 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10731 {
10732 if ((stub_entry
10733 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10734 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10735 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10736 }
906e58ca
NC		 10737 }
10738 }
10739
fe33d2fa 10740 /* Handle calls via the PLT. */
34e77a92 10741 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10742 {
10743 value = (splt->output_section->vma
10744 + splt->output_offset
34e77a92 10745 + plt_offset);
fe33d2fa 10746
eed94f8f
NC		 10747 if (globals->use_blx
10748 && r_type == R_ARM_THM_CALL
10749 && ! using_thumb_only (globals))
fe33d2fa
CL		 10750 {
10751 /* If the Thumb BLX instruction is available, convert
10752 the BL to a BLX instruction to call the ARM-mode
10753 PLT entry. */
10754 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10755 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10756 }
10757 else
10758 {
eed94f8f
NC		 10759 if (! using_thumb_only (globals))
10760 /* Target the Thumb stub before the ARM PLT entry. */
10761 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10762 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10763 }
10764 *unresolved_reloc_p = FALSE;
10765 }
10766
ba96a88f 10767 relocation = value + signed_addend;
f21f3fe0 10768
252b5132 10769 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10770 + input_section->output_offset
10771 + rel->r_offset);
9a5aca8c 10772
252b5132
RH		 10773 check = relocation >> howto->rightshift;
10774
10775 /* If this is a signed value, the rightshift just dropped
10776 leading 1 bits (assuming twos complement). */
10777 if ((bfd_signed_vma) relocation >= 0)
10778 signed_check = check;
10779 else
10780 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10781
e95de063
MS		 10782 /* Calculate the permissable maximum and minimum values for
10783 this relocation according to whether we're relocating for
10784 Thumb-2 or not. */
10785 bitsize = howto->bitsize;
5e866f5a 10786 if (!thumb2_bl)
e95de063 10787 bitsize -= 2;
f6ebfac0 10788 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10789 reloc_signed_min = ~reloc_signed_max;
10790
252b5132 10791 /* Assumes two's complement. */
ba96a88f 10792 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10793 overflow = TRUE;
252b5132 10794
bd97cb95 10795 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10796 /* For a BLX instruction, make sure that the relocation is rounded up
10797 to a word boundary. This follows the semantics of the instruction
10798 which specifies that bit 1 of the target address will come from bit
10799 1 of the base address. */
10800 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10801
e95de063
MS		 10802 /* Put RELOCATION back into the insn. Assumes two's complement.
10803 We use the Thumb-2 encoding, which is safe even if dealing with
10804 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10805 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10806 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10807 | ((relocation >> 12) & 0x3ff)
10808 | (reloc_sign << 10);
906e58ca 10809 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10810 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10811 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10812 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10813
252b5132
RH		 10814 /* Put the relocated value back in the object file: */
10815 bfd_put_16 (input_bfd, upper_insn, hit_data);
10816 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10817
10818 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10819 }
10820 break;
10821
c19d1205
ZW		 10822 case R_ARM_THM_JUMP19:
10823 /* Thumb32 conditional branch instruction. */
10824 {
10825 bfd_vma relocation;
10826 bfd_boolean overflow = FALSE;
10827 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10828 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10829 bfd_signed_vma reloc_signed_max = 0xffffe;
10830 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10831 bfd_signed_vma signed_check;
c5423981
TG		 10832 enum elf32_arm_stub_type stub_type = arm_stub_none;
10833 struct elf32_arm_stub_hash_entry *stub_entry;
10834 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10835
10836 /* Need to refetch the addend, reconstruct the top three bits,
10837 and squish the two 11 bit pieces together. */
10838 if (globals->use_rel)
10839 {
10840 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10841 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10842 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10843 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10844 bfd_vma lower = (lower_insn & 0x07ff);
10845
a00a1f35
MS		 10846 upper |= J1 << 6;
10847 upper |= J2 << 7;
10848 upper |= (!S) << 8;
c19d1205
ZW		 10849 upper -= 0x0100; /* Sign extend. */
10850
10851 addend = (upper << 12) | (lower << 1);
10852 signed_addend = addend;
10853 }
10854
bd97cb95 10855 /* Handle calls via the PLT. */
34e77a92 10856 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10857 {
10858 value = (splt->output_section->vma
10859 + splt->output_offset
34e77a92 10860 + plt_offset);
bd97cb95
DJ		 10861 /* Target the Thumb stub before the ARM PLT entry. */
10862 value -= PLT_THUMB_STUB_SIZE;
10863 *unresolved_reloc_p = FALSE;
10864 }
10865
c5423981
TG		 10866 hash = (struct elf32_arm_link_hash_entry *)h;
10867
10868 stub_type = arm_type_of_stub (info, input_section, rel,
10869 st_type, &branch_type,
10870 hash, value, sym_sec,
10871 input_bfd, sym_name);
10872 if (stub_type != arm_stub_none)
10873 {
10874 stub_entry = elf32_arm_get_stub_entry (input_section,
10875 sym_sec, h,
10876 rel, globals,
10877 stub_type);
10878 if (stub_entry != NULL)
10879 {
10880 value = (stub_entry->stub_offset
10881 + stub_entry->stub_sec->output_offset
10882 + stub_entry->stub_sec->output_section->vma);
10883 }
10884 }
c19d1205 10885
99059e56 10886 relocation = value + signed_addend;
c19d1205
ZW		 10887 relocation -= (input_section->output_section->vma
10888 + input_section->output_offset
10889 + rel->r_offset);
a00a1f35 10890 signed_check = (bfd_signed_vma) relocation;
c19d1205 10891
c19d1205
ZW		 10892 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10893 overflow = TRUE;
10894
10895 /* Put RELOCATION back into the insn. */
10896 {
10897 bfd_vma S = (relocation & 0x00100000) >> 20;
10898 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10899 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10900 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10901 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10902
a00a1f35 10903 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10904 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10905 }
10906
10907 /* Put the relocated value back in the object file: */
10908 bfd_put_16 (input_bfd, upper_insn, hit_data);
10909 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10910
10911 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10912 }
10913
10914 case R_ARM_THM_JUMP11:
10915 case R_ARM_THM_JUMP8:
10916 case R_ARM_THM_JUMP6:
51c5503b
NC		 10917 /* Thumb B (branch) instruction). */
10918 {
6cf9e9fe 10919 bfd_signed_vma relocation;
51c5503b
NC		 10920 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10921 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10922 bfd_signed_vma signed_check;
10923
c19d1205
ZW		 10924 /* CZB cannot jump backward. */
10925 if (r_type == R_ARM_THM_JUMP6)
10926 reloc_signed_min = 0;
10927
4e7fd91e 10928 if (globals->use_rel)
6cf9e9fe 10929 {
4e7fd91e
PB		 10930 /* Need to refetch addend. */
10931 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10932 if (addend & ((howto->src_mask + 1) >> 1))
10933 {
10934 signed_addend = -1;
10935 signed_addend &= ~ howto->src_mask;
10936 signed_addend |= addend;
10937 }
10938 else
10939 signed_addend = addend;
10940 /* The value in the insn has been right shifted. We need to
10941 undo this, so that we can perform the address calculation
10942 in terms of bytes. */
10943 signed_addend <<= howto->rightshift;
6cf9e9fe 10944 }
6cf9e9fe 10945 relocation = value + signed_addend;
51c5503b
NC		 10946
10947 relocation -= (input_section->output_section->vma
10948 + input_section->output_offset
10949 + rel->r_offset);
10950
6cf9e9fe
NC		 10951 relocation >>= howto->rightshift;
10952 signed_check = relocation;
c19d1205
ZW		 10953
10954 if (r_type == R_ARM_THM_JUMP6)
10955 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10956 else
10957 relocation &= howto->dst_mask;
51c5503b 10958 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10959
51c5503b
NC		 10960 bfd_put_16 (input_bfd, relocation, hit_data);
10961
10962 /* Assumes two's complement. */
10963 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10964 return bfd_reloc_overflow;
10965
10966 return bfd_reloc_ok;
10967 }
cedb70c5 10968
8375c36b
PB		 10969 case R_ARM_ALU_PCREL7_0:
10970 case R_ARM_ALU_PCREL15_8:
10971 case R_ARM_ALU_PCREL23_15:
10972 {
10973 bfd_vma insn;
10974 bfd_vma relocation;
10975
10976 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10977 if (globals->use_rel)
10978 {
10979 /* Extract the addend. */
10980 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10981 signed_addend = addend;
10982 }
8375c36b
PB		 10983 relocation = value + signed_addend;
10984
10985 relocation -= (input_section->output_section->vma
10986 + input_section->output_offset
10987 + rel->r_offset);
10988 insn = (insn & ~0xfff)
10989 | ((howto->bitpos << 7) & 0xf00)
10990 | ((relocation >> howto->bitpos) & 0xff);
10991 bfd_put_32 (input_bfd, value, hit_data);
10992 }
10993 return bfd_reloc_ok;
10994
252b5132
RH		 10995 case R_ARM_GNU_VTINHERIT:
10996 case R_ARM_GNU_VTENTRY:
10997 return bfd_reloc_ok;
10998
c19d1205 10999 case R_ARM_GOTOFF32:
252b5132 11000 /* Relocation is relative to the start of the
99059e56 11001 global offset table. */
252b5132
RH		 11002
11003 BFD_ASSERT (sgot != NULL);
11004 if (sgot == NULL)
99059e56 11005 return bfd_reloc_notsupported;
9a5aca8c 11006
cedb70c5 11007 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11008 address by one, so that attempts to call the function pointer will
11009 correctly interpret it as Thumb code. */
35fc36a8 11010 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11011 value += 1;
11012
252b5132 11013 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11014 calculation. We always want the start of .got. If we
11015 define _GLOBAL_OFFSET_TABLE in a different way, as is
11016 permitted by the ABI, we might have to change this
11017 calculation. */
252b5132 11018 value -= sgot->output_section->vma;
f21f3fe0 11019 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11020 contents, rel->r_offset, value,
00a97672 11021 rel->r_addend);
252b5132
RH		 11022
11023 case R_ARM_GOTPC:
a7c10850 11024 /* Use global offset table as symbol value. */
252b5132 11025 BFD_ASSERT (sgot != NULL);
f21f3fe0 11026
252b5132 11027 if (sgot == NULL)
99059e56 11028 return bfd_reloc_notsupported;
252b5132 11029
0945cdfd 11030 *unresolved_reloc_p = FALSE;
252b5132 11031 value = sgot->output_section->vma;
f21f3fe0 11032 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11033 contents, rel->r_offset, value,
00a97672 11034 rel->r_addend);
f21f3fe0 11035
252b5132 11036 case R_ARM_GOT32:
eb043451 11037 case R_ARM_GOT_PREL:
252b5132 11038 /* Relocation is to the entry for this symbol in the
99059e56 11039 global offset table. */
252b5132
RH		 11040 if (sgot == NULL)
11041 return bfd_reloc_notsupported;
f21f3fe0 11042
34e77a92
RS		 11043 if (dynreloc_st_type == STT_GNU_IFUNC
11044 && plt_offset != (bfd_vma) -1
11045 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11046 {
11047 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11048 symbol, and the relocation resolves directly to the runtime
11049 target rather than to the .iplt entry. This means that any
11050 .got entry would be the same value as the .igot.plt entry,
11051 so there's no point creating both. */
11052 sgot = globals->root.igotplt;
11053 value = sgot->output_offset + gotplt_offset;
11054 }
11055 else if (h != NULL)
252b5132
RH		 11056 {
11057 bfd_vma off;
f21f3fe0 11058
252b5132
RH		 11059 off = h->got.offset;
11060 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11061 if ((off & 1) != 0)
252b5132 11062 {
b436d854
RS		 11063 /* We have already processsed one GOT relocation against
11064 this symbol. */
11065 off &= ~1;
11066 if (globals->root.dynamic_sections_created
11067 && !SYMBOL_REFERENCES_LOCAL (info, h))
11068 *unresolved_reloc_p = FALSE;
11069 }
11070 else
11071 {
11072 Elf_Internal_Rela outrel;
11073
6f820c85 11074 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11075 {
11076 /* If the symbol doesn't resolve locally in a static
11077 object, we have an undefined reference. If the
11078 symbol doesn't resolve locally in a dynamic object,
11079 it should be resolved by the dynamic linker. */
11080 if (globals->root.dynamic_sections_created)
11081 {
11082 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11083 *unresolved_reloc_p = FALSE;
11084 }
11085 else
11086 outrel.r_info = 0;
11087 outrel.r_addend = 0;
11088 }
252b5132
RH		 11089 else
11090 {
34e77a92 11091 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11092 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11093 else if (bfd_link_pic (info)
11094 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11095 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11096 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11097 else
11098 outrel.r_info = 0;
34e77a92 11099 outrel.r_addend = dynreloc_value;
b436d854 11100 }
ee29b9fb 11101
b436d854
RS		 11102 /* The GOT entry is initialized to zero by default.
11103 See if we should install a different value. */
11104 if (outrel.r_addend != 0
11105 && (outrel.r_info == 0 || globals->use_rel))
11106 {
11107 bfd_put_32 (output_bfd, outrel.r_addend,
11108 sgot->contents + off);
11109 outrel.r_addend = 0;
252b5132 11110 }
f21f3fe0 11111
b436d854
RS		 11112 if (outrel.r_info != 0)
11113 {
11114 outrel.r_offset = (sgot->output_section->vma
11115 + sgot->output_offset
11116 + off);
11117 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11118 }
11119 h->got.offset |= 1;
11120 }
252b5132
RH		 11121 value = sgot->output_offset + off;
11122 }
11123 else
11124 {
11125 bfd_vma off;
f21f3fe0 11126
5025eb7c
AO		 11127 BFD_ASSERT (local_got_offsets != NULL
11128 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11129
252b5132 11130 off = local_got_offsets[r_symndx];
f21f3fe0 11131
252b5132
RH		 11132 /* The offset must always be a multiple of 4. We use the
11133 least significant bit to record whether we have already
9b485d32 11134 generated the necessary reloc. */
252b5132
RH		 11135 if ((off & 1) != 0)
11136 off &= ~1;
11137 else
11138 {
00a97672 11139 if (globals->use_rel)
34e77a92 11140 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11141
0e1862bb 11142 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11143 {
947216bf 11144 Elf_Internal_Rela outrel;
f21f3fe0 11145
34e77a92 11146 outrel.r_addend = addend + dynreloc_value;
252b5132 11147 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11148 + sgot->output_offset
252b5132 11149 + off);
34e77a92 11150 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11151 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11152 else
11153 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11154 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11155 }
f21f3fe0 11156
252b5132
RH		 11157 local_got_offsets[r_symndx] |= 1;
11158 }
f21f3fe0 11159
252b5132
RH		 11160 value = sgot->output_offset + off;
11161 }
eb043451
PB		 11162 if (r_type != R_ARM_GOT32)
11163 value += sgot->output_section->vma;
9a5aca8c 11164
f21f3fe0 11165 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11166 contents, rel->r_offset, value,
00a97672 11167 rel->r_addend);
f21f3fe0 11168
ba93b8ac
DJ		 11169 case R_ARM_TLS_LDO32:
11170 value = value - dtpoff_base (info);
11171
11172 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11173 contents, rel->r_offset, value,
11174 rel->r_addend);
ba93b8ac
DJ		 11175
11176 case R_ARM_TLS_LDM32:
11177 {
11178 bfd_vma off;
11179
362d30a1 11180 if (sgot == NULL)
ba93b8ac
DJ		 11181 abort ();
11182
11183 off = globals->tls_ldm_got.offset;
11184
11185 if ((off & 1) != 0)
11186 off &= ~1;
11187 else
11188 {
11189 /* If we don't know the module number, create a relocation
11190 for it. */
0e1862bb 11191 if (bfd_link_pic (info))
ba93b8ac
DJ		 11192 {
11193 Elf_Internal_Rela outrel;
ba93b8ac 11194
362d30a1 11195 if (srelgot == NULL)
ba93b8ac
DJ		 11196 abort ();
11197
00a97672 11198 outrel.r_addend = 0;
362d30a1
RS		 11199 outrel.r_offset = (sgot->output_section->vma
11200 + sgot->output_offset + off);
ba93b8ac
DJ		 11201 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11202
00a97672
RS		 11203 if (globals->use_rel)
11204 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11205 sgot->contents + off);
ba93b8ac 11206
47beaa6a 11207 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11208 }
11209 else
362d30a1 11210 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11211
11212 globals->tls_ldm_got.offset |= 1;
11213 }
11214
362d30a1 11215 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11216 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11217
11218 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11219 contents, rel->r_offset, value,
00a97672 11220 rel->r_addend);
ba93b8ac
DJ		 11221 }
11222
0855e32b
NS		 11223 case R_ARM_TLS_CALL:
11224 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11225 case R_ARM_TLS_GD32:
11226 case R_ARM_TLS_IE32:
0855e32b
NS		 11227 case R_ARM_TLS_GOTDESC:
11228 case R_ARM_TLS_DESCSEQ:
11229 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11230 {
0855e32b
NS		 11231 bfd_vma off, offplt;
11232 int indx = 0;
ba93b8ac
DJ		 11233 char tls_type;
11234
0855e32b 11235 BFD_ASSERT (sgot != NULL);
ba93b8ac 11236
ba93b8ac
DJ		 11237 if (h != NULL)
11238 {
11239 bfd_boolean dyn;
11240 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11241 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11242 bfd_link_pic (info),
11243 h)
11244 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11245 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11246 {
11247 *unresolved_reloc_p = FALSE;
11248 indx = h->dynindx;
11249 }
11250 off = h->got.offset;
0855e32b 11251 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11252 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11253 }
11254 else
11255 {
0855e32b 11256 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11257 off = local_got_offsets[r_symndx];
0855e32b 11258 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11259 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11260 }
11261
0855e32b 11262 /* Linker relaxations happens from one of the
b38cadfb 11263 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11264 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11265 tls_type = GOT_TLS_IE;
0855e32b
NS		 11266
11267 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11268
11269 if ((off & 1) != 0)
11270 off &= ~1;
11271 else
11272 {
11273 bfd_boolean need_relocs = FALSE;
11274 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11275 int cur_off = off;
11276
11277 /* The GOT entries have not been initialized yet. Do it
11278 now, and emit any relocations. If both an IE GOT and a
11279 GD GOT are necessary, we emit the GD first. */
11280
0e1862bb 11281 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11282 && (h == NULL
11283 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11284 || h->root.type != bfd_link_hash_undefweak))
11285 {
11286 need_relocs = TRUE;
0855e32b 11287 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11288 }
11289
0855e32b
NS		 11290 if (tls_type & GOT_TLS_GDESC)
11291 {
47beaa6a
RS		 11292 bfd_byte *loc;
11293
0855e32b
NS		 11294 /* We should have relaxed, unless this is an undefined
11295 weak symbol. */
11296 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11297 || bfd_link_pic (info));
0855e32b 11298 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11299 <= globals->root.sgotplt->size);
0855e32b
NS		 11300
11301 outrel.r_addend = 0;
11302 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11303 + globals->root.sgotplt->output_offset
11304 + offplt
11305 + globals->sgotplt_jump_table_size);
b38cadfb 11306
0855e32b
NS		 11307 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11308 sreloc = globals->root.srelplt;
11309 loc = sreloc->contents;
11310 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11311 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11312 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11313
11314 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11315
11316 /* For globals, the first word in the relocation gets
11317 the relocation index and the top bit set, or zero,
11318 if we're binding now. For locals, it gets the
11319 symbol's offset in the tls section. */
99059e56 11320 bfd_put_32 (output_bfd,
0855e32b
NS		 11321 !h ? value - elf_hash_table (info)->tls_sec->vma
11322 : info->flags & DF_BIND_NOW ? 0
11323 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11324 globals->root.sgotplt->contents + offplt
11325 + globals->sgotplt_jump_table_size);
11326
0855e32b 11327 /* Second word in the relocation is always zero. */
99059e56 11328 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11329 globals->root.sgotplt->contents + offplt
11330 + globals->sgotplt_jump_table_size + 4);
0855e32b 11331 }
ba93b8ac
DJ		 11332 if (tls_type & GOT_TLS_GD)
11333 {
11334 if (need_relocs)
11335 {
00a97672 11336 outrel.r_addend = 0;
362d30a1
RS		 11337 outrel.r_offset = (sgot->output_section->vma
11338 + sgot->output_offset
00a97672 11339 + cur_off);
ba93b8ac 11340 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11341
00a97672
RS		 11342 if (globals->use_rel)
11343 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11344 sgot->contents + cur_off);
00a97672 11345
47beaa6a 11346 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11347
11348 if (indx == 0)
11349 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11350 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11351 else
11352 {
00a97672 11353 outrel.r_addend = 0;
ba93b8ac
DJ		 11354 outrel.r_info = ELF32_R_INFO (indx,
11355 R_ARM_TLS_DTPOFF32);
11356 outrel.r_offset += 4;
00a97672
RS		 11357
11358 if (globals->use_rel)
11359 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11360 sgot->contents + cur_off + 4);
00a97672 11361
47beaa6a
RS		 11362 elf32_arm_add_dynreloc (output_bfd, info,
11363 srelgot, &outrel);
ba93b8ac
DJ		 11364 }
11365 }
11366 else
11367 {
11368 /* If we are not emitting relocations for a
11369 general dynamic reference, then we must be in a
11370 static link or an executable link with the
11371 symbol binding locally. Mark it as belonging
11372 to module 1, the executable. */
11373 bfd_put_32 (output_bfd, 1,
362d30a1 11374 sgot->contents + cur_off);
ba93b8ac 11375 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11376 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11377 }
11378
11379 cur_off += 8;
11380 }
11381
11382 if (tls_type & GOT_TLS_IE)
11383 {
11384 if (need_relocs)
11385 {
00a97672
RS		 11386 if (indx == 0)
11387 outrel.r_addend = value - dtpoff_base (info);
11388 else
11389 outrel.r_addend = 0;
362d30a1
RS		 11390 outrel.r_offset = (sgot->output_section->vma
11391 + sgot->output_offset
ba93b8ac
DJ		 11392 + cur_off);
11393 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11394
00a97672
RS		 11395 if (globals->use_rel)
11396 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11397 sgot->contents + cur_off);
ba93b8ac 11398
47beaa6a 11399 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11400 }
11401 else
11402 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11403 sgot->contents + cur_off);
ba93b8ac
DJ		 11404 cur_off += 4;
11405 }
11406
11407 if (h != NULL)
11408 h->got.offset |= 1;
11409 else
11410 local_got_offsets[r_symndx] |= 1;
11411 }
11412
11413 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11414 off += 8;
0855e32b
NS		 11415 else if (tls_type & GOT_TLS_GDESC)
11416 off = offplt;
11417
11418 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11419 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11420 {
11421 bfd_signed_vma offset;
12352d3f
PB		 11422 /* TLS stubs are arm mode. The original symbol is a
11423 data object, so branch_type is bogus. */
11424 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11425 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11426 = arm_type_of_stub (info, input_section, rel,
11427 st_type, &branch_type,
0855e32b
NS		 11428 (struct elf32_arm_link_hash_entry *)h,
11429 globals->tls_trampoline, globals->root.splt,
11430 input_bfd, sym_name);
11431
11432 if (stub_type != arm_stub_none)
11433 {
11434 struct elf32_arm_stub_hash_entry *stub_entry
11435 = elf32_arm_get_stub_entry
11436 (input_section, globals->root.splt, 0, rel,
11437 globals, stub_type);
11438 offset = (stub_entry->stub_offset
11439 + stub_entry->stub_sec->output_offset
11440 + stub_entry->stub_sec->output_section->vma);
11441 }
11442 else
11443 offset = (globals->root.splt->output_section->vma
11444 + globals->root.splt->output_offset
11445 + globals->tls_trampoline);
11446
11447 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11448 {
11449 unsigned long inst;
b38cadfb
NC		 11450
11451 offset -= (input_section->output_section->vma
11452 + input_section->output_offset
11453 + rel->r_offset + 8);
0855e32b
NS		 11454
11455 inst = offset >> 2;
11456 inst &= 0x00ffffff;
11457 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11458 }
11459 else
11460 {
11461 /* Thumb blx encodes the offset in a complicated
11462 fashion. */
11463 unsigned upper_insn, lower_insn;
11464 unsigned neg;
11465
b38cadfb
NC		 11466 offset -= (input_section->output_section->vma
11467 + input_section->output_offset
0855e32b 11468 + rel->r_offset + 4);
b38cadfb 11469
12352d3f
PB		 11470 if (stub_type != arm_stub_none
11471 && arm_stub_is_thumb (stub_type))
11472 {
11473 lower_insn = 0xd000;
11474 }
11475 else
11476 {
11477 lower_insn = 0xc000;
6a631e86 11478 /* Round up the offset to a word boundary. */
12352d3f
PB		 11479 offset = (offset + 2) & ~2;
11480 }
11481
0855e32b
NS		 11482 neg = offset < 0;
11483 upper_insn = (0xf000
11484 | ((offset >> 12) & 0x3ff)
11485 | (neg << 10));
12352d3f 11486 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11487 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11488 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11489 bfd_put_16 (input_bfd, upper_insn, hit_data);
11490 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11491 return bfd_reloc_ok;
11492 }
11493 }
11494 /* These relocations needs special care, as besides the fact
11495 they point somewhere in .gotplt, the addend must be
11496 adjusted accordingly depending on the type of instruction
6a631e86 11497 we refer to. */
0855e32b
NS		 11498 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11499 {
11500 unsigned long data, insn;
11501 unsigned thumb;
b38cadfb 11502
0855e32b
NS		 11503 data = bfd_get_32 (input_bfd, hit_data);
11504 thumb = data & 1;
11505 data &= ~1u;
b38cadfb 11506
0855e32b
NS		 11507 if (thumb)
11508 {
11509 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11510 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11511 insn = (insn << 16)
11512 | bfd_get_16 (input_bfd,
11513 contents + rel->r_offset - data + 2);
11514 if ((insn & 0xf800c000) == 0xf000c000)
11515 /* bl/blx */
11516 value = -6;
11517 else if ((insn & 0xffffff00) == 0x4400)
11518 /* add */
11519 value = -5;
11520 else
11521 {
4eca0228 11522 _bfd_error_handler
695344c0
NC		 11523 /* xgettext:c-format */
11524 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11525 input_bfd, input_section,
11526 (unsigned long)rel->r_offset, insn);
11527 return bfd_reloc_notsupported;
11528 }
11529 }
11530 else
11531 {
11532 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11533
11534 switch (insn >> 24)
11535 {
11536 case 0xeb: /* bl */
11537 case 0xfa: /* blx */
11538 value = -4;
11539 break;
11540
11541 case 0xe0: /* add */
11542 value = -8;
11543 break;
b38cadfb 11544
0855e32b 11545 default:
4eca0228 11546 _bfd_error_handler
695344c0
NC		 11547 /* xgettext:c-format */
11548 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11549 input_bfd, input_section,
11550 (unsigned long)rel->r_offset, insn);
11551 return bfd_reloc_notsupported;
11552 }
11553 }
b38cadfb 11554
0855e32b
NS		 11555 value += ((globals->root.sgotplt->output_section->vma
11556 + globals->root.sgotplt->output_offset + off)
11557 - (input_section->output_section->vma
11558 + input_section->output_offset
11559 + rel->r_offset)
11560 + globals->sgotplt_jump_table_size);
11561 }
11562 else
11563 value = ((globals->root.sgot->output_section->vma
11564 + globals->root.sgot->output_offset + off)
11565 - (input_section->output_section->vma
11566 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11567
11568 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11569 contents, rel->r_offset, value,
00a97672 11570 rel->r_addend);
ba93b8ac
DJ		 11571 }
11572
11573 case R_ARM_TLS_LE32:
3cbc1e5e 11574 if (bfd_link_dll (info))
ba93b8ac 11575 {
4eca0228 11576 _bfd_error_handler
695344c0 11577 /* xgettext:c-format */
ba93b8ac
DJ		 11578 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11579 input_bfd, input_section,
11580 (long) rel->r_offset, howto->name);
46691134 11581 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11582 }
11583 else
11584 value = tpoff (info, value);
906e58ca 11585
ba93b8ac 11586 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11587 contents, rel->r_offset, value,
11588 rel->r_addend);
ba93b8ac 11589
319850b4
JB		 11590 case R_ARM_V4BX:
11591 if (globals->fix_v4bx)
845b51d6
PB		 11592 {
11593 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11594
845b51d6
PB		 11595 /* Ensure that we have a BX instruction. */
11596 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11597
845b51d6
PB		 11598 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11599 {
11600 /* Branch to veneer. */
11601 bfd_vma glue_addr;
11602 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11603 glue_addr -= input_section->output_section->vma
11604 + input_section->output_offset
11605 + rel->r_offset + 8;
11606 insn = (insn & 0xf0000000) | 0x0a000000
11607 | ((glue_addr >> 2) & 0x00ffffff);
11608 }
11609 else
11610 {
11611 /* Preserve Rm (lowest four bits) and the condition code
11612 (highest four bits). Other bits encode MOV PC,Rm. */
11613 insn = (insn & 0xf000000f) | 0x01a0f000;
11614 }
319850b4 11615
845b51d6
PB		 11616 bfd_put_32 (input_bfd, insn, hit_data);
11617 }
319850b4
JB		 11618 return bfd_reloc_ok;
11619
b6895b4f
PB		 11620 case R_ARM_MOVW_ABS_NC:
11621 case R_ARM_MOVT_ABS:
11622 case R_ARM_MOVW_PREL_NC:
11623 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11624 /* Until we properly support segment-base-relative addressing then
11625 we assume the segment base to be zero, as for the group relocations.
11626 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11627 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11628 case R_ARM_MOVW_BREL_NC:
11629 case R_ARM_MOVW_BREL:
11630 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11631 {
11632 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11633
11634 if (globals->use_rel)
11635 {
11636 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11637 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11638 }
92f5d02b 11639
b6895b4f 11640 value += signed_addend;
b6895b4f
PB		 11641
11642 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11643 value -= (input_section->output_section->vma
11644 + input_section->output_offset + rel->r_offset);
11645
92f5d02b 11646 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11647 return bfd_reloc_overflow;
92f5d02b 11648
35fc36a8 11649 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11650 value |= 1;
11651
11652 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11653 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11654 value >>= 16;
11655
11656 insn &= 0xfff0f000;
11657 insn |= value & 0xfff;
11658 insn |= (value & 0xf000) << 4;
11659 bfd_put_32 (input_bfd, insn, hit_data);
11660 }
11661 return bfd_reloc_ok;
11662
11663 case R_ARM_THM_MOVW_ABS_NC:
11664 case R_ARM_THM_MOVT_ABS:
11665 case R_ARM_THM_MOVW_PREL_NC:
11666 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11667 /* Until we properly support segment-base-relative addressing then
11668 we assume the segment base to be zero, as for the above relocations.
11669 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11670 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11671 as R_ARM_THM_MOVT_ABS. */
11672 case R_ARM_THM_MOVW_BREL_NC:
11673 case R_ARM_THM_MOVW_BREL:
11674 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11675 {
11676 bfd_vma insn;
906e58ca 11677
b6895b4f
PB		 11678 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11679 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11680
11681 if (globals->use_rel)
11682 {
11683 addend = ((insn >> 4) & 0xf000)
11684 | ((insn >> 15) & 0x0800)
11685 | ((insn >> 4) & 0x0700)
11686 | (insn & 0x00ff);
39623e12 11687 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11688 }
92f5d02b 11689
b6895b4f 11690 value += signed_addend;
b6895b4f
PB		 11691
11692 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11693 value -= (input_section->output_section->vma
11694 + input_section->output_offset + rel->r_offset);
11695
92f5d02b 11696 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11697 return bfd_reloc_overflow;
92f5d02b 11698
35fc36a8 11699 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11700 value |= 1;
11701
11702 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11703 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11704 value >>= 16;
11705
11706 insn &= 0xfbf08f00;
11707 insn |= (value & 0xf000) << 4;
11708 insn |= (value & 0x0800) << 15;
11709 insn |= (value & 0x0700) << 4;
11710 insn |= (value & 0x00ff);
11711
11712 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11713 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11714 }
11715 return bfd_reloc_ok;
11716
4962c51a
MS		 11717 case R_ARM_ALU_PC_G0_NC:
11718 case R_ARM_ALU_PC_G1_NC:
11719 case R_ARM_ALU_PC_G0:
11720 case R_ARM_ALU_PC_G1:
11721 case R_ARM_ALU_PC_G2:
11722 case R_ARM_ALU_SB_G0_NC:
11723 case R_ARM_ALU_SB_G1_NC:
11724 case R_ARM_ALU_SB_G0:
11725 case R_ARM_ALU_SB_G1:
11726 case R_ARM_ALU_SB_G2:
11727 {
11728 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11729 bfd_vma pc = input_section->output_section->vma
4962c51a 11730 + input_section->output_offset + rel->r_offset;
31a91d61 11731 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11732 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11733 bfd_vma residual;
11734 bfd_vma g_n;
4962c51a 11735 bfd_signed_vma signed_value;
99059e56
RM		 11736 int group = 0;
11737
11738 /* Determine which group of bits to select. */
11739 switch (r_type)
11740 {
11741 case R_ARM_ALU_PC_G0_NC:
11742 case R_ARM_ALU_PC_G0:
11743 case R_ARM_ALU_SB_G0_NC:
11744 case R_ARM_ALU_SB_G0:
11745 group = 0;
11746 break;
11747
11748 case R_ARM_ALU_PC_G1_NC:
11749 case R_ARM_ALU_PC_G1:
11750 case R_ARM_ALU_SB_G1_NC:
11751 case R_ARM_ALU_SB_G1:
11752 group = 1;
11753 break;
11754
11755 case R_ARM_ALU_PC_G2:
11756 case R_ARM_ALU_SB_G2:
11757 group = 2;
11758 break;
11759
11760 default:
11761 abort ();
11762 }
11763
11764 /* If REL, extract the addend from the insn. If RELA, it will
11765 have already been fetched for us. */
4962c51a 11766 if (globals->use_rel)
99059e56
RM		 11767 {
11768 int negative;
11769 bfd_vma constant = insn & 0xff;
11770 bfd_vma rotation = (insn & 0xf00) >> 8;
11771
11772 if (rotation == 0)
11773 signed_addend = constant;
11774 else
11775 {
11776 /* Compensate for the fact that in the instruction, the
11777 rotation is stored in multiples of 2 bits. */
11778 rotation *= 2;
11779
11780 /* Rotate "constant" right by "rotation" bits. */
11781 signed_addend = (constant >> rotation) |
11782 (constant << (8 * sizeof (bfd_vma) - rotation));
11783 }
11784
11785 /* Determine if the instruction is an ADD or a SUB.
11786 (For REL, this determines the sign of the addend.) */
11787 negative = identify_add_or_sub (insn);
11788 if (negative == 0)
11789 {
4eca0228 11790 _bfd_error_handler
695344c0 11791 /* xgettext:c-format */
99059e56
RM		 11792 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11793 input_bfd, input_section,
11794 (long) rel->r_offset, howto->name);
11795 return bfd_reloc_overflow;
11796 }
11797
11798 signed_addend *= negative;
11799 }
4962c51a
MS		 11800
11801 /* Compute the value (X) to go in the place. */
99059e56
RM		 11802 if (r_type == R_ARM_ALU_PC_G0_NC
11803 || r_type == R_ARM_ALU_PC_G1_NC
11804 || r_type == R_ARM_ALU_PC_G0
11805 || r_type == R_ARM_ALU_PC_G1
11806 || r_type == R_ARM_ALU_PC_G2)
11807 /* PC relative. */
11808 signed_value = value - pc + signed_addend;
11809 else
11810 /* Section base relative. */
11811 signed_value = value - sb + signed_addend;
11812
11813 /* If the target symbol is a Thumb function, then set the
11814 Thumb bit in the address. */
35fc36a8 11815 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11816 signed_value |= 1;
11817
99059e56
RM		 11818 /* Calculate the value of the relevant G_n, in encoded
11819 constant-with-rotation format. */
b6518b38
NC		 11820 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11821 group, &residual);
99059e56
RM		 11822
11823 /* Check for overflow if required. */
11824 if ((r_type == R_ARM_ALU_PC_G0
11825 || r_type == R_ARM_ALU_PC_G1
11826 || r_type == R_ARM_ALU_PC_G2
11827 || r_type == R_ARM_ALU_SB_G0
11828 || r_type == R_ARM_ALU_SB_G1
11829 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11830 {
4eca0228 11831 _bfd_error_handler
695344c0 11832 /* xgettext:c-format */
99059e56
RM		 11833 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11834 input_bfd, input_section,
b6518b38
NC		 11835 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11836 howto->name);
99059e56
RM		 11837 return bfd_reloc_overflow;
11838 }
11839
11840 /* Mask out the value and the ADD/SUB part of the opcode; take care
11841 not to destroy the S bit. */
11842 insn &= 0xff1ff000;
11843
11844 /* Set the opcode according to whether the value to go in the
11845 place is negative. */
11846 if (signed_value < 0)
11847 insn |= 1 << 22;
11848 else
11849 insn |= 1 << 23;
11850
11851 /* Encode the offset. */
11852 insn |= g_n;
4962c51a
MS		 11853
11854 bfd_put_32 (input_bfd, insn, hit_data);
11855 }
11856 return bfd_reloc_ok;
11857
11858 case R_ARM_LDR_PC_G0:
11859 case R_ARM_LDR_PC_G1:
11860 case R_ARM_LDR_PC_G2:
11861 case R_ARM_LDR_SB_G0:
11862 case R_ARM_LDR_SB_G1:
11863 case R_ARM_LDR_SB_G2:
11864 {
11865 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11866 bfd_vma pc = input_section->output_section->vma
4962c51a 11867 + input_section->output_offset + rel->r_offset;
31a91d61 11868 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11869 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11870 bfd_vma residual;
4962c51a 11871 bfd_signed_vma signed_value;
99059e56
RM		 11872 int group = 0;
11873
11874 /* Determine which groups of bits to calculate. */
11875 switch (r_type)
11876 {
11877 case R_ARM_LDR_PC_G0:
11878 case R_ARM_LDR_SB_G0:
11879 group = 0;
11880 break;
11881
11882 case R_ARM_LDR_PC_G1:
11883 case R_ARM_LDR_SB_G1:
11884 group = 1;
11885 break;
11886
11887 case R_ARM_LDR_PC_G2:
11888 case R_ARM_LDR_SB_G2:
11889 group = 2;
11890 break;
11891
11892 default:
11893 abort ();
11894 }
11895
11896 /* If REL, extract the addend from the insn. If RELA, it will
11897 have already been fetched for us. */
4962c51a 11898 if (globals->use_rel)
99059e56
RM		 11899 {
11900 int negative = (insn & (1 << 23)) ? 1 : -1;
11901 signed_addend = negative * (insn & 0xfff);
11902 }
4962c51a
MS		 11903
11904 /* Compute the value (X) to go in the place. */
99059e56
RM		 11905 if (r_type == R_ARM_LDR_PC_G0
11906 || r_type == R_ARM_LDR_PC_G1
11907 || r_type == R_ARM_LDR_PC_G2)
11908 /* PC relative. */
11909 signed_value = value - pc + signed_addend;
11910 else
11911 /* Section base relative. */
11912 signed_value = value - sb + signed_addend;
11913
11914 /* Calculate the value of the relevant G_{n-1} to obtain
11915 the residual at that stage. */
b6518b38
NC		 11916 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11917 group - 1, &residual);
99059e56
RM		 11918
11919 /* Check for overflow. */
11920 if (residual >= 0x1000)
11921 {
4eca0228 11922 _bfd_error_handler
695344c0 11923 /* xgettext:c-format */
99059e56 11924 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11925 input_bfd, input_section,
11926 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11927 return bfd_reloc_overflow;
11928 }
11929
11930 /* Mask out the value and U bit. */
11931 insn &= 0xff7ff000;
11932
11933 /* Set the U bit if the value to go in the place is non-negative. */
11934 if (signed_value >= 0)
11935 insn |= 1 << 23;
11936
11937 /* Encode the offset. */
11938 insn |= residual;
4962c51a
MS		 11939
11940 bfd_put_32 (input_bfd, insn, hit_data);
11941 }
11942 return bfd_reloc_ok;
11943
11944 case R_ARM_LDRS_PC_G0:
11945 case R_ARM_LDRS_PC_G1:
11946 case R_ARM_LDRS_PC_G2:
11947 case R_ARM_LDRS_SB_G0:
11948 case R_ARM_LDRS_SB_G1:
11949 case R_ARM_LDRS_SB_G2:
11950 {
11951 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11952 bfd_vma pc = input_section->output_section->vma
4962c51a 11953 + input_section->output_offset + rel->r_offset;
31a91d61 11954 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11955 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11956 bfd_vma residual;
4962c51a 11957 bfd_signed_vma signed_value;
99059e56
RM		 11958 int group = 0;
11959
11960 /* Determine which groups of bits to calculate. */
11961 switch (r_type)
11962 {
11963 case R_ARM_LDRS_PC_G0:
11964 case R_ARM_LDRS_SB_G0:
11965 group = 0;
11966 break;
11967
11968 case R_ARM_LDRS_PC_G1:
11969 case R_ARM_LDRS_SB_G1:
11970 group = 1;
11971 break;
11972
11973 case R_ARM_LDRS_PC_G2:
11974 case R_ARM_LDRS_SB_G2:
11975 group = 2;
11976 break;
11977
11978 default:
11979 abort ();
11980 }
11981
11982 /* If REL, extract the addend from the insn. If RELA, it will
11983 have already been fetched for us. */
4962c51a 11984 if (globals->use_rel)
99059e56
RM		 11985 {
11986 int negative = (insn & (1 << 23)) ? 1 : -1;
11987 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11988 }
4962c51a
MS		 11989
11990 /* Compute the value (X) to go in the place. */
99059e56
RM		 11991 if (r_type == R_ARM_LDRS_PC_G0
11992 || r_type == R_ARM_LDRS_PC_G1
11993 || r_type == R_ARM_LDRS_PC_G2)
11994 /* PC relative. */
11995 signed_value = value - pc + signed_addend;
11996 else
11997 /* Section base relative. */
11998 signed_value = value - sb + signed_addend;
11999
12000 /* Calculate the value of the relevant G_{n-1} to obtain
12001 the residual at that stage. */
b6518b38
NC		 12002 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12003 group - 1, &residual);
99059e56
RM		 12004
12005 /* Check for overflow. */
12006 if (residual >= 0x100)
12007 {
4eca0228 12008 _bfd_error_handler
695344c0 12009 /* xgettext:c-format */
99059e56 12010 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12011 input_bfd, input_section,
12012 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12013 return bfd_reloc_overflow;
12014 }
12015
12016 /* Mask out the value and U bit. */
12017 insn &= 0xff7ff0f0;
12018
12019 /* Set the U bit if the value to go in the place is non-negative. */
12020 if (signed_value >= 0)
12021 insn |= 1 << 23;
12022
12023 /* Encode the offset. */
12024 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12025
12026 bfd_put_32 (input_bfd, insn, hit_data);
12027 }
12028 return bfd_reloc_ok;
12029
12030 case R_ARM_LDC_PC_G0:
12031 case R_ARM_LDC_PC_G1:
12032 case R_ARM_LDC_PC_G2:
12033 case R_ARM_LDC_SB_G0:
12034 case R_ARM_LDC_SB_G1:
12035 case R_ARM_LDC_SB_G2:
12036 {
12037 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12038 bfd_vma pc = input_section->output_section->vma
4962c51a 12039 + input_section->output_offset + rel->r_offset;
31a91d61 12040 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12041 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12042 bfd_vma residual;
4962c51a 12043 bfd_signed_vma signed_value;
99059e56
RM		 12044 int group = 0;
12045
12046 /* Determine which groups of bits to calculate. */
12047 switch (r_type)
12048 {
12049 case R_ARM_LDC_PC_G0:
12050 case R_ARM_LDC_SB_G0:
12051 group = 0;
12052 break;
12053
12054 case R_ARM_LDC_PC_G1:
12055 case R_ARM_LDC_SB_G1:
12056 group = 1;
12057 break;
12058
12059 case R_ARM_LDC_PC_G2:
12060 case R_ARM_LDC_SB_G2:
12061 group = 2;
12062 break;
12063
12064 default:
12065 abort ();
12066 }
12067
12068 /* If REL, extract the addend from the insn. If RELA, it will
12069 have already been fetched for us. */
4962c51a 12070 if (globals->use_rel)
99059e56
RM		 12071 {
12072 int negative = (insn & (1 << 23)) ? 1 : -1;
12073 signed_addend = negative * ((insn & 0xff) << 2);
12074 }
4962c51a
MS		 12075
12076 /* Compute the value (X) to go in the place. */
99059e56
RM		 12077 if (r_type == R_ARM_LDC_PC_G0
12078 || r_type == R_ARM_LDC_PC_G1
12079 || r_type == R_ARM_LDC_PC_G2)
12080 /* PC relative. */
12081 signed_value = value - pc + signed_addend;
12082 else
12083 /* Section base relative. */
12084 signed_value = value - sb + signed_addend;
12085
12086 /* Calculate the value of the relevant G_{n-1} to obtain
12087 the residual at that stage. */
b6518b38
NC		 12088 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12089 group - 1, &residual);
99059e56
RM		 12090
12091 /* Check for overflow. (The absolute value to go in the place must be
12092 divisible by four and, after having been divided by four, must
12093 fit in eight bits.) */
12094 if ((residual & 0x3) != 0 || residual >= 0x400)
12095 {
4eca0228 12096 _bfd_error_handler
695344c0 12097 /* xgettext:c-format */
99059e56
RM		 12098 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12099 input_bfd, input_section,
b6518b38 12100 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12101 return bfd_reloc_overflow;
12102 }
12103
12104 /* Mask out the value and U bit. */
12105 insn &= 0xff7fff00;
12106
12107 /* Set the U bit if the value to go in the place is non-negative. */
12108 if (signed_value >= 0)
12109 insn |= 1 << 23;
12110
12111 /* Encode the offset. */
12112 insn |= residual >> 2;
4962c51a
MS		 12113
12114 bfd_put_32 (input_bfd, insn, hit_data);
12115 }
12116 return bfd_reloc_ok;
12117
72d98d16
MG		 12118 case R_ARM_THM_ALU_ABS_G0_NC:
12119 case R_ARM_THM_ALU_ABS_G1_NC:
12120 case R_ARM_THM_ALU_ABS_G2_NC:
12121 case R_ARM_THM_ALU_ABS_G3_NC:
12122 {
12123 const int shift_array[4] = {0, 8, 16, 24};
12124 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12125 bfd_vma addr = value;
12126 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12127
12128 /* Compute address. */
12129 if (globals->use_rel)
12130 signed_addend = insn & 0xff;
12131 addr += signed_addend;
12132 if (branch_type == ST_BRANCH_TO_THUMB)
12133 addr |= 1;
12134 /* Clean imm8 insn. */
12135 insn &= 0xff00;
12136 /* And update with correct part of address. */
12137 insn |= (addr >> shift) & 0xff;
12138 /* Update insn. */
12139 bfd_put_16 (input_bfd, insn, hit_data);
12140 }
12141
12142 *unresolved_reloc_p = FALSE;
12143 return bfd_reloc_ok;
12144
252b5132
RH		 12145 default:
12146 return bfd_reloc_notsupported;
12147 }
12148}
12149
98c1d4aa
NC		 12150/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12151static void
57e8b36a
NC		 12152arm_add_to_rel (bfd * abfd,
12153 bfd_byte * address,
12154 reloc_howto_type * howto,
12155 bfd_signed_vma increment)
98c1d4aa 12156{
98c1d4aa
NC		 12157 bfd_signed_vma addend;
12158
bd97cb95
DJ		 12159 if (howto->type == R_ARM_THM_CALL
12160 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12161 {
9a5aca8c
AM		 12162 int upper_insn, lower_insn;
12163 int upper, lower;
98c1d4aa 12164
9a5aca8c
AM		 12165 upper_insn = bfd_get_16 (abfd, address);
12166 lower_insn = bfd_get_16 (abfd, address + 2);
12167 upper = upper_insn & 0x7ff;
12168 lower = lower_insn & 0x7ff;
12169
12170 addend = (upper << 12) | (lower << 1);
ddda4409 12171 addend += increment;
9a5aca8c 12172 addend >>= 1;
98c1d4aa 12173
9a5aca8c
AM		 12174 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12175 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12176
dc810e39
AM		 12177 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12178 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12179 }
12180 else
12181 {
12182 bfd_vma contents;
12183
12184 contents = bfd_get_32 (abfd, address);
12185
12186 /* Get the (signed) value from the instruction. */
12187 addend = contents & howto->src_mask;
12188 if (addend & ((howto->src_mask + 1) >> 1))
12189 {
12190 bfd_signed_vma mask;
12191
12192 mask = -1;
12193 mask &= ~ howto->src_mask;
12194 addend |= mask;
12195 }
12196
12197 /* Add in the increment, (which is a byte value). */
12198 switch (howto->type)
12199 {
12200 default:
12201 addend += increment;
12202 break;
12203
12204 case R_ARM_PC24:
c6596c5e 12205 case R_ARM_PLT32:
5b5bb741
PB		 12206 case R_ARM_CALL:
12207 case R_ARM_JUMP24:
9a5aca8c 12208 addend <<= howto->size;
dc810e39 12209 addend += increment;
9a5aca8c
AM		 12210
12211 /* Should we check for overflow here ? */
12212
12213 /* Drop any undesired bits. */
12214 addend >>= howto->rightshift;
12215 break;
12216 }
12217
12218 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12219
12220 bfd_put_32 (abfd, contents, address);
ddda4409 12221 }
98c1d4aa 12222}
252b5132 12223
ba93b8ac
DJ		 12224#define IS_ARM_TLS_RELOC(R_TYPE) \
12225 ((R_TYPE) == R_ARM_TLS_GD32 \
12226 || (R_TYPE) == R_ARM_TLS_LDO32 \
12227 || (R_TYPE) == R_ARM_TLS_LDM32 \
12228 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12229 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12230 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12231 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12232 || (R_TYPE) == R_ARM_TLS_IE32 \
12233 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12234
12235/* Specific set of relocations for the gnu tls dialect. */
12236#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12237 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12238 || (R_TYPE) == R_ARM_TLS_CALL \
12239 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12240 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12241 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12242
252b5132 12243/* Relocate an ARM ELF section. */
906e58ca 12244
b34976b6 12245static bfd_boolean
57e8b36a
NC		 12246elf32_arm_relocate_section (bfd * output_bfd,
12247 struct bfd_link_info * info,
12248 bfd * input_bfd,
12249 asection * input_section,
12250 bfd_byte * contents,
12251 Elf_Internal_Rela * relocs,
12252 Elf_Internal_Sym * local_syms,
12253 asection ** local_sections)
252b5132 12254{
b34976b6
AM		 12255 Elf_Internal_Shdr *symtab_hdr;
12256 struct elf_link_hash_entry **sym_hashes;
12257 Elf_Internal_Rela *rel;
12258 Elf_Internal_Rela *relend;
12259 const char *name;
b32d3aa2 12260 struct elf32_arm_link_hash_table * globals;
252b5132 12261
4e7fd91e 12262 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12263 if (globals == NULL)
12264 return FALSE;
b491616a 12265
0ffa91dd 12266 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12267 sym_hashes = elf_sym_hashes (input_bfd);
12268
12269 rel = relocs;
12270 relend = relocs + input_section->reloc_count;
12271 for (; rel < relend; rel++)
12272 {
ba96a88f
NC		 12273 int r_type;
12274 reloc_howto_type * howto;
12275 unsigned long r_symndx;
12276 Elf_Internal_Sym * sym;
12277 asection * sec;
252b5132 12278 struct elf_link_hash_entry * h;
ba96a88f
NC		 12279 bfd_vma relocation;
12280 bfd_reloc_status_type r;
12281 arelent bfd_reloc;
ba93b8ac 12282 char sym_type;
0945cdfd 12283 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12284 char *error_message = NULL;
f21f3fe0 12285
252b5132 12286 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12287 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12288 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12289
ba96a88f 12290 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12291 || r_type == R_ARM_GNU_VTINHERIT)
12292 continue;
252b5132 12293
b32d3aa2 12294 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12295 howto = bfd_reloc.howto;
252b5132 12296
252b5132
RH		 12297 h = NULL;
12298 sym = NULL;
12299 sec = NULL;
9b485d32 12300
252b5132
RH		 12301 if (r_symndx < symtab_hdr->sh_info)
12302 {
12303 sym = local_syms + r_symndx;
ba93b8ac 12304 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12305 sec = local_sections[r_symndx];
ffcb4889
NS		 12306
12307 /* An object file might have a reference to a local
12308 undefined symbol. This is a daft object file, but we
12309 should at least do something about it. V4BX & NONE
12310 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12311 allowed to use the undefined symbol, so allow those.
12312 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12313 if (r_type != R_ARM_V4BX
12314 && r_type != R_ARM_NONE
77b4f08f 12315 && r_symndx != STN_UNDEF
ffcb4889
NS		 12316 && bfd_is_und_section (sec)
12317 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12318 (*info->callbacks->undefined_symbol)
12319 (info, bfd_elf_string_from_elf_section
12320 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12321 input_bfd, input_section,
12322 rel->r_offset, TRUE);
b38cadfb 12323
4e7fd91e 12324 if (globals->use_rel)
f8df10f4 12325 {
4e7fd91e
PB		 12326 relocation = (sec->output_section->vma
12327 + sec->output_offset
12328 + sym->st_value);
0e1862bb 12329 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12330 && (sec->flags & SEC_MERGE)
12331 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12332 {
4e7fd91e
PB		 12333 asection *msec;
12334 bfd_vma addend, value;
12335
39623e12 12336 switch (r_type)
4e7fd91e 12337 {
39623e12
PB		 12338 case R_ARM_MOVW_ABS_NC:
12339 case R_ARM_MOVT_ABS:
12340 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12341 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12342 addend = (addend ^ 0x8000) - 0x8000;
12343 break;
f8df10f4 12344
39623e12
PB		 12345 case R_ARM_THM_MOVW_ABS_NC:
12346 case R_ARM_THM_MOVT_ABS:
12347 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12348 << 16;
12349 value |= bfd_get_16 (input_bfd,
12350 contents + rel->r_offset + 2);
12351 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12352 | ((value & 0x04000000) >> 15);
12353 addend = (addend ^ 0x8000) - 0x8000;
12354 break;
f8df10f4 12355
39623e12
PB		 12356 default:
12357 if (howto->rightshift
12358 || (howto->src_mask & (howto->src_mask + 1)))
12359 {
4eca0228 12360 _bfd_error_handler
695344c0 12361 /* xgettext:c-format */
39623e12
PB		 12362 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12363 input_bfd, input_section,
12364 (long) rel->r_offset, howto->name);
12365 return FALSE;
12366 }
12367
12368 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12369
12370 /* Get the (signed) value from the instruction. */
12371 addend = value & howto->src_mask;
12372 if (addend & ((howto->src_mask + 1) >> 1))
12373 {
12374 bfd_signed_vma mask;
12375
12376 mask = -1;
12377 mask &= ~ howto->src_mask;
12378 addend |= mask;
12379 }
12380 break;
4e7fd91e 12381 }
39623e12 12382
4e7fd91e
PB		 12383 msec = sec;
12384 addend =
12385 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12386 - relocation;
12387 addend += msec->output_section->vma + msec->output_offset;
39623e12 12388
cc643b88 12389 /* Cases here must match those in the preceding
39623e12
PB		 12390 switch statement. */
12391 switch (r_type)
12392 {
12393 case R_ARM_MOVW_ABS_NC:
12394 case R_ARM_MOVT_ABS:
12395 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12396 | (addend & 0xfff);
12397 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12398 break;
12399
12400 case R_ARM_THM_MOVW_ABS_NC:
12401 case R_ARM_THM_MOVT_ABS:
12402 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12403 | (addend & 0xff) | ((addend & 0x0800) << 15);
12404 bfd_put_16 (input_bfd, value >> 16,
12405 contents + rel->r_offset);
12406 bfd_put_16 (input_bfd, value,
12407 contents + rel->r_offset + 2);
12408 break;
12409
12410 default:
12411 value = (value & ~ howto->dst_mask)
12412 | (addend & howto->dst_mask);
12413 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12414 break;
12415 }
f8df10f4 12416 }
f8df10f4 12417 }
4e7fd91e
PB		 12418 else
12419 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12420 }
12421 else
12422 {
62d887d4 12423 bfd_boolean warned, ignored;
560e09e9 12424
b2a8e766
AM		 12425 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12426 r_symndx, symtab_hdr, sym_hashes,
12427 h, sec, relocation,
62d887d4 12428 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12429
12430 sym_type = h->type;
252b5132
RH		 12431 }
12432
dbaa2011 12433 if (sec != NULL && discarded_section (sec))
e4067dbb 12434 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12435 rel, 1, relend, howto, 0, contents);
ab96bf03 12436
0e1862bb 12437 if (bfd_link_relocatable (info))
ab96bf03
AM		 12438 {
12439 /* This is a relocatable link. We don't have to change
12440 anything, unless the reloc is against a section symbol,
12441 in which case we have to adjust according to where the
12442 section symbol winds up in the output section. */
12443 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12444 {
12445 if (globals->use_rel)
12446 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12447 howto, (bfd_signed_vma) sec->output_offset);
12448 else
12449 rel->r_addend += sec->output_offset;
12450 }
12451 continue;
12452 }
12453
252b5132
RH		 12454 if (h != NULL)
12455 name = h->root.root.string;
12456 else
12457 {
12458 name = (bfd_elf_string_from_elf_section
12459 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12460 if (name == NULL || *name == '\0')
12461 name = bfd_section_name (input_bfd, sec);
12462 }
f21f3fe0 12463
cf35638d 12464 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12465 && r_type != R_ARM_NONE
12466 && (h == NULL
12467 || h->root.type == bfd_link_hash_defined
12468 || h->root.type == bfd_link_hash_defweak)
12469 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12470 {
4eca0228 12471 _bfd_error_handler
ba93b8ac 12472 ((sym_type == STT_TLS
695344c0 12473 /* xgettext:c-format */
ba93b8ac 12474 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12475 /* xgettext:c-format */
ba93b8ac
DJ		 12476 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12477 input_bfd,
12478 input_section,
12479 (long) rel->r_offset,
12480 howto->name,
12481 name);
12482 }
12483
0855e32b 12484 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12485 done, i.e., the relaxation produced the final output we want,
12486 and we won't let anybody mess with it. Also, we have to do
12487 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12488 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12489 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12490 || (IS_ARM_TLS_GNU_RELOC (r_type)
12491 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12492 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12493 & GOT_TLS_GDESC)))
12494 {
12495 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12496 contents, rel, h == NULL);
12497 /* This may have been marked unresolved because it came from
12498 a shared library. But we've just dealt with that. */
12499 unresolved_reloc = 0;
12500 }
12501 else
12502 r = bfd_reloc_continue;
b38cadfb 12503
39d911fc
TP		 12504 if (r == bfd_reloc_continue)
12505 {
12506 unsigned char branch_type =
12507 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12508 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12509
12510 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12511 input_section, contents, rel,
12512 relocation, info, sec, name,
12513 sym_type, branch_type, h,
12514 &unresolved_reloc,
12515 &error_message);
12516 }
0945cdfd
DJ		 12517
12518 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12519 because such sections are not SEC_ALLOC and thus ld.so will
12520 not process them. */
12521 if (unresolved_reloc
99059e56
RM		 12522 && !((input_section->flags & SEC_DEBUGGING) != 0
12523 && h->def_dynamic)
1d5316ab
AM		 12524 && _bfd_elf_section_offset (output_bfd, info, input_section,
12525 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12526 {
4eca0228 12527 _bfd_error_handler
695344c0 12528 /* xgettext:c-format */
843fe662
L		 12529 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12530 input_bfd,
12531 input_section,
12532 (long) rel->r_offset,
12533 howto->name,
12534 h->root.root.string);
0945cdfd
DJ		 12535 return FALSE;
12536 }
252b5132
RH		 12537
12538 if (r != bfd_reloc_ok)
12539 {
252b5132
RH		 12540 switch (r)
12541 {
12542 case bfd_reloc_overflow:
cf919dfd
PB		 12543 /* If the overflowing reloc was to an undefined symbol,
12544 we have already printed one error message and there
12545 is no point complaining again. */
1a72702b
AM		 12546 if (!h || h->root.type != bfd_link_hash_undefined)
12547 (*info->callbacks->reloc_overflow)
12548 (info, (h ? &h->root : NULL), name, howto->name,
12549 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12550 break;
12551
12552 case bfd_reloc_undefined:
1a72702b
AM		 12553 (*info->callbacks->undefined_symbol)
12554 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12555 break;
12556
12557 case bfd_reloc_outofrange:
f2a9dd69 12558 error_message = _("out of range");
252b5132
RH		 12559 goto common_error;
12560
12561 case bfd_reloc_notsupported:
f2a9dd69 12562 error_message = _("unsupported relocation");
252b5132
RH		 12563 goto common_error;
12564
12565 case bfd_reloc_dangerous:
f2a9dd69 12566 /* error_message should already be set. */
252b5132
RH		 12567 goto common_error;
12568
12569 default:
f2a9dd69 12570 error_message = _("unknown error");
8029a119 12571 /* Fall through. */
252b5132
RH		 12572
12573 common_error:
f2a9dd69 12574 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12575 (*info->callbacks->reloc_dangerous)
12576 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12577 break;
12578 }
12579 }
12580 }
12581
b34976b6 12582 return TRUE;
252b5132
RH		 12583}
12584
91d6fa6a 12585/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12586 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12587 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12588 maintaining that condition). */
12589
12590static void
12591add_unwind_table_edit (arm_unwind_table_edit **head,
12592 arm_unwind_table_edit **tail,
12593 arm_unwind_edit_type type,
12594 asection *linked_section,
91d6fa6a 12595 unsigned int tindex)
2468f9c9 12596{
21d799b5
NC		 12597 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12598 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12599
2468f9c9
PB		 12600 new_edit->type = type;
12601 new_edit->linked_section = linked_section;
91d6fa6a 12602 new_edit->index = tindex;
b38cadfb 12603
91d6fa6a 12604 if (tindex > 0)
2468f9c9
PB		 12605 {
12606 new_edit->next = NULL;
12607
12608 if (*tail)
12609 (*tail)->next = new_edit;
12610
12611 (*tail) = new_edit;
12612
12613 if (!*head)
12614 (*head) = new_edit;
12615 }
12616 else
12617 {
12618 new_edit->next = *head;
12619
12620 if (!*tail)
12621 *tail = new_edit;
12622
12623 *head = new_edit;
12624 }
12625}
12626
12627static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12628
12629/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12630static void
12631adjust_exidx_size(asection *exidx_sec, int adjust)
12632{
12633 asection *out_sec;
12634
12635 if (!exidx_sec->rawsize)
12636 exidx_sec->rawsize = exidx_sec->size;
12637
12638 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12639 out_sec = exidx_sec->output_section;
12640 /* Adjust size of output section. */
12641 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12642}
12643
12644/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12645static void
12646insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12647{
12648 struct _arm_elf_section_data *exidx_arm_data;
12649
12650 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12651 add_unwind_table_edit (
12652 &exidx_arm_data->u.exidx.unwind_edit_list,
12653 &exidx_arm_data->u.exidx.unwind_edit_tail,
12654 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12655
491d01d3
YU		 12656 exidx_arm_data->additional_reloc_count++;
12657
2468f9c9
PB		 12658 adjust_exidx_size(exidx_sec, 8);
12659}
12660
12661/* Scan .ARM.exidx tables, and create a list describing edits which should be
12662 made to those tables, such that:
b38cadfb 12663
2468f9c9
PB		 12664 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12665 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12666 codes which have been inlined into the index).
2468f9c9 12667
85fdf906
AH		 12668 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12669
2468f9c9 12670 The edits are applied when the tables are written
b38cadfb 12671 (in elf32_arm_write_section). */
2468f9c9
PB		 12672
12673bfd_boolean
12674elf32_arm_fix_exidx_coverage (asection **text_section_order,
12675 unsigned int num_text_sections,
85fdf906
AH		 12676 struct bfd_link_info *info,
12677 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12678{
12679 bfd *inp;
12680 unsigned int last_second_word = 0, i;
12681 asection *last_exidx_sec = NULL;
12682 asection *last_text_sec = NULL;
12683 int last_unwind_type = -1;
12684
12685 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12686 text sections. */
c72f2fb2 12687 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12688 {
12689 asection *sec;
b38cadfb 12690
2468f9c9 12691 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12692 {
2468f9c9
PB		 12693 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12694 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12695
dec9d5df 12696 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12697 continue;
b38cadfb 12698
2468f9c9
PB		 12699 if (elf_sec->linked_to)
12700 {
12701 Elf_Internal_Shdr *linked_hdr
99059e56 12702 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12703 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12704 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12705
12706 if (linked_sec_arm_data == NULL)
99059e56 12707 continue;
2468f9c9
PB		 12708
12709 /* Link this .ARM.exidx section back from the text section it
99059e56 12710 describes. */
2468f9c9
PB		 12711 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12712 }
12713 }
12714 }
12715
12716 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12717 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12718 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12719
12720 for (i = 0; i < num_text_sections; i++)
12721 {
12722 asection *sec = text_section_order[i];
12723 asection *exidx_sec;
12724 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12725 struct _arm_elf_section_data *exidx_arm_data;
12726 bfd_byte *contents = NULL;
12727 int deleted_exidx_bytes = 0;
12728 bfd_vma j;
12729 arm_unwind_table_edit *unwind_edit_head = NULL;
12730 arm_unwind_table_edit *unwind_edit_tail = NULL;
12731 Elf_Internal_Shdr *hdr;
12732 bfd *ibfd;
12733
12734 if (arm_data == NULL)
99059e56 12735 continue;
2468f9c9
PB		 12736
12737 exidx_sec = arm_data->u.text.arm_exidx_sec;
12738 if (exidx_sec == NULL)
12739 {
12740 /* Section has no unwind data. */
12741 if (last_unwind_type == 0 || !last_exidx_sec)
12742 continue;
12743
12744 /* Ignore zero sized sections. */
12745 if (sec->size == 0)
12746 continue;
12747
12748 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12749 last_unwind_type = 0;
12750 continue;
12751 }
12752
22a8f80e
PB		 12753 /* Skip /DISCARD/ sections. */
12754 if (bfd_is_abs_section (exidx_sec->output_section))
12755 continue;
12756
2468f9c9
PB		 12757 hdr = &elf_section_data (exidx_sec)->this_hdr;
12758 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12759 continue;
b38cadfb 12760
2468f9c9
PB		 12761 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12762 if (exidx_arm_data == NULL)
99059e56 12763 continue;
b38cadfb 12764
2468f9c9 12765 ibfd = exidx_sec->owner;
b38cadfb 12766
2468f9c9
PB		 12767 if (hdr->contents != NULL)
12768 contents = hdr->contents;
12769 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12770 /* An error? */
12771 continue;
12772
ac06903d
YU		 12773 if (last_unwind_type > 0)
12774 {
12775 unsigned int first_word = bfd_get_32 (ibfd, contents);
12776 /* Add cantunwind if first unwind item does not match section
12777 start. */
12778 if (first_word != sec->vma)
12779 {
12780 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12781 last_unwind_type = 0;
12782 }
12783 }
12784
2468f9c9
PB		 12785 for (j = 0; j < hdr->sh_size; j += 8)
12786 {
12787 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12788 int unwind_type;
12789 int elide = 0;
12790
12791 /* An EXIDX_CANTUNWIND entry. */
12792 if (second_word == 1)
12793 {
12794 if (last_unwind_type == 0)
12795 elide = 1;
12796 unwind_type = 0;
12797 }
12798 /* Inlined unwinding data. Merge if equal to previous. */
12799 else if ((second_word & 0x80000000) != 0)
12800 {
85fdf906
AH		 12801 if (merge_exidx_entries
12802 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12803 elide = 1;
12804 unwind_type = 1;
12805 last_second_word = second_word;
12806 }
12807 /* Normal table entry. In theory we could merge these too,
12808 but duplicate entries are likely to be much less common. */
12809 else
12810 unwind_type = 2;
12811
491d01d3 12812 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12813 {
12814 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12815 DELETE_EXIDX_ENTRY, NULL, j / 8);
12816
12817 deleted_exidx_bytes += 8;
12818 }
12819
12820 last_unwind_type = unwind_type;
12821 }
12822
12823 /* Free contents if we allocated it ourselves. */
12824 if (contents != hdr->contents)
99059e56 12825 free (contents);
2468f9c9
PB		 12826
12827 /* Record edits to be applied later (in elf32_arm_write_section). */
12828 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12829 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12830
2468f9c9
PB		 12831 if (deleted_exidx_bytes > 0)
12832 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12833
12834 last_exidx_sec = exidx_sec;
12835 last_text_sec = sec;
12836 }
12837
12838 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12839 if (!bfd_link_relocatable (info) && last_exidx_sec
12840 && last_unwind_type != 0)
2468f9c9
PB		 12841 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12842
12843 return TRUE;
12844}
12845
3e6b1042
DJ		 12846static bfd_boolean
12847elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12848 bfd *ibfd, const char *name)
12849{
12850 asection *sec, *osec;
12851
3d4d4302 12852 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12853 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12854 return TRUE;
12855
12856 osec = sec->output_section;
12857 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12858 return TRUE;
12859
12860 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12861 sec->output_offset, sec->size))
12862 return FALSE;
12863
12864 return TRUE;
12865}
12866
12867static bfd_boolean
12868elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12869{
12870 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12871 asection *sec, *osec;
3e6b1042 12872
4dfe6ac6
NC		 12873 if (globals == NULL)
12874 return FALSE;
12875
3e6b1042
DJ		 12876 /* Invoke the regular ELF backend linker to do all the work. */
12877 if (!bfd_elf_final_link (abfd, info))
12878 return FALSE;
12879
fe33d2fa
CL		 12880 /* Process stub sections (eg BE8 encoding, ...). */
12881 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12882 unsigned int i;
cdb21a0a
NS		 12883 for (i=0; i<htab->top_id; i++)
12884 {
12885 sec = htab->stub_group[i].stub_sec;
12886 /* Only process it once, in its link_sec slot. */
12887 if (sec && i == htab->stub_group[i].link_sec->id)
12888 {
12889 osec = sec->output_section;
12890 elf32_arm_write_section (abfd, info, sec, sec->contents);
12891 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12892 sec->output_offset, sec->size))
12893 return FALSE;
12894 }
fe33d2fa 12895 }
fe33d2fa 12896
3e6b1042
DJ		 12897 /* Write out any glue sections now that we have created all the
12898 stubs. */
12899 if (globals->bfd_of_glue_owner != NULL)
12900 {
12901 if (! elf32_arm_output_glue_section (info, abfd,
12902 globals->bfd_of_glue_owner,
12903 ARM2THUMB_GLUE_SECTION_NAME))
12904 return FALSE;
12905
12906 if (! elf32_arm_output_glue_section (info, abfd,
12907 globals->bfd_of_glue_owner,
12908 THUMB2ARM_GLUE_SECTION_NAME))
12909 return FALSE;
12910
12911 if (! elf32_arm_output_glue_section (info, abfd,
12912 globals->bfd_of_glue_owner,
12913 VFP11_ERRATUM_VENEER_SECTION_NAME))
12914 return FALSE;
12915
a504d23a
LA		 12916 if (! elf32_arm_output_glue_section (info, abfd,
12917 globals->bfd_of_glue_owner,
12918 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12919 return FALSE;
12920
3e6b1042
DJ		 12921 if (! elf32_arm_output_glue_section (info, abfd,
12922 globals->bfd_of_glue_owner,
12923 ARM_BX_GLUE_SECTION_NAME))
12924 return FALSE;
12925 }
12926
12927 return TRUE;
12928}
12929
5968a7b8
NC		 12930/* Return a best guess for the machine number based on the attributes. */
12931
12932static unsigned int
12933bfd_arm_get_mach_from_attributes (bfd * abfd)
12934{
12935 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12936
12937 switch (arch)
12938 {
12939 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12940 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12941 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12942
12943 case TAG_CPU_ARCH_V5TE:
12944 {
12945 char * name;
12946
12947 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12948 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12949
12950 if (name)
12951 {
12952 if (strcmp (name, "IWMMXT2") == 0)
12953 return bfd_mach_arm_iWMMXt2;
12954
12955 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12956 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12957
12958 if (strcmp (name, "XSCALE") == 0)
12959 {
12960 int wmmx;
12961
12962 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12963 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12964 switch (wmmx)
12965 {
12966 case 1: return bfd_mach_arm_iWMMXt;
12967 case 2: return bfd_mach_arm_iWMMXt2;
12968 default: return bfd_mach_arm_XScale;
12969 }
12970 }
5968a7b8
NC		 12971 }
12972
12973 return bfd_mach_arm_5TE;
12974 }
12975
12976 default:
12977 return bfd_mach_arm_unknown;
12978 }
12979}
12980
c178919b
NC		 12981/* Set the right machine number. */
12982
12983static bfd_boolean
57e8b36a 12984elf32_arm_object_p (bfd *abfd)
c178919b 12985{
5a6c6817 12986 unsigned int mach;
57e8b36a 12987
5a6c6817 12988 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12989
5968a7b8
NC		 12990 if (mach == bfd_mach_arm_unknown)
12991 {
12992 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12993 mach = bfd_mach_arm_ep9312;
12994 else
12995 mach = bfd_arm_get_mach_from_attributes (abfd);
12996 }
c178919b 12997
5968a7b8 12998 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12999 return TRUE;
13000}
13001
fc830a83 13002/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13003
b34976b6 13004static bfd_boolean
57e8b36a 13005elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13006{
13007 if (elf_flags_init (abfd)
13008 && elf_elfheader (abfd)->e_flags != flags)
13009 {
fc830a83
NC		 13010 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13011 {
fd2ec330 13012 if (flags & EF_ARM_INTERWORK)
4eca0228 13013 _bfd_error_handler
d003868e
AM		 13014 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13015 abfd);
fc830a83 13016 else
d003868e
AM		 13017 _bfd_error_handler
13018 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13019 abfd);
fc830a83 13020 }
252b5132
RH		 13021 }
13022 else
13023 {
13024 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13025 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13026 }
13027
b34976b6 13028 return TRUE;
252b5132
RH		 13029}
13030
fc830a83 13031/* Copy backend specific data from one object module to another. */
9b485d32 13032
b34976b6 13033static bfd_boolean
57e8b36a 13034elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13035{
13036 flagword in_flags;
13037 flagword out_flags;
13038
0ffa91dd 13039 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13040 return TRUE;
252b5132 13041
fc830a83 13042 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13043 out_flags = elf_elfheader (obfd)->e_flags;
13044
fc830a83
NC		 13045 if (elf_flags_init (obfd)
13046 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13047 && in_flags != out_flags)
252b5132 13048 {
252b5132 13049 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13050 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13051 return FALSE;
252b5132
RH		 13052
13053 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13054 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13055 return FALSE;
252b5132
RH		 13056
13057 /* If the src and dest have different interworking flags
99059e56 13058 then turn off the interworking bit. */
fd2ec330 13059 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13060 {
fd2ec330 13061 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13062 _bfd_error_handler
13063 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13064 obfd, ibfd);
252b5132 13065
fd2ec330 13066 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13067 }
1006ba19
PB		 13068
13069 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13070 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13071 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13072 }
13073
13074 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13075 elf_flags_init (obfd) = TRUE;
252b5132 13076
e2349352 13077 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13078}
13079
13080/* Values for Tag_ABI_PCS_R9_use. */
13081enum
13082{
13083 AEABI_R9_V6,
13084 AEABI_R9_SB,
13085 AEABI_R9_TLS,
13086 AEABI_R9_unused
13087};
13088
13089/* Values for Tag_ABI_PCS_RW_data. */
13090enum
13091{
13092 AEABI_PCS_RW_data_absolute,
13093 AEABI_PCS_RW_data_PCrel,
13094 AEABI_PCS_RW_data_SBrel,
13095 AEABI_PCS_RW_data_unused
13096};
13097
13098/* Values for Tag_ABI_enum_size. */
13099enum
13100{
13101 AEABI_enum_unused,
13102 AEABI_enum_short,
13103 AEABI_enum_wide,
13104 AEABI_enum_forced_wide
13105};
13106
104d59d1
JM		 13107/* Determine whether an object attribute tag takes an integer, a
13108 string or both. */
906e58ca 13109
104d59d1
JM		 13110static int
13111elf32_arm_obj_attrs_arg_type (int tag)
13112{
13113 if (tag == Tag_compatibility)
3483fe2e 13114 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13115 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13116 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13117 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13118 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13119 else if (tag < 32)
3483fe2e 13120 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13121 else
3483fe2e 13122 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13123}
13124
5aa6ff7c
AS		 13125/* The ABI defines that Tag_conformance should be emitted first, and that
13126 Tag_nodefaults should be second (if either is defined). This sets those
13127 two positions, and bumps up the position of all the remaining tags to
13128 compensate. */
13129static int
13130elf32_arm_obj_attrs_order (int num)
13131{
3de4a297 13132 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13133 return Tag_conformance;
3de4a297 13134 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13135 return Tag_nodefaults;
13136 if ((num - 2) < Tag_nodefaults)
13137 return num - 2;
13138 if ((num - 1) < Tag_conformance)
13139 return num - 1;
13140 return num;
13141}
13142
e8b36cd1
JM		 13143/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13144static bfd_boolean
13145elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13146{
13147 if ((tag & 127) < 64)
13148 {
13149 _bfd_error_handler
13150 (_("%B: Unknown mandatory EABI object attribute %d"),
13151 abfd, tag);
13152 bfd_set_error (bfd_error_bad_value);
13153 return FALSE;
13154 }
13155 else
13156 {
13157 _bfd_error_handler
13158 (_("Warning: %B: Unknown EABI object attribute %d"),
13159 abfd, tag);
13160 return TRUE;
13161 }
13162}
13163
91e22acd
AS		 13164/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13165 Returns -1 if no architecture could be read. */
13166
13167static int
13168get_secondary_compatible_arch (bfd *abfd)
13169{
13170 obj_attribute *attr =
13171 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13172
13173 /* Note: the tag and its argument below are uleb128 values, though
13174 currently-defined values fit in one byte for each. */
13175 if (attr->s
13176 && attr->s[0] == Tag_CPU_arch
13177 && (attr->s[1] & 128) != 128
13178 && attr->s[2] == 0)
13179 return attr->s[1];
13180
13181 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13182 return -1;
13183}
13184
13185/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13186 The tag is removed if ARCH is -1. */
13187
8e79c3df 13188static void
91e22acd 13189set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13190{
91e22acd
AS		 13191 obj_attribute *attr =
13192 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13193
91e22acd
AS		 13194 if (arch == -1)
13195 {
13196 attr->s = NULL;
13197 return;
8e79c3df 13198 }
91e22acd
AS		 13199
13200 /* Note: the tag and its argument below are uleb128 values, though
13201 currently-defined values fit in one byte for each. */
13202 if (!attr->s)
21d799b5 13203 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13204 attr->s[0] = Tag_CPU_arch;
13205 attr->s[1] = arch;
13206 attr->s[2] = '\0';
8e79c3df
CM		 13207}
13208
91e22acd
AS		 13209/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13210 into account. */
13211
13212static int
13213tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13214 int newtag, int secondary_compat)
8e79c3df 13215{
91e22acd
AS		 13216#define T(X) TAG_CPU_ARCH_##X
13217 int tagl, tagh, result;
13218 const int v6t2[] =
13219 {
13220 T(V6T2), /* PRE_V4. */
13221 T(V6T2), /* V4. */
13222 T(V6T2), /* V4T. */
13223 T(V6T2), /* V5T. */
13224 T(V6T2), /* V5TE. */
13225 T(V6T2), /* V5TEJ. */
13226 T(V6T2), /* V6. */
13227 T(V7), /* V6KZ. */
13228 T(V6T2) /* V6T2. */
13229 };
13230 const int v6k[] =
13231 {
13232 T(V6K), /* PRE_V4. */
13233 T(V6K), /* V4. */
13234 T(V6K), /* V4T. */
13235 T(V6K), /* V5T. */
13236 T(V6K), /* V5TE. */
13237 T(V6K), /* V5TEJ. */
13238 T(V6K), /* V6. */
13239 T(V6KZ), /* V6KZ. */
13240 T(V7), /* V6T2. */
13241 T(V6K) /* V6K. */
13242 };
13243 const int v7[] =
13244 {
13245 T(V7), /* PRE_V4. */
13246 T(V7), /* V4. */
13247 T(V7), /* V4T. */
13248 T(V7), /* V5T. */
13249 T(V7), /* V5TE. */
13250 T(V7), /* V5TEJ. */
13251 T(V7), /* V6. */
13252 T(V7), /* V6KZ. */
13253 T(V7), /* V6T2. */
13254 T(V7), /* V6K. */
13255 T(V7) /* V7. */
13256 };
13257 const int v6_m[] =
13258 {
13259 -1, /* PRE_V4. */
13260 -1, /* V4. */
13261 T(V6K), /* V4T. */
13262 T(V6K), /* V5T. */
13263 T(V6K), /* V5TE. */
13264 T(V6K), /* V5TEJ. */
13265 T(V6K), /* V6. */
13266 T(V6KZ), /* V6KZ. */
13267 T(V7), /* V6T2. */
13268 T(V6K), /* V6K. */
13269 T(V7), /* V7. */
13270 T(V6_M) /* V6_M. */
13271 };
13272 const int v6s_m[] =
13273 {
13274 -1, /* PRE_V4. */
13275 -1, /* V4. */
13276 T(V6K), /* V4T. */
13277 T(V6K), /* V5T. */
13278 T(V6K), /* V5TE. */
13279 T(V6K), /* V5TEJ. */
13280 T(V6K), /* V6. */
13281 T(V6KZ), /* V6KZ. */
13282 T(V7), /* V6T2. */
13283 T(V6K), /* V6K. */
13284 T(V7), /* V7. */
13285 T(V6S_M), /* V6_M. */
13286 T(V6S_M) /* V6S_M. */
13287 };
9e3c6df6
PB		 13288 const int v7e_m[] =
13289 {
13290 -1, /* PRE_V4. */
13291 -1, /* V4. */
13292 T(V7E_M), /* V4T. */
13293 T(V7E_M), /* V5T. */
13294 T(V7E_M), /* V5TE. */
13295 T(V7E_M), /* V5TEJ. */
13296 T(V7E_M), /* V6. */
13297 T(V7E_M), /* V6KZ. */
13298 T(V7E_M), /* V6T2. */
13299 T(V7E_M), /* V6K. */
13300 T(V7E_M), /* V7. */
13301 T(V7E_M), /* V6_M. */
13302 T(V7E_M), /* V6S_M. */
13303 T(V7E_M) /* V7E_M. */
13304 };
bca38921
MGD		 13305 const int v8[] =
13306 {
13307 T(V8), /* PRE_V4. */
13308 T(V8), /* V4. */
13309 T(V8), /* V4T. */
13310 T(V8), /* V5T. */
13311 T(V8), /* V5TE. */
13312 T(V8), /* V5TEJ. */
13313 T(V8), /* V6. */
13314 T(V8), /* V6KZ. */
13315 T(V8), /* V6T2. */
13316 T(V8), /* V6K. */
13317 T(V8), /* V7. */
13318 T(V8), /* V6_M. */
13319 T(V8), /* V6S_M. */
13320 T(V8), /* V7E_M. */
13321 T(V8) /* V8. */
13322 };
2fd158eb
TP		 13323 const int v8m_baseline[] =
13324 {
13325 -1, /* PRE_V4. */
13326 -1, /* V4. */
13327 -1, /* V4T. */
13328 -1, /* V5T. */
13329 -1, /* V5TE. */
13330 -1, /* V5TEJ. */
13331 -1, /* V6. */
13332 -1, /* V6KZ. */
13333 -1, /* V6T2. */
13334 -1, /* V6K. */
13335 -1, /* V7. */
13336 T(V8M_BASE), /* V6_M. */
13337 T(V8M_BASE), /* V6S_M. */
13338 -1, /* V7E_M. */
13339 -1, /* V8. */
13340 -1,
13341 T(V8M_BASE) /* V8-M BASELINE. */
13342 };
13343 const int v8m_mainline[] =
13344 {
13345 -1, /* PRE_V4. */
13346 -1, /* V4. */
13347 -1, /* V4T. */
13348 -1, /* V5T. */
13349 -1, /* V5TE. */
13350 -1, /* V5TEJ. */
13351 -1, /* V6. */
13352 -1, /* V6KZ. */
13353 -1, /* V6T2. */
13354 -1, /* V6K. */
13355 T(V8M_MAIN), /* V7. */
13356 T(V8M_MAIN), /* V6_M. */
13357 T(V8M_MAIN), /* V6S_M. */
13358 T(V8M_MAIN), /* V7E_M. */
13359 -1, /* V8. */
13360 -1,
13361 T(V8M_MAIN), /* V8-M BASELINE. */
13362 T(V8M_MAIN) /* V8-M MAINLINE. */
13363 };
91e22acd
AS		 13364 const int v4t_plus_v6_m[] =
13365 {
13366 -1, /* PRE_V4. */
13367 -1, /* V4. */
13368 T(V4T), /* V4T. */
13369 T(V5T), /* V5T. */
13370 T(V5TE), /* V5TE. */
13371 T(V5TEJ), /* V5TEJ. */
13372 T(V6), /* V6. */
13373 T(V6KZ), /* V6KZ. */
13374 T(V6T2), /* V6T2. */
13375 T(V6K), /* V6K. */
13376 T(V7), /* V7. */
13377 T(V6_M), /* V6_M. */
13378 T(V6S_M), /* V6S_M. */
9e3c6df6 13379 T(V7E_M), /* V7E_M. */
bca38921 13380 T(V8), /* V8. */
4ed7ed8d 13381 -1, /* Unused. */
2fd158eb
TP		 13382 T(V8M_BASE), /* V8-M BASELINE. */
13383 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13384 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13385 };
13386 const int *comb[] =
13387 {
13388 v6t2,
13389 v6k,
13390 v7,
13391 v6_m,
13392 v6s_m,
9e3c6df6 13393 v7e_m,
bca38921 13394 v8,
4ed7ed8d 13395 NULL,
2fd158eb
TP		 13396 v8m_baseline,
13397 v8m_mainline,
91e22acd
AS		 13398 /* Pseudo-architecture. */
13399 v4t_plus_v6_m
13400 };
13401
13402 /* Check we've not got a higher architecture than we know about. */
13403
9e3c6df6 13404 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13405 {
3895f852 13406 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13407 return -1;
13408 }
13409
13410 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13411
13412 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13413 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13414 oldtag = T(V4T_PLUS_V6_M);
13415
13416 /* And override the new tag if we have a Tag_also_compatible_with on the
13417 input. */
13418
13419 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13420 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13421 newtag = T(V4T_PLUS_V6_M);
13422
13423 tagl = (oldtag < newtag) ? oldtag : newtag;
13424 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13425
13426 /* Architectures before V6KZ add features monotonically. */
13427 if (tagh <= TAG_CPU_ARCH_V6KZ)
13428 return result;
13429
4ed7ed8d 13430 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13431
13432 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13433 as the canonical version. */
13434 if (result == T(V4T_PLUS_V6_M))
13435 {
13436 result = T(V4T);
13437 *secondary_compat_out = T(V6_M);
13438 }
13439 else
13440 *secondary_compat_out = -1;
13441
13442 if (result == -1)
13443 {
3895f852 13444 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13445 ibfd, oldtag, newtag);
13446 return -1;
13447 }
13448
13449 return result;
13450#undef T
8e79c3df
CM		 13451}
13452
ac56ee8f
MGD		 13453/* Query attributes object to see if integer divide instructions may be
13454 present in an object. */
13455static bfd_boolean
13456elf32_arm_attributes_accept_div (const obj_attribute *attr)
13457{
13458 int arch = attr[Tag_CPU_arch].i;
13459 int profile = attr[Tag_CPU_arch_profile].i;
13460
13461 switch (attr[Tag_DIV_use].i)
13462 {
13463 case 0:
13464 /* Integer divide allowed if instruction contained in archetecture. */
13465 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13466 return TRUE;
13467 else if (arch >= TAG_CPU_ARCH_V7E_M)
13468 return TRUE;
13469 else
13470 return FALSE;
13471
13472 case 1:
13473 /* Integer divide explicitly prohibited. */
13474 return FALSE;
13475
13476 default:
13477 /* Unrecognised case - treat as allowing divide everywhere. */
13478 case 2:
13479 /* Integer divide allowed in ARM state. */
13480 return TRUE;
13481 }
13482}
13483
13484/* Query attributes object to see if integer divide instructions are
13485 forbidden to be in the object. This is not the inverse of
13486 elf32_arm_attributes_accept_div. */
13487static bfd_boolean
13488elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13489{
13490 return attr[Tag_DIV_use].i == 1;
13491}
13492
ee065d83
PB		 13493/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13494 are conflicting attributes. */
906e58ca 13495
ee065d83 13496static bfd_boolean
50e03d47 13497elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13498{
50e03d47 13499 bfd *obfd = info->output_bfd;
104d59d1
JM		 13500 obj_attribute *in_attr;
13501 obj_attribute *out_attr;
ee065d83
PB		 13502 /* Some tags have 0 = don't care, 1 = strong requirement,
13503 2 = weak requirement. */
91e22acd 13504 static const int order_021[3] = {0, 2, 1};
ee065d83 13505 int i;
91e22acd 13506 bfd_boolean result = TRUE;
9274e9de 13507 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13508
3e6b1042
DJ		 13509 /* Skip the linker stubs file. This preserves previous behavior
13510 of accepting unknown attributes in the first input file - but
13511 is that a bug? */
13512 if (ibfd->flags & BFD_LINKER_CREATED)
13513 return TRUE;
13514
9274e9de
TG		 13515 /* Skip any input that hasn't attribute section.
13516 This enables to link object files without attribute section with
13517 any others. */
13518 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13519 return TRUE;
13520
104d59d1 13521 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13522 {
13523 /* This is the first object. Copy the attributes. */
104d59d1 13524 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13525
cd21e546
MGD		 13526 out_attr = elf_known_obj_attributes_proc (obfd);
13527
004ae526
PB		 13528 /* Use the Tag_null value to indicate the attributes have been
13529 initialized. */
cd21e546 13530 out_attr[0].i = 1;
004ae526 13531
cd21e546
MGD		 13532 /* We do not output objects with Tag_MPextension_use_legacy - we move
13533 the attribute's value to Tag_MPextension_use. */
13534 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13535 {
13536 if (out_attr[Tag_MPextension_use].i != 0
13537 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13538 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13539 {
13540 _bfd_error_handler
13541 (_("Error: %B has both the current and legacy "
13542 "Tag_MPextension_use attributes"), ibfd);
13543 result = FALSE;
13544 }
13545
13546 out_attr[Tag_MPextension_use] =
13547 out_attr[Tag_MPextension_use_legacy];
13548 out_attr[Tag_MPextension_use_legacy].type = 0;
13549 out_attr[Tag_MPextension_use_legacy].i = 0;
13550 }
13551
13552 return result;
ee065d83
PB		 13553 }
13554
104d59d1
JM		 13555 in_attr = elf_known_obj_attributes_proc (ibfd);
13556 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13557 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13558 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13559 {
5c294fee
TG		 13560 /* Ignore mismatches if the object doesn't use floating point or is
13561 floating point ABI independent. */
13562 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13563 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13564 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13565 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13566 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13567 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13568 {
13569 _bfd_error_handler
3895f852 13570 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13571 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13572 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13573 result = FALSE;
ee065d83
PB		 13574 }
13575 }
13576
3de4a297 13577 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13578 {
13579 /* Merge this attribute with existing attributes. */
13580 switch (i)
13581 {
13582 case Tag_CPU_raw_name:
13583 case Tag_CPU_name:
6a631e86 13584 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13585 break;
13586
13587 case Tag_ABI_optimization_goals:
13588 case Tag_ABI_FP_optimization_goals:
13589 /* Use the first value seen. */
13590 break;
13591
13592 case Tag_CPU_arch:
91e22acd
AS		 13593 {
13594 int secondary_compat = -1, secondary_compat_out = -1;
13595 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13596 int arch_attr;
13597 static const char *name_table[] =
13598 {
91e22acd
AS		 13599 /* These aren't real CPU names, but we can't guess
13600 that from the architecture version alone. */
13601 "Pre v4",
13602 "ARM v4",
13603 "ARM v4T",
13604 "ARM v5T",
13605 "ARM v5TE",
13606 "ARM v5TEJ",
13607 "ARM v6",
13608 "ARM v6KZ",
13609 "ARM v6T2",
13610 "ARM v6K",
13611 "ARM v7",
13612 "ARM v6-M",
bca38921 13613 "ARM v6S-M",
2fd158eb
TP		 13614 "ARM v8",
13615 "",
13616 "ARM v8-M.baseline",
13617 "ARM v8-M.mainline",
91e22acd
AS		 13618 };
13619
13620 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13621 secondary_compat = get_secondary_compatible_arch (ibfd);
13622 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13623 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13624 &secondary_compat_out,
13625 in_attr[i].i,
13626 secondary_compat);
13627
13628 /* Return with error if failed to merge. */
13629 if (arch_attr == -1)
13630 return FALSE;
13631
13632 out_attr[i].i = arch_attr;
13633
91e22acd
AS		 13634 set_secondary_compatible_arch (obfd, secondary_compat_out);
13635
13636 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13637 if (out_attr[i].i == saved_out_attr)
13638 ; /* Leave the names alone. */
13639 else if (out_attr[i].i == in_attr[i].i)
13640 {
13641 /* The output architecture has been changed to match the
13642 input architecture. Use the input names. */
13643 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13644 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13645 : NULL;
13646 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13647 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13648 : NULL;
13649 }
13650 else
13651 {
13652 out_attr[Tag_CPU_name].s = NULL;
13653 out_attr[Tag_CPU_raw_name].s = NULL;
13654 }
13655
13656 /* If we still don't have a value for Tag_CPU_name,
13657 make one up now. Tag_CPU_raw_name remains blank. */
13658 if (out_attr[Tag_CPU_name].s == NULL
13659 && out_attr[i].i < ARRAY_SIZE (name_table))
13660 out_attr[Tag_CPU_name].s =
13661 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13662 }
13663 break;
13664
ee065d83
PB		 13665 case Tag_ARM_ISA_use:
13666 case Tag_THUMB_ISA_use:
ee065d83 13667 case Tag_WMMX_arch:
91e22acd
AS		 13668 case Tag_Advanced_SIMD_arch:
13669 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13670 case Tag_ABI_FP_rounding:
ee065d83
PB		 13671 case Tag_ABI_FP_exceptions:
13672 case Tag_ABI_FP_user_exceptions:
13673 case Tag_ABI_FP_number_model:
75375b3e 13674 case Tag_FP_HP_extension:
91e22acd
AS		 13675 case Tag_CPU_unaligned_access:
13676 case Tag_T2EE_use:
91e22acd 13677 case Tag_MPextension_use:
ee065d83
PB		 13678 /* Use the largest value specified. */
13679 if (in_attr[i].i > out_attr[i].i)
13680 out_attr[i].i = in_attr[i].i;
13681 break;
13682
75375b3e 13683 case Tag_ABI_align_preserved:
91e22acd
AS		 13684 case Tag_ABI_PCS_RO_data:
13685 /* Use the smallest value specified. */
13686 if (in_attr[i].i < out_attr[i].i)
13687 out_attr[i].i = in_attr[i].i;
13688 break;
13689
75375b3e 13690 case Tag_ABI_align_needed:
91e22acd 13691 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13692 && (in_attr[Tag_ABI_align_preserved].i == 0
13693 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13694 {
91e22acd
AS		 13695 /* This error message should be enabled once all non-conformant
13696 binaries in the toolchain have had the attributes set
13697 properly.
ee065d83 13698 _bfd_error_handler
3895f852 13699 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13700 obfd, ibfd);
13701 result = FALSE; */
ee065d83 13702 }
91e22acd
AS		 13703 /* Fall through. */
13704 case Tag_ABI_FP_denormal:
13705 case Tag_ABI_PCS_GOT_use:
13706 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13707 value if greater than 2 (for future-proofing). */
13708 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13709 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13710 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13711 out_attr[i].i = in_attr[i].i;
13712 break;
91e22acd 13713
75375b3e
MGD		 13714 case Tag_Virtualization_use:
13715 /* The virtualization tag effectively stores two bits of
13716 information: the intended use of TrustZone (in bit 0), and the
13717 intended use of Virtualization (in bit 1). */
13718 if (out_attr[i].i == 0)
13719 out_attr[i].i = in_attr[i].i;
13720 else if (in_attr[i].i != 0
13721 && in_attr[i].i != out_attr[i].i)
13722 {
13723 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13724 out_attr[i].i = 3;
13725 else
13726 {
13727 _bfd_error_handler
13728 (_("error: %B: unable to merge virtualization attributes "
13729 "with %B"),
13730 obfd, ibfd);
13731 result = FALSE;
13732 }
13733 }
13734 break;
91e22acd
AS		 13735
13736 case Tag_CPU_arch_profile:
13737 if (out_attr[i].i != in_attr[i].i)
13738 {
13739 /* 0 will merge with anything.
13740 'A' and 'S' merge to 'A'.
13741 'R' and 'S' merge to 'R'.
99059e56 13742 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13743 if (out_attr[i].i == 0
13744 || (out_attr[i].i == 'S'
13745 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13746 out_attr[i].i = in_attr[i].i;
13747 else if (in_attr[i].i == 0
13748 || (in_attr[i].i == 'S'
13749 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13750 ; /* Do nothing. */
91e22acd
AS		 13751 else
13752 {
13753 _bfd_error_handler
3895f852 13754 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13755 ibfd,
13756 in_attr[i].i ? in_attr[i].i : '0',
13757 out_attr[i].i ? out_attr[i].i : '0');
13758 result = FALSE;
13759 }
13760 }
13761 break;
15afaa63
TP		 13762
13763 case Tag_DSP_extension:
13764 /* No need to change output value if any of:
13765 - pre (<=) ARMv5T input architecture (do not have DSP)
13766 - M input profile not ARMv7E-M and do not have DSP. */
13767 if (in_attr[Tag_CPU_arch].i <= 3
13768 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13769 && in_attr[Tag_CPU_arch].i != 13
13770 && in_attr[i].i == 0))
13771 ; /* Do nothing. */
13772 /* Output value should be 0 if DSP part of architecture, ie.
13773 - post (>=) ARMv5te architecture output
13774 - A, R or S profile output or ARMv7E-M output architecture. */
13775 else if (out_attr[Tag_CPU_arch].i >= 4
13776 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13777 || out_attr[Tag_CPU_arch_profile].i == 'R'
13778 || out_attr[Tag_CPU_arch_profile].i == 'S'
13779 || out_attr[Tag_CPU_arch].i == 13))
13780 out_attr[i].i = 0;
13781 /* Otherwise, DSP instructions are added and not part of output
13782 architecture. */
13783 else
13784 out_attr[i].i = 1;
13785 break;
13786
75375b3e 13787 case Tag_FP_arch:
62f3b8c8 13788 {
4547cb56
NC		 13789 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13790 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13791 when it's 0. It might mean absence of FP hardware if
99654aaf 13792 Tag_FP_arch is zero. */
4547cb56 13793
a715796b 13794#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13795 static const struct
13796 {
13797 int ver;
13798 int regs;
bca38921 13799 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13800 {
13801 {0, 0},
13802 {1, 16},
13803 {2, 16},
13804 {3, 32},
13805 {3, 16},
13806 {4, 32},
bca38921 13807 {4, 16},
a715796b
TG		 13808 {8, 32},
13809 {8, 16}
62f3b8c8
PB		 13810 };
13811 int ver;
13812 int regs;
13813 int newval;
13814
4547cb56
NC		 13815 /* If the output has no requirement about FP hardware,
13816 follow the requirement of the input. */
13817 if (out_attr[i].i == 0)
13818 {
13819 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13820 out_attr[i].i = in_attr[i].i;
13821 out_attr[Tag_ABI_HardFP_use].i
13822 = in_attr[Tag_ABI_HardFP_use].i;
13823 break;
13824 }
13825 /* If the input has no requirement about FP hardware, do
13826 nothing. */
13827 else if (in_attr[i].i == 0)
13828 {
13829 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13830 break;
13831 }
13832
13833 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13834 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13835
13836 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13837 do nothing. */
13838 if (in_attr[Tag_ABI_HardFP_use].i == 0
13839 && out_attr[Tag_ABI_HardFP_use].i == 0)
13840 ;
13841 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13842 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13843 else if (in_attr[Tag_ABI_HardFP_use].i
13844 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13845 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13846
13847 /* Now we can handle Tag_FP_arch. */
13848
bca38921
MGD		 13849 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13850 pick the biggest. */
13851 if (in_attr[i].i >= VFP_VERSION_COUNT
13852 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13853 {
13854 out_attr[i] = in_attr[i];
13855 break;
13856 }
13857 /* The output uses the superset of input features
13858 (ISA version) and registers. */
13859 ver = vfp_versions[in_attr[i].i].ver;
13860 if (ver < vfp_versions[out_attr[i].i].ver)
13861 ver = vfp_versions[out_attr[i].i].ver;
13862 regs = vfp_versions[in_attr[i].i].regs;
13863 if (regs < vfp_versions[out_attr[i].i].regs)
13864 regs = vfp_versions[out_attr[i].i].regs;
13865 /* This assumes all possible supersets are also a valid
99059e56 13866 options. */
bca38921 13867 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13868 {
13869 if (regs == vfp_versions[newval].regs
13870 && ver == vfp_versions[newval].ver)
13871 break;
13872 }
13873 out_attr[i].i = newval;
13874 }
b1cc4aeb 13875 break;
ee065d83
PB		 13876 case Tag_PCS_config:
13877 if (out_attr[i].i == 0)
13878 out_attr[i].i = in_attr[i].i;
b6009aca 13879 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13880 {
13881 /* It's sometimes ok to mix different configs, so this is only
99059e56 13882 a warning. */
ee065d83
PB		 13883 _bfd_error_handler
13884 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13885 }
13886 break;
13887 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13888 if (in_attr[i].i != out_attr[i].i
13889 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13890 && in_attr[i].i != AEABI_R9_unused)
13891 {
13892 _bfd_error_handler
3895f852 13893 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13894 result = FALSE;
ee065d83
PB		 13895 }
13896 if (out_attr[i].i == AEABI_R9_unused)
13897 out_attr[i].i = in_attr[i].i;
13898 break;
13899 case Tag_ABI_PCS_RW_data:
13900 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13901 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13902 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13903 {
13904 _bfd_error_handler
3895f852 13905 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13906 ibfd);
91e22acd 13907 result = FALSE;
ee065d83
PB		 13908 }
13909 /* Use the smallest value specified. */
13910 if (in_attr[i].i < out_attr[i].i)
13911 out_attr[i].i = in_attr[i].i;
13912 break;
ee065d83 13913 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13914 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13915 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13916 {
13917 _bfd_error_handler
a9dc9481
JM		 13918 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13919 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13920 }
a9dc9481 13921 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13922 out_attr[i].i = in_attr[i].i;
13923 break;
ee065d83
PB		 13924 case Tag_ABI_enum_size:
13925 if (in_attr[i].i != AEABI_enum_unused)
13926 {
13927 if (out_attr[i].i == AEABI_enum_unused
13928 || out_attr[i].i == AEABI_enum_forced_wide)
13929 {
13930 /* The existing object is compatible with anything.
13931 Use whatever requirements the new object has. */
13932 out_attr[i].i = in_attr[i].i;
13933 }
13934 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13935 && out_attr[i].i != in_attr[i].i
0ffa91dd 13936 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13937 {
91e22acd 13938 static const char *aeabi_enum_names[] =
bf21ed78 13939 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13940 const char *in_name =
13941 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13942 ? aeabi_enum_names[in_attr[i].i]
13943 : "<unknown>";
13944 const char *out_name =
13945 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13946 ? aeabi_enum_names[out_attr[i].i]
13947 : "<unknown>";
ee065d83 13948 _bfd_error_handler
bf21ed78 13949 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13950 ibfd, in_name, out_name);
ee065d83
PB		 13951 }
13952 }
13953 break;
13954 case Tag_ABI_VFP_args:
13955 /* Aready done. */
13956 break;
13957 case Tag_ABI_WMMX_args:
13958 if (in_attr[i].i != out_attr[i].i)
13959 {
13960 _bfd_error_handler
3895f852 13961 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13962 ibfd, obfd);
91e22acd 13963 result = FALSE;
ee065d83
PB		 13964 }
13965 break;
7b86a9fa
AS		 13966 case Tag_compatibility:
13967 /* Merged in target-independent code. */
13968 break;
91e22acd 13969 case Tag_ABI_HardFP_use:
4547cb56 13970 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13971 break;
13972 case Tag_ABI_FP_16bit_format:
13973 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13974 {
13975 if (in_attr[i].i != out_attr[i].i)
13976 {
13977 _bfd_error_handler
3895f852 13978 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13979 ibfd, obfd);
13980 result = FALSE;
13981 }
13982 }
13983 if (in_attr[i].i != 0)
13984 out_attr[i].i = in_attr[i].i;
13985 break;
7b86a9fa 13986
cd21e546 13987 case Tag_DIV_use:
ac56ee8f
MGD		 13988 /* A value of zero on input means that the divide instruction may
13989 be used if available in the base architecture as specified via
13990 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13991 the user did not want divide instructions. A value of 2
13992 explicitly means that divide instructions were allowed in ARM
13993 and Thumb state. */
13994 if (in_attr[i].i == out_attr[i].i)
13995 /* Do nothing. */ ;
13996 else if (elf32_arm_attributes_forbid_div (in_attr)
13997 && !elf32_arm_attributes_accept_div (out_attr))
13998 out_attr[i].i = 1;
13999 else if (elf32_arm_attributes_forbid_div (out_attr)
14000 && elf32_arm_attributes_accept_div (in_attr))
14001 out_attr[i].i = in_attr[i].i;
14002 else if (in_attr[i].i == 2)
14003 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14004 break;
14005
14006 case Tag_MPextension_use_legacy:
14007 /* We don't output objects with Tag_MPextension_use_legacy - we
14008 move the value to Tag_MPextension_use. */
14009 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14010 {
14011 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14012 {
14013 _bfd_error_handler
14014 (_("%B has has both the current and legacy "
b38cadfb 14015 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14016 ibfd);
14017 result = FALSE;
14018 }
14019 }
14020
14021 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14022 out_attr[Tag_MPextension_use] = in_attr[i];
14023
14024 break;
14025
91e22acd 14026 case Tag_nodefaults:
2d0bb761
AS		 14027 /* This tag is set if it exists, but the value is unused (and is
14028 typically zero). We don't actually need to do anything here -
14029 the merge happens automatically when the type flags are merged
14030 below. */
91e22acd
AS		 14031 break;
14032 case Tag_also_compatible_with:
14033 /* Already done in Tag_CPU_arch. */
14034 break;
14035 case Tag_conformance:
14036 /* Keep the attribute if it matches. Throw it away otherwise.
14037 No attribute means no claim to conform. */
14038 if (!in_attr[i].s || !out_attr[i].s
14039 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14040 out_attr[i].s = NULL;
14041 break;
3cfad14c 14042
91e22acd 14043 default:
e8b36cd1
JM		 14044 result
14045 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14046 }
14047
14048 /* If out_attr was copied from in_attr then it won't have a type yet. */
14049 if (in_attr[i].type && !out_attr[i].type)
14050 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14051 }
14052
104d59d1 14053 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14054 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14055 return FALSE;
ee065d83 14056
104d59d1 14057 /* Check for any attributes not known on ARM. */
e8b36cd1 14058 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14059
91e22acd 14060 return result;
252b5132
RH		 14061}
14062
3a4a14e9
PB		 14063
14064/* Return TRUE if the two EABI versions are incompatible. */
14065
14066static bfd_boolean
14067elf32_arm_versions_compatible (unsigned iver, unsigned over)
14068{
14069 /* v4 and v5 are the same spec before and after it was released,
14070 so allow mixing them. */
14071 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14072 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14073 return TRUE;
14074
14075 return (iver == over);
14076}
14077
252b5132
RH		 14078/* Merge backend specific data from an object file to the output
14079 object file when linking. */
9b485d32 14080
b34976b6 14081static bfd_boolean
50e03d47 14082elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14083
9b485d32
NC		 14084/* Display the flags field. */
14085
b34976b6 14086static bfd_boolean
57e8b36a 14087elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14088{
fc830a83
NC		 14089 FILE * file = (FILE *) ptr;
14090 unsigned long flags;
252b5132
RH		 14091
14092 BFD_ASSERT (abfd != NULL && ptr != NULL);
14093
14094 /* Print normal ELF private data. */
14095 _bfd_elf_print_private_bfd_data (abfd, ptr);
14096
fc830a83 14097 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14098 /* Ignore init flag - it may not be set, despite the flags field
14099 containing valid data. */
252b5132 14100
9b485d32 14101 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14102
fc830a83
NC		 14103 switch (EF_ARM_EABI_VERSION (flags))
14104 {
14105 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14106 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14107 official ARM ELF extended ABI. Hence they are only decoded if
14108 the EABI version is not set. */
fd2ec330 14109 if (flags & EF_ARM_INTERWORK)
9b485d32 14110 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14111
fd2ec330 14112 if (flags & EF_ARM_APCS_26)
6c571f00 14113 fprintf (file, " [APCS-26]");
fc830a83 14114 else
6c571f00 14115 fprintf (file, " [APCS-32]");
9a5aca8c 14116
96a846ea
RE		 14117 if (flags & EF_ARM_VFP_FLOAT)
14118 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14119 else if (flags & EF_ARM_MAVERICK_FLOAT)
14120 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14121 else
14122 fprintf (file, _(" [FPA float format]"));
14123
fd2ec330 14124 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14125 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14126
fd2ec330 14127 if (flags & EF_ARM_PIC)
9b485d32 14128 fprintf (file, _(" [position independent]"));
fc830a83 14129
fd2ec330 14130 if (flags & EF_ARM_NEW_ABI)
9b485d32 14131 fprintf (file, _(" [new ABI]"));
9a5aca8c 14132
fd2ec330 14133 if (flags & EF_ARM_OLD_ABI)
9b485d32 14134 fprintf (file, _(" [old ABI]"));
9a5aca8c 14135
fd2ec330 14136 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14137 fprintf (file, _(" [software FP]"));
9a5aca8c 14138
96a846ea
RE		 14139 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14140 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14141 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14142 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14143 break;
9a5aca8c 14144
fc830a83 14145 case EF_ARM_EABI_VER1:
9b485d32 14146 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14147
fc830a83 14148 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14149 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14150 else
9b485d32 14151 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14152
fc830a83
NC		 14153 flags &= ~ EF_ARM_SYMSARESORTED;
14154 break;
9a5aca8c 14155
fd2ec330
PB		 14156 case EF_ARM_EABI_VER2:
14157 fprintf (file, _(" [Version2 EABI]"));
14158
14159 if (flags & EF_ARM_SYMSARESORTED)
14160 fprintf (file, _(" [sorted symbol table]"));
14161 else
14162 fprintf (file, _(" [unsorted symbol table]"));
14163
14164 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14165 fprintf (file, _(" [dynamic symbols use segment index]"));
14166
14167 if (flags & EF_ARM_MAPSYMSFIRST)
14168 fprintf (file, _(" [mapping symbols precede others]"));
14169
99e4ae17 14170 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14171 | EF_ARM_MAPSYMSFIRST);
14172 break;
14173
d507cf36
PB		 14174 case EF_ARM_EABI_VER3:
14175 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14176 break;
14177
14178 case EF_ARM_EABI_VER4:
14179 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14180 goto eabi;
d507cf36 14181
3a4a14e9
PB		 14182 case EF_ARM_EABI_VER5:
14183 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14184
14185 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14186 fprintf (file, _(" [soft-float ABI]"));
14187
14188 if (flags & EF_ARM_ABI_FLOAT_HARD)
14189 fprintf (file, _(" [hard-float ABI]"));
14190
14191 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14192
3a4a14e9 14193 eabi:
d507cf36
PB		 14194 if (flags & EF_ARM_BE8)
14195 fprintf (file, _(" [BE8]"));
14196
14197 if (flags & EF_ARM_LE8)
14198 fprintf (file, _(" [LE8]"));
14199
14200 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14201 break;
14202
fc830a83 14203 default:
9b485d32 14204 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14205 break;
14206 }
252b5132 14207
fc830a83 14208 flags &= ~ EF_ARM_EABIMASK;
252b5132 14209
fc830a83 14210 if (flags & EF_ARM_RELEXEC)
9b485d32 14211 fprintf (file, _(" [relocatable executable]"));
252b5132 14212
a5721edd 14213 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14214
14215 if (flags)
9b485d32 14216 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14217
252b5132
RH		 14218 fputc ('\n', file);
14219
b34976b6 14220 return TRUE;
252b5132
RH		 14221}
14222
14223static int
57e8b36a 14224elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14225{
2f0ca46a
NC		 14226 switch (ELF_ST_TYPE (elf_sym->st_info))
14227 {
14228 case STT_ARM_TFUNC:
14229 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14230
2f0ca46a
NC		 14231 case STT_ARM_16BIT:
14232 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14233 This allows us to distinguish between data used by Thumb instructions
14234 and non-data (which is probably code) inside Thumb regions of an
14235 executable. */
1a0eb693 14236 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14237 return ELF_ST_TYPE (elf_sym->st_info);
14238 break;
9a5aca8c 14239
ce855c42
NC		 14240 default:
14241 break;
2f0ca46a
NC		 14242 }
14243
14244 return type;
252b5132 14245}
f21f3fe0 14246
252b5132 14247static asection *
07adf181
AM		 14248elf32_arm_gc_mark_hook (asection *sec,
14249 struct bfd_link_info *info,
14250 Elf_Internal_Rela *rel,
14251 struct elf_link_hash_entry *h,
14252 Elf_Internal_Sym *sym)
252b5132
RH		 14253{
14254 if (h != NULL)
07adf181 14255 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14256 {
14257 case R_ARM_GNU_VTINHERIT:
14258 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14259 return NULL;
14260 }
9ad5cbcf 14261
07adf181 14262 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14263}
14264
780a67af
NC		 14265/* Update the got entry reference counts for the section being removed. */
14266
b34976b6 14267static bfd_boolean
ba93b8ac
DJ		 14268elf32_arm_gc_sweep_hook (bfd * abfd,
14269 struct bfd_link_info * info,
14270 asection * sec,
14271 const Elf_Internal_Rela * relocs)
252b5132 14272{
5e681ec4
PB		 14273 Elf_Internal_Shdr *symtab_hdr;
14274 struct elf_link_hash_entry **sym_hashes;
14275 bfd_signed_vma *local_got_refcounts;
14276 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14277 struct elf32_arm_link_hash_table * globals;
14278
0e1862bb 14279 if (bfd_link_relocatable (info))
7dda2462
TG		 14280 return TRUE;
14281
eb043451 14282 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14283 if (globals == NULL)
14284 return FALSE;
5e681ec4
PB		 14285
14286 elf_section_data (sec)->local_dynrel = NULL;
14287
0ffa91dd 14288 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14289 sym_hashes = elf_sym_hashes (abfd);
14290 local_got_refcounts = elf_local_got_refcounts (abfd);
14291
906e58ca 14292 check_use_blx (globals);
bd97cb95 14293
5e681ec4
PB		 14294 relend = relocs + sec->reloc_count;
14295 for (rel = relocs; rel < relend; rel++)
eb043451 14296 {
3eb128b2
AM		 14297 unsigned long r_symndx;
14298 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14299 struct elf32_arm_link_hash_entry *eh;
eb043451 14300 int r_type;
34e77a92 14301 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14302 bfd_boolean may_become_dynamic_p;
14303 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14304 union gotplt_union *root_plt;
14305 struct arm_plt_info *arm_plt;
5e681ec4 14306
3eb128b2
AM		 14307 r_symndx = ELF32_R_SYM (rel->r_info);
14308 if (r_symndx >= symtab_hdr->sh_info)
14309 {
14310 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14311 while (h->root.type == bfd_link_hash_indirect
14312 || h->root.type == bfd_link_hash_warning)
14313 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14314 }
f6e32f6d
RS		 14315 eh = (struct elf32_arm_link_hash_entry *) h;
14316
34e77a92 14317 call_reloc_p = FALSE;
f6e32f6d
RS		 14318 may_become_dynamic_p = FALSE;
14319 may_need_local_target_p = FALSE;
3eb128b2 14320
eb043451 14321 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14322 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14323 switch (r_type)
14324 {
14325 case R_ARM_GOT32:
eb043451 14326 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14327 case R_ARM_TLS_GD32:
14328 case R_ARM_TLS_IE32:
3eb128b2 14329 if (h != NULL)
eb043451 14330 {
eb043451
PB		 14331 if (h->got.refcount > 0)
14332 h->got.refcount -= 1;
14333 }
14334 else if (local_got_refcounts != NULL)
14335 {
14336 if (local_got_refcounts[r_symndx] > 0)
14337 local_got_refcounts[r_symndx] -= 1;
14338 }
14339 break;
14340
ba93b8ac 14341 case R_ARM_TLS_LDM32:
4dfe6ac6 14342 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14343 break;
14344
eb043451
PB		 14345 case R_ARM_PC24:
14346 case R_ARM_PLT32:
5b5bb741
PB		 14347 case R_ARM_CALL:
14348 case R_ARM_JUMP24:
eb043451 14349 case R_ARM_PREL31:
c19d1205 14350 case R_ARM_THM_CALL:
bd97cb95
DJ		 14351 case R_ARM_THM_JUMP24:
14352 case R_ARM_THM_JUMP19:
34e77a92 14353 call_reloc_p = TRUE;
f6e32f6d
RS		 14354 may_need_local_target_p = TRUE;
14355 break;
14356
14357 case R_ARM_ABS12:
14358 if (!globals->vxworks_p)
14359 {
14360 may_need_local_target_p = TRUE;
14361 break;
14362 }
14363 /* Fall through. */
14364 case R_ARM_ABS32:
14365 case R_ARM_ABS32_NOI:
14366 case R_ARM_REL32:
14367 case R_ARM_REL32_NOI:
b6895b4f
PB		 14368 case R_ARM_MOVW_ABS_NC:
14369 case R_ARM_MOVT_ABS:
14370 case R_ARM_MOVW_PREL_NC:
14371 case R_ARM_MOVT_PREL:
14372 case R_ARM_THM_MOVW_ABS_NC:
14373 case R_ARM_THM_MOVT_ABS:
14374 case R_ARM_THM_MOVW_PREL_NC:
14375 case R_ARM_THM_MOVT_PREL:
b7693d02 14376 /* Should the interworking branches be here also? */
0e1862bb 14377 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14378 && (sec->flags & SEC_ALLOC) != 0)
14379 {
14380 if (h == NULL
469a3493 14381 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14382 {
14383 call_reloc_p = TRUE;
14384 may_need_local_target_p = TRUE;
14385 }
14386 else
14387 may_become_dynamic_p = TRUE;
14388 }
f6e32f6d
RS		 14389 else
14390 may_need_local_target_p = TRUE;
14391 break;
b7693d02 14392
f6e32f6d
RS		 14393 default:
14394 break;
14395 }
5e681ec4 14396
34e77a92 14397 if (may_need_local_target_p
4ba2ef8f
TP		 14398 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14399 &arm_plt))
f6e32f6d 14400 {
27586251
HPN		 14401 /* If PLT refcount book-keeping is wrong and too low, we'll
14402 see a zero value (going to -1) for the root PLT reference
14403 count. */
14404 if (root_plt->refcount >= 0)
14405 {
14406 BFD_ASSERT (root_plt->refcount != 0);
14407 root_plt->refcount -= 1;
14408 }
14409 else
14410 /* A value of -1 means the symbol has become local, forced
14411 or seeing a hidden definition. Any other negative value
14412 is an error. */
14413 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14414
14415 if (!call_reloc_p)
14416 arm_plt->noncall_refcount--;
5e681ec4 14417
f6e32f6d 14418 if (r_type == R_ARM_THM_CALL)
34e77a92 14419 arm_plt->maybe_thumb_refcount--;
bd97cb95 14420
f6e32f6d
RS		 14421 if (r_type == R_ARM_THM_JUMP24
14422 || r_type == R_ARM_THM_JUMP19)
34e77a92 14423 arm_plt->thumb_refcount--;
f6e32f6d 14424 }
5e681ec4 14425
34e77a92 14426 if (may_become_dynamic_p)
f6e32f6d
RS		 14427 {
14428 struct elf_dyn_relocs **pp;
14429 struct elf_dyn_relocs *p;
5e681ec4 14430
34e77a92 14431 if (h != NULL)
9c489990 14432 pp = &(eh->dyn_relocs);
34e77a92
RS		 14433 else
14434 {
14435 Elf_Internal_Sym *isym;
14436
14437 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14438 abfd, r_symndx);
14439 if (isym == NULL)
14440 return FALSE;
14441 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14442 if (pp == NULL)
14443 return FALSE;
14444 }
9c489990 14445 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14446 if (p->sec == sec)
14447 {
14448 /* Everything must go for SEC. */
14449 *pp = p->next;
14450 break;
14451 }
eb043451
PB		 14452 }
14453 }
5e681ec4 14454
b34976b6 14455 return TRUE;
252b5132
RH		 14456}
14457
780a67af
NC		 14458/* Look through the relocs for a section during the first phase. */
14459
b34976b6 14460static bfd_boolean
57e8b36a
NC		 14461elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14462 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14463{
b34976b6
AM		 14464 Elf_Internal_Shdr *symtab_hdr;
14465 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14466 const Elf_Internal_Rela *rel;
14467 const Elf_Internal_Rela *rel_end;
14468 bfd *dynobj;
5e681ec4 14469 asection *sreloc;
5e681ec4 14470 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14471 bfd_boolean call_reloc_p;
14472 bfd_boolean may_become_dynamic_p;
14473 bfd_boolean may_need_local_target_p;
ce98a316 14474 unsigned long nsyms;
9a5aca8c 14475
0e1862bb 14476 if (bfd_link_relocatable (info))
b34976b6 14477 return TRUE;
9a5aca8c 14478
0ffa91dd
NC		 14479 BFD_ASSERT (is_arm_elf (abfd));
14480
5e681ec4 14481 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14482 if (htab == NULL)
14483 return FALSE;
14484
5e681ec4 14485 sreloc = NULL;
9a5aca8c 14486
67687978
PB		 14487 /* Create dynamic sections for relocatable executables so that we can
14488 copy relocations. */
14489 if (htab->root.is_relocatable_executable
14490 && ! htab->root.dynamic_sections_created)
14491 {
14492 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14493 return FALSE;
14494 }
14495
cbc704f3
RS		 14496 if (htab->root.dynobj == NULL)
14497 htab->root.dynobj = abfd;
34e77a92
RS		 14498 if (!create_ifunc_sections (info))
14499 return FALSE;
cbc704f3
RS		 14500
14501 dynobj = htab->root.dynobj;
14502
0ffa91dd 14503 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14504 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14505 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14506
252b5132
RH		 14507 rel_end = relocs + sec->reloc_count;
14508 for (rel = relocs; rel < rel_end; rel++)
14509 {
34e77a92 14510 Elf_Internal_Sym *isym;
252b5132 14511 struct elf_link_hash_entry *h;
b7693d02 14512 struct elf32_arm_link_hash_entry *eh;
252b5132 14513 unsigned long r_symndx;
eb043451 14514 int r_type;
9a5aca8c 14515
252b5132 14516 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14517 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14518 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14519
ce98a316
NC		 14520 if (r_symndx >= nsyms
14521 /* PR 9934: It is possible to have relocations that do not
14522 refer to symbols, thus it is also possible to have an
14523 object file containing relocations but no symbol table. */
cf35638d 14524 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14525 {
4eca0228
AM		 14526 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14527 r_symndx);
ba93b8ac
DJ		 14528 return FALSE;
14529 }
14530
34e77a92
RS		 14531 h = NULL;
14532 isym = NULL;
14533 if (nsyms > 0)
973a3492 14534 {
34e77a92
RS		 14535 if (r_symndx < symtab_hdr->sh_info)
14536 {
14537 /* A local symbol. */
14538 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14539 abfd, r_symndx);
14540 if (isym == NULL)
14541 return FALSE;
14542 }
14543 else
14544 {
14545 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14546 while (h->root.type == bfd_link_hash_indirect
14547 || h->root.type == bfd_link_hash_warning)
14548 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14549
14550 /* PR15323, ref flags aren't set for references in the
14551 same object. */
14552 h->root.non_ir_ref = 1;
34e77a92 14553 }
973a3492 14554 }
9a5aca8c 14555
b7693d02
DJ		 14556 eh = (struct elf32_arm_link_hash_entry *) h;
14557
f6e32f6d
RS		 14558 call_reloc_p = FALSE;
14559 may_become_dynamic_p = FALSE;
14560 may_need_local_target_p = FALSE;
14561
0855e32b
NS		 14562 /* Could be done earlier, if h were already available. */
14563 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14564 switch (r_type)
99059e56 14565 {
5e681ec4 14566 case R_ARM_GOT32:
eb043451 14567 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14568 case R_ARM_TLS_GD32:
14569 case R_ARM_TLS_IE32:
0855e32b
NS		 14570 case R_ARM_TLS_GOTDESC:
14571 case R_ARM_TLS_DESCSEQ:
14572 case R_ARM_THM_TLS_DESCSEQ:
14573 case R_ARM_TLS_CALL:
14574 case R_ARM_THM_TLS_CALL:
5e681ec4 14575 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14576 {
14577 int tls_type, old_tls_type;
5e681ec4 14578
ba93b8ac
DJ		 14579 switch (r_type)
14580 {
14581 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14582
ba93b8ac 14583 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14584
0855e32b
NS		 14585 case R_ARM_TLS_GOTDESC:
14586 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14587 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14588 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14589
ba93b8ac
DJ		 14590 default: tls_type = GOT_NORMAL; break;
14591 }
252b5132 14592
0e1862bb 14593 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14594 info->flags |= DF_STATIC_TLS;
14595
ba93b8ac
DJ		 14596 if (h != NULL)
14597 {
14598 h->got.refcount++;
14599 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14600 }
14601 else
14602 {
ba93b8ac 14603 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14604 if (!elf32_arm_allocate_local_sym_info (abfd))
14605 return FALSE;
14606 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14607 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14608 }
14609
0855e32b 14610 /* If a variable is accessed with both tls methods, two
99059e56 14611 slots may be created. */
0855e32b
NS		 14612 if (GOT_TLS_GD_ANY_P (old_tls_type)
14613 && GOT_TLS_GD_ANY_P (tls_type))
14614 tls_type |= old_tls_type;
14615
14616 /* We will already have issued an error message if there
14617 is a TLS/non-TLS mismatch, based on the symbol
14618 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14619 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14620 && tls_type != GOT_NORMAL)
14621 tls_type |= old_tls_type;
14622
0855e32b 14623 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14624 method, we're able to relax. Turn off the GDESC flag,
14625 without messing up with any other kind of tls types
6a631e86 14626 that may be involved. */
0855e32b
NS		 14627 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14628 tls_type &= ~GOT_TLS_GDESC;
14629
ba93b8ac
DJ		 14630 if (old_tls_type != tls_type)
14631 {
14632 if (h != NULL)
14633 elf32_arm_hash_entry (h)->tls_type = tls_type;
14634 else
14635 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14636 }
14637 }
8029a119 14638 /* Fall through. */
ba93b8ac
DJ		 14639
14640 case R_ARM_TLS_LDM32:
14641 if (r_type == R_ARM_TLS_LDM32)
14642 htab->tls_ldm_got.refcount++;
8029a119 14643 /* Fall through. */
252b5132 14644
c19d1205 14645 case R_ARM_GOTOFF32:
5e681ec4 14646 case R_ARM_GOTPC:
cbc704f3
RS		 14647 if (htab->root.sgot == NULL
14648 && !create_got_section (htab->root.dynobj, info))
14649 return FALSE;
252b5132
RH		 14650 break;
14651
252b5132 14652 case R_ARM_PC24:
7359ea65 14653 case R_ARM_PLT32:
5b5bb741
PB		 14654 case R_ARM_CALL:
14655 case R_ARM_JUMP24:
eb043451 14656 case R_ARM_PREL31:
c19d1205 14657 case R_ARM_THM_CALL:
bd97cb95
DJ		 14658 case R_ARM_THM_JUMP24:
14659 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14660 call_reloc_p = TRUE;
14661 may_need_local_target_p = TRUE;
14662 break;
14663
14664 case R_ARM_ABS12:
14665 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14666 ldr __GOTT_INDEX__ offsets. */
14667 if (!htab->vxworks_p)
14668 {
14669 may_need_local_target_p = TRUE;
14670 break;
14671 }
aebf9be7 14672 else goto jump_over;
9eaff861 14673
f6e32f6d 14674 /* Fall through. */
39623e12 14675
96c23d59
JM		 14676 case R_ARM_MOVW_ABS_NC:
14677 case R_ARM_MOVT_ABS:
14678 case R_ARM_THM_MOVW_ABS_NC:
14679 case R_ARM_THM_MOVT_ABS:
0e1862bb 14680 if (bfd_link_pic (info))
96c23d59 14681 {
4eca0228 14682 _bfd_error_handler
96c23d59
JM		 14683 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14684 abfd, elf32_arm_howto_table_1[r_type].name,
14685 (h) ? h->root.root.string : "a local symbol");
14686 bfd_set_error (bfd_error_bad_value);
14687 return FALSE;
14688 }
14689
14690 /* Fall through. */
39623e12
PB		 14691 case R_ARM_ABS32:
14692 case R_ARM_ABS32_NOI:
aebf9be7 14693 jump_over:
0e1862bb 14694 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14695 {
14696 h->pointer_equality_needed = 1;
14697 }
14698 /* Fall through. */
39623e12
PB		 14699 case R_ARM_REL32:
14700 case R_ARM_REL32_NOI:
b6895b4f
PB		 14701 case R_ARM_MOVW_PREL_NC:
14702 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14703 case R_ARM_THM_MOVW_PREL_NC:
14704 case R_ARM_THM_MOVT_PREL:
39623e12 14705
b7693d02 14706 /* Should the interworking branches be listed here? */
0e1862bb 14707 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14708 && (sec->flags & SEC_ALLOC) != 0)
14709 {
14710 if (h == NULL
469a3493 14711 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14712 {
14713 /* In shared libraries and relocatable executables,
14714 we treat local relative references as calls;
14715 see the related SYMBOL_CALLS_LOCAL code in
14716 allocate_dynrelocs. */
14717 call_reloc_p = TRUE;
14718 may_need_local_target_p = TRUE;
14719 }
14720 else
14721 /* We are creating a shared library or relocatable
14722 executable, and this is a reloc against a global symbol,
14723 or a non-PC-relative reloc against a local symbol.
14724 We may need to copy the reloc into the output. */
14725 may_become_dynamic_p = TRUE;
14726 }
f6e32f6d
RS		 14727 else
14728 may_need_local_target_p = TRUE;
252b5132
RH		 14729 break;
14730
99059e56
RM		 14731 /* This relocation describes the C++ object vtable hierarchy.
14732 Reconstruct it for later use during GC. */
14733 case R_ARM_GNU_VTINHERIT:
14734 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14735 return FALSE;
14736 break;
14737
14738 /* This relocation describes which C++ vtable entries are actually
14739 used. Record for later use during GC. */
14740 case R_ARM_GNU_VTENTRY:
14741 BFD_ASSERT (h != NULL);
14742 if (h != NULL
14743 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14744 return FALSE;
14745 break;
14746 }
f6e32f6d
RS		 14747
14748 if (h != NULL)
14749 {
14750 if (call_reloc_p)
14751 /* We may need a .plt entry if the function this reloc
14752 refers to is in a different object, regardless of the
14753 symbol's type. We can't tell for sure yet, because
14754 something later might force the symbol local. */
14755 h->needs_plt = 1;
14756 else if (may_need_local_target_p)
14757 /* If this reloc is in a read-only section, we might
14758 need a copy reloc. We can't check reliably at this
14759 stage whether the section is read-only, as input
14760 sections have not yet been mapped to output sections.
14761 Tentatively set the flag for now, and correct in
14762 adjust_dynamic_symbol. */
14763 h->non_got_ref = 1;
14764 }
14765
34e77a92
RS		 14766 if (may_need_local_target_p
14767 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14768 {
34e77a92
RS		 14769 union gotplt_union *root_plt;
14770 struct arm_plt_info *arm_plt;
14771 struct arm_local_iplt_info *local_iplt;
14772
14773 if (h != NULL)
14774 {
14775 root_plt = &h->plt;
14776 arm_plt = &eh->plt;
14777 }
14778 else
14779 {
14780 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14781 if (local_iplt == NULL)
14782 return FALSE;
14783 root_plt = &local_iplt->root;
14784 arm_plt = &local_iplt->arm;
14785 }
14786
f6e32f6d
RS		 14787 /* If the symbol is a function that doesn't bind locally,
14788 this relocation will need a PLT entry. */
a8c887dd
NC		 14789 if (root_plt->refcount != -1)
14790 root_plt->refcount += 1;
34e77a92
RS		 14791
14792 if (!call_reloc_p)
14793 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14794
14795 /* It's too early to use htab->use_blx here, so we have to
14796 record possible blx references separately from
14797 relocs that definitely need a thumb stub. */
14798
14799 if (r_type == R_ARM_THM_CALL)
34e77a92 14800 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14801
14802 if (r_type == R_ARM_THM_JUMP24
14803 || r_type == R_ARM_THM_JUMP19)
34e77a92 14804 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14805 }
14806
14807 if (may_become_dynamic_p)
14808 {
14809 struct elf_dyn_relocs *p, **head;
14810
14811 /* Create a reloc section in dynobj. */
14812 if (sreloc == NULL)
14813 {
14814 sreloc = _bfd_elf_make_dynamic_reloc_section
14815 (sec, dynobj, 2, abfd, ! htab->use_rel);
14816
14817 if (sreloc == NULL)
14818 return FALSE;
14819
14820 /* BPABI objects never have dynamic relocations mapped. */
14821 if (htab->symbian_p)
14822 {
14823 flagword flags;
14824
14825 flags = bfd_get_section_flags (dynobj, sreloc);
14826 flags &= ~(SEC_LOAD | SEC_ALLOC);
14827 bfd_set_section_flags (dynobj, sreloc, flags);
14828 }
14829 }
14830
14831 /* If this is a global symbol, count the number of
14832 relocations we need for this symbol. */
14833 if (h != NULL)
14834 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14835 else
14836 {
34e77a92
RS		 14837 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14838 if (head == NULL)
f6e32f6d 14839 return FALSE;
f6e32f6d
RS		 14840 }
14841
14842 p = *head;
14843 if (p == NULL || p->sec != sec)
14844 {
14845 bfd_size_type amt = sizeof *p;
14846
14847 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14848 if (p == NULL)
14849 return FALSE;
14850 p->next = *head;
14851 *head = p;
14852 p->sec = sec;
14853 p->count = 0;
14854 p->pc_count = 0;
14855 }
14856
469a3493 14857 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14858 p->pc_count += 1;
14859 p->count += 1;
14860 }
252b5132 14861 }
f21f3fe0 14862
b34976b6 14863 return TRUE;
252b5132
RH		 14864}
14865
9eaff861
AO		 14866static void
14867elf32_arm_update_relocs (asection *o,
14868 struct bfd_elf_section_reloc_data *reldata)
14869{
14870 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14871 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14872 const struct elf_backend_data *bed;
14873 _arm_elf_section_data *eado;
14874 struct bfd_link_order *p;
14875 bfd_byte *erela_head, *erela;
14876 Elf_Internal_Rela *irela_head, *irela;
14877 Elf_Internal_Shdr *rel_hdr;
14878 bfd *abfd;
14879 unsigned int count;
14880
14881 eado = get_arm_elf_section_data (o);
14882
14883 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14884 return;
14885
14886 abfd = o->owner;
14887 bed = get_elf_backend_data (abfd);
14888 rel_hdr = reldata->hdr;
14889
14890 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14891 {
14892 swap_in = bed->s->swap_reloc_in;
14893 swap_out = bed->s->swap_reloc_out;
14894 }
14895 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14896 {
14897 swap_in = bed->s->swap_reloca_in;
14898 swap_out = bed->s->swap_reloca_out;
14899 }
14900 else
14901 abort ();
14902
14903 erela_head = rel_hdr->contents;
14904 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14905 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14906
14907 erela = erela_head;
14908 irela = irela_head;
14909 count = 0;
14910
14911 for (p = o->map_head.link_order; p; p = p->next)
14912 {
14913 if (p->type == bfd_section_reloc_link_order
14914 || p->type == bfd_symbol_reloc_link_order)
14915 {
14916 (*swap_in) (abfd, erela, irela);
14917 erela += rel_hdr->sh_entsize;
14918 irela++;
14919 count++;
14920 }
14921 else if (p->type == bfd_indirect_link_order)
14922 {
14923 struct bfd_elf_section_reloc_data *input_reldata;
14924 arm_unwind_table_edit *edit_list, *edit_tail;
14925 _arm_elf_section_data *eadi;
14926 bfd_size_type j;
14927 bfd_vma offset;
14928 asection *i;
14929
14930 i = p->u.indirect.section;
14931
14932 eadi = get_arm_elf_section_data (i);
14933 edit_list = eadi->u.exidx.unwind_edit_list;
14934 edit_tail = eadi->u.exidx.unwind_edit_tail;
14935 offset = o->vma + i->output_offset;
14936
14937 if (eadi->elf.rel.hdr &&
14938 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14939 input_reldata = &eadi->elf.rel;
14940 else if (eadi->elf.rela.hdr &&
14941 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14942 input_reldata = &eadi->elf.rela;
14943 else
14944 abort ();
14945
14946 if (edit_list)
14947 {
14948 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14949 {
14950 arm_unwind_table_edit *edit_node, *edit_next;
14951 bfd_vma bias;
c48182bf 14952 bfd_vma reloc_index;
9eaff861
AO		 14953
14954 (*swap_in) (abfd, erela, irela);
c48182bf 14955 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14956
14957 bias = 0;
14958 edit_node = edit_list;
14959 for (edit_next = edit_list;
c48182bf 14960 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14961 edit_next = edit_node->next)
14962 {
14963 bias++;
14964 edit_node = edit_next;
14965 }
14966
14967 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14968 || edit_node->index != reloc_index)
9eaff861
AO		 14969 {
14970 irela->r_offset -= bias * 8;
14971 irela++;
14972 count++;
14973 }
14974
14975 erela += rel_hdr->sh_entsize;
14976 }
14977
14978 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14979 {
14980 /* New relocation entity. */
14981 asection *text_sec = edit_tail->linked_section;
14982 asection *text_out = text_sec->output_section;
14983 bfd_vma exidx_offset = offset + i->size - 8;
14984
14985 irela->r_addend = 0;
14986 irela->r_offset = exidx_offset;
14987 irela->r_info = ELF32_R_INFO
14988 (text_out->target_index, R_ARM_PREL31);
14989 irela++;
14990 count++;
14991 }
14992 }
14993 else
14994 {
14995 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14996 {
14997 (*swap_in) (abfd, erela, irela);
14998 erela += rel_hdr->sh_entsize;
14999 irela++;
15000 }
15001
15002 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15003 }
15004 }
15005 }
15006
15007 reldata->count = count;
15008 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15009
15010 erela = erela_head;
15011 irela = irela_head;
15012 while (count > 0)
15013 {
15014 (*swap_out) (abfd, irela, erela);
15015 erela += rel_hdr->sh_entsize;
15016 irela++;
15017 count--;
15018 }
15019
15020 free (irela_head);
15021
15022 /* Hashes are no longer valid. */
15023 free (reldata->hashes);
15024 reldata->hashes = NULL;
15025}
15026
6a5bb875 15027/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15028 required if the corresponding code section is marked. Similarly, ARMv8-M
15029 secure entry functions can only be referenced by SG veneers which are
15030 created after the GC process. They need to be marked in case they reside in
15031 their own section (as would be the case if code was compiled with
15032 -ffunction-sections). */
6a5bb875
PB		 15033
15034static bfd_boolean
906e58ca
NC		 15035elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15036 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15037{
15038 bfd *sub;
15039 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15040 asection *cmse_sec;
15041 obj_attribute *out_attr;
15042 Elf_Internal_Shdr *symtab_hdr;
15043 unsigned i, sym_count, ext_start;
15044 const struct elf_backend_data *bed;
15045 struct elf_link_hash_entry **sym_hashes;
15046 struct elf32_arm_link_hash_entry *cmse_hash;
15047 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15048
7f6ab9f8
AM		 15049 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15050
4ba2ef8f
TP		 15051 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15052 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15053 && out_attr[Tag_CPU_arch_profile].i == 'M';
15054
6a5bb875
PB		 15055 /* Marking EH data may cause additional code sections to be marked,
15056 requiring multiple passes. */
15057 again = TRUE;
15058 while (again)
15059 {
15060 again = FALSE;
c72f2fb2 15061 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15062 {
15063 asection *o;
15064
0ffa91dd 15065 if (! is_arm_elf (sub))
6a5bb875
PB		 15066 continue;
15067
15068 elf_shdrp = elf_elfsections (sub);
15069 for (o = sub->sections; o != NULL; o = o->next)
15070 {
15071 Elf_Internal_Shdr *hdr;
0ffa91dd 15072
6a5bb875 15073 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15074 if (hdr->sh_type == SHT_ARM_EXIDX
15075 && hdr->sh_link
15076 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15077 && !o->gc_mark
15078 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15079 {
15080 again = TRUE;
15081 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15082 return FALSE;
15083 }
15084 }
4ba2ef8f
TP		 15085
15086 /* Mark section holding ARMv8-M secure entry functions. We mark all
15087 of them so no need for a second browsing. */
15088 if (is_v8m && first_bfd_browse)
15089 {
15090 sym_hashes = elf_sym_hashes (sub);
15091 bed = get_elf_backend_data (sub);
15092 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15093 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15094 ext_start = symtab_hdr->sh_info;
15095
15096 /* Scan symbols. */
15097 for (i = ext_start; i < sym_count; i++)
15098 {
15099 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15100
15101 /* Assume it is a special symbol. If not, cmse_scan will
15102 warn about it and user can do something about it. */
15103 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15104 {
15105 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15106 if (!cmse_sec->gc_mark
15107 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15108 return FALSE;
15109 }
15110 }
15111 }
6a5bb875 15112 }
4ba2ef8f 15113 first_bfd_browse = FALSE;
6a5bb875
PB		 15114 }
15115
15116 return TRUE;
15117}
15118
3c9458e9
NC		 15119/* Treat mapping symbols as special target symbols. */
15120
15121static bfd_boolean
15122elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15123{
b0796911
PB		 15124 return bfd_is_arm_special_symbol_name (sym->name,
15125 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15126}
15127
0367ecfb
NC		 15128/* This is a copy of elf_find_function() from elf.c except that
15129 ARM mapping symbols are ignored when looking for function names
15130 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15131
0367ecfb
NC		 15132static bfd_boolean
15133arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15134 asymbol ** symbols,
fb167eb2 15135 asection * section,
0367ecfb
NC		 15136 bfd_vma offset,
15137 const char ** filename_ptr,
15138 const char ** functionname_ptr)
15139{
15140 const char * filename = NULL;
15141 asymbol * func = NULL;
15142 bfd_vma low_func = 0;
15143 asymbol ** p;
252b5132
RH		 15144
15145 for (p = symbols; *p != NULL; p++)
15146 {
15147 elf_symbol_type *q;
15148
15149 q = (elf_symbol_type *) *p;
15150
252b5132
RH		 15151 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15152 {
15153 default:
15154 break;
15155 case STT_FILE:
15156 filename = bfd_asymbol_name (&q->symbol);
15157 break;
252b5132
RH		 15158 case STT_FUNC:
15159 case STT_ARM_TFUNC:
9d2da7ca 15160 case STT_NOTYPE:
b0796911 15161 /* Skip mapping symbols. */
0367ecfb 15162 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15163 && bfd_is_arm_special_symbol_name (q->symbol.name,
15164 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15165 continue;
15166 /* Fall through. */
6b40fcba 15167 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15168 && q->symbol.value >= low_func
15169 && q->symbol.value <= offset)
15170 {
15171 func = (asymbol *) q;
15172 low_func = q->symbol.value;
15173 }
15174 break;
15175 }
15176 }
15177
15178 if (func == NULL)
b34976b6 15179 return FALSE;
252b5132 15180
0367ecfb
NC		 15181 if (filename_ptr)
15182 *filename_ptr = filename;
15183 if (functionname_ptr)
15184 *functionname_ptr = bfd_asymbol_name (func);
15185
15186 return TRUE;
906e58ca 15187}
0367ecfb
NC		 15188
15189
15190/* Find the nearest line to a particular section and offset, for error
15191 reporting. This code is a duplicate of the code in elf.c, except
15192 that it uses arm_elf_find_function. */
15193
15194static bfd_boolean
15195elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15196 asymbol ** symbols,
fb167eb2 15197 asection * section,
0367ecfb
NC		 15198 bfd_vma offset,
15199 const char ** filename_ptr,
15200 const char ** functionname_ptr,
fb167eb2
AM		 15201 unsigned int * line_ptr,
15202 unsigned int * discriminator_ptr)
0367ecfb
NC		 15203{
15204 bfd_boolean found = FALSE;
15205
fb167eb2 15206 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15207 filename_ptr, functionname_ptr,
fb167eb2
AM		 15208 line_ptr, discriminator_ptr,
15209 dwarf_debug_sections, 0,
0367ecfb
NC		 15210 & elf_tdata (abfd)->dwarf2_find_line_info))
15211 {
15212 if (!*functionname_ptr)
fb167eb2 15213 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15214 *filename_ptr ? NULL : filename_ptr,
15215 functionname_ptr);
f21f3fe0 15216
0367ecfb
NC		 15217 return TRUE;
15218 }
15219
fb167eb2
AM		 15220 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15221 uses DWARF1. */
15222
0367ecfb
NC		 15223 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15224 & found, filename_ptr,
15225 functionname_ptr, line_ptr,
15226 & elf_tdata (abfd)->line_info))
15227 return FALSE;
15228
15229 if (found && (*functionname_ptr || *line_ptr))
15230 return TRUE;
15231
15232 if (symbols == NULL)
15233 return FALSE;
15234
fb167eb2 15235 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15236 filename_ptr, functionname_ptr))
15237 return FALSE;
15238
15239 *line_ptr = 0;
b34976b6 15240 return TRUE;
252b5132
RH		 15241}
15242
4ab527b0
FF		 15243static bfd_boolean
15244elf32_arm_find_inliner_info (bfd * abfd,
15245 const char ** filename_ptr,
15246 const char ** functionname_ptr,
15247 unsigned int * line_ptr)
15248{
15249 bfd_boolean found;
15250 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15251 functionname_ptr, line_ptr,
15252 & elf_tdata (abfd)->dwarf2_find_line_info);
15253 return found;
15254}
15255
252b5132
RH		 15256/* Adjust a symbol defined by a dynamic object and referenced by a
15257 regular object. The current definition is in some section of the
15258 dynamic object, but we're not including those sections. We have to
15259 change the definition to something the rest of the link can
15260 understand. */
15261
b34976b6 15262static bfd_boolean
57e8b36a
NC		 15263elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15264 struct elf_link_hash_entry * h)
252b5132
RH		 15265{
15266 bfd * dynobj;
15267 asection * s;
b7693d02 15268 struct elf32_arm_link_hash_entry * eh;
67687978 15269 struct elf32_arm_link_hash_table *globals;
252b5132 15270
67687978 15271 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15272 if (globals == NULL)
15273 return FALSE;
15274
252b5132
RH		 15275 dynobj = elf_hash_table (info)->dynobj;
15276
15277 /* Make sure we know what is going on here. */
15278 BFD_ASSERT (dynobj != NULL
f5385ebf 15279 && (h->needs_plt
34e77a92 15280 || h->type == STT_GNU_IFUNC
f6e332e6 15281 || h->u.weakdef != NULL
f5385ebf
AM		 15282 || (h->def_dynamic
15283 && h->ref_regular
15284 && !h->def_regular)));
252b5132 15285
b7693d02
DJ		 15286 eh = (struct elf32_arm_link_hash_entry *) h;
15287
252b5132
RH		 15288 /* If this is a function, put it in the procedure linkage table. We
15289 will fill in the contents of the procedure linkage table later,
15290 when we know the address of the .got section. */
34e77a92 15291 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15292 {
34e77a92
RS		 15293 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15294 symbol binds locally. */
5e681ec4 15295 if (h->plt.refcount <= 0
34e77a92
RS		 15296 || (h->type != STT_GNU_IFUNC
15297 && (SYMBOL_CALLS_LOCAL (info, h)
15298 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15299 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15300 {
15301 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15302 file, but the symbol was never referred to by a dynamic
15303 object, or if all references were garbage collected. In
15304 such a case, we don't actually need to build a procedure
15305 linkage table, and we can just do a PC24 reloc instead. */
15306 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15307 eh->plt.thumb_refcount = 0;
15308 eh->plt.maybe_thumb_refcount = 0;
15309 eh->plt.noncall_refcount = 0;
f5385ebf 15310 h->needs_plt = 0;
252b5132
RH		 15311 }
15312
b34976b6 15313 return TRUE;
252b5132 15314 }
5e681ec4 15315 else
b7693d02
DJ		 15316 {
15317 /* It's possible that we incorrectly decided a .plt reloc was
15318 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15319 in check_relocs. We can't decide accurately between function
15320 and non-function syms in check-relocs; Objects loaded later in
15321 the link may change h->type. So fix it now. */
15322 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15323 eh->plt.thumb_refcount = 0;
15324 eh->plt.maybe_thumb_refcount = 0;
15325 eh->plt.noncall_refcount = 0;
b7693d02 15326 }
252b5132
RH		 15327
15328 /* If this is a weak symbol, and there is a real definition, the
15329 processor independent code will have arranged for us to see the
15330 real definition first, and we can just use the same value. */
f6e332e6 15331 if (h->u.weakdef != NULL)
252b5132 15332 {
f6e332e6
AM		 15333 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15334 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15335 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15336 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15337 return TRUE;
252b5132
RH		 15338 }
15339
ba93b8ac
DJ		 15340 /* If there are no non-GOT references, we do not need a copy
15341 relocation. */
15342 if (!h->non_got_ref)
15343 return TRUE;
15344
252b5132
RH		 15345 /* This is a reference to a symbol defined by a dynamic object which
15346 is not a function. */
15347
15348 /* If we are creating a shared library, we must presume that the
15349 only references to the symbol are via the global offset table.
15350 For such cases we need not do anything here; the relocations will
67687978
PB		 15351 be handled correctly by relocate_section. Relocatable executables
15352 can reference data in shared objects directly, so we don't need to
15353 do anything here. */
0e1862bb 15354 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15355 return TRUE;
252b5132
RH		 15356
15357 /* We must allocate the symbol in our .dynbss section, which will
15358 become part of the .bss section of the executable. There will be
15359 an entry for this symbol in the .dynsym section. The dynamic
15360 object will contain position independent code, so all references
15361 from the dynamic object to this symbol will go through the global
15362 offset table. The dynamic linker will use the .dynsym entry to
15363 determine the address it must put in the global offset table, so
15364 both the dynamic object and the regular object will refer to the
15365 same memory location for the variable. */
9d19e4fd 15366 s = globals->root.sdynbss;
252b5132
RH		 15367 BFD_ASSERT (s != NULL);
15368
5522f910
NC		 15369 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15370 linker to copy the initial value out of the dynamic object and into
15371 the runtime process image. We need to remember the offset into the
00a97672 15372 .rel(a).bss section we are going to use. */
5522f910
NC		 15373 if (info->nocopyreloc == 0
15374 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15375 && h->size != 0)
252b5132
RH		 15376 {
15377 asection *srel;
15378
3d4d4302 15379 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15380 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15381 h->needs_copy = 1;
252b5132
RH		 15382 }
15383
6cabe1ea 15384 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15385}
15386
5e681ec4
PB		 15387/* Allocate space in .plt, .got and associated reloc sections for
15388 dynamic relocs. */
15389
15390static bfd_boolean
47beaa6a 15391allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15392{
15393 struct bfd_link_info *info;
15394 struct elf32_arm_link_hash_table *htab;
15395 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15396 struct elf_dyn_relocs *p;
5e681ec4
PB		 15397
15398 if (h->root.type == bfd_link_hash_indirect)
15399 return TRUE;
15400
e6a6bb22
AM		 15401 eh = (struct elf32_arm_link_hash_entry *) h;
15402
5e681ec4
PB		 15403 info = (struct bfd_link_info *) inf;
15404 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15405 if (htab == NULL)
15406 return FALSE;
5e681ec4 15407
34e77a92 15408 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15409 && h->plt.refcount > 0)
15410 {
15411 /* Make sure this symbol is output as a dynamic symbol.
15412 Undefined weak syms won't yet be marked as dynamic. */
15413 if (h->dynindx == -1
f5385ebf 15414 && !h->forced_local)
5e681ec4 15415 {
c152c796 15416 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15417 return FALSE;
15418 }
15419
34e77a92
RS		 15420 /* If the call in the PLT entry binds locally, the associated
15421 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15422 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15423 than the .plt section. */
15424 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15425 {
15426 eh->is_iplt = 1;
15427 if (eh->plt.noncall_refcount == 0
15428 && SYMBOL_REFERENCES_LOCAL (info, h))
15429 /* All non-call references can be resolved directly.
15430 This means that they can (and in some cases, must)
15431 resolve directly to the run-time target, rather than
15432 to the PLT. That in turns means that any .got entry
15433 would be equal to the .igot.plt entry, so there's
15434 no point having both. */
15435 h->got.refcount = 0;
15436 }
15437
0e1862bb 15438 if (bfd_link_pic (info)
34e77a92 15439 || eh->is_iplt
7359ea65 15440 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15441 {
34e77a92 15442 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15443
5e681ec4
PB		 15444 /* If this symbol is not defined in a regular file, and we are
15445 not generating a shared library, then set the symbol to this
15446 location in the .plt. This is required to make function
15447 pointers compare as equal between the normal executable and
15448 the shared library. */
0e1862bb 15449 if (! bfd_link_pic (info)
f5385ebf 15450 && !h->def_regular)
5e681ec4 15451 {
34e77a92 15452 h->root.u.def.section = htab->root.splt;
5e681ec4 15453 h->root.u.def.value = h->plt.offset;
5e681ec4 15454
67d74e43
DJ		 15455 /* Make sure the function is not marked as Thumb, in case
15456 it is the target of an ABS32 relocation, which will
15457 point to the PLT entry. */
39d911fc 15458 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15459 }
022f8312 15460
00a97672
RS		 15461 /* VxWorks executables have a second set of relocations for
15462 each PLT entry. They go in a separate relocation section,
15463 which is processed by the kernel loader. */
0e1862bb 15464 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15465 {
15466 /* There is a relocation for the initial PLT entry:
15467 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15468 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15469 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15470
15471 /* There are two extra relocations for each subsequent
15472 PLT entry: an R_ARM_32 relocation for the GOT entry,
15473 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15474 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15475 }
5e681ec4
PB		 15476 }
15477 else
15478 {
15479 h->plt.offset = (bfd_vma) -1;
f5385ebf 15480 h->needs_plt = 0;
5e681ec4
PB		 15481 }
15482 }
15483 else
15484 {
15485 h->plt.offset = (bfd_vma) -1;
f5385ebf 15486 h->needs_plt = 0;
5e681ec4
PB		 15487 }
15488
0855e32b
NS		 15489 eh = (struct elf32_arm_link_hash_entry *) h;
15490 eh->tlsdesc_got = (bfd_vma) -1;
15491
5e681ec4
PB		 15492 if (h->got.refcount > 0)
15493 {
15494 asection *s;
15495 bfd_boolean dyn;
ba93b8ac
DJ		 15496 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15497 int indx;
5e681ec4
PB		 15498
15499 /* Make sure this symbol is output as a dynamic symbol.
15500 Undefined weak syms won't yet be marked as dynamic. */
15501 if (h->dynindx == -1
f5385ebf 15502 && !h->forced_local)
5e681ec4 15503 {
c152c796 15504 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15505 return FALSE;
15506 }
15507
e5a52504
MM		 15508 if (!htab->symbian_p)
15509 {
362d30a1 15510 s = htab->root.sgot;
e5a52504 15511 h->got.offset = s->size;
ba93b8ac
DJ		 15512
15513 if (tls_type == GOT_UNKNOWN)
15514 abort ();
15515
15516 if (tls_type == GOT_NORMAL)
15517 /* Non-TLS symbols need one GOT slot. */
15518 s->size += 4;
15519 else
15520 {
99059e56
RM		 15521 if (tls_type & GOT_TLS_GDESC)
15522 {
0855e32b 15523 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15524 eh->tlsdesc_got
0855e32b
NS		 15525 = (htab->root.sgotplt->size
15526 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15527 htab->root.sgotplt->size += 8;
15528 h->got.offset = (bfd_vma) -2;
34e77a92 15529 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15530 reloc in the middle of .got.plt. */
99059e56
RM		 15531 htab->num_tls_desc++;
15532 }
0855e32b 15533
ba93b8ac 15534 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15535 {
15536 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15537 the symbol is both GD and GDESC, got.offset may
15538 have been overwritten. */
15539 h->got.offset = s->size;
15540 s->size += 8;
15541 }
15542
ba93b8ac
DJ		 15543 if (tls_type & GOT_TLS_IE)
15544 /* R_ARM_TLS_IE32 needs one GOT slot. */
15545 s->size += 4;
15546 }
15547
e5a52504 15548 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15549
15550 indx = 0;
0e1862bb
L		 15551 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15552 bfd_link_pic (info),
15553 h)
15554 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15555 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15556 indx = h->dynindx;
15557
15558 if (tls_type != GOT_NORMAL
0e1862bb 15559 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15560 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15561 || h->root.type != bfd_link_hash_undefweak))
15562 {
15563 if (tls_type & GOT_TLS_IE)
47beaa6a 15564 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15565
15566 if (tls_type & GOT_TLS_GD)
47beaa6a 15567 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15568
b38cadfb 15569 if (tls_type & GOT_TLS_GDESC)
0855e32b 15570 {
47beaa6a 15571 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15572 /* GDESC needs a trampoline to jump to. */
15573 htab->tls_trampoline = -1;
15574 }
15575
15576 /* Only GD needs it. GDESC just emits one relocation per
15577 2 entries. */
b38cadfb 15578 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15579 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15580 }
6f820c85 15581 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15582 {
15583 if (htab->root.dynamic_sections_created)
15584 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15585 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15586 }
34e77a92
RS		 15587 else if (h->type == STT_GNU_IFUNC
15588 && eh->plt.noncall_refcount == 0)
15589 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15590 they all resolve dynamically instead. Reserve room for the
15591 GOT entry's R_ARM_IRELATIVE relocation. */
15592 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15593 else if (bfd_link_pic (info)
15594 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15595 || h->root.type != bfd_link_hash_undefweak))
b436d854 15596 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15597 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15598 }
5e681ec4
PB		 15599 }
15600 else
15601 h->got.offset = (bfd_vma) -1;
15602
a4fd1a8e
PB		 15603 /* Allocate stubs for exported Thumb functions on v4t. */
15604 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15605 && h->def_regular
39d911fc 15606 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15607 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15608 {
15609 struct elf_link_hash_entry * th;
15610 struct bfd_link_hash_entry * bh;
15611 struct elf_link_hash_entry * myh;
15612 char name[1024];
15613 asection *s;
15614 bh = NULL;
15615 /* Create a new symbol to regist the real location of the function. */
15616 s = h->root.u.def.section;
906e58ca 15617 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15618 _bfd_generic_link_add_one_symbol (info, s->owner,
15619 name, BSF_GLOBAL, s,
15620 h->root.u.def.value,
15621 NULL, TRUE, FALSE, &bh);
15622
15623 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15624 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15625 myh->forced_local = 1;
39d911fc 15626 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15627 eh->export_glue = myh;
15628 th = record_arm_to_thumb_glue (info, h);
15629 /* Point the symbol at the stub. */
15630 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15631 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15632 h->root.u.def.section = th->root.u.def.section;
15633 h->root.u.def.value = th->root.u.def.value & ~1;
15634 }
15635
0bdcacaf 15636 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15637 return TRUE;
15638
15639 /* In the shared -Bsymbolic case, discard space allocated for
15640 dynamic pc-relative relocs against symbols which turn out to be
15641 defined in regular objects. For the normal shared case, discard
15642 space for pc-relative relocs that have become local due to symbol
15643 visibility changes. */
15644
0e1862bb 15645 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15646 {
469a3493
RM		 15647 /* Relocs that use pc_count are PC-relative forms, which will appear
15648 on something like ".long foo - ." or "movw REG, foo - .". We want
15649 calls to protected symbols to resolve directly to the function
15650 rather than going via the plt. If people want function pointer
15651 comparisons to work as expected then they should avoid writing
15652 assembly like ".long foo - .". */
ba93b8ac
DJ		 15653 if (SYMBOL_CALLS_LOCAL (info, h))
15654 {
0bdcacaf 15655 struct elf_dyn_relocs **pp;
ba93b8ac 15656
0bdcacaf 15657 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15658 {
15659 p->count -= p->pc_count;
15660 p->pc_count = 0;
15661 if (p->count == 0)
15662 *pp = p->next;
15663 else
15664 pp = &p->next;
15665 }
15666 }
15667
4dfe6ac6 15668 if (htab->vxworks_p)
3348747a 15669 {
0bdcacaf 15670 struct elf_dyn_relocs **pp;
3348747a 15671
0bdcacaf 15672 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15673 {
0bdcacaf 15674 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15675 *pp = p->next;
15676 else
15677 pp = &p->next;
15678 }
15679 }
15680
ba93b8ac 15681 /* Also discard relocs on undefined weak syms with non-default
99059e56 15682 visibility. */
0bdcacaf 15683 if (eh->dyn_relocs != NULL
5e681ec4 15684 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15685 {
15686 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15687 eh->dyn_relocs = NULL;
22d606e9
AM		 15688
15689 /* Make sure undefined weak symbols are output as a dynamic
15690 symbol in PIEs. */
15691 else if (h->dynindx == -1
15692 && !h->forced_local)
15693 {
15694 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15695 return FALSE;
15696 }
15697 }
15698
67687978
PB		 15699 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15700 && h->root.type == bfd_link_hash_new)
15701 {
15702 /* Output absolute symbols so that we can create relocations
15703 against them. For normal symbols we output a relocation
15704 against the section that contains them. */
15705 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15706 return FALSE;
15707 }
15708
5e681ec4
PB		 15709 }
15710 else
15711 {
15712 /* For the non-shared case, discard space for relocs against
15713 symbols which turn out to need copy relocs or are not
15714 dynamic. */
15715
f5385ebf
AM		 15716 if (!h->non_got_ref
15717 && ((h->def_dynamic
15718 && !h->def_regular)
5e681ec4
PB		 15719 || (htab->root.dynamic_sections_created
15720 && (h->root.type == bfd_link_hash_undefweak
15721 || h->root.type == bfd_link_hash_undefined))))
15722 {
15723 /* Make sure this symbol is output as a dynamic symbol.
15724 Undefined weak syms won't yet be marked as dynamic. */
15725 if (h->dynindx == -1
f5385ebf 15726 && !h->forced_local)
5e681ec4 15727 {
c152c796 15728 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15729 return FALSE;
15730 }
15731
15732 /* If that succeeded, we know we'll be keeping all the
15733 relocs. */
15734 if (h->dynindx != -1)
15735 goto keep;
15736 }
15737
0bdcacaf 15738 eh->dyn_relocs = NULL;
5e681ec4
PB		 15739
15740 keep: ;
15741 }
15742
15743 /* Finally, allocate space. */
0bdcacaf 15744 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15745 {
0bdcacaf 15746 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15747 if (h->type == STT_GNU_IFUNC
15748 && eh->plt.noncall_refcount == 0
15749 && SYMBOL_REFERENCES_LOCAL (info, h))
15750 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15751 else
15752 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15753 }
15754
15755 return TRUE;
15756}
15757
08d1f311
DJ		 15758/* Find any dynamic relocs that apply to read-only sections. */
15759
15760static bfd_boolean
8029a119 15761elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15762{
8029a119 15763 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15764 struct elf_dyn_relocs * p;
08d1f311 15765
08d1f311 15766 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15767 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15768 {
0bdcacaf 15769 asection *s = p->sec;
08d1f311
DJ		 15770
15771 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15772 {
15773 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15774
15775 info->flags |= DF_TEXTREL;
15776
15777 /* Not an error, just cut short the traversal. */
15778 return FALSE;
15779 }
15780 }
15781 return TRUE;
15782}
15783
d504ffc8
DJ		 15784void
15785bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15786 int byteswap_code)
15787{
15788 struct elf32_arm_link_hash_table *globals;
15789
15790 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15791 if (globals == NULL)
15792 return;
15793
d504ffc8
DJ		 15794 globals->byteswap_code = byteswap_code;
15795}
15796
252b5132
RH		 15797/* Set the sizes of the dynamic sections. */
15798
b34976b6 15799static bfd_boolean
57e8b36a
NC		 15800elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15801 struct bfd_link_info * info)
252b5132
RH		 15802{
15803 bfd * dynobj;
15804 asection * s;
b34976b6
AM		 15805 bfd_boolean plt;
15806 bfd_boolean relocs;
5e681ec4
PB		 15807 bfd *ibfd;
15808 struct elf32_arm_link_hash_table *htab;
252b5132 15809
5e681ec4 15810 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15811 if (htab == NULL)
15812 return FALSE;
15813
252b5132
RH		 15814 dynobj = elf_hash_table (info)->dynobj;
15815 BFD_ASSERT (dynobj != NULL);
39b41c9c 15816 check_use_blx (htab);
252b5132
RH		 15817
15818 if (elf_hash_table (info)->dynamic_sections_created)
15819 {
15820 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15821 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15822 {
3d4d4302 15823 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15824 BFD_ASSERT (s != NULL);
eea6121a 15825 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15826 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15827 }
15828 }
5e681ec4
PB		 15829
15830 /* Set up .got offsets for local syms, and space for local dynamic
15831 relocs. */
c72f2fb2 15832 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15833 {
5e681ec4
PB		 15834 bfd_signed_vma *local_got;
15835 bfd_signed_vma *end_local_got;
34e77a92 15836 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15837 char *local_tls_type;
0855e32b 15838 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15839 bfd_size_type locsymcount;
15840 Elf_Internal_Shdr *symtab_hdr;
15841 asection *srel;
4dfe6ac6 15842 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15843 unsigned int symndx;
5e681ec4 15844
0ffa91dd 15845 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15846 continue;
15847
15848 for (s = ibfd->sections; s != NULL; s = s->next)
15849 {
0bdcacaf 15850 struct elf_dyn_relocs *p;
5e681ec4 15851
0bdcacaf 15852 for (p = (struct elf_dyn_relocs *)
99059e56 15853 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15854 {
0bdcacaf
RS		 15855 if (!bfd_is_abs_section (p->sec)
15856 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15857 {
15858 /* Input section has been discarded, either because
15859 it is a copy of a linkonce section or due to
15860 linker script /DISCARD/, so we'll be discarding
15861 the relocs too. */
15862 }
3348747a 15863 else if (is_vxworks
0bdcacaf 15864 && strcmp (p->sec->output_section->name,
3348747a
NS		 15865 ".tls_vars") == 0)
15866 {
15867 /* Relocations in vxworks .tls_vars sections are
15868 handled specially by the loader. */
15869 }
5e681ec4
PB		 15870 else if (p->count != 0)
15871 {
0bdcacaf 15872 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15873 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15874 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15875 info->flags |= DF_TEXTREL;
15876 }
15877 }
15878 }
15879
15880 local_got = elf_local_got_refcounts (ibfd);
15881 if (!local_got)
15882 continue;
15883
0ffa91dd 15884 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15885 locsymcount = symtab_hdr->sh_info;
15886 end_local_got = local_got + locsymcount;
34e77a92 15887 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15888 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15889 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15890 symndx = 0;
362d30a1
RS		 15891 s = htab->root.sgot;
15892 srel = htab->root.srelgot;
0855e32b 15893 for (; local_got < end_local_got;
34e77a92
RS		 15894 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15895 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15896 {
0855e32b 15897 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15898 local_iplt = *local_iplt_ptr;
15899 if (local_iplt != NULL)
15900 {
15901 struct elf_dyn_relocs *p;
15902
15903 if (local_iplt->root.refcount > 0)
15904 {
15905 elf32_arm_allocate_plt_entry (info, TRUE,
15906 &local_iplt->root,
15907 &local_iplt->arm);
15908 if (local_iplt->arm.noncall_refcount == 0)
15909 /* All references to the PLT are calls, so all
15910 non-call references can resolve directly to the
15911 run-time target. This means that the .got entry
15912 would be the same as the .igot.plt entry, so there's
15913 no point creating both. */
15914 *local_got = 0;
15915 }
15916 else
15917 {
15918 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15919 local_iplt->root.offset = (bfd_vma) -1;
15920 }
15921
15922 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15923 {
15924 asection *psrel;
15925
15926 psrel = elf_section_data (p->sec)->sreloc;
15927 if (local_iplt->arm.noncall_refcount == 0)
15928 elf32_arm_allocate_irelocs (info, psrel, p->count);
15929 else
15930 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15931 }
15932 }
5e681ec4
PB		 15933 if (*local_got > 0)
15934 {
34e77a92
RS		 15935 Elf_Internal_Sym *isym;
15936
eea6121a 15937 *local_got = s->size;
ba93b8ac
DJ		 15938 if (*local_tls_type & GOT_TLS_GD)
15939 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15940 s->size += 8;
0855e32b
NS		 15941 if (*local_tls_type & GOT_TLS_GDESC)
15942 {
15943 *local_tlsdesc_gotent = htab->root.sgotplt->size
15944 - elf32_arm_compute_jump_table_size (htab);
15945 htab->root.sgotplt->size += 8;
15946 *local_got = (bfd_vma) -2;
34e77a92 15947 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15948 reloc in the middle of .got.plt. */
99059e56 15949 htab->num_tls_desc++;
0855e32b 15950 }
ba93b8ac
DJ		 15951 if (*local_tls_type & GOT_TLS_IE)
15952 s->size += 4;
ba93b8ac 15953
0855e32b
NS		 15954 if (*local_tls_type & GOT_NORMAL)
15955 {
15956 /* If the symbol is both GD and GDESC, *local_got
15957 may have been overwritten. */
15958 *local_got = s->size;
15959 s->size += 4;
15960 }
15961
34e77a92
RS		 15962 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15963 if (isym == NULL)
15964 return FALSE;
15965
15966 /* If all references to an STT_GNU_IFUNC PLT are calls,
15967 then all non-call references, including this GOT entry,
15968 resolve directly to the run-time target. */
15969 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15970 && (local_iplt == NULL
15971 || local_iplt->arm.noncall_refcount == 0))
15972 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15973 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15974 {
0e1862bb 15975 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15976 || *local_tls_type & GOT_TLS_GD)
15977 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15978
0e1862bb 15979 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15980 {
15981 elf32_arm_allocate_dynrelocs (info,
15982 htab->root.srelplt, 1);
15983 htab->tls_trampoline = -1;
15984 }
0855e32b 15985 }
5e681ec4
PB		 15986 }
15987 else
15988 *local_got = (bfd_vma) -1;
15989 }
252b5132
RH		 15990 }
15991
ba93b8ac
DJ		 15992 if (htab->tls_ldm_got.refcount > 0)
15993 {
15994 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15995 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15996 htab->tls_ldm_got.offset = htab->root.sgot->size;
15997 htab->root.sgot->size += 8;
0e1862bb 15998 if (bfd_link_pic (info))
47beaa6a 15999 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16000 }
16001 else
16002 htab->tls_ldm_got.offset = -1;
16003
5e681ec4
PB		 16004 /* Allocate global sym .plt and .got entries, and space for global
16005 sym dynamic relocs. */
47beaa6a 16006 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16007
d504ffc8 16008 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16009 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16010 {
0ffa91dd 16011 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16012 continue;
16013
c7b8f16e
JB		 16014 /* Initialise mapping tables for code/data. */
16015 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16016
c7b8f16e 16017 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16018 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16019 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56 16020 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 16021 ibfd->filename);
16022 }
d504ffc8 16023
3e6b1042
DJ		 16024 /* Allocate space for the glue sections now that we've sized them. */
16025 bfd_elf32_arm_allocate_interworking_sections (info);
16026
0855e32b
NS		 16027 /* For every jump slot reserved in the sgotplt, reloc_count is
16028 incremented. However, when we reserve space for TLS descriptors,
16029 it's not incremented, so in order to compute the space reserved
16030 for them, it suffices to multiply the reloc count by the jump
16031 slot size. */
16032 if (htab->root.srelplt)
16033 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16034
16035 if (htab->tls_trampoline)
16036 {
16037 if (htab->root.splt->size == 0)
16038 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16039
0855e32b
NS		 16040 htab->tls_trampoline = htab->root.splt->size;
16041 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16042
0855e32b 16043 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16044 PLT and GOT entries they require. */
0855e32b
NS		 16045 if (!(info->flags & DF_BIND_NOW))
16046 {
16047 htab->dt_tlsdesc_got = htab->root.sgot->size;
16048 htab->root.sgot->size += 4;
16049
16050 htab->dt_tlsdesc_plt = htab->root.splt->size;
16051 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16052 }
16053 }
16054
252b5132
RH		 16055 /* The check_relocs and adjust_dynamic_symbol entry points have
16056 determined the sizes of the various dynamic sections. Allocate
16057 memory for them. */
b34976b6
AM		 16058 plt = FALSE;
16059 relocs = FALSE;
252b5132
RH		 16060 for (s = dynobj->sections; s != NULL; s = s->next)
16061 {
16062 const char * name;
252b5132
RH		 16063
16064 if ((s->flags & SEC_LINKER_CREATED) == 0)
16065 continue;
16066
16067 /* It's OK to base decisions on the section name, because none
16068 of the dynobj section names depend upon the input files. */
16069 name = bfd_get_section_name (dynobj, s);
16070
34e77a92 16071 if (s == htab->root.splt)
252b5132 16072 {
c456f082
AM		 16073 /* Remember whether there is a PLT. */
16074 plt = s->size != 0;
252b5132 16075 }
0112cd26 16076 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16077 {
c456f082 16078 if (s->size != 0)
252b5132 16079 {
252b5132 16080 /* Remember whether there are any reloc sections other
00a97672 16081 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16082 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16083 relocs = TRUE;
252b5132
RH		 16084
16085 /* We use the reloc_count field as a counter if we need
16086 to copy relocs into the output file. */
16087 s->reloc_count = 0;
16088 }
16089 }
34e77a92
RS		 16090 else if (s != htab->root.sgot
16091 && s != htab->root.sgotplt
16092 && s != htab->root.iplt
16093 && s != htab->root.igotplt
9d19e4fd 16094 && s != htab->root.sdynbss)
252b5132
RH		 16095 {
16096 /* It's not one of our sections, so don't allocate space. */
16097 continue;
16098 }
16099
c456f082 16100 if (s->size == 0)
252b5132 16101 {
c456f082 16102 /* If we don't need this section, strip it from the
00a97672
RS		 16103 output file. This is mostly to handle .rel(a).bss and
16104 .rel(a).plt. We must create both sections in
c456f082
AM		 16105 create_dynamic_sections, because they must be created
16106 before the linker maps input sections to output
16107 sections. The linker does that before
16108 adjust_dynamic_symbol is called, and it is that
16109 function which decides whether anything needs to go
16110 into these sections. */
8423293d 16111 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16112 continue;
16113 }
16114
c456f082
AM		 16115 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16116 continue;
16117
252b5132 16118 /* Allocate memory for the section contents. */
21d799b5 16119 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16120 if (s->contents == NULL)
b34976b6 16121 return FALSE;
252b5132
RH		 16122 }
16123
16124 if (elf_hash_table (info)->dynamic_sections_created)
16125 {
16126 /* Add some entries to the .dynamic section. We fill in the
16127 values later, in elf32_arm_finish_dynamic_sections, but we
16128 must add the entries now so that we get the correct size for
16129 the .dynamic section. The DT_DEBUG entry is filled in by the
16130 dynamic linker and used by the debugger. */
dc810e39 16131#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16132 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16133
0e1862bb 16134 if (bfd_link_executable (info))
252b5132 16135 {
dc810e39 16136 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16137 return FALSE;
252b5132
RH		 16138 }
16139
16140 if (plt)
16141 {
dc810e39
AM		 16142 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16143 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16144 || !add_dynamic_entry (DT_PLTREL,
16145 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16146 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16147 return FALSE;
0855e32b 16148
5025eb7c
AO		 16149 if (htab->dt_tlsdesc_plt
16150 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16151 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16152 return FALSE;
252b5132
RH		 16153 }
16154
16155 if (relocs)
16156 {
00a97672
RS		 16157 if (htab->use_rel)
16158 {
16159 if (!add_dynamic_entry (DT_REL, 0)
16160 || !add_dynamic_entry (DT_RELSZ, 0)
16161 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16162 return FALSE;
16163 }
16164 else
16165 {
16166 if (!add_dynamic_entry (DT_RELA, 0)
16167 || !add_dynamic_entry (DT_RELASZ, 0)
16168 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16169 return FALSE;
16170 }
252b5132
RH		 16171 }
16172
08d1f311
DJ		 16173 /* If any dynamic relocs apply to a read-only section,
16174 then we need a DT_TEXTREL entry. */
16175 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16176 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16177 info);
08d1f311 16178
99e4ae17 16179 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16180 {
dc810e39 16181 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16182 return FALSE;
252b5132 16183 }
7a2b07ff
NS		 16184 if (htab->vxworks_p
16185 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16186 return FALSE;
252b5132 16187 }
8532796c 16188#undef add_dynamic_entry
252b5132 16189
b34976b6 16190 return TRUE;
252b5132
RH		 16191}
16192
0855e32b
NS		 16193/* Size sections even though they're not dynamic. We use it to setup
16194 _TLS_MODULE_BASE_, if needed. */
16195
16196static bfd_boolean
16197elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16198 struct bfd_link_info *info)
0855e32b
NS		 16199{
16200 asection *tls_sec;
16201
0e1862bb 16202 if (bfd_link_relocatable (info))
0855e32b
NS		 16203 return TRUE;
16204
16205 tls_sec = elf_hash_table (info)->tls_sec;
16206
16207 if (tls_sec)
16208 {
16209 struct elf_link_hash_entry *tlsbase;
16210
16211 tlsbase = elf_link_hash_lookup
16212 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16213
16214 if (tlsbase)
99059e56
RM		 16215 {
16216 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16217 const struct elf_backend_data *bed
99059e56 16218 = get_elf_backend_data (output_bfd);
0855e32b 16219
99059e56 16220 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16221 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16222 tls_sec, 0, NULL, FALSE,
16223 bed->collect, &bh)))
16224 return FALSE;
b38cadfb 16225
99059e56
RM		 16226 tlsbase->type = STT_TLS;
16227 tlsbase = (struct elf_link_hash_entry *)bh;
16228 tlsbase->def_regular = 1;
16229 tlsbase->other = STV_HIDDEN;
16230 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16231 }
16232 }
16233 return TRUE;
16234}
16235
252b5132
RH		 16236/* Finish up dynamic symbol handling. We set the contents of various
16237 dynamic sections here. */
16238
b34976b6 16239static bfd_boolean
906e58ca
NC		 16240elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16241 struct bfd_link_info * info,
16242 struct elf_link_hash_entry * h,
16243 Elf_Internal_Sym * sym)
252b5132 16244{
e5a52504 16245 struct elf32_arm_link_hash_table *htab;
b7693d02 16246 struct elf32_arm_link_hash_entry *eh;
252b5132 16247
e5a52504 16248 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16249 if (htab == NULL)
16250 return FALSE;
16251
b7693d02 16252 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16253
16254 if (h->plt.offset != (bfd_vma) -1)
16255 {
34e77a92 16256 if (!eh->is_iplt)
e5a52504 16257 {
34e77a92 16258 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16259 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16260 h->dynindx, 0))
16261 return FALSE;
e5a52504 16262 }
57e8b36a 16263
f5385ebf 16264 if (!h->def_regular)
252b5132
RH		 16265 {
16266 /* Mark the symbol as undefined, rather than as defined in
3a635617 16267 the .plt section. */
252b5132 16268 sym->st_shndx = SHN_UNDEF;
3a635617 16269 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16270 Otherwise, the PLT entry would provide a definition for
16271 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16272 and so the symbol would never be NULL. Leave the value if
16273 there were any relocations where pointer equality matters
16274 (this is a clue for the dynamic linker, to make function
16275 pointer comparisons work between an application and shared
16276 library). */
97323ad1 16277 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16278 sym->st_value = 0;
252b5132 16279 }
34e77a92
RS		 16280 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16281 {
16282 /* At least one non-call relocation references this .iplt entry,
16283 so the .iplt entry is the function's canonical address. */
16284 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16285 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16286 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16287 (output_bfd, htab->root.iplt->output_section));
16288 sym->st_value = (h->plt.offset
16289 + htab->root.iplt->output_section->vma
16290 + htab->root.iplt->output_offset);
16291 }
252b5132
RH		 16292 }
16293
f5385ebf 16294 if (h->needs_copy)
252b5132
RH		 16295 {
16296 asection * s;
947216bf 16297 Elf_Internal_Rela rel;
252b5132
RH		 16298
16299 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16300 BFD_ASSERT (h->dynindx != -1
16301 && (h->root.type == bfd_link_hash_defined
16302 || h->root.type == bfd_link_hash_defweak));
16303
9d19e4fd 16304 s = htab->root.srelbss;
252b5132
RH		 16305 BFD_ASSERT (s != NULL);
16306
00a97672 16307 rel.r_addend = 0;
252b5132
RH		 16308 rel.r_offset = (h->root.u.def.value
16309 + h->root.u.def.section->output_section->vma
16310 + h->root.u.def.section->output_offset);
16311 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16312 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16313 }
16314
00a97672
RS		 16315 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16316 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16317 to the ".got" section. */
9637f6ef 16318 if (h == htab->root.hdynamic
00a97672 16319 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16320 sym->st_shndx = SHN_ABS;
16321
b34976b6 16322 return TRUE;
252b5132
RH		 16323}
16324
0855e32b
NS		 16325static void
16326arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16327 void *contents,
16328 const unsigned long *template, unsigned count)
16329{
16330 unsigned ix;
b38cadfb 16331
0855e32b
NS		 16332 for (ix = 0; ix != count; ix++)
16333 {
16334 unsigned long insn = template[ix];
16335
16336 /* Emit mov pc,rx if bx is not permitted. */
16337 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16338 insn = (insn & 0xf000000f) | 0x01a0f000;
16339 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16340 }
16341}
16342
99059e56
RM		 16343/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16344 other variants, NaCl needs this entry in a static executable's
16345 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16346 zero. For .iplt really only the last bundle is useful, and .iplt
16347 could have a shorter first entry, with each individual PLT entry's
16348 relative branch calculated differently so it targets the last
16349 bundle instead of the instruction before it (labelled .Lplt_tail
16350 above). But it's simpler to keep the size and layout of PLT0
16351 consistent with the dynamic case, at the cost of some dead code at
16352 the start of .iplt and the one dead store to the stack at the start
16353 of .Lplt_tail. */
16354static void
16355arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16356 asection *plt, bfd_vma got_displacement)
16357{
16358 unsigned int i;
16359
16360 put_arm_insn (htab, output_bfd,
16361 elf32_arm_nacl_plt0_entry[0]
16362 | arm_movw_immediate (got_displacement),
16363 plt->contents + 0);
16364 put_arm_insn (htab, output_bfd,
16365 elf32_arm_nacl_plt0_entry[1]
16366 | arm_movt_immediate (got_displacement),
16367 plt->contents + 4);
16368
16369 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16370 put_arm_insn (htab, output_bfd,
16371 elf32_arm_nacl_plt0_entry[i],
16372 plt->contents + (i * 4));
16373}
16374
252b5132
RH		 16375/* Finish up the dynamic sections. */
16376
b34976b6 16377static bfd_boolean
57e8b36a 16378elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16379{
16380 bfd * dynobj;
16381 asection * sgot;
16382 asection * sdyn;
4dfe6ac6
NC		 16383 struct elf32_arm_link_hash_table *htab;
16384
16385 htab = elf32_arm_hash_table (info);
16386 if (htab == NULL)
16387 return FALSE;
252b5132
RH		 16388
16389 dynobj = elf_hash_table (info)->dynobj;
16390
362d30a1 16391 sgot = htab->root.sgotplt;
894891db
NC		 16392 /* A broken linker script might have discarded the dynamic sections.
16393 Catch this here so that we do not seg-fault later on. */
16394 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16395 return FALSE;
3d4d4302 16396 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16397
16398 if (elf_hash_table (info)->dynamic_sections_created)
16399 {
16400 asection *splt;
16401 Elf32_External_Dyn *dyncon, *dynconend;
16402
362d30a1 16403 splt = htab->root.splt;
24a1ba0f 16404 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16405 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16406
16407 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16408 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16409
252b5132
RH		 16410 for (; dyncon < dynconend; dyncon++)
16411 {
16412 Elf_Internal_Dyn dyn;
16413 const char * name;
16414 asection * s;
16415
16416 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16417
16418 switch (dyn.d_tag)
16419 {
229fcec5
MM		 16420 unsigned int type;
16421
252b5132 16422 default:
7a2b07ff
NS		 16423 if (htab->vxworks_p
16424 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16425 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16426 break;
16427
229fcec5
MM		 16428 case DT_HASH:
16429 name = ".hash";
16430 goto get_vma_if_bpabi;
16431 case DT_STRTAB:
16432 name = ".dynstr";
16433 goto get_vma_if_bpabi;
16434 case DT_SYMTAB:
16435 name = ".dynsym";
16436 goto get_vma_if_bpabi;
c0042f5d
MM		 16437 case DT_VERSYM:
16438 name = ".gnu.version";
16439 goto get_vma_if_bpabi;
16440 case DT_VERDEF:
16441 name = ".gnu.version_d";
16442 goto get_vma_if_bpabi;
16443 case DT_VERNEED:
16444 name = ".gnu.version_r";
16445 goto get_vma_if_bpabi;
16446
252b5132 16447 case DT_PLTGOT:
4ade44b7 16448 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16449 goto get_vma;
16450 case DT_JMPREL:
00a97672 16451 name = RELOC_SECTION (htab, ".plt");
252b5132 16452 get_vma:
4ade44b7 16453 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16454 if (s == NULL)
16455 {
4eca0228 16456 _bfd_error_handler
4ade44b7 16457 (_("could not find section %s"), name);
05456594
NC		 16458 bfd_set_error (bfd_error_invalid_operation);
16459 return FALSE;
16460 }
229fcec5 16461 if (!htab->symbian_p)
4ade44b7 16462 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16463 else
16464 /* In the BPABI, tags in the PT_DYNAMIC section point
16465 at the file offset, not the memory address, for the
16466 convenience of the post linker. */
4ade44b7 16467 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16468 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16469 break;
16470
229fcec5
MM		 16471 get_vma_if_bpabi:
16472 if (htab->symbian_p)
16473 goto get_vma;
16474 break;
16475
252b5132 16476 case DT_PLTRELSZ:
362d30a1 16477 s = htab->root.srelplt;
252b5132 16478 BFD_ASSERT (s != NULL);
eea6121a 16479 dyn.d_un.d_val = s->size;
252b5132
RH		 16480 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16481 break;
906e58ca 16482
252b5132 16483 case DT_RELSZ:
00a97672 16484 case DT_RELASZ:
229fcec5
MM		 16485 case DT_REL:
16486 case DT_RELA:
229fcec5
MM		 16487 /* In the BPABI, the DT_REL tag must point at the file
16488 offset, not the VMA, of the first relocation
16489 section. So, we use code similar to that in
16490 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16491 relocation section, since relocation sections are
16492 never allocated under the BPABI. PLT relocs are also
16493 included. */
229fcec5
MM		 16494 if (htab->symbian_p)
16495 {
16496 unsigned int i;
16497 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16498 ? SHT_REL : SHT_RELA);
16499 dyn.d_un.d_val = 0;
16500 for (i = 1; i < elf_numsections (output_bfd); i++)
16501 {
906e58ca 16502 Elf_Internal_Shdr *hdr
229fcec5
MM		 16503 = elf_elfsections (output_bfd)[i];
16504 if (hdr->sh_type == type)
16505 {
906e58ca 16506 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16507 || dyn.d_tag == DT_RELASZ)
16508 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16509 else if ((ufile_ptr) hdr->sh_offset
16510 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16511 dyn.d_un.d_val = hdr->sh_offset;
16512 }
16513 }
16514 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16515 }
252b5132 16516 break;
88f7bcd5 16517
0855e32b 16518 case DT_TLSDESC_PLT:
99059e56 16519 s = htab->root.splt;
0855e32b
NS		 16520 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16521 + htab->dt_tlsdesc_plt);
16522 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16523 break;
16524
16525 case DT_TLSDESC_GOT:
99059e56 16526 s = htab->root.sgot;
0855e32b 16527 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16528 + htab->dt_tlsdesc_got);
0855e32b
NS		 16529 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16530 break;
16531
88f7bcd5
NC		 16532 /* Set the bottom bit of DT_INIT/FINI if the
16533 corresponding function is Thumb. */
16534 case DT_INIT:
16535 name = info->init_function;
16536 goto get_sym;
16537 case DT_FINI:
16538 name = info->fini_function;
16539 get_sym:
16540 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16541 then there is nothing to adjust. */
88f7bcd5
NC		 16542 if (dyn.d_un.d_val != 0)
16543 {
16544 struct elf_link_hash_entry * eh;
16545
16546 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16547 FALSE, FALSE, TRUE);
39d911fc
TP		 16548 if (eh != NULL
16549 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16550 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16551 {
16552 dyn.d_un.d_val |= 1;
b34976b6 16553 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16554 }
16555 }
16556 break;
252b5132
RH		 16557 }
16558 }
16559
24a1ba0f 16560 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16561 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16562 {
00a97672
RS		 16563 const bfd_vma *plt0_entry;
16564 bfd_vma got_address, plt_address, got_displacement;
16565
16566 /* Calculate the addresses of the GOT and PLT. */
16567 got_address = sgot->output_section->vma + sgot->output_offset;
16568 plt_address = splt->output_section->vma + splt->output_offset;
16569
16570 if (htab->vxworks_p)
16571 {
16572 /* The VxWorks GOT is relocated by the dynamic linker.
16573 Therefore, we must emit relocations rather than simply
16574 computing the values now. */
16575 Elf_Internal_Rela rel;
16576
16577 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16578 put_arm_insn (htab, output_bfd, plt0_entry[0],
16579 splt->contents + 0);
16580 put_arm_insn (htab, output_bfd, plt0_entry[1],
16581 splt->contents + 4);
16582 put_arm_insn (htab, output_bfd, plt0_entry[2],
16583 splt->contents + 8);
00a97672
RS		 16584 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16585
8029a119 16586 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16587 rel.r_offset = plt_address + 12;
16588 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16589 rel.r_addend = 0;
16590 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16591 htab->srelplt2->contents);
16592 }
b38cadfb 16593 else if (htab->nacl_p)
99059e56
RM		 16594 arm_nacl_put_plt0 (htab, output_bfd, splt,
16595 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16596 else if (using_thumb_only (htab))
16597 {
16598 got_displacement = got_address - (plt_address + 12);
16599
16600 plt0_entry = elf32_thumb2_plt0_entry;
16601 put_arm_insn (htab, output_bfd, plt0_entry[0],
16602 splt->contents + 0);
16603 put_arm_insn (htab, output_bfd, plt0_entry[1],
16604 splt->contents + 4);
16605 put_arm_insn (htab, output_bfd, plt0_entry[2],
16606 splt->contents + 8);
16607
16608 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16609 }
00a97672
RS		 16610 else
16611 {
16612 got_displacement = got_address - (plt_address + 16);
16613
16614 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16615 put_arm_insn (htab, output_bfd, plt0_entry[0],
16616 splt->contents + 0);
16617 put_arm_insn (htab, output_bfd, plt0_entry[1],
16618 splt->contents + 4);
16619 put_arm_insn (htab, output_bfd, plt0_entry[2],
16620 splt->contents + 8);
16621 put_arm_insn (htab, output_bfd, plt0_entry[3],
16622 splt->contents + 12);
5e681ec4 16623
5e681ec4 16624#ifdef FOUR_WORD_PLT
00a97672
RS		 16625 /* The displacement value goes in the otherwise-unused
16626 last word of the second entry. */
16627 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16628#else
00a97672 16629 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16630#endif
00a97672 16631 }
f7a74f8c 16632 }
252b5132
RH		 16633
16634 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16635 really seem like the right value. */
74541ad4
AM		 16636 if (splt->output_section->owner == output_bfd)
16637 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16638
0855e32b
NS		 16639 if (htab->dt_tlsdesc_plt)
16640 {
16641 bfd_vma got_address
16642 = sgot->output_section->vma + sgot->output_offset;
16643 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16644 + htab->root.sgot->output_offset);
16645 bfd_vma plt_address
16646 = splt->output_section->vma + splt->output_offset;
16647
b38cadfb 16648 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16649 splt->contents + htab->dt_tlsdesc_plt,
16650 dl_tlsdesc_lazy_trampoline, 6);
16651
16652 bfd_put_32 (output_bfd,
16653 gotplt_address + htab->dt_tlsdesc_got
16654 - (plt_address + htab->dt_tlsdesc_plt)
16655 - dl_tlsdesc_lazy_trampoline[6],
16656 splt->contents + htab->dt_tlsdesc_plt + 24);
16657 bfd_put_32 (output_bfd,
16658 got_address - (plt_address + htab->dt_tlsdesc_plt)
16659 - dl_tlsdesc_lazy_trampoline[7],
16660 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16661 }
16662
16663 if (htab->tls_trampoline)
16664 {
b38cadfb 16665 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16666 splt->contents + htab->tls_trampoline,
16667 tls_trampoline, 3);
16668#ifdef FOUR_WORD_PLT
16669 bfd_put_32 (output_bfd, 0x00000000,
16670 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16671#endif
0855e32b
NS		 16672 }
16673
0e1862bb
L		 16674 if (htab->vxworks_p
16675 && !bfd_link_pic (info)
16676 && htab->root.splt->size > 0)
00a97672
RS		 16677 {
16678 /* Correct the .rel(a).plt.unloaded relocations. They will have
16679 incorrect symbol indexes. */
16680 int num_plts;
eed62c48 16681 unsigned char *p;
00a97672 16682
362d30a1 16683 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16684 / htab->plt_entry_size);
16685 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16686
16687 for (; num_plts; num_plts--)
16688 {
16689 Elf_Internal_Rela rel;
16690
16691 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16692 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16693 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16694 p += RELOC_SIZE (htab);
16695
16696 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16697 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16698 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16699 p += RELOC_SIZE (htab);
16700 }
16701 }
252b5132
RH		 16702 }
16703
99059e56
RM		 16704 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16705 /* NaCl uses a special first entry in .iplt too. */
16706 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16707
252b5132 16708 /* Fill in the first three entries in the global offset table. */
229fcec5 16709 if (sgot)
252b5132 16710 {
229fcec5
MM		 16711 if (sgot->size > 0)
16712 {
16713 if (sdyn == NULL)
16714 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16715 else
16716 bfd_put_32 (output_bfd,
16717 sdyn->output_section->vma + sdyn->output_offset,
16718 sgot->contents);
16719 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16720 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16721 }
252b5132 16722
229fcec5
MM		 16723 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16724 }
252b5132 16725
b34976b6 16726 return TRUE;
252b5132
RH		 16727}
16728
ba96a88f 16729static void
57e8b36a 16730elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16731{
9b485d32 16732 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16733 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16734 struct elf_segment_map *m;
ba96a88f
NC		 16735
16736 i_ehdrp = elf_elfheader (abfd);
16737
94a3258f
PB		 16738 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16739 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16740 else
7394f108 16741 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16742 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16743
93204d3a
PB		 16744 if (link_info)
16745 {
16746 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16747 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16748 i_ehdrp->e_flags |= EF_ARM_BE8;
16749 }
3bfcb652
NC		 16750
16751 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16752 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16753 {
16754 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16755 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16756 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16757 else
16758 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16759 }
ac4c9b04
MG		 16760
16761 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16762 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16763 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16764 {
16765 unsigned int j;
16766
16767 if (m->count == 0)
16768 continue;
16769 for (j = 0; j < m->count; j++)
16770 {
f0728ee3 16771 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16772 break;
16773 }
16774 if (j == m->count)
16775 {
16776 m->p_flags = PF_X;
16777 m->p_flags_valid = 1;
16778 }
16779 }
ba96a88f
NC		 16780}
16781
99e4ae17 16782static enum elf_reloc_type_class
7e612e98
AM		 16783elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16784 const asection *rel_sec ATTRIBUTE_UNUSED,
16785 const Elf_Internal_Rela *rela)
99e4ae17 16786{
f51e552e 16787 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16788 {
16789 case R_ARM_RELATIVE:
16790 return reloc_class_relative;
16791 case R_ARM_JUMP_SLOT:
16792 return reloc_class_plt;
16793 case R_ARM_COPY:
16794 return reloc_class_copy;
109575d7
JW		 16795 case R_ARM_IRELATIVE:
16796 return reloc_class_ifunc;
99e4ae17
AJ		 16797 default:
16798 return reloc_class_normal;
16799 }
16800}
16801
e489d0ae 16802static void
57e8b36a 16803elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16804{
5a6c6817 16805 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16806}
16807
40a18ebd
NC		 16808/* Return TRUE if this is an unwinding table entry. */
16809
16810static bfd_boolean
16811is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16812{
0112cd26
NC		 16813 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16814 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16815}
16816
16817
16818/* Set the type and flags for an ARM section. We do this by
16819 the section name, which is a hack, but ought to work. */
16820
16821static bfd_boolean
16822elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16823{
16824 const char * name;
16825
16826 name = bfd_get_section_name (abfd, sec);
16827
16828 if (is_arm_elf_unwind_section_name (abfd, name))
16829 {
16830 hdr->sh_type = SHT_ARM_EXIDX;
16831 hdr->sh_flags |= SHF_LINK_ORDER;
16832 }
ac4c9b04 16833
f0728ee3
AV		 16834 if (sec->flags & SEC_ELF_PURECODE)
16835 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16836
40a18ebd
NC		 16837 return TRUE;
16838}
16839
6dc132d9
L		 16840/* Handle an ARM specific section when reading an object file. This is
16841 called when bfd_section_from_shdr finds a section with an unknown
16842 type. */
40a18ebd
NC		 16843
16844static bfd_boolean
16845elf32_arm_section_from_shdr (bfd *abfd,
16846 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16847 const char *name,
16848 int shindex)
40a18ebd
NC		 16849{
16850 /* There ought to be a place to keep ELF backend specific flags, but
16851 at the moment there isn't one. We just keep track of the
16852 sections by their name, instead. Fortunately, the ABI gives
16853 names for all the ARM specific sections, so we will probably get
16854 away with this. */
16855 switch (hdr->sh_type)
16856 {
16857 case SHT_ARM_EXIDX:
0951f019
RE		 16858 case SHT_ARM_PREEMPTMAP:
16859 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16860 break;
16861
16862 default:
16863 return FALSE;
16864 }
16865
6dc132d9 16866 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16867 return FALSE;
16868
16869 return TRUE;
16870}
e489d0ae 16871
44444f50
NC		 16872static _arm_elf_section_data *
16873get_arm_elf_section_data (asection * sec)
16874{
47b2e99c
JZ		 16875 if (sec && sec->owner && is_arm_elf (sec->owner))
16876 return elf32_arm_section_data (sec);
44444f50
NC		 16877 else
16878 return NULL;
8e3de13a
NC		 16879}
16880
4e617b1e
PB		 16881typedef struct
16882{
57402f1e 16883 void *flaginfo;
4e617b1e 16884 struct bfd_link_info *info;
91a5743d
PB		 16885 asection *sec;
16886 int sec_shndx;
6e0b88f1
AM		 16887 int (*func) (void *, const char *, Elf_Internal_Sym *,
16888 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16889} output_arch_syminfo;
16890
16891enum map_symbol_type
16892{
16893 ARM_MAP_ARM,
16894 ARM_MAP_THUMB,
16895 ARM_MAP_DATA
16896};
16897
16898
7413f23f 16899/* Output a single mapping symbol. */
4e617b1e
PB		 16900
16901static bfd_boolean
7413f23f
DJ		 16902elf32_arm_output_map_sym (output_arch_syminfo *osi,
16903 enum map_symbol_type type,
16904 bfd_vma offset)
4e617b1e
PB		 16905{
16906 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16907 Elf_Internal_Sym sym;
16908
91a5743d
PB		 16909 sym.st_value = osi->sec->output_section->vma
16910 + osi->sec->output_offset
16911 + offset;
4e617b1e
PB		 16912 sym.st_size = 0;
16913 sym.st_other = 0;
16914 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16915 sym.st_shndx = osi->sec_shndx;
35fc36a8 16916 sym.st_target_internal = 0;
fe33d2fa 16917 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16918 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16919}
16920
34e77a92
RS		 16921/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16922 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16923
16924static bfd_boolean
34e77a92
RS		 16925elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16926 bfd_boolean is_iplt_entry_p,
16927 union gotplt_union *root_plt,
16928 struct arm_plt_info *arm_plt)
4e617b1e 16929{
4e617b1e 16930 struct elf32_arm_link_hash_table *htab;
34e77a92 16931 bfd_vma addr, plt_header_size;
4e617b1e 16932
34e77a92 16933 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16934 return TRUE;
16935
4dfe6ac6
NC		 16936 htab = elf32_arm_hash_table (osi->info);
16937 if (htab == NULL)
16938 return FALSE;
16939
34e77a92
RS		 16940 if (is_iplt_entry_p)
16941 {
16942 osi->sec = htab->root.iplt;
16943 plt_header_size = 0;
16944 }
16945 else
16946 {
16947 osi->sec = htab->root.splt;
16948 plt_header_size = htab->plt_header_size;
16949 }
16950 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16951 (osi->info->output_bfd, osi->sec->output_section));
16952
16953 addr = root_plt->offset & -2;
4e617b1e
PB		 16954 if (htab->symbian_p)
16955 {
7413f23f 16956 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16957 return FALSE;
7413f23f 16958 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16959 return FALSE;
16960 }
16961 else if (htab->vxworks_p)
16962 {
7413f23f 16963 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16964 return FALSE;
7413f23f 16965 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16966 return FALSE;
7413f23f 16967 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16968 return FALSE;
7413f23f 16969 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16970 return FALSE;
16971 }
b38cadfb
NC		 16972 else if (htab->nacl_p)
16973 {
16974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16975 return FALSE;
16976 }
eed94f8f
NC		 16977 else if (using_thumb_only (htab))
16978 {
16979 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16980 return FALSE;
6a631e86 16981 }
4e617b1e
PB		 16982 else
16983 {
34e77a92 16984 bfd_boolean thumb_stub_p;
bd97cb95 16985
34e77a92
RS		 16986 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16987 if (thumb_stub_p)
4e617b1e 16988 {
7413f23f 16989 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16990 return FALSE;
16991 }
16992#ifdef FOUR_WORD_PLT
7413f23f 16993 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16994 return FALSE;
7413f23f 16995 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16996 return FALSE;
16997#else
906e58ca 16998 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16999 so only need to output a mapping symbol for the first PLT entry and
17000 entries with thumb thunks. */
34e77a92 17001 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17002 {
7413f23f 17003 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17004 return FALSE;
17005 }
17006#endif
17007 }
17008
17009 return TRUE;
17010}
17011
34e77a92
RS		 17012/* Output mapping symbols for PLT entries associated with H. */
17013
17014static bfd_boolean
17015elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17016{
17017 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17018 struct elf32_arm_link_hash_entry *eh;
17019
17020 if (h->root.type == bfd_link_hash_indirect)
17021 return TRUE;
17022
17023 if (h->root.type == bfd_link_hash_warning)
17024 /* When warning symbols are created, they **replace** the "real"
17025 entry in the hash table, thus we never get to see the real
17026 symbol in a hash traversal. So look at it now. */
17027 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17028
17029 eh = (struct elf32_arm_link_hash_entry *) h;
17030 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17031 &h->plt, &eh->plt);
17032}
17033
4f4faa4d
TP		 17034/* Bind a veneered symbol to its veneer identified by its hash entry
17035 STUB_ENTRY. The veneered location thus loose its symbol. */
17036
17037static void
17038arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17039{
17040 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17041
17042 BFD_ASSERT (hash);
17043 hash->root.root.u.def.section = stub_entry->stub_sec;
17044 hash->root.root.u.def.value = stub_entry->stub_offset;
17045 hash->root.size = stub_entry->stub_size;
17046}
17047
7413f23f
DJ		 17048/* Output a single local symbol for a generated stub. */
17049
17050static bfd_boolean
17051elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17052 bfd_vma offset, bfd_vma size)
17053{
7413f23f
DJ		 17054 Elf_Internal_Sym sym;
17055
7413f23f
DJ		 17056 sym.st_value = osi->sec->output_section->vma
17057 + osi->sec->output_offset
17058 + offset;
17059 sym.st_size = size;
17060 sym.st_other = 0;
17061 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17062 sym.st_shndx = osi->sec_shndx;
35fc36a8 17063 sym.st_target_internal = 0;
57402f1e 17064 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17065}
4e617b1e 17066
da5938a2 17067static bfd_boolean
8029a119
NC		 17068arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17069 void * in_arg)
da5938a2
NC		 17070{
17071 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17072 asection *stub_sec;
17073 bfd_vma addr;
7413f23f 17074 char *stub_name;
9a008db3 17075 output_arch_syminfo *osi;
d3ce72d0 17076 const insn_sequence *template_sequence;
461a49ca
DJ		 17077 enum stub_insn_type prev_type;
17078 int size;
17079 int i;
17080 enum map_symbol_type sym_type;
da5938a2
NC		 17081
17082 /* Massage our args to the form they really have. */
17083 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17084 osi = (output_arch_syminfo *) in_arg;
da5938a2 17085
da5938a2
NC		 17086 stub_sec = stub_entry->stub_sec;
17087
17088 /* Ensure this stub is attached to the current section being
7413f23f 17089 processed. */
da5938a2
NC		 17090 if (stub_sec != osi->sec)
17091 return TRUE;
17092
7413f23f 17093 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17094 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17095
17096 if (arm_stub_sym_claimed (stub_entry->stub_type))
17097 arm_stub_claim_sym (stub_entry);
17098 else
7413f23f 17099 {
4f4faa4d
TP		 17100 stub_name = stub_entry->output_name;
17101 switch (template_sequence[0].type)
17102 {
17103 case ARM_TYPE:
17104 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17105 stub_entry->stub_size))
17106 return FALSE;
17107 break;
17108 case THUMB16_TYPE:
17109 case THUMB32_TYPE:
17110 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17111 stub_entry->stub_size))
17112 return FALSE;
17113 break;
17114 default:
17115 BFD_FAIL ();
17116 return 0;
17117 }
7413f23f 17118 }
da5938a2 17119
461a49ca
DJ		 17120 prev_type = DATA_TYPE;
17121 size = 0;
17122 for (i = 0; i < stub_entry->stub_template_size; i++)
17123 {
d3ce72d0 17124 switch (template_sequence[i].type)
461a49ca
DJ		 17125 {
17126 case ARM_TYPE:
17127 sym_type = ARM_MAP_ARM;
17128 break;
17129
17130 case THUMB16_TYPE:
48229727 17131 case THUMB32_TYPE:
461a49ca
DJ		 17132 sym_type = ARM_MAP_THUMB;
17133 break;
17134
17135 case DATA_TYPE:
17136 sym_type = ARM_MAP_DATA;
17137 break;
17138
17139 default:
17140 BFD_FAIL ();
4e31c731 17141 return FALSE;
461a49ca
DJ		 17142 }
17143
d3ce72d0 17144 if (template_sequence[i].type != prev_type)
461a49ca 17145 {
d3ce72d0 17146 prev_type = template_sequence[i].type;
461a49ca
DJ		 17147 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17148 return FALSE;
17149 }
17150
d3ce72d0 17151 switch (template_sequence[i].type)
461a49ca
DJ		 17152 {
17153 case ARM_TYPE:
48229727 17154 case THUMB32_TYPE:
461a49ca
DJ		 17155 size += 4;
17156 break;
17157
17158 case THUMB16_TYPE:
17159 size += 2;
17160 break;
17161
17162 case DATA_TYPE:
17163 size += 4;
17164 break;
17165
17166 default:
17167 BFD_FAIL ();
4e31c731 17168 return FALSE;
461a49ca
DJ		 17169 }
17170 }
17171
da5938a2
NC		 17172 return TRUE;
17173}
17174
33811162
DG		 17175/* Output mapping symbols for linker generated sections,
17176 and for those data-only sections that do not have a
17177 $d. */
4e617b1e
PB		 17178
17179static bfd_boolean
17180elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17181 struct bfd_link_info *info,
57402f1e 17182 void *flaginfo,
6e0b88f1
AM		 17183 int (*func) (void *, const char *,
17184 Elf_Internal_Sym *,
17185 asection *,
17186 struct elf_link_hash_entry *))
4e617b1e
PB		 17187{
17188 output_arch_syminfo osi;
17189 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17190 bfd_vma offset;
17191 bfd_size_type size;
33811162 17192 bfd *input_bfd;
4e617b1e
PB		 17193
17194 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17195 if (htab == NULL)
17196 return FALSE;
17197
906e58ca 17198 check_use_blx (htab);
91a5743d 17199
57402f1e 17200 osi.flaginfo = flaginfo;
4e617b1e
PB		 17201 osi.info = info;
17202 osi.func = func;
906e58ca 17203
33811162
DG		 17204 /* Add a $d mapping symbol to data-only sections that
17205 don't have any mapping symbol. This may result in (harmless) redundant
17206 mapping symbols. */
17207 for (input_bfd = info->input_bfds;
17208 input_bfd != NULL;
c72f2fb2 17209 input_bfd = input_bfd->link.next)
33811162
DG		 17210 {
17211 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17212 for (osi.sec = input_bfd->sections;
17213 osi.sec != NULL;
17214 osi.sec = osi.sec->next)
17215 {
17216 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17217 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17218 != 0)
33811162
DG		 17219 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17220 == SEC_HAS_CONTENTS
17221 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17222 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17223 && osi.sec->size > 0
17224 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17225 {
17226 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17227 (output_bfd, osi.sec->output_section);
17228 if (osi.sec_shndx != (int)SHN_BAD)
17229 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17230 }
17231 }
17232 }
17233
91a5743d
PB		 17234 /* ARM->Thumb glue. */
17235 if (htab->arm_glue_size > 0)
17236 {
3d4d4302
AM		 17237 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17238 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17239
17240 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17241 (output_bfd, osi.sec->output_section);
0e1862bb 17242 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17243 || htab->pic_veneer)
17244 size = ARM2THUMB_PIC_GLUE_SIZE;
17245 else if (htab->use_blx)
17246 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17247 else
17248 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17249
91a5743d
PB		 17250 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17251 {
7413f23f
DJ		 17252 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17253 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17254 }
17255 }
17256
17257 /* Thumb->ARM glue. */
17258 if (htab->thumb_glue_size > 0)
17259 {
3d4d4302
AM		 17260 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17261 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17262
17263 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17264 (output_bfd, osi.sec->output_section);
17265 size = THUMB2ARM_GLUE_SIZE;
17266
17267 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17268 {
7413f23f
DJ		 17269 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17270 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17271 }
17272 }
17273
845b51d6
PB		 17274 /* ARMv4 BX veneers. */
17275 if (htab->bx_glue_size > 0)
17276 {
3d4d4302
AM		 17277 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17278 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17279
17280 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17281 (output_bfd, osi.sec->output_section);
17282
7413f23f 17283 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17284 }
17285
8029a119
NC		 17286 /* Long calls stubs. */
17287 if (htab->stub_bfd && htab->stub_bfd->sections)
17288 {
da5938a2 17289 asection* stub_sec;
8029a119 17290
da5938a2
NC		 17291 for (stub_sec = htab->stub_bfd->sections;
17292 stub_sec != NULL;
8029a119
NC		 17293 stub_sec = stub_sec->next)
17294 {
17295 /* Ignore non-stub sections. */
17296 if (!strstr (stub_sec->name, STUB_SUFFIX))
17297 continue;
da5938a2 17298
8029a119 17299 osi.sec = stub_sec;
da5938a2 17300
8029a119
NC		 17301 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17302 (output_bfd, osi.sec->output_section);
da5938a2 17303
8029a119
NC		 17304 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17305 }
17306 }
da5938a2 17307
91a5743d 17308 /* Finally, output mapping symbols for the PLT. */
34e77a92 17309 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17310 {
34e77a92
RS		 17311 osi.sec = htab->root.splt;
17312 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17313 (output_bfd, osi.sec->output_section));
17314
17315 /* Output mapping symbols for the plt header. SymbianOS does not have a
17316 plt header. */
17317 if (htab->vxworks_p)
17318 {
17319 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17320 if (!bfd_link_pic (info))
34e77a92
RS		 17321 {
17322 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17323 return FALSE;
17324 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17325 return FALSE;
17326 }
17327 }
b38cadfb
NC		 17328 else if (htab->nacl_p)
17329 {
17330 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17331 return FALSE;
17332 }
eed94f8f
NC		 17333 else if (using_thumb_only (htab))
17334 {
17335 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17336 return FALSE;
17337 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17338 return FALSE;
17339 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17340 return FALSE;
17341 }
34e77a92 17342 else if (!htab->symbian_p)
4e617b1e 17343 {
7413f23f 17344 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17345 return FALSE;
34e77a92
RS		 17346#ifndef FOUR_WORD_PLT
17347 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17348 return FALSE;
34e77a92 17349#endif
4e617b1e
PB		 17350 }
17351 }
99059e56
RM		 17352 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17353 {
17354 /* NaCl uses a special first entry in .iplt too. */
17355 osi.sec = htab->root.iplt;
17356 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17357 (output_bfd, osi.sec->output_section));
17358 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17359 return FALSE;
17360 }
34e77a92
RS		 17361 if ((htab->root.splt && htab->root.splt->size > 0)
17362 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17363 {
34e77a92
RS		 17364 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17365 for (input_bfd = info->input_bfds;
17366 input_bfd != NULL;
c72f2fb2 17367 input_bfd = input_bfd->link.next)
34e77a92
RS		 17368 {
17369 struct arm_local_iplt_info **local_iplt;
17370 unsigned int i, num_syms;
4e617b1e 17371
34e77a92
RS		 17372 local_iplt = elf32_arm_local_iplt (input_bfd);
17373 if (local_iplt != NULL)
17374 {
17375 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17376 for (i = 0; i < num_syms; i++)
17377 if (local_iplt[i] != NULL
17378 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17379 &local_iplt[i]->root,
17380 &local_iplt[i]->arm))
17381 return FALSE;
17382 }
17383 }
17384 }
0855e32b
NS		 17385 if (htab->dt_tlsdesc_plt != 0)
17386 {
17387 /* Mapping symbols for the lazy tls trampoline. */
17388 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17389 return FALSE;
b38cadfb 17390
0855e32b
NS		 17391 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17392 htab->dt_tlsdesc_plt + 24))
17393 return FALSE;
17394 }
17395 if (htab->tls_trampoline != 0)
17396 {
17397 /* Mapping symbols for the tls trampoline. */
17398 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17399 return FALSE;
17400#ifdef FOUR_WORD_PLT
17401 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17402 htab->tls_trampoline + 12))
17403 return FALSE;
b38cadfb 17404#endif
0855e32b 17405 }
b38cadfb 17406
4e617b1e
PB		 17407 return TRUE;
17408}
17409
54ddd295
TP		 17410/* Filter normal symbols of CMSE entry functions of ABFD to include in
17411 the import library. All SYMCOUNT symbols of ABFD can be examined
17412 from their pointers in SYMS. Pointers of symbols to keep should be
17413 stored continuously at the beginning of that array.
17414
17415 Returns the number of symbols to keep. */
17416
17417static unsigned int
17418elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17419 struct bfd_link_info *info,
17420 asymbol **syms, long symcount)
17421{
17422 size_t maxnamelen;
17423 char *cmse_name;
17424 long src_count, dst_count = 0;
17425 struct elf32_arm_link_hash_table *htab;
17426
17427 htab = elf32_arm_hash_table (info);
17428 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17429 symcount = 0;
17430
17431 maxnamelen = 128;
17432 cmse_name = (char *) bfd_malloc (maxnamelen);
17433 for (src_count = 0; src_count < symcount; src_count++)
17434 {
17435 struct elf32_arm_link_hash_entry *cmse_hash;
17436 asymbol *sym;
17437 flagword flags;
17438 char *name;
17439 size_t namelen;
17440
17441 sym = syms[src_count];
17442 flags = sym->flags;
17443 name = (char *) bfd_asymbol_name (sym);
17444
17445 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17446 continue;
17447 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17448 continue;
17449
17450 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17451 if (namelen > maxnamelen)
17452 {
17453 cmse_name = (char *)
17454 bfd_realloc (cmse_name, namelen);
17455 maxnamelen = namelen;
17456 }
17457 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17458 cmse_hash = (struct elf32_arm_link_hash_entry *)
17459 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17460
17461 if (!cmse_hash
17462 || (cmse_hash->root.root.type != bfd_link_hash_defined
17463 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17464 || cmse_hash->root.type != STT_FUNC)
17465 continue;
17466
17467 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17468 continue;
17469
17470 syms[dst_count++] = sym;
17471 }
17472 free (cmse_name);
17473
17474 syms[dst_count] = NULL;
17475
17476 return dst_count;
17477}
17478
17479/* Filter symbols of ABFD to include in the import library. All
17480 SYMCOUNT symbols of ABFD can be examined from their pointers in
17481 SYMS. Pointers of symbols to keep should be stored continuously at
17482 the beginning of that array.
17483
17484 Returns the number of symbols to keep. */
17485
17486static unsigned int
17487elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17488 struct bfd_link_info *info,
17489 asymbol **syms, long symcount)
17490{
17491 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17492
17493 if (globals->cmse_implib)
17494 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17495 else
17496 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17497}
17498
e489d0ae
PB		 17499/* Allocate target specific section data. */
17500
17501static bfd_boolean
17502elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17503{
f592407e
AM		 17504 if (!sec->used_by_bfd)
17505 {
17506 _arm_elf_section_data *sdata;
17507 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17508
21d799b5 17509 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17510 if (sdata == NULL)
17511 return FALSE;
17512 sec->used_by_bfd = sdata;
17513 }
e489d0ae
PB		 17514
17515 return _bfd_elf_new_section_hook (abfd, sec);
17516}
17517
17518
17519/* Used to order a list of mapping symbols by address. */
17520
17521static int
17522elf32_arm_compare_mapping (const void * a, const void * b)
17523{
7f6a71ff
JM		 17524 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17525 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17526
17527 if (amap->vma > bmap->vma)
17528 return 1;
17529 else if (amap->vma < bmap->vma)
17530 return -1;
17531 else if (amap->type > bmap->type)
17532 /* Ensure results do not depend on the host qsort for objects with
17533 multiple mapping symbols at the same address by sorting on type
17534 after vma. */
17535 return 1;
17536 else if (amap->type < bmap->type)
17537 return -1;
17538 else
17539 return 0;
e489d0ae
PB		 17540}
17541
2468f9c9
PB		 17542/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17543
17544static unsigned long
17545offset_prel31 (unsigned long addr, bfd_vma offset)
17546{
17547 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17548}
17549
17550/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17551 relocations. */
17552
17553static void
17554copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17555{
17556 unsigned long first_word = bfd_get_32 (output_bfd, from);
17557 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17558
2468f9c9
PB		 17559 /* High bit of first word is supposed to be zero. */
17560 if ((first_word & 0x80000000ul) == 0)
17561 first_word = offset_prel31 (first_word, offset);
b38cadfb 17562
2468f9c9
PB		 17563 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17564 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17565 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17566 second_word = offset_prel31 (second_word, offset);
b38cadfb 17567
2468f9c9
PB		 17568 bfd_put_32 (output_bfd, first_word, to);
17569 bfd_put_32 (output_bfd, second_word, to + 4);
17570}
e489d0ae 17571
48229727
JB		 17572/* Data for make_branch_to_a8_stub(). */
17573
b38cadfb
NC		 17574struct a8_branch_to_stub_data
17575{
48229727
JB		 17576 asection *writing_section;
17577 bfd_byte *contents;
17578};
17579
17580
17581/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17582 places for a particular section. */
17583
17584static bfd_boolean
17585make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17586 void *in_arg)
48229727
JB		 17587{
17588 struct elf32_arm_stub_hash_entry *stub_entry;
17589 struct a8_branch_to_stub_data *data;
17590 bfd_byte *contents;
17591 unsigned long branch_insn;
17592 bfd_vma veneered_insn_loc, veneer_entry_loc;
17593 bfd_signed_vma branch_offset;
17594 bfd *abfd;
8d9d9490 17595 unsigned int loc;
48229727
JB		 17596
17597 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17598 data = (struct a8_branch_to_stub_data *) in_arg;
17599
17600 if (stub_entry->target_section != data->writing_section
4563a860 17601 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17602 return TRUE;
17603
17604 contents = data->contents;
17605
8d9d9490
TP		 17606 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17607 generated when both source and target are in the same section. */
48229727
JB		 17608 veneered_insn_loc = stub_entry->target_section->output_section->vma
17609 + stub_entry->target_section->output_offset
8d9d9490 17610 + stub_entry->source_value;
48229727
JB		 17611
17612 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17613 + stub_entry->stub_sec->output_offset
17614 + stub_entry->stub_offset;
17615
17616 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17617 veneered_insn_loc &= ~3u;
17618
17619 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17620
17621 abfd = stub_entry->target_section->owner;
8d9d9490 17622 loc = stub_entry->source_value;
48229727
JB		 17623
17624 /* We attempt to avoid this condition by setting stubs_always_after_branch
17625 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17626 This check is just to be on the safe side... */
17627 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17628 {
4eca0228
AM		 17629 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17630 "allocated in unsafe location"), abfd);
48229727
JB		 17631 return FALSE;
17632 }
17633
17634 switch (stub_entry->stub_type)
17635 {
17636 case arm_stub_a8_veneer_b:
17637 case arm_stub_a8_veneer_b_cond:
17638 branch_insn = 0xf0009000;
17639 goto jump24;
17640
17641 case arm_stub_a8_veneer_blx:
17642 branch_insn = 0xf000e800;
17643 goto jump24;
17644
17645 case arm_stub_a8_veneer_bl:
17646 {
17647 unsigned int i1, j1, i2, j2, s;
17648
17649 branch_insn = 0xf000d000;
17650
17651 jump24:
17652 if (branch_offset < -16777216 || branch_offset > 16777214)
17653 {
17654 /* There's not much we can do apart from complain if this
17655 happens. */
4eca0228
AM		 17656 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17657 "of range (input file too large)"), abfd);
48229727
JB		 17658 return FALSE;
17659 }
17660
17661 /* i1 = not(j1 eor s), so:
17662 not i1 = j1 eor s
17663 j1 = (not i1) eor s. */
17664
17665 branch_insn |= (branch_offset >> 1) & 0x7ff;
17666 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17667 i2 = (branch_offset >> 22) & 1;
17668 i1 = (branch_offset >> 23) & 1;
17669 s = (branch_offset >> 24) & 1;
17670 j1 = (!i1) ^ s;
17671 j2 = (!i2) ^ s;
17672 branch_insn |= j2 << 11;
17673 branch_insn |= j1 << 13;
17674 branch_insn |= s << 26;
17675 }
17676 break;
17677
17678 default:
17679 BFD_FAIL ();
17680 return FALSE;
17681 }
17682
8d9d9490
TP		 17683 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17684 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17685
17686 return TRUE;
17687}
17688
a504d23a
LA		 17689/* Beginning of stm32l4xx work-around. */
17690
17691/* Functions encoding instructions necessary for the emission of the
17692 fix-stm32l4xx-629360.
17693 Encoding is extracted from the
17694 ARM (C) Architecture Reference Manual
17695 ARMv7-A and ARMv7-R edition
17696 ARM DDI 0406C.b (ID072512). */
17697
17698static inline bfd_vma
82188b29 17699create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17700{
17701 /* A8.8.18 B (A8-334)
17702 B target_address (Encoding T4). */
17703 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17704 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17705 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17706
a504d23a
LA		 17707 int s = ((branch_offset & 0x1000000) >> 24);
17708 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17709 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17710
17711 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17712 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17713
17714 bfd_vma patched_inst = 0xf0009000
17715 | s << 26 /* S. */
17716 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17717 | j1 << 13 /* J1. */
17718 | j2 << 11 /* J2. */
17719 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17720
17721 return patched_inst;
17722}
17723
17724static inline bfd_vma
17725create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17726{
17727 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17728 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17729 bfd_vma patched_inst = 0xe8900000
17730 | (/*W=*/wback << 21)
17731 | (base_reg << 16)
17732 | (reg_mask & 0x0000ffff);
17733
17734 return patched_inst;
17735}
17736
17737static inline bfd_vma
17738create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17739{
17740 /* A8.8.60 LDMDB/LDMEA (A8-402)
17741 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17742 bfd_vma patched_inst = 0xe9100000
17743 | (/*W=*/wback << 21)
17744 | (base_reg << 16)
17745 | (reg_mask & 0x0000ffff);
17746
17747 return patched_inst;
17748}
17749
17750static inline bfd_vma
17751create_instruction_mov (int target_reg, int source_reg)
17752{
17753 /* A8.8.103 MOV (register) (A8-486)
17754 MOV Rd, Rm (Encoding T1). */
17755 bfd_vma patched_inst = 0x4600
17756 | (target_reg & 0x7)
17757 | ((target_reg & 0x8) >> 3) << 7
17758 | (source_reg << 3);
17759
17760 return patched_inst;
17761}
17762
17763static inline bfd_vma
17764create_instruction_sub (int target_reg, int source_reg, int value)
17765{
17766 /* A8.8.221 SUB (immediate) (A8-708)
17767 SUB Rd, Rn, #value (Encoding T3). */
17768 bfd_vma patched_inst = 0xf1a00000
17769 | (target_reg << 8)
17770 | (source_reg << 16)
17771 | (/*S=*/0 << 20)
17772 | ((value & 0x800) >> 11) << 26
17773 | ((value & 0x700) >> 8) << 12
17774 | (value & 0x0ff);
17775
17776 return patched_inst;
17777}
17778
17779static inline bfd_vma
9239bbd3 17780create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17781 int first_reg)
17782{
17783 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17784 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17785 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17786 | (/*W=*/wback << 21)
17787 | (base_reg << 16)
9239bbd3
CM		 17788 | (num_words & 0x000000ff)
17789 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17790 | (first_reg & 0x00000001) << 22;
17791
17792 return patched_inst;
17793}
17794
17795static inline bfd_vma
9239bbd3
CM		 17796create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17797 int first_reg)
a504d23a
LA		 17798{
17799 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17800 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17801 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17802 | (base_reg << 16)
9239bbd3
CM		 17803 | (num_words & 0x000000ff)
17804 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17805 | (first_reg & 0x00000001) << 22;
17806
17807 return patched_inst;
17808}
17809
17810static inline bfd_vma
17811create_instruction_udf_w (int value)
17812{
17813 /* A8.8.247 UDF (A8-758)
17814 Undefined (Encoding T2). */
17815 bfd_vma patched_inst = 0xf7f0a000
17816 | (value & 0x00000fff)
17817 | (value & 0x000f0000) << 16;
17818
17819 return patched_inst;
17820}
17821
17822static inline bfd_vma
17823create_instruction_udf (int value)
17824{
17825 /* A8.8.247 UDF (A8-758)
17826 Undefined (Encoding T1). */
17827 bfd_vma patched_inst = 0xde00
17828 | (value & 0xff);
17829
17830 return patched_inst;
17831}
17832
17833/* Functions writing an instruction in memory, returning the next
17834 memory position to write to. */
17835
17836static inline bfd_byte *
17837push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17838 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17839{
17840 put_thumb2_insn (htab, output_bfd, insn, pt);
17841 return pt + 4;
17842}
17843
17844static inline bfd_byte *
17845push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17846 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17847{
17848 put_thumb_insn (htab, output_bfd, insn, pt);
17849 return pt + 2;
17850}
17851
17852/* Function filling up a region in memory with T1 and T2 UDFs taking
17853 care of alignment. */
17854
17855static bfd_byte *
17856stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17857 bfd * output_bfd,
17858 const bfd_byte * const base_stub_contents,
17859 bfd_byte * const from_stub_contents,
17860 const bfd_byte * const end_stub_contents)
17861{
17862 bfd_byte *current_stub_contents = from_stub_contents;
17863
17864 /* Fill the remaining of the stub with deterministic contents : UDF
17865 instructions.
17866 Check if realignment is needed on modulo 4 frontier using T1, to
17867 further use T2. */
17868 if ((current_stub_contents < end_stub_contents)
17869 && !((current_stub_contents - base_stub_contents) % 2)
17870 && ((current_stub_contents - base_stub_contents) % 4))
17871 current_stub_contents =
17872 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17873 create_instruction_udf (0));
17874
17875 for (; current_stub_contents < end_stub_contents;)
17876 current_stub_contents =
17877 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17878 create_instruction_udf_w (0));
17879
17880 return current_stub_contents;
17881}
17882
17883/* Functions writing the stream of instructions equivalent to the
17884 derived sequence for ldmia, ldmdb, vldm respectively. */
17885
17886static void
17887stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17888 bfd * output_bfd,
17889 const insn32 initial_insn,
17890 const bfd_byte *const initial_insn_addr,
17891 bfd_byte *const base_stub_contents)
17892{
17893 int wback = (initial_insn & 0x00200000) >> 21;
17894 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17895 int insn_all_registers = initial_insn & 0x0000ffff;
17896 int insn_low_registers, insn_high_registers;
17897 int usable_register_mask;
b25e998d 17898 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17899 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17900 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17901 bfd_byte *current_stub_contents = base_stub_contents;
17902
17903 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17904
17905 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17906 smaller than 8 registers load sequences that do not cause the
17907 hardware issue. */
17908 if (nb_registers <= 8)
17909 {
17910 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17911 current_stub_contents =
17912 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17913 initial_insn);
17914
17915 /* B initial_insn_addr+4. */
17916 if (!restore_pc)
17917 current_stub_contents =
17918 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17919 create_instruction_branch_absolute
82188b29 17920 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17921
17922 /* Fill the remaining of the stub with deterministic contents. */
17923 current_stub_contents =
17924 stm32l4xx_fill_stub_udf (htab, output_bfd,
17925 base_stub_contents, current_stub_contents,
17926 base_stub_contents +
17927 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17928
17929 return;
17930 }
17931
17932 /* - reg_list[13] == 0. */
17933 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17934
17935 /* - reg_list[14] & reg_list[15] != 1. */
17936 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17937
17938 /* - if (wback==1) reg_list[rn] == 0. */
17939 BFD_ASSERT (!wback || !restore_rn);
17940
17941 /* - nb_registers > 8. */
b25e998d 17942 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17943
17944 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17945
17946 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17947 - One with the 7 lowest registers (register mask 0x007F)
17948 This LDM will finally contain between 2 and 7 registers
17949 - One with the 7 highest registers (register mask 0xDF80)
17950 This ldm will finally contain between 2 and 7 registers. */
17951 insn_low_registers = insn_all_registers & 0x007F;
17952 insn_high_registers = insn_all_registers & 0xDF80;
17953
17954 /* A spare register may be needed during this veneer to temporarily
17955 handle the base register. This register will be restored with the
17956 last LDM operation.
17957 The usable register may be any general purpose register (that
17958 excludes PC, SP, LR : register mask is 0x1FFF). */
17959 usable_register_mask = 0x1FFF;
17960
17961 /* Generate the stub function. */
17962 if (wback)
17963 {
17964 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17965 current_stub_contents =
17966 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17967 create_instruction_ldmia
17968 (rn, /*wback=*/1, insn_low_registers));
17969
17970 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17971 current_stub_contents =
17972 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17973 create_instruction_ldmia
17974 (rn, /*wback=*/1, insn_high_registers));
17975 if (!restore_pc)
17976 {
17977 /* B initial_insn_addr+4. */
17978 current_stub_contents =
17979 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17980 create_instruction_branch_absolute
82188b29 17981 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17982 }
17983 }
17984 else /* if (!wback). */
17985 {
17986 ri = rn;
17987
17988 /* If Rn is not part of the high-register-list, move it there. */
17989 if (!(insn_high_registers & (1 << rn)))
17990 {
17991 /* Choose a Ri in the high-register-list that will be restored. */
17992 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17993
17994 /* MOV Ri, Rn. */
17995 current_stub_contents =
17996 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17997 create_instruction_mov (ri, rn));
17998 }
17999
18000 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18001 current_stub_contents =
18002 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18003 create_instruction_ldmia
18004 (ri, /*wback=*/1, insn_low_registers));
18005
18006 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18007 current_stub_contents =
18008 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18009 create_instruction_ldmia
18010 (ri, /*wback=*/0, insn_high_registers));
18011
18012 if (!restore_pc)
18013 {
18014 /* B initial_insn_addr+4. */
18015 current_stub_contents =
18016 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18017 create_instruction_branch_absolute
82188b29 18018 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18019 }
18020 }
18021
18022 /* Fill the remaining of the stub with deterministic contents. */
18023 current_stub_contents =
18024 stm32l4xx_fill_stub_udf (htab, output_bfd,
18025 base_stub_contents, current_stub_contents,
18026 base_stub_contents +
18027 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18028}
18029
18030static void
18031stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18032 bfd * output_bfd,
18033 const insn32 initial_insn,
18034 const bfd_byte *const initial_insn_addr,
18035 bfd_byte *const base_stub_contents)
18036{
18037 int wback = (initial_insn & 0x00200000) >> 21;
18038 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18039 int insn_all_registers = initial_insn & 0x0000ffff;
18040 int insn_low_registers, insn_high_registers;
18041 int usable_register_mask;
18042 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18043 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18044 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18045 bfd_byte *current_stub_contents = base_stub_contents;
18046
18047 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18048
18049 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18050 smaller than 8 registers load sequences that do not cause the
18051 hardware issue. */
18052 if (nb_registers <= 8)
18053 {
18054 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18055 current_stub_contents =
18056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18057 initial_insn);
18058
18059 /* B initial_insn_addr+4. */
18060 current_stub_contents =
18061 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18062 create_instruction_branch_absolute
82188b29 18063 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18064
18065 /* Fill the remaining of the stub with deterministic contents. */
18066 current_stub_contents =
18067 stm32l4xx_fill_stub_udf (htab, output_bfd,
18068 base_stub_contents, current_stub_contents,
18069 base_stub_contents +
18070 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18071
18072 return;
18073 }
18074
18075 /* - reg_list[13] == 0. */
18076 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18077
18078 /* - reg_list[14] & reg_list[15] != 1. */
18079 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18080
18081 /* - if (wback==1) reg_list[rn] == 0. */
18082 BFD_ASSERT (!wback || !restore_rn);
18083
18084 /* - nb_registers > 8. */
b25e998d 18085 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18086
18087 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18088
18089 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18090 - One with the 7 lowest registers (register mask 0x007F)
18091 This LDM will finally contain between 2 and 7 registers
18092 - One with the 7 highest registers (register mask 0xDF80)
18093 This ldm will finally contain between 2 and 7 registers. */
18094 insn_low_registers = insn_all_registers & 0x007F;
18095 insn_high_registers = insn_all_registers & 0xDF80;
18096
18097 /* A spare register may be needed during this veneer to temporarily
18098 handle the base register. This register will be restored with
18099 the last LDM operation.
18100 The usable register may be any general purpose register (that excludes
18101 PC, SP, LR : register mask is 0x1FFF). */
18102 usable_register_mask = 0x1FFF;
18103
18104 /* Generate the stub function. */
18105 if (!wback && !restore_pc && !restore_rn)
18106 {
18107 /* Choose a Ri in the low-register-list that will be restored. */
18108 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18109
18110 /* MOV Ri, Rn. */
18111 current_stub_contents =
18112 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18113 create_instruction_mov (ri, rn));
18114
18115 /* LDMDB Ri!, {R-high-register-list}. */
18116 current_stub_contents =
18117 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18118 create_instruction_ldmdb
18119 (ri, /*wback=*/1, insn_high_registers));
18120
18121 /* LDMDB Ri, {R-low-register-list}. */
18122 current_stub_contents =
18123 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18124 create_instruction_ldmdb
18125 (ri, /*wback=*/0, insn_low_registers));
18126
18127 /* B initial_insn_addr+4. */
18128 current_stub_contents =
18129 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18130 create_instruction_branch_absolute
82188b29 18131 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18132 }
18133 else if (wback && !restore_pc && !restore_rn)
18134 {
18135 /* LDMDB Rn!, {R-high-register-list}. */
18136 current_stub_contents =
18137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18138 create_instruction_ldmdb
18139 (rn, /*wback=*/1, insn_high_registers));
18140
18141 /* LDMDB Rn!, {R-low-register-list}. */
18142 current_stub_contents =
18143 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18144 create_instruction_ldmdb
18145 (rn, /*wback=*/1, insn_low_registers));
18146
18147 /* B initial_insn_addr+4. */
18148 current_stub_contents =
18149 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18150 create_instruction_branch_absolute
82188b29 18151 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18152 }
18153 else if (!wback && restore_pc && !restore_rn)
18154 {
18155 /* Choose a Ri in the high-register-list that will be restored. */
18156 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18157
18158 /* SUB Ri, Rn, #(4*nb_registers). */
18159 current_stub_contents =
18160 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18161 create_instruction_sub (ri, rn, (4 * nb_registers)));
18162
18163 /* LDMIA Ri!, {R-low-register-list}. */
18164 current_stub_contents =
18165 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18166 create_instruction_ldmia
18167 (ri, /*wback=*/1, insn_low_registers));
18168
18169 /* LDMIA Ri, {R-high-register-list}. */
18170 current_stub_contents =
18171 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18172 create_instruction_ldmia
18173 (ri, /*wback=*/0, insn_high_registers));
18174 }
18175 else if (wback && restore_pc && !restore_rn)
18176 {
18177 /* Choose a Ri in the high-register-list that will be restored. */
18178 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18179
18180 /* SUB Rn, Rn, #(4*nb_registers) */
18181 current_stub_contents =
18182 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18183 create_instruction_sub (rn, rn, (4 * nb_registers)));
18184
18185 /* MOV Ri, Rn. */
18186 current_stub_contents =
18187 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18188 create_instruction_mov (ri, rn));
18189
18190 /* LDMIA Ri!, {R-low-register-list}. */
18191 current_stub_contents =
18192 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18193 create_instruction_ldmia
18194 (ri, /*wback=*/1, insn_low_registers));
18195
18196 /* LDMIA Ri, {R-high-register-list}. */
18197 current_stub_contents =
18198 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18199 create_instruction_ldmia
18200 (ri, /*wback=*/0, insn_high_registers));
18201 }
18202 else if (!wback && !restore_pc && restore_rn)
18203 {
18204 ri = rn;
18205 if (!(insn_low_registers & (1 << rn)))
18206 {
18207 /* Choose a Ri in the low-register-list that will be restored. */
18208 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18209
18210 /* MOV Ri, Rn. */
18211 current_stub_contents =
18212 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18213 create_instruction_mov (ri, rn));
18214 }
18215
18216 /* LDMDB Ri!, {R-high-register-list}. */
18217 current_stub_contents =
18218 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18219 create_instruction_ldmdb
18220 (ri, /*wback=*/1, insn_high_registers));
18221
18222 /* LDMDB Ri, {R-low-register-list}. */
18223 current_stub_contents =
18224 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18225 create_instruction_ldmdb
18226 (ri, /*wback=*/0, insn_low_registers));
18227
18228 /* B initial_insn_addr+4. */
18229 current_stub_contents =
18230 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18231 create_instruction_branch_absolute
82188b29 18232 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18233 }
18234 else if (!wback && restore_pc && restore_rn)
18235 {
18236 ri = rn;
18237 if (!(insn_high_registers & (1 << rn)))
18238 {
18239 /* Choose a Ri in the high-register-list that will be restored. */
18240 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18241 }
18242
18243 /* SUB Ri, Rn, #(4*nb_registers). */
18244 current_stub_contents =
18245 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18246 create_instruction_sub (ri, rn, (4 * nb_registers)));
18247
18248 /* LDMIA Ri!, {R-low-register-list}. */
18249 current_stub_contents =
18250 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18251 create_instruction_ldmia
18252 (ri, /*wback=*/1, insn_low_registers));
18253
18254 /* LDMIA Ri, {R-high-register-list}. */
18255 current_stub_contents =
18256 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18257 create_instruction_ldmia
18258 (ri, /*wback=*/0, insn_high_registers));
18259 }
18260 else if (wback && restore_rn)
18261 {
18262 /* The assembler should not have accepted to encode this. */
18263 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18264 "undefined behavior.\n");
18265 }
18266
18267 /* Fill the remaining of the stub with deterministic contents. */
18268 current_stub_contents =
18269 stm32l4xx_fill_stub_udf (htab, output_bfd,
18270 base_stub_contents, current_stub_contents,
18271 base_stub_contents +
18272 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18273
18274}
18275
18276static void
18277stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18278 bfd * output_bfd,
18279 const insn32 initial_insn,
18280 const bfd_byte *const initial_insn_addr,
18281 bfd_byte *const base_stub_contents)
18282{
9239bbd3 18283 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18284 bfd_byte *current_stub_contents = base_stub_contents;
18285
18286 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18287
18288 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18289 smaller than 8 words load sequences that do not cause the
a504d23a 18290 hardware issue. */
9239bbd3 18291 if (num_words <= 8)
a504d23a
LA		 18292 {
18293 /* Untouched instruction. */
18294 current_stub_contents =
18295 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18296 initial_insn);
18297
18298 /* B initial_insn_addr+4. */
18299 current_stub_contents =
18300 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18301 create_instruction_branch_absolute
82188b29 18302 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18303 }
18304 else
18305 {
9eaff861 18306 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18307 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18308 bfd_boolean is_ia_nobang = /* (IA without !). */
18309 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18310 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18311 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18312 bfd_boolean is_db_bang = /* (DB with !). */
18313 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18314 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18315 /* d = UInt (Vd:D);. */
9239bbd3 18316 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18317 | (((unsigned int)initial_insn << 9) >> 31);
18318
9239bbd3
CM		 18319 /* Compute the number of 8-words chunks needed to split. */
18320 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18321 int chunk;
18322
18323 /* The test coverage has been done assuming the following
18324 hypothesis that exactly one of the previous is_ predicates is
18325 true. */
9239bbd3
CM		 18326 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18327 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18328
9239bbd3 18329 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18330 cases, then we emit the adjustments:
18331
18332 vldm rx, {...}
18333 -> vldm rx!, {8_words_or_less} for each needed 8_word
18334 -> sub rx, rx, #size (list)
18335
18336 vldm rx!, {...}
18337 -> vldm rx!, {8_words_or_less} for each needed 8_word
18338 This also handles vpop instruction (when rx is sp)
18339
18340 vldmd rx!, {...}
18341 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18342 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18343 {
9239bbd3
CM		 18344 bfd_vma new_insn = 0;
18345
a504d23a
LA		 18346 if (is_ia_nobang || is_ia_bang)
18347 {
9239bbd3
CM		 18348 new_insn = create_instruction_vldmia
18349 (base_reg,
18350 is_dp,
18351 /*wback= . */1,
18352 chunks - (chunk + 1) ?
18353 8 : num_words - chunk * 8,
18354 first_reg + chunk * 8);
a504d23a
LA		 18355 }
18356 else if (is_db_bang)
18357 {
9239bbd3
CM		 18358 new_insn = create_instruction_vldmdb
18359 (base_reg,
18360 is_dp,
18361 chunks - (chunk + 1) ?
18362 8 : num_words - chunk * 8,
18363 first_reg + chunk * 8);
a504d23a 18364 }
9239bbd3
CM		 18365
18366 if (new_insn)
18367 current_stub_contents =
18368 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18369 new_insn);
a504d23a
LA		 18370 }
18371
18372 /* Only this case requires the base register compensation
18373 subtract. */
18374 if (is_ia_nobang)
18375 {
18376 current_stub_contents =
18377 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18378 create_instruction_sub
9239bbd3 18379 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18380 }
18381
18382 /* B initial_insn_addr+4. */
18383 current_stub_contents =
18384 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18385 create_instruction_branch_absolute
82188b29 18386 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18387 }
18388
18389 /* Fill the remaining of the stub with deterministic contents. */
18390 current_stub_contents =
18391 stm32l4xx_fill_stub_udf (htab, output_bfd,
18392 base_stub_contents, current_stub_contents,
18393 base_stub_contents +
18394 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18395}
18396
18397static void
18398stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18399 bfd * output_bfd,
18400 const insn32 wrong_insn,
18401 const bfd_byte *const wrong_insn_addr,
18402 bfd_byte *const stub_contents)
18403{
18404 if (is_thumb2_ldmia (wrong_insn))
18405 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18406 wrong_insn, wrong_insn_addr,
18407 stub_contents);
18408 else if (is_thumb2_ldmdb (wrong_insn))
18409 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18410 wrong_insn, wrong_insn_addr,
18411 stub_contents);
18412 else if (is_thumb2_vldm (wrong_insn))
18413 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18414 wrong_insn, wrong_insn_addr,
18415 stub_contents);
18416}
18417
18418/* End of stm32l4xx work-around. */
18419
18420
e489d0ae
PB		 18421/* Do code byteswapping. Return FALSE afterwards so that the section is
18422 written out as normal. */
18423
18424static bfd_boolean
c7b8f16e 18425elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18426 struct bfd_link_info *link_info,
18427 asection *sec,
e489d0ae
PB		 18428 bfd_byte *contents)
18429{
48229727 18430 unsigned int mapcount, errcount;
8e3de13a 18431 _arm_elf_section_data *arm_data;
c7b8f16e 18432 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18433 elf32_arm_section_map *map;
c7b8f16e 18434 elf32_vfp11_erratum_list *errnode;
a504d23a 18435 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18436 bfd_vma ptr;
18437 bfd_vma end;
c7b8f16e 18438 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18439 bfd_byte tmp;
48229727 18440 unsigned int i;
57e8b36a 18441
4dfe6ac6
NC		 18442 if (globals == NULL)
18443 return FALSE;
18444
8e3de13a
NC		 18445 /* If this section has not been allocated an _arm_elf_section_data
18446 structure then we cannot record anything. */
18447 arm_data = get_arm_elf_section_data (sec);
18448 if (arm_data == NULL)
18449 return FALSE;
18450
18451 mapcount = arm_data->mapcount;
18452 map = arm_data->map;
c7b8f16e
JB		 18453 errcount = arm_data->erratumcount;
18454
18455 if (errcount != 0)
18456 {
18457 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18458
18459 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18460 errnode = errnode->next)
18461 {
18462 bfd_vma target = errnode->vma - offset;
18463
18464 switch (errnode->type)
18465 {
18466 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18467 {
18468 bfd_vma branch_to_veneer;
18469 /* Original condition code of instruction, plus bit mask for
18470 ARM B instruction. */
18471 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18472 | 0x0a000000;
c7b8f16e
JB		 18473
18474 /* The instruction is before the label. */
91d6fa6a 18475 target -= 4;
c7b8f16e
JB		 18476
18477 /* Above offset included in -4 below. */
18478 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18479 - errnode->vma - 4;
c7b8f16e
JB		 18480
18481 if ((signed) branch_to_veneer < -(1 << 25)
18482 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18483 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18484 "range"), output_bfd);
c7b8f16e 18485
99059e56
RM		 18486 insn |= (branch_to_veneer >> 2) & 0xffffff;
18487 contents[endianflip ^ target] = insn & 0xff;
18488 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18489 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18490 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18491 }
18492 break;
c7b8f16e
JB		 18493
18494 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18495 {
18496 bfd_vma branch_from_veneer;
18497 unsigned int insn;
c7b8f16e 18498
99059e56
RM		 18499 /* Take size of veneer into account. */
18500 branch_from_veneer = errnode->u.v.branch->vma
18501 - errnode->vma - 12;
c7b8f16e
JB		 18502
18503 if ((signed) branch_from_veneer < -(1 << 25)
18504 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18505 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18506 "range"), output_bfd);
c7b8f16e 18507
99059e56
RM		 18508 /* Original instruction. */
18509 insn = errnode->u.v.branch->u.b.vfp_insn;
18510 contents[endianflip ^ target] = insn & 0xff;
18511 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18512 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18513 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18514
18515 /* Branch back to insn after original insn. */
18516 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18517 contents[endianflip ^ (target + 4)] = insn & 0xff;
18518 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18519 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18520 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18521 }
18522 break;
c7b8f16e 18523
99059e56
RM		 18524 default:
18525 abort ();
18526 }
18527 }
c7b8f16e 18528 }
e489d0ae 18529
a504d23a
LA		 18530 if (arm_data->stm32l4xx_erratumcount != 0)
18531 {
18532 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18533 stm32l4xx_errnode != 0;
18534 stm32l4xx_errnode = stm32l4xx_errnode->next)
18535 {
18536 bfd_vma target = stm32l4xx_errnode->vma - offset;
18537
18538 switch (stm32l4xx_errnode->type)
18539 {
18540 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18541 {
18542 unsigned int insn;
18543 bfd_vma branch_to_veneer =
18544 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18545
18546 if ((signed) branch_to_veneer < -(1 << 24)
18547 || (signed) branch_to_veneer >= (1 << 24))
18548 {
18549 bfd_vma out_of_range =
18550 ((signed) branch_to_veneer < -(1 << 24)) ?
18551 - branch_to_veneer - (1 << 24) :
18552 ((signed) branch_to_veneer >= (1 << 24)) ?
18553 branch_to_veneer - (1 << 24) : 0;
18554
4eca0228 18555 _bfd_error_handler
a504d23a 18556 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18557 "Jump out of range by %ld bytes. "
a504d23a
LA		 18558 "Cannot encode branch instruction. "),
18559 output_bfd,
eee926f2 18560 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18561 out_of_range);
18562 continue;
18563 }
18564
18565 insn = create_instruction_branch_absolute
82188b29 18566 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18567
18568 /* The instruction is before the label. */
18569 target -= 4;
18570
18571 put_thumb2_insn (globals, output_bfd,
18572 (bfd_vma) insn, contents + target);
18573 }
18574 break;
18575
18576 case STM32L4XX_ERRATUM_VENEER:
18577 {
82188b29
NC		 18578 bfd_byte * veneer;
18579 bfd_byte * veneer_r;
a504d23a
LA		 18580 unsigned int insn;
18581
82188b29
NC		 18582 veneer = contents + target;
18583 veneer_r = veneer
18584 + stm32l4xx_errnode->u.b.veneer->vma
18585 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18586
18587 if ((signed) (veneer_r - veneer -
18588 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18589 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18590 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18591 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18592 || (signed) (veneer_r - veneer) >= (1 << 24))
18593 {
4eca0228
AM		 18594 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18595 "veneer."), output_bfd);
a504d23a
LA		 18596 continue;
18597 }
18598
18599 /* Original instruction. */
18600 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18601
18602 stm32l4xx_create_replacing_stub
18603 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18604 }
18605 break;
18606
18607 default:
18608 abort ();
18609 }
18610 }
18611 }
18612
2468f9c9
PB		 18613 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18614 {
18615 arm_unwind_table_edit *edit_node
99059e56 18616 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18617 /* Now, sec->size is the size of the section we will write. The original
99059e56 18618 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18619 markers) was sec->rawsize. (This isn't the case if we perform no
18620 edits, then rawsize will be zero and we should use size). */
21d799b5 18621 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18622 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18623 unsigned int in_index, out_index;
18624 bfd_vma add_to_offsets = 0;
18625
18626 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18627 {
2468f9c9
PB		 18628 if (edit_node)
18629 {
18630 unsigned int edit_index = edit_node->index;
b38cadfb 18631
2468f9c9 18632 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18633 {
2468f9c9
PB		 18634 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18635 contents + in_index * 8, add_to_offsets);
18636 out_index++;
18637 in_index++;
18638 }
18639 else if (in_index == edit_index
18640 || (in_index * 8 >= input_size
18641 && edit_index == UINT_MAX))
99059e56 18642 {
2468f9c9
PB		 18643 switch (edit_node->type)
18644 {
18645 case DELETE_EXIDX_ENTRY:
18646 in_index++;
18647 add_to_offsets += 8;
18648 break;
b38cadfb 18649
2468f9c9
PB		 18650 case INSERT_EXIDX_CANTUNWIND_AT_END:
18651 {
99059e56 18652 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18653 bfd_vma text_offset = text_sec->output_section->vma
18654 + text_sec->output_offset
18655 + text_sec->size;
18656 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18657 unsigned long prel31_offset;
2468f9c9
PB		 18658
18659 /* Note: this is meant to be equivalent to an
18660 R_ARM_PREL31 relocation. These synthetic
18661 EXIDX_CANTUNWIND markers are not relocated by the
18662 usual BFD method. */
18663 prel31_offset = (text_offset - exidx_offset)
18664 & 0x7ffffffful;
491d01d3
YU		 18665 if (bfd_link_relocatable (link_info))
18666 {
18667 /* Here relocation for new EXIDX_CANTUNWIND is
18668 created, so there is no need to
18669 adjust offset by hand. */
18670 prel31_offset = text_sec->output_offset
18671 + text_sec->size;
491d01d3 18672 }
2468f9c9
PB		 18673
18674 /* First address we can't unwind. */
18675 bfd_put_32 (output_bfd, prel31_offset,
18676 &edited_contents[out_index * 8]);
18677
18678 /* Code for EXIDX_CANTUNWIND. */
18679 bfd_put_32 (output_bfd, 0x1,
18680 &edited_contents[out_index * 8 + 4]);
18681
18682 out_index++;
18683 add_to_offsets -= 8;
18684 }
18685 break;
18686 }
b38cadfb 18687
2468f9c9
PB		 18688 edit_node = edit_node->next;
18689 }
18690 }
18691 else
18692 {
18693 /* No more edits, copy remaining entries verbatim. */
18694 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18695 contents + in_index * 8, add_to_offsets);
18696 out_index++;
18697 in_index++;
18698 }
18699 }
18700
18701 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18702 bfd_set_section_contents (output_bfd, sec->output_section,
18703 edited_contents,
18704 (file_ptr) sec->output_offset, sec->size);
18705
18706 return TRUE;
18707 }
18708
48229727
JB		 18709 /* Fix code to point to Cortex-A8 erratum stubs. */
18710 if (globals->fix_cortex_a8)
18711 {
18712 struct a8_branch_to_stub_data data;
18713
18714 data.writing_section = sec;
18715 data.contents = contents;
18716
a504d23a
LA		 18717 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18718 & data);
48229727
JB		 18719 }
18720
e489d0ae
PB		 18721 if (mapcount == 0)
18722 return FALSE;
18723
c7b8f16e 18724 if (globals->byteswap_code)
e489d0ae 18725 {
c7b8f16e 18726 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18727
c7b8f16e
JB		 18728 ptr = map[0].vma;
18729 for (i = 0; i < mapcount; i++)
99059e56
RM		 18730 {
18731 if (i == mapcount - 1)
c7b8f16e 18732 end = sec->size;
99059e56
RM		 18733 else
18734 end = map[i + 1].vma;
e489d0ae 18735
99059e56 18736 switch (map[i].type)
e489d0ae 18737 {
c7b8f16e
JB		 18738 case 'a':
18739 /* Byte swap code words. */
18740 while (ptr + 3 < end)
99059e56
RM		 18741 {
18742 tmp = contents[ptr];
18743 contents[ptr] = contents[ptr + 3];
18744 contents[ptr + 3] = tmp;
18745 tmp = contents[ptr + 1];
18746 contents[ptr + 1] = contents[ptr + 2];
18747 contents[ptr + 2] = tmp;
18748 ptr += 4;
18749 }
c7b8f16e 18750 break;
e489d0ae 18751
c7b8f16e
JB		 18752 case 't':
18753 /* Byte swap code halfwords. */
18754 while (ptr + 1 < end)
99059e56
RM		 18755 {
18756 tmp = contents[ptr];
18757 contents[ptr] = contents[ptr + 1];
18758 contents[ptr + 1] = tmp;
18759 ptr += 2;
18760 }
c7b8f16e
JB		 18761 break;
18762
18763 case 'd':
18764 /* Leave data alone. */
18765 break;
18766 }
99059e56
RM		 18767 ptr = end;
18768 }
e489d0ae 18769 }
8e3de13a 18770
93204d3a 18771 free (map);
47b2e99c 18772 arm_data->mapcount = -1;
c7b8f16e 18773 arm_data->mapsize = 0;
8e3de13a 18774 arm_data->map = NULL;
8e3de13a 18775
e489d0ae
PB		 18776 return FALSE;
18777}
18778
0beaef2b
PB		 18779/* Mangle thumb function symbols as we read them in. */
18780
8384fb8f 18781static bfd_boolean
0beaef2b
PB		 18782elf32_arm_swap_symbol_in (bfd * abfd,
18783 const void *psrc,
18784 const void *pshn,
18785 Elf_Internal_Sym *dst)
18786{
4ba2ef8f
TP		 18787 Elf_Internal_Shdr *symtab_hdr;
18788 const char *name = NULL;
18789
8384fb8f
AM		 18790 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18791 return FALSE;
39d911fc 18792 dst->st_target_internal = 0;
0beaef2b
PB		 18793
18794 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18795 the address. */
63e1a0fc
PB		 18796 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18797 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18798 {
63e1a0fc
PB		 18799 if (dst->st_value & 1)
18800 {
18801 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18802 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18803 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18804 }
18805 else
39d911fc 18806 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18807 }
18808 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18809 {
18810 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18811 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18812 }
35fc36a8 18813 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18814 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18815 else
39d911fc 18816 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18817
4ba2ef8f
TP		 18818 /* Mark CMSE special symbols. */
18819 symtab_hdr = & elf_symtab_hdr (abfd);
18820 if (symtab_hdr->sh_size)
18821 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18822 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18823 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18824
8384fb8f 18825 return TRUE;
0beaef2b
PB		 18826}
18827
18828
18829/* Mangle thumb function symbols as we write them out. */
18830
18831static void
18832elf32_arm_swap_symbol_out (bfd *abfd,
18833 const Elf_Internal_Sym *src,
18834 void *cdst,
18835 void *shndx)
18836{
18837 Elf_Internal_Sym newsym;
18838
18839 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18840 of the address set, as per the new EABI. We do this unconditionally
18841 because objcopy does not set the elf header flags until after
18842 it writes out the symbol table. */
39d911fc 18843 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18844 {
18845 newsym = *src;
34e77a92
RS		 18846 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18847 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18848 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18849 {
18850 /* Do this only for defined symbols. At link type, the static
18851 linker will simulate the work of dynamic linker of resolving
18852 symbols and will carry over the thumbness of found symbols to
18853 the output symbol table. It's not clear how it happens, but
18854 the thumbness of undefined symbols can well be different at
18855 runtime, and writing '1' for them will be confusing for users
18856 and possibly for dynamic linker itself.
18857 */
18858 newsym.st_value |= 1;
18859 }
906e58ca 18860
0beaef2b
PB		 18861 src = &newsym;
18862 }
18863 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18864}
18865
b294bdf8
MM		 18866/* Add the PT_ARM_EXIDX program header. */
18867
18868static bfd_boolean
906e58ca 18869elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18870 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18871{
18872 struct elf_segment_map *m;
18873 asection *sec;
18874
18875 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18876 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18877 {
18878 /* If there is already a PT_ARM_EXIDX header, then we do not
18879 want to add another one. This situation arises when running
18880 "strip"; the input binary already has the header. */
12bd6957 18881 m = elf_seg_map (abfd);
b294bdf8
MM		 18882 while (m && m->p_type != PT_ARM_EXIDX)
18883 m = m->next;
18884 if (!m)
18885 {
21d799b5 18886 m = (struct elf_segment_map *)
99059e56 18887 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18888 if (m == NULL)
18889 return FALSE;
18890 m->p_type = PT_ARM_EXIDX;
18891 m->count = 1;
18892 m->sections[0] = sec;
18893
12bd6957
AM		 18894 m->next = elf_seg_map (abfd);
18895 elf_seg_map (abfd) = m;
b294bdf8
MM		 18896 }
18897 }
18898
18899 return TRUE;
18900}
18901
18902/* We may add a PT_ARM_EXIDX program header. */
18903
18904static int
a6b96beb
AM		 18905elf32_arm_additional_program_headers (bfd *abfd,
18906 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18907{
18908 asection *sec;
18909
18910 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18911 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18912 return 1;
18913 else
18914 return 0;
18915}
18916
34e77a92
RS		 18917/* Hook called by the linker routine which adds symbols from an object
18918 file. */
18919
18920static bfd_boolean
18921elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18922 Elf_Internal_Sym *sym, const char **namep,
18923 flagword *flagsp, asection **secp, bfd_vma *valp)
18924{
a43942db 18925 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18926 && (abfd->flags & DYNAMIC) == 0
18927 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18928 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18929
c792917c
NC		 18930 if (elf32_arm_hash_table (info) == NULL)
18931 return FALSE;
18932
34e77a92
RS		 18933 if (elf32_arm_hash_table (info)->vxworks_p
18934 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18935 flagsp, secp, valp))
18936 return FALSE;
18937
18938 return TRUE;
18939}
18940
0beaef2b 18941/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18942const struct elf_size_info elf32_arm_size_info =
18943{
0beaef2b
PB		 18944 sizeof (Elf32_External_Ehdr),
18945 sizeof (Elf32_External_Phdr),
18946 sizeof (Elf32_External_Shdr),
18947 sizeof (Elf32_External_Rel),
18948 sizeof (Elf32_External_Rela),
18949 sizeof (Elf32_External_Sym),
18950 sizeof (Elf32_External_Dyn),
18951 sizeof (Elf_External_Note),
18952 4,
18953 1,
18954 32, 2,
18955 ELFCLASS32, EV_CURRENT,
18956 bfd_elf32_write_out_phdrs,
18957 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18958 bfd_elf32_checksum_contents,
0beaef2b
PB		 18959 bfd_elf32_write_relocs,
18960 elf32_arm_swap_symbol_in,
18961 elf32_arm_swap_symbol_out,
18962 bfd_elf32_slurp_reloc_table,
18963 bfd_elf32_slurp_symbol_table,
18964 bfd_elf32_swap_dyn_in,
18965 bfd_elf32_swap_dyn_out,
18966 bfd_elf32_swap_reloc_in,
18967 bfd_elf32_swap_reloc_out,
18968 bfd_elf32_swap_reloca_in,
18969 bfd_elf32_swap_reloca_out
18970};
18971
685e70ae
VK		 18972static bfd_vma
18973read_code32 (const bfd *abfd, const bfd_byte *addr)
18974{
18975 /* V7 BE8 code is always little endian. */
18976 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18977 return bfd_getl32 (addr);
18978
18979 return bfd_get_32 (abfd, addr);
18980}
18981
18982static bfd_vma
18983read_code16 (const bfd *abfd, const bfd_byte *addr)
18984{
18985 /* V7 BE8 code is always little endian. */
18986 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18987 return bfd_getl16 (addr);
18988
18989 return bfd_get_16 (abfd, addr);
18990}
18991
6a631e86
YG		 18992/* Return size of plt0 entry starting at ADDR
18993 or (bfd_vma) -1 if size can not be determined. */
18994
18995static bfd_vma
18996elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18997{
18998 bfd_vma first_word;
18999 bfd_vma plt0_size;
19000
685e70ae 19001 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19002
19003 if (first_word == elf32_arm_plt0_entry[0])
19004 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19005 else if (first_word == elf32_thumb2_plt0_entry[0])
19006 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19007 else
19008 /* We don't yet handle this PLT format. */
19009 return (bfd_vma) -1;
19010
19011 return plt0_size;
19012}
19013
19014/* Return size of plt entry starting at offset OFFSET
19015 of plt section located at address START
19016 or (bfd_vma) -1 if size can not be determined. */
19017
19018static bfd_vma
19019elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19020{
19021 bfd_vma first_insn;
19022 bfd_vma plt_size = 0;
19023 const bfd_byte *addr = start + offset;
19024
19025 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19026 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19027 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19028
19029 /* Respect Thumb stub if necessary. */
685e70ae 19030 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19031 {
19032 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19033 }
19034
19035 /* Strip immediate from first add. */
685e70ae 19036 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19037
19038#ifdef FOUR_WORD_PLT
19039 if (first_insn == elf32_arm_plt_entry[0])
19040 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19041#else
19042 if (first_insn == elf32_arm_plt_entry_long[0])
19043 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19044 else if (first_insn == elf32_arm_plt_entry_short[0])
19045 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19046#endif
19047 else
19048 /* We don't yet handle this PLT format. */
19049 return (bfd_vma) -1;
19050
19051 return plt_size;
19052}
19053
19054/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19055
19056static long
19057elf32_arm_get_synthetic_symtab (bfd *abfd,
19058 long symcount ATTRIBUTE_UNUSED,
19059 asymbol **syms ATTRIBUTE_UNUSED,
19060 long dynsymcount,
19061 asymbol **dynsyms,
19062 asymbol **ret)
19063{
19064 asection *relplt;
19065 asymbol *s;
19066 arelent *p;
19067 long count, i, n;
19068 size_t size;
19069 Elf_Internal_Shdr *hdr;
19070 char *names;
19071 asection *plt;
19072 bfd_vma offset;
19073 bfd_byte *data;
19074
19075 *ret = NULL;
19076
19077 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19078 return 0;
19079
19080 if (dynsymcount <= 0)
19081 return 0;
19082
19083 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19084 if (relplt == NULL)
19085 return 0;
19086
19087 hdr = &elf_section_data (relplt)->this_hdr;
19088 if (hdr->sh_link != elf_dynsymtab (abfd)
19089 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19090 return 0;
19091
19092 plt = bfd_get_section_by_name (abfd, ".plt");
19093 if (plt == NULL)
19094 return 0;
19095
19096 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19097 return -1;
19098
19099 data = plt->contents;
19100 if (data == NULL)
19101 {
19102 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19103 return -1;
19104 bfd_cache_section_contents((asection *) plt, data);
19105 }
19106
19107 count = relplt->size / hdr->sh_entsize;
19108 size = count * sizeof (asymbol);
19109 p = relplt->relocation;
19110 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19111 {
19112 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19113 if (p->addend != 0)
19114 size += sizeof ("+0x") - 1 + 8;
19115 }
19116
19117 s = *ret = (asymbol *) bfd_malloc (size);
19118 if (s == NULL)
19119 return -1;
19120
19121 offset = elf32_arm_plt0_size (abfd, data);
19122 if (offset == (bfd_vma) -1)
19123 return -1;
19124
19125 names = (char *) (s + count);
19126 p = relplt->relocation;
19127 n = 0;
19128 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19129 {
19130 size_t len;
19131
19132 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19133 if (plt_size == (bfd_vma) -1)
19134 break;
19135
19136 *s = **p->sym_ptr_ptr;
19137 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19138 we are defining a symbol, ensure one of them is set. */
19139 if ((s->flags & BSF_LOCAL) == 0)
19140 s->flags |= BSF_GLOBAL;
19141 s->flags |= BSF_SYNTHETIC;
19142 s->section = plt;
19143 s->value = offset;
19144 s->name = names;
19145 s->udata.p = NULL;
19146 len = strlen ((*p->sym_ptr_ptr)->name);
19147 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19148 names += len;
19149 if (p->addend != 0)
19150 {
19151 char buf[30], *a;
19152
19153 memcpy (names, "+0x", sizeof ("+0x") - 1);
19154 names += sizeof ("+0x") - 1;
19155 bfd_sprintf_vma (abfd, buf, p->addend);
19156 for (a = buf; *a == '0'; ++a)
19157 ;
19158 len = strlen (a);
19159 memcpy (names, a, len);
19160 names += len;
19161 }
19162 memcpy (names, "@plt", sizeof ("@plt"));
19163 names += sizeof ("@plt");
19164 ++s, ++n;
19165 offset += plt_size;
19166 }
19167
19168 return n;
19169}
19170
ac4c9b04
MG		 19171static bfd_boolean
19172elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19173{
f0728ee3
AV		 19174 if (hdr->sh_flags & SHF_ARM_PURECODE)
19175 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19176 return TRUE;
19177}
19178
19179static flagword
19180elf32_arm_lookup_section_flags (char *flag_name)
19181{
f0728ee3
AV		 19182 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19183 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19184
19185 return SEC_NO_FLAGS;
19186}
19187
491d01d3
YU		 19188static unsigned int
19189elf32_arm_count_additional_relocs (asection *sec)
19190{
19191 struct _arm_elf_section_data *arm_data;
19192 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19193
6342be70 19194 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19195}
19196
5522f910 19197/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19198 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19199 FALSE otherwise. ISECTION is the best guess matching section from the
19200 input bfd IBFD, but it might be NULL. */
19201
19202static bfd_boolean
19203elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19204 bfd *obfd ATTRIBUTE_UNUSED,
19205 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19206 Elf_Internal_Shdr *osection)
19207{
19208 switch (osection->sh_type)
19209 {
19210 case SHT_ARM_EXIDX:
19211 {
19212 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19213 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19214 unsigned i = 0;
19215
19216 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19217 osection->sh_info = 0;
19218
19219 /* The sh_link field must be set to the text section associated with
19220 this index section. Unfortunately the ARM EHABI does not specify
19221 exactly how to determine this association. Our caller does try
19222 to match up OSECTION with its corresponding input section however
19223 so that is a good first guess. */
19224 if (isection != NULL
19225 && osection->bfd_section != NULL
19226 && isection->bfd_section != NULL
19227 && isection->bfd_section->output_section != NULL
19228 && isection->bfd_section->output_section == osection->bfd_section
19229 && iheaders != NULL
19230 && isection->sh_link > 0
19231 && isection->sh_link < elf_numsections (ibfd)
19232 && iheaders[isection->sh_link]->bfd_section != NULL
19233 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19234 )
19235 {
19236 for (i = elf_numsections (obfd); i-- > 0;)
19237 if (oheaders[i]->bfd_section
19238 == iheaders[isection->sh_link]->bfd_section->output_section)
19239 break;
19240 }
9eaff861 19241
5522f910
NC		 19242 if (i == 0)
19243 {
19244 /* Failing that we have to find a matching section ourselves. If
19245 we had the output section name available we could compare that
19246 with input section names. Unfortunately we don't. So instead
19247 we use a simple heuristic and look for the nearest executable
19248 section before this one. */
19249 for (i = elf_numsections (obfd); i-- > 0;)
19250 if (oheaders[i] == osection)
19251 break;
19252 if (i == 0)
19253 break;
19254
19255 while (i-- > 0)
19256 if (oheaders[i]->sh_type == SHT_PROGBITS
19257 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19258 == (SHF_ALLOC | SHF_EXECINSTR))
19259 break;
19260 }
19261
19262 if (i)
19263 {
19264 osection->sh_link = i;
19265 /* If the text section was part of a group
19266 then the index section should be too. */
19267 if (oheaders[i]->sh_flags & SHF_GROUP)
19268 osection->sh_flags |= SHF_GROUP;
19269 return TRUE;
19270 }
19271 }
19272 break;
19273
19274 case SHT_ARM_PREEMPTMAP:
19275 osection->sh_flags = SHF_ALLOC;
19276 break;
19277
19278 case SHT_ARM_ATTRIBUTES:
19279 case SHT_ARM_DEBUGOVERLAY:
19280 case SHT_ARM_OVERLAYSECTION:
19281 default:
19282 break;
19283 }
19284
19285 return FALSE;
19286}
19287
d691934d
NC		 19288/* Returns TRUE if NAME is an ARM mapping symbol.
19289 Traditionally the symbols $a, $d and $t have been used.
19290 The ARM ELF standard also defines $x (for A64 code). It also allows a
19291 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19292 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19293 not support them here. $t.x indicates the start of ThumbEE instructions. */
19294
19295static bfd_boolean
19296is_arm_mapping_symbol (const char * name)
19297{
19298 return name != NULL /* Paranoia. */
19299 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19300 the mapping symbols could have acquired a prefix.
19301 We do not support this here, since such symbols no
19302 longer conform to the ARM ELF ABI. */
19303 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19304 && (name[2] == 0 || name[2] == '.');
19305 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19306 any characters that follow the period are legal characters for the body
19307 of a symbol's name. For now we just assume that this is the case. */
19308}
19309
fca2a38f
NC		 19310/* Make sure that mapping symbols in object files are not removed via the
19311 "strip --strip-unneeded" tool. These symbols are needed in order to
19312 correctly generate interworking veneers, and for byte swapping code
19313 regions. Once an object file has been linked, it is safe to remove the
19314 symbols as they will no longer be needed. */
19315
19316static void
19317elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19318{
19319 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19320 && sym->section != bfd_abs_section_ptr
d691934d 19321 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19322 sym->flags |= BSF_KEEP;
19323}
19324
5522f910
NC		 19325#undef elf_backend_copy_special_section_fields
19326#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19327
252b5132 19328#define ELF_ARCH bfd_arch_arm
ae95ffa6 19329#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19330#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19331#ifdef __QNXTARGET__
19332#define ELF_MAXPAGESIZE 0x1000
19333#else
7572ca89 19334#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19335#endif
b1342370 19336#define ELF_MINPAGESIZE 0x1000
24718e3b 19337#define ELF_COMMONPAGESIZE 0x1000
252b5132 19338
ba93b8ac
DJ		 19339#define bfd_elf32_mkobject elf32_arm_mkobject
19340
99e4ae17
AJ		 19341#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19342#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19343#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19344#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19345#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19346#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19347#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19348#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19349#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19350#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19351#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19352#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19353#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19354
19355#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19356#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19357#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19358#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19359#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19360#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19361#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19362#define elf_backend_write_section elf32_arm_write_section
252b5132 19363#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19364#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19365#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19366#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19367#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19368#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19369#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19370#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19371#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19372#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19373#define elf_backend_fake_sections elf32_arm_fake_sections
19374#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19375#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19376#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19377#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19378#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19379#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19380#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19381#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19382#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19383#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19384#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19385#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19386
19387#define elf_backend_can_refcount 1
19388#define elf_backend_can_gc_sections 1
19389#define elf_backend_plt_readonly 1
19390#define elf_backend_want_got_plt 1
19391#define elf_backend_want_plt_sym 0
19392#define elf_backend_may_use_rel_p 1
19393#define elf_backend_may_use_rela_p 0
4e7fd91e 19394#define elf_backend_default_use_rela_p 0
64f52338 19395#define elf_backend_dtrel_excludes_plt 1
252b5132 19396
04f7c78d 19397#define elf_backend_got_header_size 12
b68a20d6 19398#define elf_backend_extern_protected_data 1
04f7c78d 19399
906e58ca
NC		 19400#undef elf_backend_obj_attrs_vendor
19401#define elf_backend_obj_attrs_vendor "aeabi"
19402#undef elf_backend_obj_attrs_section
19403#define elf_backend_obj_attrs_section ".ARM.attributes"
19404#undef elf_backend_obj_attrs_arg_type
19405#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19406#undef elf_backend_obj_attrs_section_type
104d59d1 19407#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19408#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19409#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19410
5025eb7c 19411#undef elf_backend_section_flags
ac4c9b04 19412#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19413#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19414#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19415
252b5132 19416#include "elf32-target.h"
7f266840 19417
b38cadfb
NC		 19418/* Native Client targets. */
19419
19420#undef TARGET_LITTLE_SYM
6d00b590 19421#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19422#undef TARGET_LITTLE_NAME
19423#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19424#undef TARGET_BIG_SYM
6d00b590 19425#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19426#undef TARGET_BIG_NAME
19427#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19428
19429/* Like elf32_arm_link_hash_table_create -- but overrides
19430 appropriately for NaCl. */
19431
19432static struct bfd_link_hash_table *
19433elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19434{
19435 struct bfd_link_hash_table *ret;
19436
19437 ret = elf32_arm_link_hash_table_create (abfd);
19438 if (ret)
19439 {
19440 struct elf32_arm_link_hash_table *htab
19441 = (struct elf32_arm_link_hash_table *) ret;
19442
19443 htab->nacl_p = 1;
19444
19445 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19446 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19447 }
19448 return ret;
19449}
19450
19451/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19452 really need to use elf32_arm_modify_segment_map. But we do it
19453 anyway just to reduce gratuitous differences with the stock ARM backend. */
19454
19455static bfd_boolean
19456elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19457{
19458 return (elf32_arm_modify_segment_map (abfd, info)
19459 && nacl_modify_segment_map (abfd, info));
19460}
19461
887badb3
RM		 19462static void
19463elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19464{
19465 elf32_arm_final_write_processing (abfd, linker);
19466 nacl_final_write_processing (abfd, linker);
19467}
19468
6a631e86
YG		 19469static bfd_vma
19470elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19471 const arelent *rel ATTRIBUTE_UNUSED)
19472{
19473 return plt->vma
19474 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19475 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19476}
887badb3 19477
b38cadfb 19478#undef elf32_bed
6a631e86 19479#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19480#undef bfd_elf32_bfd_link_hash_table_create
19481#define bfd_elf32_bfd_link_hash_table_create \
19482 elf32_arm_nacl_link_hash_table_create
19483#undef elf_backend_plt_alignment
6a631e86 19484#define elf_backend_plt_alignment 4
b38cadfb
NC		 19485#undef elf_backend_modify_segment_map
19486#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19487#undef elf_backend_modify_program_headers
19488#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19489#undef elf_backend_final_write_processing
19490#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19491#undef bfd_elf32_get_synthetic_symtab
19492#undef elf_backend_plt_sym_val
19493#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19494#undef elf_backend_copy_special_section_fields
b38cadfb 19495
887badb3
RM		 19496#undef ELF_MINPAGESIZE
19497#undef ELF_COMMONPAGESIZE
19498
b38cadfb
NC		 19499
19500#include "elf32-target.h"
19501
19502/* Reset to defaults. */
19503#undef elf_backend_plt_alignment
19504#undef elf_backend_modify_segment_map
19505#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19506#undef elf_backend_modify_program_headers
887badb3
RM		 19507#undef elf_backend_final_write_processing
19508#define elf_backend_final_write_processing elf32_arm_final_write_processing
19509#undef ELF_MINPAGESIZE
19510#define ELF_MINPAGESIZE 0x1000
19511#undef ELF_COMMONPAGESIZE
19512#define ELF_COMMONPAGESIZE 0x1000
19513
b38cadfb 19514
906e58ca 19515/* VxWorks Targets. */
4e7fd91e 19516
906e58ca 19517#undef TARGET_LITTLE_SYM
6d00b590 19518#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19519#undef TARGET_LITTLE_NAME
4e7fd91e 19520#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19521#undef TARGET_BIG_SYM
6d00b590 19522#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19523#undef TARGET_BIG_NAME
4e7fd91e
PB		 19524#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19525
19526/* Like elf32_arm_link_hash_table_create -- but overrides
19527 appropriately for VxWorks. */
906e58ca 19528
4e7fd91e
PB		 19529static struct bfd_link_hash_table *
19530elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19531{
19532 struct bfd_link_hash_table *ret;
19533
19534 ret = elf32_arm_link_hash_table_create (abfd);
19535 if (ret)
19536 {
19537 struct elf32_arm_link_hash_table *htab
00a97672 19538 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19539 htab->use_rel = 0;
00a97672 19540 htab->vxworks_p = 1;
4e7fd91e
PB		 19541 }
19542 return ret;
906e58ca 19543}
4e7fd91e 19544
00a97672
RS		 19545static void
19546elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19547{
19548 elf32_arm_final_write_processing (abfd, linker);
19549 elf_vxworks_final_write_processing (abfd, linker);
19550}
19551
906e58ca 19552#undef elf32_bed
4e7fd91e
PB		 19553#define elf32_bed elf32_arm_vxworks_bed
19554
906e58ca
NC		 19555#undef bfd_elf32_bfd_link_hash_table_create
19556#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19557#undef elf_backend_final_write_processing
19558#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19559#undef elf_backend_emit_relocs
9eaff861 19560#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19561
906e58ca 19562#undef elf_backend_may_use_rel_p
00a97672 19563#define elf_backend_may_use_rel_p 0
906e58ca 19564#undef elf_backend_may_use_rela_p
00a97672 19565#define elf_backend_may_use_rela_p 1
906e58ca 19566#undef elf_backend_default_use_rela_p
00a97672 19567#define elf_backend_default_use_rela_p 1
906e58ca 19568#undef elf_backend_want_plt_sym
00a97672 19569#define elf_backend_want_plt_sym 1
906e58ca 19570#undef ELF_MAXPAGESIZE
00a97672 19571#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19572
19573#include "elf32-target.h"
19574
19575
21d799b5
NC		 19576/* Merge backend specific data from an object file to the output
19577 object file when linking. */
19578
19579static bfd_boolean
50e03d47 19580elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19581{
50e03d47 19582 bfd *obfd = info->output_bfd;
21d799b5
NC		 19583 flagword out_flags;
19584 flagword in_flags;
19585 bfd_boolean flags_compatible = TRUE;
19586 asection *sec;
19587
cc643b88 19588 /* Check if we have the same endianness. */
50e03d47 19589 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19590 return FALSE;
19591
19592 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19593 return TRUE;
19594
50e03d47 19595 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19596 return FALSE;
19597
19598 /* The input BFD must have had its flags initialised. */
19599 /* The following seems bogus to me -- The flags are initialized in
19600 the assembler but I don't think an elf_flags_init field is
19601 written into the object. */
19602 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19603
19604 in_flags = elf_elfheader (ibfd)->e_flags;
19605 out_flags = elf_elfheader (obfd)->e_flags;
19606
19607 /* In theory there is no reason why we couldn't handle this. However
19608 in practice it isn't even close to working and there is no real
19609 reason to want it. */
19610 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19611 && !(ibfd->flags & DYNAMIC)
19612 && (in_flags & EF_ARM_BE8))
19613 {
19614 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19615 ibfd);
19616 return FALSE;
19617 }
19618
19619 if (!elf_flags_init (obfd))
19620 {
19621 /* If the input is the default architecture and had the default
19622 flags then do not bother setting the flags for the output
19623 architecture, instead allow future merges to do this. If no
19624 future merges ever set these flags then they will retain their
99059e56
RM		 19625 uninitialised values, which surprise surprise, correspond
19626 to the default values. */
21d799b5
NC		 19627 if (bfd_get_arch_info (ibfd)->the_default
19628 && elf_elfheader (ibfd)->e_flags == 0)
19629 return TRUE;
19630
19631 elf_flags_init (obfd) = TRUE;
19632 elf_elfheader (obfd)->e_flags = in_flags;
19633
19634 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19635 && bfd_get_arch_info (obfd)->the_default)
19636 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19637
19638 return TRUE;
19639 }
19640
19641 /* Determine what should happen if the input ARM architecture
19642 does not match the output ARM architecture. */
19643 if (! bfd_arm_merge_machines (ibfd, obfd))
19644 return FALSE;
19645
19646 /* Identical flags must be compatible. */
19647 if (in_flags == out_flags)
19648 return TRUE;
19649
19650 /* Check to see if the input BFD actually contains any sections. If
19651 not, its flags may not have been initialised either, but it
19652 cannot actually cause any incompatiblity. Do not short-circuit
19653 dynamic objects; their section list may be emptied by
19654 elf_link_add_object_symbols.
19655
19656 Also check to see if there are no code sections in the input.
19657 In this case there is no need to check for code specific flags.
19658 XXX - do we need to worry about floating-point format compatability
19659 in data sections ? */
19660 if (!(ibfd->flags & DYNAMIC))
19661 {
19662 bfd_boolean null_input_bfd = TRUE;
19663 bfd_boolean only_data_sections = TRUE;
19664
19665 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19666 {
19667 /* Ignore synthetic glue sections. */
19668 if (strcmp (sec->name, ".glue_7")
19669 && strcmp (sec->name, ".glue_7t"))
19670 {
19671 if ((bfd_get_section_flags (ibfd, sec)
19672 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19673 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19674 only_data_sections = FALSE;
21d799b5
NC		 19675
19676 null_input_bfd = FALSE;
19677 break;
19678 }
19679 }
19680
19681 if (null_input_bfd || only_data_sections)
19682 return TRUE;
19683 }
19684
19685 /* Complain about various flag mismatches. */
19686 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19687 EF_ARM_EABI_VERSION (out_flags)))
19688 {
19689 _bfd_error_handler
19690 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19691 ibfd, obfd,
19692 (in_flags & EF_ARM_EABIMASK) >> 24,
19693 (out_flags & EF_ARM_EABIMASK) >> 24);
19694 return FALSE;
19695 }
19696
19697 /* Not sure what needs to be checked for EABI versions >= 1. */
19698 /* VxWorks libraries do not use these flags. */
19699 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19700 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19701 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19702 {
19703 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19704 {
19705 _bfd_error_handler
19706 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19707 ibfd, obfd,
19708 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19709 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19710 flags_compatible = FALSE;
19711 }
19712
19713 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19714 {
19715 if (in_flags & EF_ARM_APCS_FLOAT)
19716 _bfd_error_handler
19717 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19718 ibfd, obfd);
19719 else
19720 _bfd_error_handler
19721 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19722 ibfd, obfd);
19723
19724 flags_compatible = FALSE;
19725 }
19726
19727 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19728 {
19729 if (in_flags & EF_ARM_VFP_FLOAT)
19730 _bfd_error_handler
19731 (_("error: %B uses VFP instructions, whereas %B does not"),
19732 ibfd, obfd);
19733 else
19734 _bfd_error_handler
19735 (_("error: %B uses FPA instructions, whereas %B does not"),
19736 ibfd, obfd);
19737
19738 flags_compatible = FALSE;
19739 }
19740
19741 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19742 {
19743 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19744 _bfd_error_handler
19745 (_("error: %B uses Maverick instructions, whereas %B does not"),
19746 ibfd, obfd);
19747 else
19748 _bfd_error_handler
19749 (_("error: %B does not use Maverick instructions, whereas %B does"),
19750 ibfd, obfd);
19751
19752 flags_compatible = FALSE;
19753 }
19754
19755#ifdef EF_ARM_SOFT_FLOAT
19756 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19757 {
19758 /* We can allow interworking between code that is VFP format
19759 layout, and uses either soft float or integer regs for
19760 passing floating point arguments and results. We already
19761 know that the APCS_FLOAT flags match; similarly for VFP
19762 flags. */
19763 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19764 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19765 {
19766 if (in_flags & EF_ARM_SOFT_FLOAT)
19767 _bfd_error_handler
19768 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19769 ibfd, obfd);
19770 else
19771 _bfd_error_handler
19772 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19773 ibfd, obfd);
19774
19775 flags_compatible = FALSE;
19776 }
19777 }
19778#endif
19779
19780 /* Interworking mismatch is only a warning. */
19781 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19782 {
19783 if (in_flags & EF_ARM_INTERWORK)
19784 {
19785 _bfd_error_handler
19786 (_("Warning: %B supports interworking, whereas %B does not"),
19787 ibfd, obfd);
19788 }
19789 else
19790 {
19791 _bfd_error_handler
19792 (_("Warning: %B does not support interworking, whereas %B does"),
19793 ibfd, obfd);
19794 }
19795 }
19796 }
19797
19798 return flags_compatible;
19799}
19800
19801
906e58ca 19802/* Symbian OS Targets. */
7f266840 19803
906e58ca 19804#undef TARGET_LITTLE_SYM
6d00b590 19805#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19806#undef TARGET_LITTLE_NAME
7f266840 19807#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19808#undef TARGET_BIG_SYM
6d00b590 19809#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19810#undef TARGET_BIG_NAME
7f266840
DJ		 19811#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19812
19813/* Like elf32_arm_link_hash_table_create -- but overrides
19814 appropriately for Symbian OS. */
906e58ca 19815
7f266840
DJ		 19816static struct bfd_link_hash_table *
19817elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19818{
19819 struct bfd_link_hash_table *ret;
19820
19821 ret = elf32_arm_link_hash_table_create (abfd);
19822 if (ret)
19823 {
19824 struct elf32_arm_link_hash_table *htab
19825 = (struct elf32_arm_link_hash_table *)ret;
19826 /* There is no PLT header for Symbian OS. */
19827 htab->plt_header_size = 0;
95720a86
DJ		 19828 /* The PLT entries are each one instruction and one word. */
19829 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19830 htab->symbian_p = 1;
33bfe774
JB		 19831 /* Symbian uses armv5t or above, so use_blx is always true. */
19832 htab->use_blx = 1;
67687978 19833 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19834 }
19835 return ret;
906e58ca 19836}
7f266840 19837
b35d266b 19838static const struct bfd_elf_special_section
551b43fd 19839elf32_arm_symbian_special_sections[] =
7f266840 19840{
5cd3778d
MM		 19841 /* In a BPABI executable, the dynamic linking sections do not go in
19842 the loadable read-only segment. The post-linker may wish to
19843 refer to these sections, but they are not part of the final
19844 program image. */
0112cd26
NC		 19845 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19846 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19847 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19848 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19849 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19850 /* These sections do not need to be writable as the SymbianOS
19851 postlinker will arrange things so that no dynamic relocation is
19852 required. */
0112cd26
NC		 19853 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19854 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19855 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19856 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19857};
19858
c3c76620 19859static void
906e58ca 19860elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19861 struct bfd_link_info *link_info)
c3c76620
MM		 19862{
19863 /* BPABI objects are never loaded directly by an OS kernel; they are
19864 processed by a postlinker first, into an OS-specific format. If
19865 the D_PAGED bit is set on the file, BFD will align segments on
19866 page boundaries, so that an OS can directly map the file. With
19867 BPABI objects, that just results in wasted space. In addition,
19868 because we clear the D_PAGED bit, map_sections_to_segments will
19869 recognize that the program headers should not be mapped into any
19870 loadable segment. */
19871 abfd->flags &= ~D_PAGED;
906e58ca 19872 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19873}
7f266840
DJ		 19874
19875static bfd_boolean
906e58ca 19876elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19877 struct bfd_link_info *info)
7f266840
DJ		 19878{
19879 struct elf_segment_map *m;
19880 asection *dynsec;
19881
7f266840
DJ		 19882 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19883 segment. However, because the .dynamic section is not marked
19884 with SEC_LOAD, the generic ELF code will not create such a
19885 segment. */
19886 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19887 if (dynsec)
19888 {
12bd6957 19889 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19890 if (m->p_type == PT_DYNAMIC)
19891 break;
19892
19893 if (m == NULL)
19894 {
19895 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19896 m->next = elf_seg_map (abfd);
19897 elf_seg_map (abfd) = m;
8ded5a0f 19898 }
7f266840
DJ		 19899 }
19900
b294bdf8
MM		 19901 /* Also call the generic arm routine. */
19902 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19903}
19904
95720a86
DJ		 19905/* Return address for Ith PLT stub in section PLT, for relocation REL
19906 or (bfd_vma) -1 if it should not be included. */
19907
19908static bfd_vma
19909elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19910 const arelent *rel ATTRIBUTE_UNUSED)
19911{
19912 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19913}
19914
8029a119 19915#undef elf32_bed
7f266840
DJ		 19916#define elf32_bed elf32_arm_symbian_bed
19917
19918/* The dynamic sections are not allocated on SymbianOS; the postlinker
19919 will process them and then discard them. */
906e58ca 19920#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19921#define ELF_DYNAMIC_SEC_FLAGS \
19922 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19923
9eaff861 19924#undef elf_backend_emit_relocs
c3c76620 19925
906e58ca
NC		 19926#undef bfd_elf32_bfd_link_hash_table_create
19927#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19928#undef elf_backend_special_sections
19929#define elf_backend_special_sections elf32_arm_symbian_special_sections
19930#undef elf_backend_begin_write_processing
19931#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19932#undef elf_backend_final_write_processing
19933#define elf_backend_final_write_processing elf32_arm_final_write_processing
19934
19935#undef elf_backend_modify_segment_map
7f266840
DJ		 19936#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19937
19938/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19939#undef elf_backend_got_header_size
7f266840
DJ		 19940#define elf_backend_got_header_size 0
19941
19942/* Similarly, there is no .got.plt section. */
906e58ca 19943#undef elf_backend_want_got_plt
7f266840
DJ		 19944#define elf_backend_want_got_plt 0
19945
906e58ca 19946#undef elf_backend_plt_sym_val
95720a86
DJ		 19947#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19948
906e58ca 19949#undef elf_backend_may_use_rel_p
00a97672 19950#define elf_backend_may_use_rel_p 1
906e58ca 19951#undef elf_backend_may_use_rela_p
00a97672 19952#define elf_backend_may_use_rela_p 0
906e58ca 19953#undef elf_backend_default_use_rela_p
00a97672 19954#define elf_backend_default_use_rela_p 0
906e58ca 19955#undef elf_backend_want_plt_sym
00a97672 19956#define elf_backend_want_plt_sym 0
64f52338
AM		 19957#undef elf_backend_dtrel_excludes_plt
19958#define elf_backend_dtrel_excludes_plt 0
906e58ca 19959#undef ELF_MAXPAGESIZE
00a97672 19960#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19961
7f266840 19962#include "elf32-target.h"
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