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Make compare-sections work against all targets; add compare-sections [-r] tests.
[thirdparty/binutils-gdb.git] / bfd / elf32-msp430.c
CommitLineData
2469cfa2 1/* MSP430-specific support for 32-bit ELF
4b95cf5c 2 Copyright (C) 2002-2014 Free Software Foundation, Inc.
2469cfa2
NC		 3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
2469cfa2
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
2469cfa2 21
2469cfa2 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
2469cfa2
NC		 24#include "libiberty.h"
25#include "libbfd.h"
26#include "elf-bfd.h"
27#include "elf/msp430.h"
28
2469cfa2
NC		 29static reloc_howto_type elf_msp430_howto_table[] =
30{
31 HOWTO (R_MSP430_NONE, /* type */
32 0, /* rightshift */
33 2, /* size (0 = byte, 1 = short, 2 = long) */
34 32, /* bitsize */
35 FALSE, /* pc_relative */
36 0, /* bitpos */
b18c562e 37 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 38 bfd_elf_generic_reloc, /* special_function */
39 "R_MSP430_NONE", /* name */
40 FALSE, /* partial_inplace */
41 0, /* src_mask */
42 0, /* dst_mask */
43 FALSE), /* pcrel_offset */
44
45 HOWTO (R_MSP430_32, /* type */
46 0, /* rightshift */
47 2, /* size (0 = byte, 1 = short, 2 = long) */
48 32, /* bitsize */
49 FALSE, /* pc_relative */
50 0, /* bitpos */
b18c562e 51 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 52 bfd_elf_generic_reloc, /* special_function */
53 "R_MSP430_32", /* name */
54 FALSE, /* partial_inplace */
55 0xffffffff, /* src_mask */
56 0xffffffff, /* dst_mask */
57 FALSE), /* pcrel_offset */
58
df301bfc 59 /* A 10 bit PC relative relocation. */
2469cfa2
NC		 60 HOWTO (R_MSP430_10_PCREL, /* type */
61 1, /* rightshift */
62 1, /* size (0 = byte, 1 = short, 2 = long) */
63 10, /* bitsize */
64 TRUE, /* pc_relative */
65 0, /* bitpos */
b18c562e 66 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2 67 bfd_elf_generic_reloc, /* special_function */
13761a11 68 "R_MSP430_10_PCREL", /* name */
2469cfa2 69 FALSE, /* partial_inplace */
df301bfc
NC		 70 0x3ff, /* src_mask */
71 0x3ff, /* dst_mask */
2469cfa2
NC		 72 TRUE), /* pcrel_offset */
73
74 /* A 16 bit absolute relocation. */
75 HOWTO (R_MSP430_16, /* type */
76 0, /* rightshift */
77 1, /* size (0 = byte, 1 = short, 2 = long) */
78 16, /* bitsize */
79 FALSE, /* pc_relative */
80 0, /* bitpos */
81 complain_overflow_dont,/* complain_on_overflow */
82 bfd_elf_generic_reloc, /* special_function */
83 "R_MSP430_16", /* name */
84 FALSE, /* partial_inplace */
b18c562e 85 0, /* src_mask */
2469cfa2
NC		 86 0xffff, /* dst_mask */
87 FALSE), /* pcrel_offset */
88
13761a11 89 /* A 16 bit PC relative relocation for command address. */
2469cfa2
NC		 90 HOWTO (R_MSP430_16_PCREL, /* type */
91 1, /* rightshift */
92 1, /* size (0 = byte, 1 = short, 2 = long) */
93 16, /* bitsize */
94 TRUE, /* pc_relative */
95 0, /* bitpos */
96 complain_overflow_dont,/* complain_on_overflow */
97 bfd_elf_generic_reloc, /* special_function */
98 "R_MSP430_16_PCREL", /* name */
99 FALSE, /* partial_inplace */
b18c562e 100 0, /* src_mask */
2469cfa2
NC		 101 0xffff, /* dst_mask */
102 TRUE), /* pcrel_offset */
103
104 /* A 16 bit absolute relocation, byte operations. */
105 HOWTO (R_MSP430_16_BYTE, /* type */
106 0, /* rightshift */
107 1, /* size (0 = byte, 1 = short, 2 = long) */
108 16, /* bitsize */
109 FALSE, /* pc_relative */
110 0, /* bitpos */
111 complain_overflow_dont,/* complain_on_overflow */
112 bfd_elf_generic_reloc, /* special_function */
113 "R_MSP430_16_BYTE", /* name */
114 FALSE, /* partial_inplace */
115 0xffff, /* src_mask */
116 0xffff, /* dst_mask */
117 FALSE), /* pcrel_offset */
118
119 /* A 16 bit absolute relocation for command address. */
120 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
121 1, /* rightshift */
122 1, /* size (0 = byte, 1 = short, 2 = long) */
123 16, /* bitsize */
124 TRUE, /* pc_relative */
125 0, /* bitpos */
126 complain_overflow_dont,/* complain_on_overflow */
127 bfd_elf_generic_reloc, /* special_function */
b18c562e 128 "R_MSP430_16_PCREL_BYTE",/* name */
2469cfa2
NC		 129 FALSE, /* partial_inplace */
130 0xffff, /* src_mask */
131 0xffff, /* dst_mask */
b18c562e
NC		 132 TRUE), /* pcrel_offset */
133
df301bfc 134 /* A 10 bit PC relative relocation for complicated polymorphs. */
b18c562e
NC		 135 HOWTO (R_MSP430_2X_PCREL, /* type */
136 1, /* rightshift */
137 2, /* size (0 = byte, 1 = short, 2 = long) */
138 10, /* bitsize */
139 TRUE, /* pc_relative */
140 0, /* bitpos */
141 complain_overflow_bitfield,/* complain_on_overflow */
142 bfd_elf_generic_reloc, /* special_function */
143 "R_MSP430_2X_PCREL", /* name */
144 FALSE, /* partial_inplace */
df301bfc
NC		 145 0x3ff, /* src_mask */
146 0x3ff, /* dst_mask */
b18c562e
NC		 147 TRUE), /* pcrel_offset */
148
149 /* A 16 bit relaxable relocation for command address. */
150 HOWTO (R_MSP430_RL_PCREL, /* type */
151 1, /* rightshift */
152 1, /* size (0 = byte, 1 = short, 2 = long) */
153 16, /* bitsize */
154 TRUE, /* pc_relative */
155 0, /* bitpos */
156 complain_overflow_dont,/* complain_on_overflow */
157 bfd_elf_generic_reloc, /* special_function */
158 "R_MSP430_RL_PCREL", /* name */
159 FALSE, /* partial_inplace */
160 0, /* src_mask */
161 0xffff, /* dst_mask */
2469cfa2 162 TRUE) /* pcrel_offset */
13761a11
NC		 163
164 /* A 8-bit absolute relocation. */
165 , HOWTO (R_MSP430_8, /* type */
166 0, /* rightshift */
167 0, /* size (0 = byte, 1 = short, 2 = long) */
168 8, /* bitsize */
169 FALSE, /* pc_relative */
170 0, /* bitpos */
171 complain_overflow_dont,/* complain_on_overflow */
172 bfd_elf_generic_reloc, /* special_function */
173 "R_MSP430_8", /* name */
174 FALSE, /* partial_inplace */
175 0, /* src_mask */
176 0xffff, /* dst_mask */
177 FALSE), /* pcrel_offset */
178
179 /* Together with a following reloc, allows for the difference
180 between two symbols to be the real addend of the second reloc. */
181 HOWTO (R_MSP430_SYM_DIFF, /* type */
182 0, /* rightshift */
183 2, /* size (0 = byte, 1 = short, 2 = long) */
184 32, /* bitsize */
185 FALSE, /* pc_relative */
186 0, /* bitpos */
187 complain_overflow_dont,/* complain_on_overflow */
188 NULL, /* special handler. */
189 "R_MSP430_SYM_DIFF", /* name */
190 FALSE, /* partial_inplace */
191 0xffffffff, /* src_mask */
192 0xffffffff, /* dst_mask */
193 FALSE) /* pcrel_offset */
194};
195
196static reloc_howto_type elf_msp430x_howto_table[] =
197{
198 HOWTO (R_MSP430_NONE, /* type */
199 0, /* rightshift */
200 2, /* size (0 = byte, 1 = short, 2 = long) */
201 32, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_MSP430_NONE", /* name */
207 FALSE, /* partial_inplace */
208 0, /* src_mask */
209 0, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_MSP430_ABS32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_bitfield,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_MSP430_ABS32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
226 HOWTO (R_MSP430_ABS16, /* type */
227 0, /* rightshift */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
230 FALSE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_dont,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
234 "R_MSP430_ABS16", /* name */
235 FALSE, /* partial_inplace */
236 0, /* src_mask */
237 0xffff, /* dst_mask */
238 FALSE), /* pcrel_offset */
239
240 HOWTO (R_MSP430_ABS8, /* type */
241 0, /* rightshift */
242 0, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 FALSE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_bitfield,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_MSP430_ABS8", /* name */
249 FALSE, /* partial_inplace */
250 0xff, /* src_mask */
251 0xff, /* dst_mask */
252 FALSE), /* pcrel_offset */
253
254 HOWTO (R_MSP430_PCR16, /* type */
255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
257 16, /* bitsize */
258 TRUE, /* pc_relative */
259 0, /* bitpos */
260 complain_overflow_dont,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
262 "R_MSP430_PCR16", /* name */
263 FALSE, /* partial_inplace */
264 0, /* src_mask */
265 0xffff, /* dst_mask */
266 TRUE), /* pcrel_offset */
267
268 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
269 0, /* rightshift */
270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
272 TRUE, /* pc_relative */
273 0, /* bitpos */
274 complain_overflow_dont,/* complain_on_overflow */
275 bfd_elf_generic_reloc, /* special_function */
276 "R_MSP430X_PCR20_EXT_SRC",/* name */
277 FALSE, /* partial_inplace */
278 0, /* src_mask */
279 0xffff, /* dst_mask */
280 TRUE), /* pcrel_offset */
281
282 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
283 0, /* rightshift */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
285 32, /* bitsize */
286 TRUE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_dont,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_MSP430X_PCR20_EXT_DST",/* name */
291 FALSE, /* partial_inplace */
292 0, /* src_mask */
293 0xffff, /* dst_mask */
294 TRUE), /* pcrel_offset */
295
296 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_dont,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_MSP430X_PCR20_EXT_ODST",/* name */
305 FALSE, /* partial_inplace */
306 0, /* src_mask */
307 0xffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
314 TRUE, /* pc_relative */
315 0, /* bitpos */
316 complain_overflow_dont,/* complain_on_overflow */
317 bfd_elf_generic_reloc, /* special_function */
318 "R_MSP430X_ABS20_EXT_SRC",/* name */
319 FALSE, /* partial_inplace */
320 0, /* src_mask */
321 0xffff, /* dst_mask */
322 TRUE), /* pcrel_offset */
323
324 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
328 TRUE, /* pc_relative */
329 0, /* bitpos */
330 complain_overflow_dont,/* complain_on_overflow */
331 bfd_elf_generic_reloc, /* special_function */
332 "R_MSP430X_ABS20_EXT_DST",/* name */
333 FALSE, /* partial_inplace */
334 0, /* src_mask */
335 0xffff, /* dst_mask */
336 TRUE), /* pcrel_offset */
337
338 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
342 TRUE, /* pc_relative */
343 0, /* bitpos */
344 complain_overflow_dont,/* complain_on_overflow */
345 bfd_elf_generic_reloc, /* special_function */
346 "R_MSP430X_ABS20_EXT_ODST",/* name */
347 FALSE, /* partial_inplace */
348 0, /* src_mask */
349 0xffff, /* dst_mask */
350 TRUE), /* pcrel_offset */
351
352 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
353 0, /* rightshift */
354 2, /* size (0 = byte, 1 = short, 2 = long) */
355 32, /* bitsize */
356 TRUE, /* pc_relative */
357 0, /* bitpos */
358 complain_overflow_dont,/* complain_on_overflow */
359 bfd_elf_generic_reloc, /* special_function */
360 "R_MSP430X_ABS20_ADR_SRC",/* name */
361 FALSE, /* partial_inplace */
362 0, /* src_mask */
363 0xffff, /* dst_mask */
364 TRUE), /* pcrel_offset */
365
366 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
367 0, /* rightshift */
368 2, /* size (0 = byte, 1 = short, 2 = long) */
369 32, /* bitsize */
370 TRUE, /* pc_relative */
371 0, /* bitpos */
372 complain_overflow_dont,/* complain_on_overflow */
373 bfd_elf_generic_reloc, /* special_function */
374 "R_MSP430X_ABS20_ADR_DST",/* name */
375 FALSE, /* partial_inplace */
376 0, /* src_mask */
377 0xffff, /* dst_mask */
378 TRUE), /* pcrel_offset */
379
380 HOWTO (R_MSP430X_PCR16, /* type */
381 0, /* rightshift */
382 2, /* size (0 = byte, 1 = short, 2 = long) */
383 32, /* bitsize */
384 TRUE, /* pc_relative */
385 0, /* bitpos */
386 complain_overflow_dont,/* complain_on_overflow */
387 bfd_elf_generic_reloc, /* special_function */
388 "R_MSP430X_PCR16", /* name */
389 FALSE, /* partial_inplace */
390 0, /* src_mask */
391 0xffff, /* dst_mask */
392 TRUE), /* pcrel_offset */
393
394 HOWTO (R_MSP430X_PCR20_CALL, /* type */
395 0, /* rightshift */
396 2, /* size (0 = byte, 1 = short, 2 = long) */
397 32, /* bitsize */
398 TRUE, /* pc_relative */
399 0, /* bitpos */
400 complain_overflow_dont,/* complain_on_overflow */
401 bfd_elf_generic_reloc, /* special_function */
402 "R_MSP430X_PCR20_CALL",/* name */
403 FALSE, /* partial_inplace */
404 0, /* src_mask */
405 0xffff, /* dst_mask */
406 TRUE), /* pcrel_offset */
407
408 HOWTO (R_MSP430X_ABS16, /* type */
409 0, /* rightshift */
410 2, /* size (0 = byte, 1 = short, 2 = long) */
411 32, /* bitsize */
412 TRUE, /* pc_relative */
413 0, /* bitpos */
414 complain_overflow_dont,/* complain_on_overflow */
415 bfd_elf_generic_reloc, /* special_function */
416 "R_MSP430X_ABS16", /* name */
417 FALSE, /* partial_inplace */
418 0, /* src_mask */
419 0xffff, /* dst_mask */
420 TRUE), /* pcrel_offset */
421
422 HOWTO (R_MSP430_ABS_HI16, /* type */
423 0, /* rightshift */
424 2, /* size (0 = byte, 1 = short, 2 = long) */
425 32, /* bitsize */
426 TRUE, /* pc_relative */
427 0, /* bitpos */
428 complain_overflow_dont,/* complain_on_overflow */
429 bfd_elf_generic_reloc, /* special_function */
430 "R_MSP430_ABS_HI16", /* name */
431 FALSE, /* partial_inplace */
432 0, /* src_mask */
433 0xffff, /* dst_mask */
434 TRUE), /* pcrel_offset */
435
436 HOWTO (R_MSP430_PREL31, /* type */
437 0, /* rightshift */
438 2, /* size (0 = byte, 1 = short, 2 = long) */
439 32, /* bitsize */
440 TRUE, /* pc_relative */
441 0, /* bitpos */
442 complain_overflow_dont,/* complain_on_overflow */
443 bfd_elf_generic_reloc, /* special_function */
444 "R_MSP430_PREL31", /* name */
445 FALSE, /* partial_inplace */
446 0, /* src_mask */
447 0xffff, /* dst_mask */
448 TRUE), /* pcrel_offset */
449
450 EMPTY_HOWTO (R_MSP430_EHTYPE),
451
df301bfc 452 /* A 10 bit PC relative relocation. */
13761a11
NC		 453 HOWTO (R_MSP430X_10_PCREL, /* type */
454 1, /* rightshift */
455 1, /* size (0 = byte, 1 = short, 2 = long) */
456 10, /* bitsize */
457 TRUE, /* pc_relative */
458 0, /* bitpos */
459 complain_overflow_bitfield,/* complain_on_overflow */
460 bfd_elf_generic_reloc, /* special_function */
461 "R_MSP430X_10_PCREL", /* name */
462 FALSE, /* partial_inplace */
df301bfc
NC		 463 0x3ff, /* src_mask */
464 0x3ff, /* dst_mask */
13761a11
NC		 465 TRUE), /* pcrel_offset */
466
df301bfc 467 /* A 10 bit PC relative relocation for complicated polymorphs. */
13761a11
NC		 468 HOWTO (R_MSP430X_2X_PCREL, /* type */
469 1, /* rightshift */
470 2, /* size (0 = byte, 1 = short, 2 = long) */
471 10, /* bitsize */
472 TRUE, /* pc_relative */
473 0, /* bitpos */
474 complain_overflow_bitfield,/* complain_on_overflow */
475 bfd_elf_generic_reloc, /* special_function */
476 "R_MSP430X_2X_PCREL", /* name */
477 FALSE, /* partial_inplace */
df301bfc
NC		 478 0x3ff, /* src_mask */
479 0x3ff, /* dst_mask */
13761a11
NC		 480 TRUE), /* pcrel_offset */
481
482 /* Together with a following reloc, allows for the difference
483 between two symbols to be the real addend of the second reloc. */
484 HOWTO (R_MSP430X_SYM_DIFF, /* type */
485 0, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 32, /* bitsize */
488 FALSE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_dont,/* complain_on_overflow */
491 NULL, /* special handler. */
492 "R_MSP430X_SYM_DIFF", /* name */
493 FALSE, /* partial_inplace */
494 0xffffffff, /* src_mask */
495 0xffffffff, /* dst_mask */
496 FALSE) /* pcrel_offset */
2469cfa2
NC		 497};
498
499/* Map BFD reloc types to MSP430 ELF reloc types. */
500
501struct msp430_reloc_map
502{
503 bfd_reloc_code_real_type bfd_reloc_val;
504 unsigned int elf_reloc_val;
505};
506
507static const struct msp430_reloc_map msp430_reloc_map[] =
13761a11
NC		 508{
509 {BFD_RELOC_NONE, R_MSP430_NONE},
510 {BFD_RELOC_32, R_MSP430_32},
511 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
512 {BFD_RELOC_16, R_MSP430_16_BYTE},
513 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
514 {BFD_RELOC_MSP430_16, R_MSP430_16},
515 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
516 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
517 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
518 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
519 {BFD_RELOC_8, R_MSP430_8},
520 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
521};
522
523static const struct msp430_reloc_map msp430x_reloc_map[] =
524{
525 {BFD_RELOC_NONE, R_MSP430_NONE},
526 {BFD_RELOC_32, R_MSP430_ABS32},
527 {BFD_RELOC_16, R_MSP430_ABS16},
528 {BFD_RELOC_8, R_MSP430_ABS8},
529 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
530 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
531 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
532 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
533 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
534 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
535 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
536 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
537 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
538 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
539 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
540 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
541 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
542 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
543 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
544 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
545 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
546 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
547};
548
549static inline bfd_boolean
550uses_msp430x_relocs (bfd * abfd)
551{
6d00b590 552 extern const bfd_target msp430_elf32_ti_vec;
13761a11
NC		 553
554 return bfd_get_mach (abfd) == bfd_mach_msp430x
6d00b590 555 || abfd->xvec == & msp430_elf32_ti_vec;
13761a11 556}
2469cfa2
NC		 557
558static reloc_howto_type *
b18c562e
NC		 559bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
560 bfd_reloc_code_real_type code)
2469cfa2
NC		 561{
562 unsigned int i;
563
13761a11
NC		 564 if (uses_msp430x_relocs (abfd))
565 {
566 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
567 if (msp430x_reloc_map[i].bfd_reloc_val == code)
568 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
569 }
570 else
571 {
572 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
573 if (msp430_reloc_map[i].bfd_reloc_val == code)
574 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
575 }
2469cfa2
NC		 576
577 return NULL;
578}
579
157090f7
AM		 580static reloc_howto_type *
581bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
582 const char *r_name)
583{
584 unsigned int i;
585
13761a11
NC		 586 if (uses_msp430x_relocs (abfd))
587 {
588 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
589 if (elf_msp430x_howto_table[i].name != NULL
590 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
591 return elf_msp430x_howto_table + i;
592 }
593 else
594 {
595 for (i = 0;
596 i < (sizeof (elf_msp430_howto_table)
597 / sizeof (elf_msp430_howto_table[0]));
598 i++)
599 if (elf_msp430_howto_table[i].name != NULL
600 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
601 return &elf_msp430_howto_table[i];
602 }
157090f7
AM		 603
604 return NULL;
605}
606
2469cfa2
NC		 607/* Set the howto pointer for an MSP430 ELF reloc. */
608
609static void
b18c562e
NC		 610msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
611 arelent * cache_ptr,
612 Elf_Internal_Rela * dst)
2469cfa2
NC		 613{
614 unsigned int r_type;
615
616 r_type = ELF32_R_TYPE (dst->r_info);
13761a11
NC		 617
618 if (uses_msp430x_relocs (abfd))
619 {
620 BFD_ASSERT (r_type < (unsigned int) R_MSP430x_max);
621 cache_ptr->howto = elf_msp430x_howto_table + r_type;
622 return;
623 }
624
2469cfa2
NC		 625 BFD_ASSERT (r_type < (unsigned int) R_MSP430_max);
626 cache_ptr->howto = &elf_msp430_howto_table[r_type];
627}
628
2469cfa2
NC		 629/* Look through the relocs for a section during the first phase.
630 Since we don't do .gots or .plts, we just need to consider the
631 virtual table relocs for gc. */
632
633static bfd_boolean
b18c562e
NC		 634elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
635 asection * sec, const Elf_Internal_Rela * relocs)
2469cfa2
NC		 636{
637 Elf_Internal_Shdr *symtab_hdr;
5582a088 638 struct elf_link_hash_entry **sym_hashes;
2469cfa2
NC		 639 const Elf_Internal_Rela *rel;
640 const Elf_Internal_Rela *rel_end;
641
1049f94e 642 if (info->relocatable)
2469cfa2
NC		 643 return TRUE;
644
645 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
646 sym_hashes = elf_sym_hashes (abfd);
2469cfa2
NC		 647
648 rel_end = relocs + sec->reloc_count;
649 for (rel = relocs; rel < rel_end; rel++)
650 {
651 struct elf_link_hash_entry *h;
652 unsigned long r_symndx;
653
654 r_symndx = ELF32_R_SYM (rel->r_info);
655 if (r_symndx < symtab_hdr->sh_info)
656 h = NULL;
657 else
973a3492
L		 658 {
659 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
660 while (h->root.type == bfd_link_hash_indirect
661 || h->root.type == bfd_link_hash_warning)
662 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 663
664 /* PR15323, ref flags aren't set for references in the same
665 object. */
666 h->root.non_ir_ref = 1;
973a3492 667 }
2469cfa2
NC		 668 }
669
670 return TRUE;
671}
672
673/* Perform a single relocation. By default we use the standard BFD
674 routines, but a few relocs, we have to do them ourselves. */
675
676static bfd_reloc_status_type
13761a11
NC		 677msp430_final_link_relocate (reloc_howto_type * howto,
678 bfd * input_bfd,
679 asection * input_section,
680 bfd_byte * contents,
681 Elf_Internal_Rela * rel,
682 bfd_vma relocation,
683 struct bfd_link_info * info)
2469cfa2 684{
13761a11
NC		 685 static asection * sym_diff_section;
686 static bfd_vma sym_diff_value;
687
688 struct bfd_elf_section_data * esd = elf_section_data (input_section);
2469cfa2
NC		 689 bfd_reloc_status_type r = bfd_reloc_ok;
690 bfd_vma x;
691 bfd_signed_vma srel;
13761a11
NC		 692 bfd_boolean is_rel_reloc = FALSE;
693
694 if (uses_msp430x_relocs (input_bfd))
695 {
696 /* See if we have a REL type relocation. */
697 is_rel_reloc = (esd->rel.hdr != NULL);
698 /* Sanity check - only one type of relocation per section.
699 FIXME: Theoretically it is possible to have both types,
700 but if that happens how can we distinguish between the two ? */
701 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
702 /* If we are using a REL relocation then the addend should be empty. */
703 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
704 }
2469cfa2 705
13761a11 706 if (sym_diff_section != NULL)
2469cfa2 707 {
13761a11
NC		 708 BFD_ASSERT (sym_diff_section == input_section);
709
710 if (uses_msp430x_relocs (input_bfd))
711 switch (howto->type)
712 {
713 case R_MSP430_ABS32:
714 /* If we are computing a 32-bit value for the location lists
715 and the result is 0 then we add one to the value. A zero
716 value can result because of linker relaxation deleteing
717 prologue instructions and using a value of 1 (for the begin
718 and end offsets in the location list entry) results in a
719 nul entry which does not prevent the following entries from
720 being parsed. */
721 if (relocation == sym_diff_value
722 && strcmp (input_section->name, ".debug_loc") == 0)
723 ++ relocation;
724 /* Fall through. */
725 case R_MSP430_ABS16:
726 case R_MSP430X_ABS16:
727 case R_MSP430_ABS8:
728 BFD_ASSERT (! is_rel_reloc);
729 relocation -= sym_diff_value;
730 break;
731
732 default:
733 return bfd_reloc_dangerous;
734 }
735 else
736 switch (howto->type)
737 {
738 case R_MSP430_32:
739 case R_MSP430_16:
740 case R_MSP430_16_BYTE:
741 case R_MSP430_8:
742 relocation -= sym_diff_value;
743 break;
744
745 default:
746 return bfd_reloc_dangerous;
747 }
748
749 sym_diff_section = NULL;
750 }
751
752 if (uses_msp430x_relocs (input_bfd))
753 switch (howto->type)
754 {
755 case R_MSP430X_SYM_DIFF:
756 /* Cache the input section and value.
757 The offset is unreliable, since relaxation may
758 have reduced the following reloc's offset. */
759 BFD_ASSERT (! is_rel_reloc);
760 sym_diff_section = input_section;
761 sym_diff_value = relocation;
762 return bfd_reloc_ok;
763
764 case R_MSP430_ABS16:
765 contents += rel->r_offset;
766 srel = (bfd_signed_vma) relocation;
767 if (is_rel_reloc)
768 srel += bfd_get_16 (input_bfd, contents);
769 else
770 srel += rel->r_addend;
771 bfd_put_16 (input_bfd, srel & 0xffff, contents);
772 break;
773
774 case R_MSP430X_10_PCREL:
775 contents += rel->r_offset;
776 srel = (bfd_signed_vma) relocation;
777 if (is_rel_reloc)
778 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
779 else
780 srel += rel->r_addend;
781 srel -= rel->r_offset;
782 srel -= 2; /* Branch instructions add 2 to the PC... */
783 srel -= (input_section->output_section->vma +
784 input_section->output_offset);
785 if (srel & 1)
786 return bfd_reloc_outofrange;
787
788 /* MSP430 addresses commands as words. */
789 srel >>= 1;
790
791 /* Check for an overflow. */
792 if (srel < -512 || srel > 511)
793 {
794 if (info->disable_target_specific_optimizations < 0)
795 {
796 static bfd_boolean warned = FALSE;
797 if (! warned)
798 {
799 info->callbacks->warning
800 (info,
801 _("Try enabling relaxation to avoid relocation truncations"),
802 NULL, input_bfd, input_section, relocation);
803 warned = TRUE;
804 }
805 }
806 return bfd_reloc_overflow;
807 }
808
809 x = bfd_get_16 (input_bfd, contents);
810 x = (x & 0xfc00) | (srel & 0x3ff);
811 bfd_put_16 (input_bfd, x, contents);
812 break;
813
814 case R_MSP430X_PCR20_EXT_ODST:
815 /* [0,4]+[48,16] = ---F ---- FFFF */
816 contents += rel->r_offset;
817 srel = (bfd_signed_vma) relocation;
818 if (is_rel_reloc)
819 {
820 bfd_vma addend;
821 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
822 addend |= bfd_get_16 (input_bfd, contents+4);
823 srel += addend;
824
825 }
826 else
827 srel += rel->r_addend;
828 srel -= rel->r_offset;
829 srel -= (input_section->output_section->vma +
830 input_section->output_offset);
831 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
832 x = bfd_get_16 (input_bfd, contents);
833 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
834 bfd_put_16 (input_bfd, x, contents);
835 break;
836
837 case R_MSP430X_ABS20_EXT_SRC:
838 /* [7,4]+[32,16] = -78- FFFF */
839 contents += rel->r_offset;
840 srel = (bfd_signed_vma) relocation;
841 if (is_rel_reloc)
842 {
843 bfd_vma addend;
844 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
845 addend |= bfd_get_16 (input_bfd, contents+2);
846 srel += addend;
847 }
848 else
849 srel += rel->r_addend;
850 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
851 srel >>= 16;
852 x = bfd_get_16 (input_bfd, contents);
853 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
854 bfd_put_16 (input_bfd, x, contents);
855 break;
856
857 case R_MSP430_16_PCREL:
858 contents += rel->r_offset;
859 srel = (bfd_signed_vma) relocation;
860 if (is_rel_reloc)
861 srel += bfd_get_16 (input_bfd, contents);
862 else
863 srel += rel->r_addend;
864 srel -= rel->r_offset;
865 /* Only branch instructions add 2 to the PC... */
866 srel -= (input_section->output_section->vma +
867 input_section->output_offset);
868 if (srel & 1)
869 return bfd_reloc_outofrange;
870 bfd_put_16 (input_bfd, srel & 0xffff, contents);
871 break;
872
873 case R_MSP430X_PCR20_EXT_DST:
874 /* [0,4]+[32,16] = ---F FFFF */
875 contents += rel->r_offset;
876 srel = (bfd_signed_vma) relocation;
877 if (is_rel_reloc)
878 {
879 bfd_vma addend;
880 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
881 addend |= bfd_get_16 (input_bfd, contents+2);
882 srel += addend;
883 }
884 else
885 srel += rel->r_addend;
886 srel -= rel->r_offset;
887 srel -= (input_section->output_section->vma +
888 input_section->output_offset);
889 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
890 srel >>= 16;
891 x = bfd_get_16 (input_bfd, contents);
892 x = (x & 0xfff0) | (srel & 0xf);
893 bfd_put_16 (input_bfd, x, contents);
894 break;
895
896 case R_MSP430X_PCR20_EXT_SRC:
897 /* [7,4]+32,16] = -78- FFFF */
898 contents += rel->r_offset;
899 srel = (bfd_signed_vma) relocation;
900 if (is_rel_reloc)
901 {
902 bfd_vma addend;
903 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
904 addend |= bfd_get_16 (input_bfd, contents+2);
905 srel += addend;;
906 }
907 else
908 srel += rel->r_addend;
909 srel -= rel->r_offset;
910 /* Only branch instructions add 2 to the PC... */
911 srel -= (input_section->output_section->vma +
912 input_section->output_offset);
913 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
914 srel >>= 16;
915 x = bfd_get_16 (input_bfd, contents);
916 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
917 bfd_put_16 (input_bfd, x, contents);
918 break;
919
920 case R_MSP430_ABS8:
921 contents += rel->r_offset;
922 srel = (bfd_signed_vma) relocation;
923 if (is_rel_reloc)
924 srel += bfd_get_8 (input_bfd, contents);
925 else
926 srel += rel->r_addend;
927 bfd_put_8 (input_bfd, srel & 0xff, contents);
928 break;
929
930 case R_MSP430X_ABS20_EXT_DST:
931 contents += rel->r_offset;
932 srel = (bfd_signed_vma) relocation;
933 if (is_rel_reloc)
934 srel += bfd_get_16 (input_bfd, contents) & 0xf;
935 else
936 srel += rel->r_addend;
937 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
938 srel >>= 16;
939 x = bfd_get_16 (input_bfd, contents);
940 x = (x & 0xfff0) | (srel & 0xf);
941 bfd_put_16 (input_bfd, x, contents);
942 break;
943
944 case R_MSP430X_ABS20_EXT_ODST:
945 /* [0,4]+[48,16] = ---F ---- FFFF */
946 contents += rel->r_offset;
947 srel = (bfd_signed_vma) relocation;
948 if (is_rel_reloc)
949 {
950 bfd_vma addend;
951 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
952 addend |= bfd_get_16 (input_bfd, contents+4);
953 srel += addend;
954 }
955 else
956 srel += rel->r_addend;
957 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
958 srel >>= 16;
959 x = bfd_get_16 (input_bfd, contents);
960 x = (x & 0xfff0) | (srel & 0xf);
961 bfd_put_16 (input_bfd, x, contents);
962 break;
963
964 case R_MSP430X_ABS20_ADR_SRC:
965 /* [8,4]+[32,16] = -F-- FFFF */
966 contents += rel->r_offset;
967 srel = (bfd_signed_vma) relocation;
968 if (is_rel_reloc)
969 {
970 bfd_vma addend;
971
972 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
973 addend |= bfd_get_16 (input_bfd, contents+2);
974 srel += addend;
975 }
976 else
977 srel += rel->r_addend;
978 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
979 srel >>= 16;
980 x = bfd_get_16 (input_bfd, contents);
981 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
982 bfd_put_16 (input_bfd, x, contents);
983 break;
984
985 case R_MSP430X_ABS20_ADR_DST:
986 /* [0,4]+[32,16] = ---F FFFF */
987 contents += rel->r_offset;
988 srel = (bfd_signed_vma) relocation;
989 if (is_rel_reloc)
990 {
991 bfd_vma addend;
992 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
993 addend |= bfd_get_16 (input_bfd, contents+2);
994 srel += addend;
995 }
996 else
997 srel += rel->r_addend;
998 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
999 srel >>= 16;
1000 x = bfd_get_16 (input_bfd, contents);
1001 x = (x & 0xfff0) | (srel & 0xf);
1002 bfd_put_16 (input_bfd, x, contents);
1003 break;
1004
1005 case R_MSP430X_ABS16:
1006 contents += rel->r_offset;
1007 srel = (bfd_signed_vma) relocation;
1008 if (is_rel_reloc)
1009 srel += bfd_get_16 (input_bfd, contents);
1010 else
1011 srel += rel->r_addend;
1012 x = srel;
1013 if (x > 0xffff)
1014 return bfd_reloc_overflow;
1015 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1016 break;
1017
1018 case R_MSP430_ABS_HI16:
1019 /* The EABI specifies that this must be a RELA reloc. */
1020 BFD_ASSERT (! is_rel_reloc);
1021 contents += rel->r_offset;
1022 srel = (bfd_signed_vma) relocation;
1023 srel += rel->r_addend;
1024 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1025 break;
1026
1027 case R_MSP430X_PCR20_CALL:
1028 /* [0,4]+[32,16] = ---F FFFF*/
1029 contents += rel->r_offset;
1030 srel = (bfd_signed_vma) relocation;
1031 if (is_rel_reloc)
1032 {
1033 bfd_vma addend;
1034 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1035 addend |= bfd_get_16 (input_bfd, contents+2);
1036 srel += addend;
1037 }
1038 else
1039 srel += rel->r_addend;
1040 srel -= rel->r_offset;
1041 srel -= (input_section->output_section->vma +
1042 input_section->output_offset);
1043 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1044 srel >>= 16;
1045 x = bfd_get_16 (input_bfd, contents);
1046 x = (x & 0xfff0) | (srel & 0xf);
1047 bfd_put_16 (input_bfd, x, contents);
1048 break;
1049
1050 case R_MSP430X_PCR16:
1051 contents += rel->r_offset;
1052 srel = (bfd_signed_vma) relocation;
1053 if (is_rel_reloc)
1054 srel += bfd_get_16 (input_bfd, contents);
1055 else
1056 srel += rel->r_addend;
1057 srel -= rel->r_offset;
1058 srel -= (input_section->output_section->vma +
1059 input_section->output_offset);
1060 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1061 break;
1062
1063 case R_MSP430_PREL31:
1064 contents += rel->r_offset;
1065 srel = (bfd_signed_vma) relocation;
1066 if (is_rel_reloc)
1067 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1068 else
1069 srel += rel->r_addend;
1070 srel += rel->r_addend;
1071 x = bfd_get_32 (input_bfd, contents);
1072 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1073 bfd_put_32 (input_bfd, x, contents);
1074 break;
1075
1076 default:
1077 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1078 contents, rel->r_offset,
1079 relocation, rel->r_addend);
1080 }
1081 else
1082 switch (howto->type)
1083 {
2469cfa2
NC		 1084 case R_MSP430_10_PCREL:
1085 contents += rel->r_offset;
1086 srel = (bfd_signed_vma) relocation;
1087 srel += rel->r_addend;
1088 srel -= rel->r_offset;
1089 srel -= 2; /* Branch instructions add 2 to the PC... */
1090 srel -= (input_section->output_section->vma +
1091 input_section->output_offset);
1092
1093 if (srel & 1)
1094 return bfd_reloc_outofrange;
1095
1096 /* MSP430 addresses commands as words. */
1097 srel >>= 1;
1098
1099 /* Check for an overflow. */
1100 if (srel < -512 || srel > 511)
13761a11
NC		 1101 {
1102 if (info->disable_target_specific_optimizations < 0)
1103 {
1104 static bfd_boolean warned = FALSE;
1105 if (! warned)
1106 {
1107 info->callbacks->warning
1108 (info,
1109 _("Try enabling relaxation to avoid relocation truncations"),
1110 NULL, input_bfd, input_section, relocation);
1111 warned = TRUE;
1112 }
1113 }
1114 return bfd_reloc_overflow;
1115 }
1116
2469cfa2
NC		 1117 x = bfd_get_16 (input_bfd, contents);
1118 x = (x & 0xfc00) | (srel & 0x3ff);
1119 bfd_put_16 (input_bfd, x, contents);
1120 break;
1121
b18c562e
NC		 1122 case R_MSP430_2X_PCREL:
1123 contents += rel->r_offset;
1124 srel = (bfd_signed_vma) relocation;
1125 srel += rel->r_addend;
1126 srel -= rel->r_offset;
1127 srel -= 2; /* Branch instructions add 2 to the PC... */
1128 srel -= (input_section->output_section->vma +
1129 input_section->output_offset);
1130
1131 if (srel & 1)
1132 return bfd_reloc_outofrange;
1133
1134 /* MSP430 addresses commands as words. */
1135 srel >>= 1;
1136
1137 /* Check for an overflow. */
1138 if (srel < -512 || srel > 511)
1139 return bfd_reloc_overflow;
1140
1141 x = bfd_get_16 (input_bfd, contents);
1142 x = (x & 0xfc00) | (srel & 0x3ff);
1143 bfd_put_16 (input_bfd, x, contents);
1144 /* Handle second jump instruction. */
1145 x = bfd_get_16 (input_bfd, contents - 2);
1146 srel += 1;
1147 x = (x & 0xfc00) | (srel & 0x3ff);
1148 bfd_put_16 (input_bfd, x, contents - 2);
1149 break;
1150
b18c562e 1151 case R_MSP430_RL_PCREL:
77bf820f 1152 case R_MSP430_16_PCREL:
2469cfa2
NC		 1153 contents += rel->r_offset;
1154 srel = (bfd_signed_vma) relocation;
1155 srel += rel->r_addend;
1156 srel -= rel->r_offset;
1157 /* Only branch instructions add 2 to the PC... */
1158 srel -= (input_section->output_section->vma +
1159 input_section->output_offset);
1160
1161 if (srel & 1)
1162 return bfd_reloc_outofrange;
1163
1164 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1165 break;
1166
1167 case R_MSP430_16_PCREL_BYTE:
1168 contents += rel->r_offset;
1169 srel = (bfd_signed_vma) relocation;
1170 srel += rel->r_addend;
1171 srel -= rel->r_offset;
1172 /* Only branch instructions add 2 to the PC... */
1173 srel -= (input_section->output_section->vma +
1174 input_section->output_offset);
1175
1176 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1177 break;
1178
1179 case R_MSP430_16_BYTE:
1180 contents += rel->r_offset;
1181 srel = (bfd_signed_vma) relocation;
1182 srel += rel->r_addend;
1183 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1184 break;
1185
1186 case R_MSP430_16:
1187 contents += rel->r_offset;
1188 srel = (bfd_signed_vma) relocation;
1189 srel += rel->r_addend;
1190
1191 if (srel & 1)
1192 return bfd_reloc_notsupported;
1193
1194 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1195 break;
1196
13761a11
NC		 1197 case R_MSP430_8:
1198 contents += rel->r_offset;
1199 srel = (bfd_signed_vma) relocation;
1200 srel += rel->r_addend;
1201
1202 bfd_put_8 (input_bfd, srel & 0xff, contents);
1203 break;
1204
1205 case R_MSP430_SYM_DIFF:
1206 /* Cache the input section and value.
1207 The offset is unreliable, since relaxation may
1208 have reduced the following reloc's offset. */
1209 sym_diff_section = input_section;
1210 sym_diff_value = relocation;
1211 return bfd_reloc_ok;
1212
1213 default:
1214 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1215 contents, rel->r_offset,
1216 relocation, rel->r_addend);
1217 }
2469cfa2
NC		 1218
1219 return r;
1220}
1221
1222/* Relocate an MSP430 ELF section. */
1223
1224static bfd_boolean
b18c562e
NC		 1225elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1226 struct bfd_link_info * info,
1227 bfd * input_bfd,
1228 asection * input_section,
1229 bfd_byte * contents,
1230 Elf_Internal_Rela * relocs,
1231 Elf_Internal_Sym * local_syms,
1232 asection ** local_sections)
2469cfa2
NC		 1233{
1234 Elf_Internal_Shdr *symtab_hdr;
1235 struct elf_link_hash_entry **sym_hashes;
1236 Elf_Internal_Rela *rel;
1237 Elf_Internal_Rela *relend;
1238
1239 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1240 sym_hashes = elf_sym_hashes (input_bfd);
1241 relend = relocs + input_section->reloc_count;
1242
1243 for (rel = relocs; rel < relend; rel++)
1244 {
1245 reloc_howto_type *howto;
1246 unsigned long r_symndx;
1247 Elf_Internal_Sym *sym;
1248 asection *sec;
1249 struct elf_link_hash_entry *h;
1250 bfd_vma relocation;
1251 bfd_reloc_status_type r;
1252 const char *name = NULL;
1253 int r_type;
1254
2469cfa2
NC		 1255 r_type = ELF32_R_TYPE (rel->r_info);
1256 r_symndx = ELF32_R_SYM (rel->r_info);
13761a11
NC		 1257
1258 if (uses_msp430x_relocs (input_bfd))
1259 howto = elf_msp430x_howto_table + r_type;
1260 else
1261 howto = elf_msp430_howto_table + r_type;
1262
2469cfa2
NC		 1263 h = NULL;
1264 sym = NULL;
1265 sec = NULL;
1266
1267 if (r_symndx < symtab_hdr->sh_info)
1268 {
1269 sym = local_syms + r_symndx;
1270 sec = local_sections[r_symndx];
8517fae7 1271 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
2469cfa2
NC		 1272
1273 name = bfd_elf_string_from_elf_section
1274 (input_bfd, symtab_hdr->sh_link, sym->st_name);
13761a11 1275 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name;
2469cfa2
NC		 1276 }
1277 else
1278 {
62d887d4 1279 bfd_boolean unresolved_reloc, warned, ignored;
2469cfa2 1280
b2a8e766
AM		 1281 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1282 r_symndx, symtab_hdr, sym_hashes,
1283 h, sec, relocation,
62d887d4 1284 unresolved_reloc, warned, ignored);
13761a11 1285 name = h->root.root.string;
2469cfa2
NC		 1286 }
1287
dbaa2011 1288 if (sec != NULL && discarded_section (sec))
e4067dbb 1289 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 1290 rel, 1, relend, howto, 0, contents);
ab96bf03
AM		 1291
1292 if (info->relocatable)
1293 continue;
1294
2469cfa2 1295 r = msp430_final_link_relocate (howto, input_bfd, input_section,
13761a11 1296 contents, rel, relocation, info);
2469cfa2
NC		 1297
1298 if (r != bfd_reloc_ok)
1299 {
1300 const char *msg = (const char *) NULL;
1301
1302 switch (r)
1303 {
1304 case bfd_reloc_overflow:
1305 r = info->callbacks->reloc_overflow
13761a11 1306 (info, (h ? &h->root : NULL), name, howto->name,
dfeffb9f
L		 1307 (bfd_vma) 0, input_bfd, input_section,
1308 rel->r_offset);
2469cfa2
NC		 1309 break;
1310
1311 case bfd_reloc_undefined:
1312 r = info->callbacks->undefined_symbol
1313 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1314 break;
1315
1316 case bfd_reloc_outofrange:
13761a11 1317 msg = _("internal error: branch/jump to an odd address detected");
2469cfa2
NC		 1318 break;
1319
1320 case bfd_reloc_notsupported:
1321 msg = _("internal error: unsupported relocation error");
1322 break;
1323
1324 case bfd_reloc_dangerous:
1325 msg = _("internal error: dangerous relocation");
1326 break;
1327
1328 default:
1329 msg = _("internal error: unknown error");
1330 break;
1331 }
1332
1333 if (msg)
1334 r = info->callbacks->warning
1335 (info, msg, name, input_bfd, input_section, rel->r_offset);
1336
1337 if (!r)
1338 return FALSE;
1339 }
1340
1341 }
1342
1343 return TRUE;
1344}
1345
1346/* The final processing done just before writing out a MSP430 ELF object
1347 file. This gets the MSP430 architecture right based on the machine
1348 number. */
1349
1350static void
b18c562e
NC		 1351bfd_elf_msp430_final_write_processing (bfd * abfd,
1352 bfd_boolean linker ATTRIBUTE_UNUSED)
2469cfa2
NC		 1353{
1354 unsigned long val;
1355
1356 switch (bfd_get_mach (abfd))
1357 {
1358 default:
13761a11
NC		 1359 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1360 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1361 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1362 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1363 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1364 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1365 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1366 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1367 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1368 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1369 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1370 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1371 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1372 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1373 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1374 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1375 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1376 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1377 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1378 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1379 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1380 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1381 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
2469cfa2
NC		 1382 }
1383
1384 elf_elfheader (abfd)->e_machine = EM_MSP430;
1385 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1386 elf_elfheader (abfd)->e_flags |= val;
1387}
1388
1389/* Set the right machine number. */
1390
1391static bfd_boolean
b18c562e 1392elf32_msp430_object_p (bfd * abfd)
2469cfa2
NC		 1393{
1394 int e_set = bfd_mach_msp14;
1395
1396 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1397 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1398 {
1399 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1400
1401 switch (e_mach)
1402 {
1403 default:
13761a11
NC		 1404 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1405 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1406 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1407 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1408 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1409 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1410 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1411 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1412 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1413 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1414 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1415 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1416 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1417 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1418 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1419 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1420 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1421 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1422 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1423 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1424 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1425 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1426 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
2469cfa2
NC		 1427 }
1428 }
13761a11 1429
2469cfa2
NC		 1430 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1431}
1432
b18c562e
NC		 1433/* These functions handle relaxing for the msp430.
1434 Relaxation required only in two cases:
1435 - Bad hand coding like jumps from one section to another or
1436 from file to file.
77bf820f 1437 - Sibling calls. This will affect only 'jump label' polymorph. Without
b18c562e
NC		 1438 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1439 do not work in gcc's port by the reason I do not know.
13761a11
NC		 1440 - To convert out of range conditional jump instructions (found inside
1441 a function) into inverted jumps over an unconditional branch instruction.
b18c562e
NC		 1442 Anyway, if a relaxation required, user should pass -relax option to the
1443 linker.
1444
1445 There are quite a few relaxing opportunities available on the msp430:
1446
1447 ================================================================
1448
1449 1. 3 words -> 1 word
1450
1451 eq == jeq label jne +4; br lab
1452 ne != jne label jeq +4; br lab
1453 lt < jl label jge +4; br lab
1454 ltu < jlo label lhs +4; br lab
1455 ge >= jge label jl +4; br lab
1456 geu >= jhs label jlo +4; br lab
1457
1458 2. 4 words -> 1 word
1459
1460 ltn < jn jn +2; jmp +4; br lab
1461
1462 3. 4 words -> 2 words
1463
1464 gt > jeq +2; jge label jeq +6; jl +4; br label
1465 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1466
1467 4. 4 words -> 2 words and 2 labels
1468
1469 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1470 le <= jeq label; jl label jeq +2; jge +4; br label
1471 =================================================================
1472
1473 codemap for first cases is (labels masked ):
1474 eq: 0x2002,0x4010,0x0000 -> 0x2400
1475 ne: 0x2402,0x4010,0x0000 -> 0x2000
1476 lt: 0x3402,0x4010,0x0000 -> 0x3800
1477 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1478 ge: 0x3802,0x4010,0x0000 -> 0x3400
1479 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1480
1481 second case:
1482 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1483
1484 third case:
1485 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1486 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1487
1488 fourth case:
1489 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1490 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1491
1492 Unspecified case :)
1493 jump: 0x4010,0x0000 -> 0x3c00. */
1494
1495#define NUMB_RELAX_CODES 12
1496static struct rcodes_s
1497{
1498 int f0, f1; /* From code. */
1499 int t0, t1; /* To code. */
1500 int labels; /* Position of labels: 1 - one label at first
1501 word, 2 - one at second word, 3 - two
1502 labels at both. */
1503 int cdx; /* Words to match. */
1504 int bs; /* Shrink bytes. */
1505 int off; /* Offset from old label for new code. */
1506 int ncl; /* New code length. */
1507} rcode[] =
1508{/* lab,cdx,bs,off,ncl */
1509 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1510 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1511 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1512 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1513 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1514 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1515 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1516 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1517 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1518 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1519 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1520 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1521 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1522};
1523
1524/* Return TRUE if a symbol exists at the given address. */
1525
1526static bfd_boolean
1527msp430_elf_symbol_address_p (bfd * abfd,
1528 asection * sec,
1529 Elf_Internal_Sym * isym,
1530 bfd_vma addr)
1531{
1532 Elf_Internal_Shdr *symtab_hdr;
1533 unsigned int sec_shndx;
1534 Elf_Internal_Sym *isymend;
1535 struct elf_link_hash_entry **sym_hashes;
1536 struct elf_link_hash_entry **end_hashes;
1537 unsigned int symcount;
1538
1539 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1540
1541 /* Examine all the local symbols. */
1542 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1543 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1544 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1545 return TRUE;
1546
1547 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1548 - symtab_hdr->sh_info);
1549 sym_hashes = elf_sym_hashes (abfd);
1550 end_hashes = sym_hashes + symcount;
1551 for (; sym_hashes < end_hashes; sym_hashes++)
1552 {
1553 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1554
1555 if ((sym_hash->root.type == bfd_link_hash_defined
1556 || sym_hash->root.type == bfd_link_hash_defweak)
1557 && sym_hash->root.u.def.section == sec
1558 && sym_hash->root.u.def.value == addr)
1559 return TRUE;
1560 }
1561
1562 return FALSE;
1563}
1564
13761a11
NC		 1565/* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1566 sec_shndx) referenced from current and other sections. */
1567
046aeb74 1568static bfd_boolean
13761a11
NC		 1569msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1570 int count, unsigned int sec_shndx,
1571 bfd_vma toaddr)
046aeb74
DD		 1572{
1573 Elf_Internal_Shdr *symtab_hdr;
1574 Elf_Internal_Rela *irel;
1575 Elf_Internal_Rela *irelend;
1576 Elf_Internal_Sym *isym;
1577
1578 irel = elf_section_data (sec)->relocs;
13761a11
NC		 1579 if (irel == NULL)
1580 return TRUE;
1581
046aeb74
DD		 1582 irelend = irel + sec->reloc_count;
1583 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1584 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11
NC		 1585
1586 for (;irel < irelend; irel++)
046aeb74
DD		 1587 {
1588 int sidx = ELF32_R_SYM(irel->r_info);
1589 Elf_Internal_Sym *lsym = isym + sidx;
13761a11 1590
046aeb74 1591 /* Adjust symbols referenced by .sec+0xXX */
13761a11 1592 if (irel->r_addend > addr && irel->r_addend < toaddr
046aeb74
DD		 1593 && lsym->st_shndx == sec_shndx)
1594 irel->r_addend -= count;
1595 }
13761a11 1596
046aeb74
DD		 1597 return TRUE;
1598}
1599
b18c562e
NC		 1600/* Delete some bytes from a section while relaxing. */
1601
1602static bfd_boolean
1603msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1604 int count)
1605{
1606 Elf_Internal_Shdr *symtab_hdr;
1607 unsigned int sec_shndx;
1608 bfd_byte *contents;
1609 Elf_Internal_Rela *irel;
1610 Elf_Internal_Rela *irelend;
b18c562e
NC		 1611 bfd_vma toaddr;
1612 Elf_Internal_Sym *isym;
1613 Elf_Internal_Sym *isymend;
1614 struct elf_link_hash_entry **sym_hashes;
1615 struct elf_link_hash_entry **end_hashes;
1616 unsigned int symcount;
046aeb74 1617 asection *p;
b18c562e
NC		 1618
1619 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1620
1621 contents = elf_section_data (sec)->this_hdr.contents;
1622
b18c562e
NC		 1623 toaddr = sec->size;
1624
1625 irel = elf_section_data (sec)->relocs;
1626 irelend = irel + sec->reloc_count;
1627
1628 /* Actually delete the bytes. */
1629 memmove (contents + addr, contents + addr + count,
1630 (size_t) (toaddr - addr - count));
1631 sec->size -= count;
1632
1633 /* Adjust all the relocs. */
fa9ee72b
DD		 1634 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1635 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11 1636 for (; irel < irelend; irel++)
fa9ee72b 1637 {
fa9ee72b
DD		 1638 /* Get the new reloc address. */
1639 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1640 irel->r_offset -= count;
fa9ee72b 1641 }
b18c562e 1642
046aeb74 1643 for (p = abfd->sections; p != NULL; p = p->next)
13761a11
NC		 1644 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1645
b18c562e
NC		 1646 /* Adjust the local symbols defined in this section. */
1647 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1648 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1649 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1650 if (isym->st_shndx == sec_shndx
1651 && isym->st_value > addr && isym->st_value < toaddr)
1652 isym->st_value -= count;
1653
1654 /* Now adjust the global symbols defined in this section. */
1655 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1656 - symtab_hdr->sh_info);
1657 sym_hashes = elf_sym_hashes (abfd);
1658 end_hashes = sym_hashes + symcount;
1659 for (; sym_hashes < end_hashes; sym_hashes++)
1660 {
1661 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1662
1663 if ((sym_hash->root.type == bfd_link_hash_defined
1664 || sym_hash->root.type == bfd_link_hash_defweak)
1665 && sym_hash->root.u.def.section == sec
1666 && sym_hash->root.u.def.value > addr
1667 && sym_hash->root.u.def.value < toaddr)
1668 sym_hash->root.u.def.value -= count;
1669 }
1670
1671 return TRUE;
1672}
1673
13761a11
NC		 1674/* Insert two words into a section whilst relaxing. */
1675
1676static bfd_byte *
1677msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1678 int word1, int word2)
1679{
1680 Elf_Internal_Shdr *symtab_hdr;
1681 unsigned int sec_shndx;
1682 bfd_byte *contents;
1683 Elf_Internal_Rela *irel;
1684 Elf_Internal_Rela *irelend;
1685 Elf_Internal_Sym *isym;
1686 Elf_Internal_Sym *isymend;
1687 struct elf_link_hash_entry **sym_hashes;
1688 struct elf_link_hash_entry **end_hashes;
1689 unsigned int symcount;
1690 bfd_vma sec_end;
1691 asection *p;
1692
1693 contents = elf_section_data (sec)->this_hdr.contents;
1694 sec_end = sec->size;
1695
1696 /* Make space for the new words. */
1697 contents = bfd_realloc (contents, sec_end + 4);
1698 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1699
1700 /* Insert the new words. */
1701 bfd_put_16 (abfd, word1, contents + addr);
1702 bfd_put_16 (abfd, word2, contents + addr + 2);
1703
1704 /* Update the section information. */
1705 sec->size += 4;
1706 elf_section_data (sec)->this_hdr.contents = contents;
1707
1708 /* Adjust all the relocs. */
1709 irel = elf_section_data (sec)->relocs;
1710 irelend = irel + sec->reloc_count;
1711
1712 for (; irel < irelend; irel++)
1713 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1714 irel->r_offset += 4;
1715
1716 /* Adjust the local symbols defined in this section. */
1717 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1718 for (p = abfd->sections; p != NULL; p = p->next)
1719 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1720 sec_shndx, sec_end);
1721
1722 /* Adjust the global symbols affected by the move. */
1723 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1724 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1725 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1726 if (isym->st_shndx == sec_shndx
1727 && isym->st_value >= addr && isym->st_value < sec_end)
1728 isym->st_value += 4;
1729
1730 /* Now adjust the global symbols defined in this section. */
1731 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1732 - symtab_hdr->sh_info);
1733 sym_hashes = elf_sym_hashes (abfd);
1734 end_hashes = sym_hashes + symcount;
1735 for (; sym_hashes < end_hashes; sym_hashes++)
1736 {
1737 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1738
1739 if ((sym_hash->root.type == bfd_link_hash_defined
1740 || sym_hash->root.type == bfd_link_hash_defweak)
1741 && sym_hash->root.u.def.section == sec
1742 && sym_hash->root.u.def.value >= addr
1743 && sym_hash->root.u.def.value < sec_end)
1744 sym_hash->root.u.def.value += 4;
1745 }
1746
1747 return contents;
1748}
1749
b18c562e
NC		 1750static bfd_boolean
1751msp430_elf_relax_section (bfd * abfd, asection * sec,
1752 struct bfd_link_info * link_info,
1753 bfd_boolean * again)
1754{
1755 Elf_Internal_Shdr * symtab_hdr;
1756 Elf_Internal_Rela * internal_relocs;
1757 Elf_Internal_Rela * irel;
1758 Elf_Internal_Rela * irelend;
1759 bfd_byte * contents = NULL;
1760 Elf_Internal_Sym * isymbuf = NULL;
1761
13761a11 1762
b18c562e
NC		 1763 /* Assume nothing changes. */
1764 *again = FALSE;
1765
1766 /* We don't have to do anything for a relocatable link, if
1767 this section does not have relocs, or if this is not a
1768 code section. */
1769 if (link_info->relocatable
13761a11
NC		 1770 || (sec->flags & SEC_RELOC) == 0
1771 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
b18c562e
NC		 1772 return TRUE;
1773
1774 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1775
1776 /* Get a copy of the native relocations. */
1777 internal_relocs =
1778 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1779 if (internal_relocs == NULL)
1780 goto error_return;
1781
1782 /* Walk through them looking for relaxing opportunities. */
1783 irelend = internal_relocs + sec->reloc_count;
13761a11
NC		 1784
1785 /* Do code size growing relocs first. */
b18c562e
NC		 1786 for (irel = internal_relocs; irel < irelend; irel++)
1787 {
1788 bfd_vma symval;
1789
1790 /* If this isn't something that can be relaxed, then ignore
1791 this reloc. */
13761a11
NC		 1792 if (uses_msp430x_relocs (abfd)
1793 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1794 ;
1795 else if (! uses_msp430x_relocs (abfd)
1796 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1797 ;
1798 else
b18c562e
NC		 1799 continue;
1800
1801 /* Get the section contents if we haven't done so already. */
1802 if (contents == NULL)
1803 {
1804 /* Get cached copy if it exists. */
1805 if (elf_section_data (sec)->this_hdr.contents != NULL)
1806 contents = elf_section_data (sec)->this_hdr.contents;
1807 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1808 goto error_return;
1809 }
1810
1811 /* Read this BFD's local symbols if we haven't done so already. */
1812 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1813 {
1814 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1815 if (isymbuf == NULL)
1816 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1817 symtab_hdr->sh_info, 0,
1818 NULL, NULL, NULL);
1819 if (isymbuf == NULL)
1820 goto error_return;
1821 }
1822
1823 /* Get the value of the symbol referred to by the reloc. */
1824 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1825 {
1826 /* A local symbol. */
1827 Elf_Internal_Sym *isym;
1828 asection *sym_sec;
1829
1830 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1831 if (isym->st_shndx == SHN_UNDEF)
1832 sym_sec = bfd_und_section_ptr;
1833 else if (isym->st_shndx == SHN_ABS)
1834 sym_sec = bfd_abs_section_ptr;
1835 else if (isym->st_shndx == SHN_COMMON)
1836 sym_sec = bfd_com_section_ptr;
1837 else
1838 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1839 symval = (isym->st_value
1840 + sym_sec->output_section->vma + sym_sec->output_offset);
1841 }
1842 else
1843 {
1844 unsigned long indx;
1845 struct elf_link_hash_entry *h;
1846
1847 /* An external symbol. */
1848 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1849 h = elf_sym_hashes (abfd)[indx];
1850 BFD_ASSERT (h != NULL);
1851
1852 if (h->root.type != bfd_link_hash_defined
1853 && h->root.type != bfd_link_hash_defweak)
1854 /* This appears to be a reference to an undefined
1855 symbol. Just ignore it--it will be caught by the
1856 regular reloc processing. */
1857 continue;
1858
1859 symval = (h->root.u.def.value
1860 + h->root.u.def.section->output_section->vma
1861 + h->root.u.def.section->output_offset);
1862 }
1863
1864 /* For simplicity of coding, we are going to modify the section
1865 contents, the section relocs, and the BFD symbol table. We
1866 must tell the rest of the code not to free up this
1867 information. It would be possible to instead create a table
1868 of changes which have to be made, as is done in coff-mips.c;
1869 that would be more work, but would require less memory when
1870 the linker is run. */
1871
13761a11
NC		 1872 bfd_signed_vma value = symval;
1873 int opcode;
b18c562e 1874
13761a11
NC		 1875 /* Compute the value that will be relocated. */
1876 value += irel->r_addend;
1877 /* Convert to PC relative. */
1878 value -= (sec->output_section->vma + sec->output_offset);
1879 value -= irel->r_offset;
1880 value -= 2;
1881 /* Scale. */
1882 value >>= 1;
b18c562e 1883
13761a11
NC		 1884 /* If it is in range then no modifications are needed. */
1885 if (value >= -512 && value <= 511)
1886 continue;
b18c562e 1887
13761a11
NC		 1888 /* Get the opcode. */
1889 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1890
1891 /* Compute the new opcode. We are going to convert:
1892 J<cond> label
1893 into:
1894 J<inv-cond> 1f
1895 BR[A] #label
1896 1: */
1897 switch (opcode & 0xfc00)
1898 {
1899 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
1900 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1901 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1902 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1903 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1904 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1905 case 0x3000: /* jn */
1906 /* There is no direct inverse of the Jn insn.
1907 FIXME: we could do this as:
1908 Jn 1f
1909 br 2f
1910 1: br label
1911 2: */
1912 continue;
1913 default:
1914 /* Not a conditional branch instruction. */
1915 /* fprintf (stderr, "unrecog: %x\n", opcode); */
1916 goto error_return;
1917 }
b18c562e 1918
13761a11
NC		 1919 /* Note that we've changed the relocs, section contents, etc. */
1920 elf_section_data (sec)->relocs = internal_relocs;
1921 elf_section_data (sec)->this_hdr.contents = contents;
1922 symtab_hdr->contents = (unsigned char *) isymbuf;
b18c562e 1923
13761a11
NC		 1924 /* Install the new opcode. */
1925 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
b18c562e 1926
13761a11
NC		 1927 /* Insert the new branch instruction. */
1928 if (uses_msp430x_relocs (abfd))
1929 {
1930 /* Insert an absolute branch (aka MOVA) instruction. */
1931 contents = msp430_elf_relax_add_two_words
1932 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
1933
1934 /* Update the relocation to point to the inserted branch
1935 instruction. Note - we are changing a PC-relative reloc
1936 into an absolute reloc, but this is OK because we have
1937 arranged with the assembler to have the reloc's value be
1938 a (local) symbol, not a section+offset value. */
1939 irel->r_offset += 2;
1940 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1941 R_MSP430X_ABS20_ADR_SRC);
1942 }
1943 else
1944 {
1945 contents = msp430_elf_relax_add_two_words
1946 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
1947
1948 /* See comment above about converting a 10-bit PC-rel
1949 relocation into a 16-bit absolute relocation. */
1950 irel->r_offset += 4;
1951 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1952 R_MSP430_16);
1953 }
b18c562e 1954
13761a11
NC		 1955 /* Growing the section may mean that other
1956 conditional branches need to be fixed. */
1957 *again = TRUE;
1958 }
b18c562e 1959
13761a11
NC		 1960 if (! uses_msp430x_relocs (abfd))
1961 /* Now perform the relocations that shrink the code size.
1962 We only do this for non msp430x as gas only generates the RL
1963 reloc for the msp430. */
1964 for (irel = internal_relocs; irel < irelend; irel++)
1965 {
1966 bfd_vma symval;
1967
1968 /* Get the section contents if we haven't done so already. */
1969 if (contents == NULL)
1970 {
1971 /* Get cached copy if it exists. */
1972 if (elf_section_data (sec)->this_hdr.contents != NULL)
1973 contents = elf_section_data (sec)->this_hdr.contents;
1974 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1975 goto error_return;
1976 }
1977
1978 /* Read this BFD's local symbols if we haven't done so already. */
1979 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1980 {
1981 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1982 if (isymbuf == NULL)
1983 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1984 symtab_hdr->sh_info, 0,
1985 NULL, NULL, NULL);
1986 if (isymbuf == NULL)
1987 goto error_return;
1988 }
1989
1990 /* Get the value of the symbol referred to by the reloc. */
1991 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1992 {
1993 /* A local symbol. */
1994 Elf_Internal_Sym *isym;
1995 asection *sym_sec;
1996
1997 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1998 if (isym->st_shndx == SHN_UNDEF)
1999 sym_sec = bfd_und_section_ptr;
2000 else if (isym->st_shndx == SHN_ABS)
2001 sym_sec = bfd_abs_section_ptr;
2002 else if (isym->st_shndx == SHN_COMMON)
2003 sym_sec = bfd_com_section_ptr;
2004 else
2005 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2006 symval = (isym->st_value
2007 + sym_sec->output_section->vma + sym_sec->output_offset);
2008 }
2009 else
2010 {
2011 unsigned long indx;
2012 struct elf_link_hash_entry *h;
2013
2014 /* An external symbol. */
2015 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2016 h = elf_sym_hashes (abfd)[indx];
2017 BFD_ASSERT (h != NULL);
2018
2019 if (h->root.type != bfd_link_hash_defined
2020 && h->root.type != bfd_link_hash_defweak)
2021 /* This appears to be a reference to an undefined
2022 symbol. Just ignore it--it will be caught by the
2023 regular reloc processing. */
2024 continue;
2025
2026 symval = (h->root.u.def.value
2027 + h->root.u.def.section->output_section->vma
2028 + h->root.u.def.section->output_offset);
2029 }
2030
2031 /* For simplicity of coding, we are going to modify the section
2032 contents, the section relocs, and the BFD symbol table. We
2033 must tell the rest of the code not to free up this
2034 information. It would be possible to instead create a table
2035 of changes which have to be made, as is done in coff-mips.c;
2036 that would be more work, but would require less memory when
2037 the linker is run. */
2038
2039 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2040 branch. */
2041 /* Paranoia? paranoia... */
2042 if (ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
2043 {
2044 bfd_vma value = symval;
2045
2046 /* Deal with pc-relative gunk. */
2047 value -= (sec->output_section->vma + sec->output_offset);
2048 value -= irel->r_offset;
2049 value += irel->r_addend;
2050
2051 /* See if the value will fit in 10 bits, note the high value is
2052 1016 as the target will be two bytes closer if we are
2053 able to relax. */
2054 if ((long) value < 1016 && (long) value > -1016)
2055 {
2056 int code0 = 0, code1 = 0, code2 = 0;
2057 int i;
2058 struct rcodes_s *rx;
2059
2060 /* Get the opcode. */
2061 if (irel->r_offset >= 6)
2062 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2063
2064 if (irel->r_offset >= 4)
2065 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2066
2067 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2068
2069 if (code2 != 0x4010)
2070 continue;
2071
2072 /* Check r4 and r3. */
2073 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2074 {
2075 rx = &rcode[i];
2076 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2077 break;
2078 else if (rx->cdx == 1 && rx->f1 == code1)
2079 break;
2080 else if (rx->cdx == 0) /* This is an unconditional jump. */
2081 break;
2082 }
2083
2084 /* Check labels:
b18c562e 2085 .Label0: ; we do not care about this label
13761a11 2086 jeq +6
b18c562e 2087 .Label1: ; make sure there is no label here
13761a11 2088 jl +4
b18c562e 2089 .Label2: ; make sure there is no label here
13761a11
NC		 2090 br .Label_dst
2091
2092 So, if there is .Label1 or .Label2 we cannot relax this code.
2093 This actually should not happen, cause for relaxable
2094 instructions we use RL_PCREL reloc instead of 16_PCREL.
2095 Will change this in the future. */
2096
2097 if (rx->cdx > 0
2098 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2099 irel->r_offset - 2))
2100 continue;
2101 if (rx->cdx > 1
2102 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2103 irel->r_offset - 4))
2104 continue;
2105
2106 /* Note that we've changed the relocs, section contents, etc. */
2107 elf_section_data (sec)->relocs = internal_relocs;
2108 elf_section_data (sec)->this_hdr.contents = contents;
2109 symtab_hdr->contents = (unsigned char *) isymbuf;
2110
2111 /* Fix the relocation's type. */
2112 if (uses_msp430x_relocs (abfd))
2113 {
2114 if (rx->labels == 3) /* Handle special cases. */
2115 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2116 R_MSP430X_2X_PCREL);
2117 else
2118 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2119 R_MSP430X_10_PCREL);
2120 }
2121 else
2122 {
2123 if (rx->labels == 3) /* Handle special cases. */
2124 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2125 R_MSP430_2X_PCREL);
2126 else
2127 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2128 R_MSP430_10_PCREL);
2129 }
2130
2131 /* Fix the opcode right way. */
2132 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2133 if (rx->t1)
2134 bfd_put_16 (abfd, rx->t1,
2135 contents + irel->r_offset - rx->off + 2);
2136
2137 /* Delete bytes. */
2138 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2139 irel->r_offset - rx->off +
2140 rx->ncl, rx->bs))
2141 goto error_return;
2142
2143 /* Handle unconditional jumps. */
2144 if (rx->cdx == 0)
2145 irel->r_offset -= 2;
2146
2147 /* That will change things, so, we should relax again.
2148 Note that this is not required, and it may be slow. */
2149 *again = TRUE;
2150 }
2151 }
2152 }
b18c562e
NC		 2153
2154 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2155 {
2156 if (!link_info->keep_memory)
2157 free (isymbuf);
2158 else
2159 {
2160 /* Cache the symbols for elf_link_input_bfd. */
2161 symtab_hdr->contents = (unsigned char *) isymbuf;
2162 }
2163 }
2164
2165 if (contents != NULL
2166 && elf_section_data (sec)->this_hdr.contents != contents)
2167 {
2168 if (!link_info->keep_memory)
2169 free (contents);
2170 else
2171 {
2172 /* Cache the section contents for elf_link_input_bfd. */
2173 elf_section_data (sec)->this_hdr.contents = contents;
2174 }
2175 }
2176
2177 if (internal_relocs != NULL
2178 && elf_section_data (sec)->relocs != internal_relocs)
2179 free (internal_relocs);
2180
2181 return TRUE;
2182
2183error_return:
2184 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2185 free (isymbuf);
2186 if (contents != NULL
2187 && elf_section_data (sec)->this_hdr.contents != contents)
2188 free (contents);
2189 if (internal_relocs != NULL
2190 && elf_section_data (sec)->relocs != internal_relocs)
2191 free (internal_relocs);
2192
2193 return FALSE;
2194}
2195
13761a11
NC		 2196/* Handle an MSP430 specific section when reading an object file.
2197 This is called when bfd_section_from_shdr finds a section with
2198 an unknown type. */
2199
2200static bfd_boolean
2201elf32_msp430_section_from_shdr (bfd *abfd,
2202 Elf_Internal_Shdr * hdr,
2203 const char *name,
2204 int shindex)
2205{
2206 switch (hdr->sh_type)
2207 {
2208 case SHT_MSP430_SEC_FLAGS:
2209 case SHT_MSP430_SYM_ALIASES:
2210 case SHT_MSP430_ATTRIBUTES:
2211 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2212 default:
2213 return FALSE;
2214 }
2215}
2216
2217static bfd_boolean
2218elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2219{
2220 _bfd_error_handler
2221 (_("Warning: %B: Unknown MSPABI object attribute %d"),
2222 abfd, tag);
2223 return TRUE;
2224}
2225
2226/* Determine whether an object attribute tag takes an integer, a
2227 string or both. */
2228
2229static int
2230elf32_msp430_obj_attrs_arg_type (int tag)
2231{
2232 if (tag == Tag_compatibility)
2233 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2234
2235 if (tag < 32)
2236 return ATTR_TYPE_FLAG_INT_VAL;
2237
2238 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2239}
2240
2241static inline const char *
2242isa_type (int isa)
2243{
2244 switch (isa)
2245 {
2246 case 1: return "MSP430";
2247 case 2: return "MSP430X";
2248 default: return "unknown";
2249 }
2250}
2251
2252static inline const char *
2253code_model (int model)
2254{
2255 switch (model)
2256 {
2257 case 1: return "small";
2258 case 2: return "large";
2259 default: return "unknown";
2260 }
2261}
2262
2263static inline const char *
2264data_model (int model)
2265{
2266 switch (model)
2267 {
2268 case 1: return "small";
2269 case 2: return "large";
2270 case 3: return "restricted large";
2271 default: return "unknown";
2272 }
2273}
2274
2275/* Merge MSPABI object attributes from IBFD into OBFD.
2276 Raise an error if there are conflicting attributes. */
2277
2278static bfd_boolean
2279elf32_msp430_merge_mspabi_attributes (bfd *ibfd, bfd *obfd)
2280{
2281 obj_attribute *in_attr;
2282 obj_attribute *out_attr;
2283 bfd_boolean result = TRUE;
2284 static bfd * first_input_bfd = NULL;
2285
2286 /* Skip linker created files. */
2287 if (ibfd->flags & BFD_LINKER_CREATED)
2288 return TRUE;
2289
2290 /* If this is the first real object just copy the attributes. */
2291 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2292 {
2293 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2294
2295 out_attr = elf_known_obj_attributes_proc (obfd);
2296
2297 /* Use the Tag_null value to indicate that
2298 the attributes have been initialized. */
2299 out_attr[0].i = 1;
2300
2301 first_input_bfd = ibfd;
2302 return TRUE;
2303 }
2304
2305 in_attr = elf_known_obj_attributes_proc (ibfd);
2306 out_attr = elf_known_obj_attributes_proc (obfd);
2307
2308 /* The ISAs must be the same. */
2309 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i)
2310 {
2311 _bfd_error_handler
2312 (_("error: %B uses %s instructions but %B uses %s"),
2313 ibfd, first_input_bfd,
2314 isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i),
2315 isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i));
2316 result = FALSE;
2317 }
2318
2319 /* The code models must be the same. */
2320 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i !=
2321 out_attr[OFBA_MSPABI_Tag_Code_Model].i)
2322 {
2323 _bfd_error_handler
2324 (_("error: %B uses the %s code model whereas %B uses the %s code model"),
2325 ibfd, first_input_bfd,
2326 code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i),
2327 code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i));
2328 result = FALSE;
2329 }
2330
2331 /* The large code model is only supported by the MSP430X. */
2332 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2333 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2334 {
2335 _bfd_error_handler
2336 (_("error: %B uses the large code model but %B uses MSP430 instructions"),
2337 ibfd, first_input_bfd);
2338 result = FALSE;
2339 }
2340
2341 /* The data models must be the same. */
2342 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i !=
2343 out_attr[OFBA_MSPABI_Tag_Data_Model].i)
2344 {
2345 _bfd_error_handler
2346 (_("error: %B uses the %s data model whereas %B uses the %s data model"),
2347 ibfd, first_input_bfd,
2348 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2349 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2350 result = FALSE;
2351 }
2352
2353 /* The small code model requires the use of the small data model. */
2354 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2355 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2356 {
2357 _bfd_error_handler
2358 (_("error: %B uses the small code model but %B uses the %s data model"),
2359 ibfd, first_input_bfd,
2360 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2361 result = FALSE;
2362 }
2363
2364 /* The large data models are only supported by the MSP430X. */
2365 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2366 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2367 {
2368 _bfd_error_handler
2369 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"),
2370 ibfd, first_input_bfd,
2371 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i));
2372 result = FALSE;
2373 }
2374
2375 return result;
2376}
2377
2378/* Merge backend specific data from an object file to the output
2379 object file when linking. */
2380
2381static bfd_boolean
2382elf32_msp430_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
2383{
2384 /* Make sure that the machine number reflects the most
2385 advanced version of the MSP architecture required. */
2386#define max(a,b) ((a) > (b) ? (a) : (b))
2387 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2388 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2389 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2390#undef max
2391
2392 return elf32_msp430_merge_mspabi_attributes (ibfd, obfd);
2393}
2394
13761a11
NC		 2395static bfd_boolean
2396msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2397{
2398 return _bfd_elf_is_local_label_name (abfd, sym->name);
2399}
2400
2401/* This is gross. The MSP430 EABI says that (sec 11.5):
2402
2403 "An implementation may choose to use Rel or Rela
2404 type relocations for other relocations."
2405
2406 But it also says that:
2407
2408 "Certain relocations are identified as Rela only. [snip]
2409 Where Rela is specified, an implementation must honor
2410 this requirement."
2411
2412 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2413 to keep things simple we choose to use RELA relocations throughout. The
2414 problem is that the TI compiler generates REL relocations, so we have to
2415 be able to accept those as well. */
2416
2417#define elf_backend_may_use_rel_p 1
2418#define elf_backend_may_use_rela_p 1
2419#define elf_backend_default_use_rela_p 1
2420
2421#undef elf_backend_obj_attrs_vendor
2422#define elf_backend_obj_attrs_vendor "mspabi"
2423#undef elf_backend_obj_attrs_section
2424#define elf_backend_obj_attrs_section ".MSP430.attributes"
2425#undef elf_backend_obj_attrs_section_type
2426#define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2427#define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2428#define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2429#undef elf_backend_obj_attrs_arg_type
2430#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
13761a11 2431#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
2469cfa2
NC		 2432
2433#define ELF_ARCH bfd_arch_msp430
2434#define ELF_MACHINE_CODE EM_MSP430
2435#define ELF_MACHINE_ALT1 EM_MSP430_OLD
13761a11 2436#define ELF_MAXPAGESIZE 4
d1036acb 2437#define ELF_OSABI ELFOSABI_STANDALONE
2469cfa2 2438
6d00b590 2439#define TARGET_LITTLE_SYM msp430_elf32_vec
2469cfa2
NC		 2440#define TARGET_LITTLE_NAME "elf32-msp430"
2441
2442#define elf_info_to_howto msp430_info_to_howto_rela
2443#define elf_info_to_howto_rel NULL
2444#define elf_backend_relocate_section elf32_msp430_relocate_section
2469cfa2
NC		 2445#define elf_backend_check_relocs elf32_msp430_check_relocs
2446#define elf_backend_can_gc_sections 1
2447#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2448#define elf_backend_object_p elf32_msp430_object_p
b18c562e 2449#define bfd_elf32_bfd_relax_section msp430_elf_relax_section
13761a11
NC		 2450#define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2451
2452#undef elf32_bed
2453#define elf32_bed elf32_msp430_bed
2454
2455#include "elf32-target.h"
2456
2457/* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2458#undef TARGET_LITTLE_SYM
6d00b590 2459#define TARGET_LITTLE_SYM msp430_elf32_ti_vec
13761a11
NC		 2460
2461#undef elf32_bed
2462#define elf32_bed elf32_msp430_ti_bed
2463
2464#undef ELF_OSABI
2465#define ELF_OSABI ELFOSABI_NONE
2466
2467static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2468{
2469 /* prefix, prefix_length, suffix_len, type, attributes. */
2470 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2471 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2472 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2473 { NULL, 0, 0, 0, 0 }
2474};
2469cfa2
NC		 2475
2476#include "elf32-target.h"
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