[thirdparty/binutils-gdb.git] / bfd / elfxx-aarch64.c

/* AArch64-specific support for ELF.
   Copyright (C) 2009-2015 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#include "sysdep.h"
#include "elfxx-aarch64.h"
#include <stdarg.h>
#include <string.h>

#define MASK(n) ((1u << (n)) - 1)

/* Sign-extend VALUE, which has the indicated number of BITS.  */

bfd_signed_vma
_bfd_aarch64_sign_extend (bfd_vma value, int bits)
{
  if (value & ((bfd_vma) 1 << (bits - 1)))
    /* VALUE is negative.  */
    value |= ((bfd_vma) - 1) << bits;

  return value;
}

/* Decode the IMM field of ADRP.  */

uint32_t
_bfd_aarch64_decode_adrp_imm (uint32_t insn)
{
  return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2));
}

/* Reencode the imm field of add immediate.  */
static inline uint32_t
reencode_add_imm (uint32_t insn, uint32_t imm)
{
  return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
}

/* Reencode the IMM field of ADR.  */

uint32_t
_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
{
  return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
    | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
}

/* Reencode the imm field of ld/st pos immediate.  */
static inline uint32_t
reencode_ldst_pos_imm (uint32_t insn, uint32_t imm)
{
  return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
}

/* Encode the 26-bit offset of unconditional branch.  */
static inline uint32_t
reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs)
{
  return (insn & ~MASK (26)) | (ofs & MASK (26));
}

/* Encode the 19-bit offset of conditional branch and compare & branch.  */
static inline uint32_t
reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs)
{
  return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
}

/* Decode the 19-bit offset of load literal.  */
static inline uint32_t
reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs)
{
  return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
}

/* Encode the 14-bit offset of test & branch.  */
static inline uint32_t
reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
{
  return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5);
}

/* Reencode the imm field of move wide.  */
static inline uint32_t
reencode_movw_imm (uint32_t insn, uint32_t imm)
{
  return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5);
}

/* Reencode mov[zn] to movz.  */
static inline uint32_t
reencode_movzn_to_movz (uint32_t opcode)
{
  return opcode | (1 << 30);
}

/* Reencode mov[zn] to movn.  */
static inline uint32_t
reencode_movzn_to_movn (uint32_t opcode)
{
  return opcode & ~(1 << 30);
}

/* Return non-zero if the indicated VALUE has overflowed the maximum
   range expressible by a unsigned number with the indicated number of
   BITS.  */

static bfd_reloc_status_type
aarch64_unsigned_overflow (bfd_vma value, unsigned int bits)
{
  bfd_vma lim;
  if (bits >= sizeof (bfd_vma) * 8)
    return bfd_reloc_ok;
  lim = (bfd_vma) 1 << bits;
  if (value >= lim)
    return bfd_reloc_overflow;
  return bfd_reloc_ok;
}

/* Return non-zero if the indicated VALUE has overflowed the maximum
   range expressible by an signed number with the indicated number of
   BITS.  */

static bfd_reloc_status_type
aarch64_signed_overflow (bfd_vma value, unsigned int bits)
{
  bfd_signed_vma svalue = (bfd_signed_vma) value;
  bfd_signed_vma lim;

  if (bits >= sizeof (bfd_vma) * 8)
    return bfd_reloc_ok;
  lim = (bfd_signed_vma) 1 << (bits - 1);
  if (svalue < -lim || svalue >= lim)
    return bfd_reloc_overflow;
  return bfd_reloc_ok;
}

/* Insert the addend/value into the instruction or data object being
   relocated.  */
bfd_reloc_status_type
_bfd_aarch64_elf_put_addend (bfd *abfd,
			     bfd_byte *address, bfd_reloc_code_real_type r_type,
			     reloc_howto_type *howto, bfd_signed_vma addend)
{
  bfd_reloc_status_type status = bfd_reloc_ok;
  bfd_signed_vma old_addend = addend;
  bfd_vma contents;
  int size;

  size = bfd_get_reloc_size (howto);
  switch (size)
    {
    case 0:
      return status;
    case 2:
      contents = bfd_get_16 (abfd, address);
      break;
    case 4:
      if (howto->src_mask != 0xffffffff)
	/* Must be 32-bit instruction, always little-endian.  */
	contents = bfd_getl32 (address);
      else
	/* Must be 32-bit data (endianness dependent).  */
	contents = bfd_get_32 (abfd, address);
      break;
    case 8:
      contents = bfd_get_64 (abfd, address);
      break;
    default:
      abort ();
    }

  switch (howto->complain_on_overflow)
    {
    case complain_overflow_dont:
      break;
    case complain_overflow_signed:
      status = aarch64_signed_overflow (addend,
					howto->bitsize + howto->rightshift);
      break;
    case complain_overflow_unsigned:
      status = aarch64_unsigned_overflow (addend,
					  howto->bitsize + howto->rightshift);
      break;
    case complain_overflow_bitfield:
    default:
      abort ();
    }

  addend >>= howto->rightshift;

  switch (r_type)
    {
    case BFD_RELOC_AARCH64_CALL26:
    case BFD_RELOC_AARCH64_JUMP26:
      contents = reencode_branch_ofs_26 (contents, addend);
      break;

    case BFD_RELOC_AARCH64_BRANCH19:
      contents = reencode_cond_branch_ofs_19 (contents, addend);
      break;

    case BFD_RELOC_AARCH64_TSTBR14:
      contents = reencode_tst_branch_ofs_14 (contents, addend);
      break;

    case BFD_RELOC_AARCH64_GOT_LD_PREL19:
    case BFD_RELOC_AARCH64_LD_LO19_PCREL:
    case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
    case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
      if (old_addend & ((1 << howto->rightshift) - 1))
	return bfd_reloc_overflow;
      contents = reencode_ld_lit_ofs_19 (contents, addend);
      break;

    case BFD_RELOC_AARCH64_TLSDESC_CALL:
      break;

    case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
    case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
    case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
    case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
    case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
    case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
    case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
    case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
    case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
    case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
    case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
      contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
      break;

    case BFD_RELOC_AARCH64_ADD_LO12:
    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
    case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
    case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
    case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
      /* Corresponds to: add rd, rn, #uimm12 to provide the low order
         12 bits of the page offset following
         BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the
         (pc-relative) page base.  */
      contents = reencode_add_imm (contents, addend);
      break;

    case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
    case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
    case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
    case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
    case BFD_RELOC_AARCH64_LDST128_LO12:
    case BFD_RELOC_AARCH64_LDST16_LO12:
    case BFD_RELOC_AARCH64_LDST32_LO12:
    case BFD_RELOC_AARCH64_LDST64_LO12:
    case BFD_RELOC_AARCH64_LDST8_LO12:
    case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
    case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
    case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
      if (old_addend & ((1 << howto->rightshift) - 1))
	return bfd_reloc_overflow;
      /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order
         12 bits of the page offset following BFD_RELOC_AARCH64_ADR_HI21_PCREL
         which computes the (pc-relative) page base.  */
      contents = reencode_ldst_pos_imm (contents, addend);
      break;

      /* Group relocations to create high bits of a 16, 32, 48 or 64
         bit signed data or abs address inline. Will change
         instruction to MOVN or MOVZ depending on sign of calculated
         value.  */

    case BFD_RELOC_AARCH64_MOVW_G0_S:
    case BFD_RELOC_AARCH64_MOVW_G1_S:
    case BFD_RELOC_AARCH64_MOVW_G2_S:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
      /* NOTE: We can only come here with movz or movn.  */
      if (addend < 0)
	{
	  /* Force use of MOVN.  */
	  addend = ~addend;
	  contents = reencode_movzn_to_movn (contents);
	}
      else
	{
	  /* Force use of MOVZ.  */
	  contents = reencode_movzn_to_movz (contents);
	}
      /* fall through */

      /* Group relocations to create a 16, 32, 48 or 64 bit unsigned
         data or abs address inline.  */

    case BFD_RELOC_AARCH64_MOVW_G0:
    case BFD_RELOC_AARCH64_MOVW_G0_NC:
    case BFD_RELOC_AARCH64_MOVW_G1:
    case BFD_RELOC_AARCH64_MOVW_G1_NC:
    case BFD_RELOC_AARCH64_MOVW_G2:
    case BFD_RELOC_AARCH64_MOVW_G2_NC:
    case BFD_RELOC_AARCH64_MOVW_G3:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
      contents = reencode_movw_imm (contents, addend);
      break;

    default:
      /* Repack simple data */
      if (howto->dst_mask & (howto->dst_mask + 1))
	return bfd_reloc_notsupported;

      contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask));
      break;
    }

  switch (size)
    {
    case 2:
      bfd_put_16 (abfd, contents, address);
      break;
    case 4:
      if (howto->dst_mask != 0xffffffff)
	/* must be 32-bit instruction, always little-endian */
	bfd_putl32 (contents, address);
      else
	/* must be 32-bit data (endianness dependent) */
	bfd_put_32 (abfd, contents, address);
      break;
    case 8:
      bfd_put_64 (abfd, contents, address);
      break;
    default:
      abort ();
    }

  return status;
}

bfd_vma
_bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
				     bfd_vma place, bfd_vma value,
				     bfd_vma addend, bfd_boolean weak_undef_p)
{
  switch (r_type)
    {
    case BFD_RELOC_AARCH64_NONE:
    case BFD_RELOC_AARCH64_TLSDESC_CALL:
      break;

    case BFD_RELOC_AARCH64_16_PCREL:
    case BFD_RELOC_AARCH64_32_PCREL:
    case BFD_RELOC_AARCH64_64_PCREL:
    case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
    case BFD_RELOC_AARCH64_BRANCH19:
    case BFD_RELOC_AARCH64_LD_LO19_PCREL:
    case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
    case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
    case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
    case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
    case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
    case BFD_RELOC_AARCH64_TSTBR14:
      if (weak_undef_p)
	value = place;
      value = value + addend - place;
      break;

    case BFD_RELOC_AARCH64_CALL26:
    case BFD_RELOC_AARCH64_JUMP26:
      value = value + addend - place;
      break;

    case BFD_RELOC_AARCH64_16:
    case BFD_RELOC_AARCH64_32:
    case BFD_RELOC_AARCH64_MOVW_G0:
    case BFD_RELOC_AARCH64_MOVW_G0_NC:
    case BFD_RELOC_AARCH64_MOVW_G0_S:
    case BFD_RELOC_AARCH64_MOVW_G1:
    case BFD_RELOC_AARCH64_MOVW_G1_NC:
    case BFD_RELOC_AARCH64_MOVW_G1_S:
    case BFD_RELOC_AARCH64_MOVW_G2:
    case BFD_RELOC_AARCH64_MOVW_G2_NC:
    case BFD_RELOC_AARCH64_MOVW_G2_S:
    case BFD_RELOC_AARCH64_MOVW_G3:
    case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
      value = value + addend;
      break;

    case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
    case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
      if (weak_undef_p)
	value = PG (place);
      value = PG (value + addend) - PG (place);
      break;

    case BFD_RELOC_AARCH64_GOT_LD_PREL19:
      value = value + addend - place;
      break;

    case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
    case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
    case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
    case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
    case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
      value = PG (value + addend) - PG (place);
      break;

    case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
    case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
      /* Caller must make sure addend is the base address of .got section.  */
      value = value - PG (addend);
      break;

    case BFD_RELOC_AARCH64_ADD_LO12:
    case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
    case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
    case BFD_RELOC_AARCH64_LDST128_LO12:
    case BFD_RELOC_AARCH64_LDST16_LO12:
    case BFD_RELOC_AARCH64_LDST32_LO12:
    case BFD_RELOC_AARCH64_LDST64_LO12:
    case BFD_RELOC_AARCH64_LDST8_LO12:
    case BFD_RELOC_AARCH64_TLSDESC_ADD:
    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
    case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
    case BFD_RELOC_AARCH64_TLSDESC_LDR:
    case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
    case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
    case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
      value = PG_OFFSET (value + addend);
      break;

    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
      value = value + addend;
      break;

    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
      value = (value + addend) & (bfd_vma) 0xffff0000;
      break;
    case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
      /* Mask off low 12bits, keep all other high bits, so that the later
	 generic code could check whehter there is overflow.  */
      value = (value + addend) & ~(bfd_vma) 0xfff;
      break;

    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
      value = (value + addend) & (bfd_vma) 0xffff;
      break;

    case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
      value = (value + addend) & ~(bfd_vma) 0xffffffff;
      value -= place & ~(bfd_vma) 0xffffffff;
      break;

    default:
      break;
    }

  return value;
}

/* Hook called by the linker routine which adds symbols from an object
   file.  */

bfd_boolean
_bfd_aarch64_elf_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
				  Elf_Internal_Sym *sym,
				  const char **namep ATTRIBUTE_UNUSED,
				  flagword *flagsp ATTRIBUTE_UNUSED,
				  asection **secp ATTRIBUTE_UNUSED,
				  bfd_vma *valp ATTRIBUTE_UNUSED)
{
  if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
       || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
      && (abfd->flags & DYNAMIC) == 0
      && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
    elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;

  return TRUE;
}

/* Support for core dump NOTE sections.  */

bfd_boolean
_bfd_aarch64_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
{
  int offset;
  size_t size;

  switch (note->descsz)
    {
      default:
	return FALSE;

      case 392:		/* sizeof(struct elf_prstatus) on Linux/arm64.  */
	/* pr_cursig */
	elf_tdata (abfd)->core->signal
	  = bfd_get_16 (abfd, note->descdata + 12);

	/* pr_pid */
	elf_tdata (abfd)->core->lwpid
	  = bfd_get_32 (abfd, note->descdata + 32);

	/* pr_reg */
	offset = 112;
	size = 272;

	break;
    }

  /* Make a ".reg/999" section.  */
  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
					  size, note->descpos + offset);
}

bfd_boolean
_bfd_aarch64_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
{
  switch (note->descsz)
    {
    default:
      return FALSE;

    case 136:        /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64.  */
      elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
      elf_tdata (abfd)->core->program
	= _bfd_elfcore_strndup (abfd, note->descdata + 40, 16);
      elf_tdata (abfd)->core->command
	= _bfd_elfcore_strndup (abfd, note->descdata + 56, 80);
    }

  /* Note that for some reason, a spurious space is tacked
     onto the end of the args in some (at least one anyway)
     implementations, so strip it off if it exists.  */

  {
    char *command = elf_tdata (abfd)->core->command;
    int n = strlen (command);

    if (0 < n && command[n - 1] == ' ')
      command[n - 1] = '\0';
  }

  return TRUE;
}

char *
_bfd_aarch64_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type,
				  ...)
{
  switch (note_type)
    {
    default:
      return NULL;

    case NT_PRPSINFO:
      {
        char data[136];
        va_list ap;

        va_start (ap, note_type);
        memset (data, 0, sizeof (data));
        strncpy (data + 40, va_arg (ap, const char *), 16);
        strncpy (data + 56, va_arg (ap, const char *), 80);
        va_end (ap);

        return elfcore_write_note (abfd, buf, bufsiz, "CORE",
				   note_type, data, sizeof (data));
      }

    case NT_PRSTATUS:
      {
        char data[392];
        va_list ap;
        long pid;
        int cursig;
        const void *greg;

        va_start (ap, note_type);
        memset (data, 0, sizeof (data));
        pid = va_arg (ap, long);
        bfd_put_32 (abfd, pid, data + 32);
        cursig = va_arg (ap, int);
        bfd_put_16 (abfd, cursig, data + 12);
        greg = va_arg (ap, const void *);
        memcpy (data + 112, greg, 272);
        va_end (ap);

        return elfcore_write_note (abfd, buf, bufsiz, "CORE",
				   note_type, data, sizeof (data));
      }
    }
}
Commit	Line	Data
caed7120	1	/* AArch64-specific support for ELF.
b90efa5b	2	Copyright (C) 2009-2015 Free Software Foundation, Inc.
caed7120 YZ	3	Contributed by ARM Ltd.
	4
	5	This file is part of BFD, the Binary File Descriptor library.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; see the file COPYING3. If not,
	19	see <http://www.gnu.org/licenses/>. */
	20
	21	#include "sysdep.h"
	22	#include "elfxx-aarch64.h"
d0ae9fbd OJ	23	#include <stdarg.h>
d0ae9fbd OJ	24	#include <string.h>
caed7120 YZ	25
	26	#define MASK(n) ((1u << (n)) - 1)
	27
4106101c MS	28	/* Sign-extend VALUE, which has the indicated number of BITS. */
	29
	30	bfd_signed_vma
	31	_bfd_aarch64_sign_extend (bfd_vma value, int bits)
	32	{
	33	if (value & ((bfd_vma) 1 << (bits - 1)))
	34	/* VALUE is negative. */
	35	value \|= ((bfd_vma) - 1) << bits;
	36
	37	return value;
	38	}
	39
	40	/* Decode the IMM field of ADRP. */
	41
	42	uint32_t
	43	_bfd_aarch64_decode_adrp_imm (uint32_t insn)
	44	{
	45	return (((insn >> 5) & MASK (19)) << 2) \| ((insn >> 29) & MASK (2));
	46	}
	47
caed7120 YZ	48	/* Reencode the imm field of add immediate. */
	49	static inline uint32_t
	50	reencode_add_imm (uint32_t insn, uint32_t imm)
	51	{
	52	return (insn & ~(MASK (12) << 10)) \| ((imm & MASK (12)) << 10);
	53	}
	54
4106101c MS	55	/* Reencode the IMM field of ADR. */
	56
	57	uint32_t
	58	_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
caed7120 YZ	59	{
	60	return (insn & ~((MASK (2) << 29) \| (MASK (19) << 5)))
	61	\| ((imm & MASK (2)) << 29) \| ((imm & (MASK (19) << 2)) << 3);
	62	}
	63
	64	/* Reencode the imm field of ld/st pos immediate. */
	65	static inline uint32_t
	66	reencode_ldst_pos_imm (uint32_t insn, uint32_t imm)
	67	{
	68	return (insn & ~(MASK (12) << 10)) \| ((imm & MASK (12)) << 10);
	69	}
	70
	71	/* Encode the 26-bit offset of unconditional branch. */
	72	static inline uint32_t
	73	reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs)
	74	{
	75	return (insn & ~MASK (26)) \| (ofs & MASK (26));
	76	}
	77
	78	/* Encode the 19-bit offset of conditional branch and compare & branch. */
	79	static inline uint32_t
	80	reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs)
	81	{
	82	return (insn & ~(MASK (19) << 5)) \| ((ofs & MASK (19)) << 5);
	83	}
	84
	85	/* Decode the 19-bit offset of load literal. */
	86	static inline uint32_t
	87	reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs)
	88	{
	89	return (insn & ~(MASK (19) << 5)) \| ((ofs & MASK (19)) << 5);
	90	}
	91
	92	/* Encode the 14-bit offset of test & branch. */
	93	static inline uint32_t
	94	reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
	95	{
	96	return (insn & ~(MASK (14) << 5)) \| ((ofs & MASK (14)) << 5);
	97	}
	98
	99	/* Reencode the imm field of move wide. */
	100	static inline uint32_t
	101	reencode_movw_imm (uint32_t insn, uint32_t imm)
	102	{
	103	return (insn & ~(MASK (16) << 5)) \| ((imm & MASK (16)) << 5);
	104	}
	105
	106	/* Reencode mov[zn] to movz. */
	107	static inline uint32_t
	108	reencode_movzn_to_movz (uint32_t opcode)
	109	{
	110	return opcode \| (1 << 30);
	111	}
	112
	113	/* Reencode mov[zn] to movn. */
	114	static inline uint32_t
	115	reencode_movzn_to_movn (uint32_t opcode)
	116	{
	117	return opcode & ~(1 << 30);
	118	}
	119
	120	/* Return non-zero if the indicated VALUE has overflowed the maximum
	121	range expressible by a unsigned number with the indicated number of
	122	BITS. */
123
124	static bfd_reloc_status_type
125	aarch64_unsigned_overflow (bfd_vma value, unsigned int bits)
126	{
127	bfd_vma lim;
128	if (bits >= sizeof (bfd_vma) * 8)
129	return bfd_reloc_ok;
130	lim = (bfd_vma) 1 << bits;
131	if (value >= lim)
132	return bfd_reloc_overflow;
133	return bfd_reloc_ok;
134	}
135
136	/* Return non-zero if the indicated VALUE has overflowed the maximum
137	range expressible by an signed number with the indicated number of
138	BITS. */
139
140	static bfd_reloc_status_type
141	aarch64_signed_overflow (bfd_vma value, unsigned int bits)
142	{
143	bfd_signed_vma svalue = (bfd_signed_vma) value;
144	bfd_signed_vma lim;
145
146	if (bits >= sizeof (bfd_vma) * 8)
147	return bfd_reloc_ok;
148	lim = (bfd_signed_vma) 1 << (bits - 1);
149	if (svalue < -lim \|\| svalue >= lim)
150	return bfd_reloc_overflow;
151	return bfd_reloc_ok;
152	}
153
154	/* Insert the addend/value into the instruction or data object being
155	relocated. */
156	bfd_reloc_status_type
157	_bfd_aarch64_elf_put_addend (bfd *abfd,
158	bfd_byte *address, bfd_reloc_code_real_type r_type,
159	reloc_howto_type *howto, bfd_signed_vma addend)
160	{
161	bfd_reloc_status_type status = bfd_reloc_ok;
162	bfd_signed_vma old_addend = addend;
163	bfd_vma contents;
164	int size;
165
166	size = bfd_get_reloc_size (howto);
167	switch (size)
168	{
6346d5ca AM	169	case 0:
6346d5ca AM	170	return status;
caed7120 YZ	171	case 2:
	172	contents = bfd_get_16 (abfd, address);
	173	break;
	174	case 4:
	175	if (howto->src_mask != 0xffffffff)
	176	/* Must be 32-bit instruction, always little-endian. */
	177	contents = bfd_getl32 (address);
	178	else
	179	/* Must be 32-bit data (endianness dependent). */
	180	contents = bfd_get_32 (abfd, address);
	181	break;
	182	case 8:
	183	contents = bfd_get_64 (abfd, address);
	184	break;
	185	default:
	186	abort ();
	187	}
	188
	189	switch (howto->complain_on_overflow)
	190	{
	191	case complain_overflow_dont:
	192	break;
	193	case complain_overflow_signed:
	194	status = aarch64_signed_overflow (addend,
	195	howto->bitsize + howto->rightshift);
	196	break;
	197	case complain_overflow_unsigned:
	198	status = aarch64_unsigned_overflow (addend,
	199	howto->bitsize + howto->rightshift);
	200	break;
	201	case complain_overflow_bitfield:
	202	default:
	203	abort ();
	204	}
	205
	206	addend >>= howto->rightshift;
	207
	208	switch (r_type)
	209	{
caed7120	210	case BFD_RELOC_AARCH64_CALL26:
ce336788	211	case BFD_RELOC_AARCH64_JUMP26:
caed7120 YZ	212	contents = reencode_branch_ofs_26 (contents, addend);
	213	break;
	214
	215	case BFD_RELOC_AARCH64_BRANCH19:
	216	contents = reencode_cond_branch_ofs_19 (contents, addend);
	217	break;
	218
	219	case BFD_RELOC_AARCH64_TSTBR14:
	220	contents = reencode_tst_branch_ofs_14 (contents, addend);
	221	break;
	222
caed7120	223	case BFD_RELOC_AARCH64_GOT_LD_PREL19:
ce336788 JW	224	case BFD_RELOC_AARCH64_LD_LO19_PCREL:
ce336788 JW	225	case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
043bf05a	226	case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
caed7120 YZ	227	if (old_addend & ((1 << howto->rightshift) - 1))
	228	return bfd_reloc_overflow;
	229	contents = reencode_ld_lit_ofs_19 (contents, addend);
	230	break;
	231
	232	case BFD_RELOC_AARCH64_TLSDESC_CALL:
	233	break;
	234
ce336788 JW	235	case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
	236	case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
	237	case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
	238	case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
	239	case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
389b8029	240	case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
caed7120	241	case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
ce336788	242	case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
caed7120	243	case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
f69e4920	244	case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
77a69ff8	245	case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
4106101c	246	contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
caed7120 YZ	247	break;
caed7120 YZ	248
ce336788 JW	249	case BFD_RELOC_AARCH64_ADD_LO12:
ce336788 JW	250	case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
caed7120	251	case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
40fbed84	252	case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
73f925cc	253	case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
caed7120	254	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
ce336788	255	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
caed7120	256	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
caed7120 YZ	257	/* Corresponds to: add rd, rn, #uimm12 to provide the low order
	258	12 bits of the page offset following
	259	BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the
	260	(pc-relative) page base. */
	261	contents = reencode_add_imm (contents, addend);
	262	break;
	263
7018c030	264	case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
ce336788	265	case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
99ad26cb	266	case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
ce336788 JW	267	case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
ce336788 JW	268	case BFD_RELOC_AARCH64_LDST128_LO12:
caed7120 YZ	269	case BFD_RELOC_AARCH64_LDST16_LO12:
	270	case BFD_RELOC_AARCH64_LDST32_LO12:
	271	case BFD_RELOC_AARCH64_LDST64_LO12:
ce336788	272	case BFD_RELOC_AARCH64_LDST8_LO12:
caed7120	273	case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
ce336788	274	case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
caed7120	275	case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
ce336788	276	case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
caed7120 YZ	277	if (old_addend & ((1 << howto->rightshift) - 1))
	278	return bfd_reloc_overflow;
	279	/* Used for ldr\|str rt, [rn, #uimm12] to provide the low order
	280	12 bits of the page offset following BFD_RELOC_AARCH64_ADR_HI21_PCREL
	281	which computes the (pc-relative) page base. */
	282	contents = reencode_ldst_pos_imm (contents, addend);
	283	break;
	284
	285	/* Group relocations to create high bits of a 16, 32, 48 or 64
	286	bit signed data or abs address inline. Will change
	287	instruction to MOVN or MOVZ depending on sign of calculated
	288	value. */
	289
caed7120 YZ	290	case BFD_RELOC_AARCH64_MOVW_G0_S:
	291	case BFD_RELOC_AARCH64_MOVW_G1_S:
	292	case BFD_RELOC_AARCH64_MOVW_G2_S:
ce336788 JW	293	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
	294	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
	295	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
caed7120 YZ	296	/* NOTE: We can only come here with movz or movn. */
	297	if (addend < 0)
	298	{
	299	/* Force use of MOVN. */
	300	addend = ~addend;
	301	contents = reencode_movzn_to_movn (contents);
	302	}
	303	else
	304	{
	305	/* Force use of MOVZ. */
	306	contents = reencode_movzn_to_movz (contents);
	307	}
	308	/* fall through */
	309
	310	/* Group relocations to create a 16, 32, 48 or 64 bit unsigned
	311	data or abs address inline. */
	312
	313	case BFD_RELOC_AARCH64_MOVW_G0:
	314	case BFD_RELOC_AARCH64_MOVW_G0_NC:
	315	case BFD_RELOC_AARCH64_MOVW_G1:
	316	case BFD_RELOC_AARCH64_MOVW_G1_NC:
	317	case BFD_RELOC_AARCH64_MOVW_G2:
	318	case BFD_RELOC_AARCH64_MOVW_G2_NC:
	319	case BFD_RELOC_AARCH64_MOVW_G3:
ce336788 JW	320	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
ce336788 JW	321	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
caed7120 YZ	322	contents = reencode_movw_imm (contents, addend);
	323	break;
	324
	325	default:
	326	/* Repack simple data */
	327	if (howto->dst_mask & (howto->dst_mask + 1))
	328	return bfd_reloc_notsupported;
	329
	330	contents = ((contents & ~howto->dst_mask) \| (addend & howto->dst_mask));
	331	break;
	332	}
	333
	334	switch (size)
	335	{
	336	case 2:
	337	bfd_put_16 (abfd, contents, address);
	338	break;
	339	case 4:
	340	if (howto->dst_mask != 0xffffffff)
	341	/* must be 32-bit instruction, always little-endian */
	342	bfd_putl32 (contents, address);
	343	else
	344	/* must be 32-bit data (endianness dependent) */
	345	bfd_put_32 (abfd, contents, address);
	346	break;
	347	case 8:
	348	bfd_put_64 (abfd, contents, address);
	349	break;
	350	default:
	351	abort ();
	352	}
	353
	354	return status;
	355	}
	356
	357	bfd_vma
	358	_bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
	359	bfd_vma place, bfd_vma value,
	360	bfd_vma addend, bfd_boolean weak_undef_p)
	361	{
	362	switch (r_type)
	363	{
caed7120	364	case BFD_RELOC_AARCH64_NONE:
ce336788	365	case BFD_RELOC_AARCH64_TLSDESC_CALL:
caed7120 YZ	366	break;
caed7120 YZ	367
ce336788 JW	368	case BFD_RELOC_AARCH64_16_PCREL:
	369	case BFD_RELOC_AARCH64_32_PCREL:
	370	case BFD_RELOC_AARCH64_64_PCREL:
	371	case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
	372	case BFD_RELOC_AARCH64_BRANCH19:
	373	case BFD_RELOC_AARCH64_LD_LO19_PCREL:
389b8029	374	case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
1ada945d	375	case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
3c12b054	376	case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
043bf05a	377	case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
77a69ff8	378	case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
caed7120 YZ	379	case BFD_RELOC_AARCH64_TSTBR14:
	380	if (weak_undef_p)
	381	value = place;
	382	value = value + addend - place;
	383	break;
	384
	385	case BFD_RELOC_AARCH64_CALL26:
	386	case BFD_RELOC_AARCH64_JUMP26:
	387	value = value + addend - place;
	388	break;
	389
	390	case BFD_RELOC_AARCH64_16:
	391	case BFD_RELOC_AARCH64_32:
caed7120 YZ	392	case BFD_RELOC_AARCH64_MOVW_G0:
caed7120 YZ	393	case BFD_RELOC_AARCH64_MOVW_G0_NC:
ce336788	394	case BFD_RELOC_AARCH64_MOVW_G0_S:
caed7120 YZ	395	case BFD_RELOC_AARCH64_MOVW_G1:
caed7120 YZ	396	case BFD_RELOC_AARCH64_MOVW_G1_NC:
ce336788	397	case BFD_RELOC_AARCH64_MOVW_G1_S:
caed7120 YZ	398	case BFD_RELOC_AARCH64_MOVW_G2:
caed7120 YZ	399	case BFD_RELOC_AARCH64_MOVW_G2_NC:
ce336788	400	case BFD_RELOC_AARCH64_MOVW_G2_S:
caed7120	401	case BFD_RELOC_AARCH64_MOVW_G3:
40fbed84	402	case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
caed7120 YZ	403	value = value + addend;
	404	break;
	405
caed7120	406	case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
ce336788	407	case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
caed7120 YZ	408	if (weak_undef_p)
	409	value = PG (place);
	410	value = PG (value + addend) - PG (place);
	411	break;
	412
	413	case BFD_RELOC_AARCH64_GOT_LD_PREL19:
	414	value = value + addend - place;
	415	break;
	416
	417	case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
	418	case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
	419	case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
	420	case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
f69e4920	421	case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
caed7120 YZ	422	value = PG (value + addend) - PG (place);
	423	break;
	424
7018c030	425	case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
99ad26cb JW	426	case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
	427	/* Caller must make sure addend is the base address of .got section. */
	428	value = value - PG (addend);
	429	break;
	430
caed7120	431	case BFD_RELOC_AARCH64_ADD_LO12:
caed7120	432	case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
ce336788 JW	433	case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
ce336788 JW	434	case BFD_RELOC_AARCH64_LDST128_LO12:
caed7120 YZ	435	case BFD_RELOC_AARCH64_LDST16_LO12:
	436	case BFD_RELOC_AARCH64_LDST32_LO12:
	437	case BFD_RELOC_AARCH64_LDST64_LO12:
ce336788	438	case BFD_RELOC_AARCH64_LDST8_LO12:
caed7120	439	case BFD_RELOC_AARCH64_TLSDESC_ADD:
ce336788	440	case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
caed7120	441	case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
ce336788	442	case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
caed7120 YZ	443	case BFD_RELOC_AARCH64_TLSDESC_LDR:
caed7120 YZ	444	case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
caed7120	445	case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
ce336788	446	case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
caed7120 YZ	447	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
	448	value = PG_OFFSET (value + addend);
	449	break;
	450
36e6c140 JW	451	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
	452	value = value + addend;
	453	break;
	454
caed7120 YZ	455	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
	456	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
	457	value = (value + addend) & (bfd_vma) 0xffff0000;
	458	break;
	459	case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
bab91cce JW	460	/* Mask off low 12bits, keep all other high bits, so that the later
	461	generic code could check whehter there is overflow. */
	462	value = (value + addend) & ~(bfd_vma) 0xfff;
caed7120 YZ	463	break;
	464
	465	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
	466	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
	467	value = (value + addend) & (bfd_vma) 0xffff;
	468	break;
	469
	470	case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
	471	value = (value + addend) & ~(bfd_vma) 0xffffffff;
	472	value -= place & ~(bfd_vma) 0xffffffff;
	473	break;
	474
	475	default:
	476	break;
	477	}
	478
	479	return value;
	480	}
	481
	482	/* Hook called by the linker routine which adds symbols from an object
	483	file. */
	484
	485	bfd_boolean
	486	_bfd_aarch64_elf_add_symbol_hook (bfd abfd, struct bfd_link_info info,
	487	Elf_Internal_Sym *sym,
	488	const char **namep ATTRIBUTE_UNUSED,
	489	flagword *flagsp ATTRIBUTE_UNUSED,
	490	asection **secp ATTRIBUTE_UNUSED,
	491	bfd_vma *valp ATTRIBUTE_UNUSED)
	492	{
f1885d1e AM	493	if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
	494	\|\| ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
	495	&& (abfd->flags & DYNAMIC) == 0
	496	&& bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29	497	elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
caed7120 YZ	498
	499	return TRUE;
	500	}
	501
	502	/* Support for core dump NOTE sections. */
	503
	504	bfd_boolean
	505	_bfd_aarch64_elf_grok_prstatus (bfd abfd, Elf_Internal_Note note)
	506	{
	507	int offset;
	508	size_t size;
	509
	510	switch (note->descsz)
	511	{
	512	default:
	513	return FALSE;
	514
3b570dee	515	case 392: /* sizeof(struct elf_prstatus) on Linux/arm64. */
caed7120 YZ	516	/* pr_cursig */
	517	elf_tdata (abfd)->core->signal
	518	= bfd_get_16 (abfd, note->descdata + 12);
	519
	520	/* pr_pid */
	521	elf_tdata (abfd)->core->lwpid
	522	= bfd_get_32 (abfd, note->descdata + 32);
	523
	524	/* pr_reg */
	525	offset = 112;
	526	size = 272;
	527
	528	break;
	529	}
	530
	531	/* Make a ".reg/999" section. */
	532	return _bfd_elfcore_make_pseudosection (abfd, ".reg",
	533	size, note->descpos + offset);
	534	}
d0ae9fbd OJ	535
	536	bfd_boolean
	537	_bfd_aarch64_elf_grok_psinfo (bfd abfd, Elf_Internal_Note note)
	538	{
	539	switch (note->descsz)
	540	{
	541	default:
	542	return FALSE;
	543
	544	case 136: /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64. */
	545	elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
	546	elf_tdata (abfd)->core->program
	547	= _bfd_elfcore_strndup (abfd, note->descdata + 40, 16);
	548	elf_tdata (abfd)->core->command
	549	= _bfd_elfcore_strndup (abfd, note->descdata + 56, 80);
	550	}
	551
	552	/* Note that for some reason, a spurious space is tacked
	553	onto the end of the args in some (at least one anyway)
	554	implementations, so strip it off if it exists. */
	555
	556	{
	557	char *command = elf_tdata (abfd)->core->command;
	558	int n = strlen (command);
	559
	560	if (0 < n && command[n - 1] == ' ')
	561	command[n - 1] = '\0';
	562	}
	563
	564	return TRUE;
	565	}
	566
	567	char *
	568	_bfd_aarch64_elf_write_core_note (bfd abfd, char buf, int *bufsiz, int note_type,
	569	...)
	570	{
	571	switch (note_type)
	572	{
	573	default:
	574	return NULL;
	575
	576	case NT_PRPSINFO:
	577	{
	578	char data[136];
	579	va_list ap;
	580
	581	va_start (ap, note_type);
	582	memset (data, 0, sizeof (data));
	583	strncpy (data + 40, va_arg (ap, const char *), 16);
	584	strncpy (data + 56, va_arg (ap, const char *), 80);
	585	va_end (ap);
	586
	587	return elfcore_write_note (abfd, buf, bufsiz, "CORE",
	588	note_type, data, sizeof (data));
	589	}
	590
	591	case NT_PRSTATUS:
	592	{
	593	char data[392];
	594	va_list ap;
	595	long pid;
	596	int cursig;
	597	const void *greg;
	598
599	va_start (ap, note_type);
600	memset (data, 0, sizeof (data));
601	pid = va_arg (ap, long);
602	bfd_put_32 (abfd, pid, data + 32);
603	cursig = va_arg (ap, int);
604	bfd_put_16 (abfd, cursig, data + 12);
605	greg = va_arg (ap, const void *);
606	memcpy (data + 112, greg, 272);
607	va_end (ap);
608
609	return elfcore_write_note (abfd, buf, bufsiz, "CORE",
610	note_type, data, sizeof (data));
611	}
612	}
613	}